[mirror_ubuntu-bionic-kernel.git] / drivers / char / agp / via-agp.c

/*
 * VIA AGPGART routines.
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include "agp.h"

static const struct pci_device_id agp_via_pci_table[];

#define VIA_GARTCTRL	0x80
#define VIA_APSIZE	0x84
#define VIA_ATTBASE	0x88

#define VIA_AGP3_GARTCTRL	0x90
#define VIA_AGP3_APSIZE		0x94
#define VIA_AGP3_ATTBASE	0x98
#define VIA_AGPSEL		0xfd

static int via_fetch_size(void)
{
	int i;
	u8 temp;
	struct aper_size_info_8 *values;

	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
	pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		if (temp == values[i].size_value) {
			agp_bridge->previous_size =
			    agp_bridge->current_size = (void *) (values + i);
			agp_bridge->aperture_size_idx = i;
			return values[i].size;
		}
	}
	printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
	return 0;
}


static int via_configure(void)
{
	struct aper_size_info_8 *current_size;

	current_size = A_SIZE_8(agp_bridge->current_size);
	/* aperture size */
	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
			      current_size->size_value);
	/* address to map to */
	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
						    AGP_APERTURE_BAR);

	/* GART control register */
	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);

	/* attbase - aperture GATT base */
	pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
			    (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
	return 0;
}


static void via_cleanup(void)
{
	struct aper_size_info_8 *previous_size;

	previous_size = A_SIZE_8(agp_bridge->previous_size);
	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
			      previous_size->size_value);
	/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
	 * during reinitialization.
	 */
}


static void via_tlbflush(struct agp_memory *mem)
{
	u32 temp;

	pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp);
	temp |= (1<<7);
	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
	temp &= ~(1<<7);
	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
}


static const struct aper_size_info_8 via_generic_sizes[9] =
{
	{256, 65536, 6, 0},
	{128, 32768, 5, 128},
	{64, 16384, 4, 192},
	{32, 8192, 3, 224},
	{16, 4096, 2, 240},
	{8, 2048, 1, 248},
	{4, 1024, 0, 252},
	{2, 512, 0, 254},
	{1, 256, 0, 255}
};


static int via_fetch_size_agp3(void)
{
	int i;
	u16 temp;
	struct aper_size_info_16 *values;

	values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
	pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
	temp &= 0xfff;

	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		if (temp == values[i].size_value) {
			agp_bridge->previous_size =
				agp_bridge->current_size = (void *) (values + i);
			agp_bridge->aperture_size_idx = i;
			return values[i].size;
		}
	}
	return 0;
}


static int via_configure_agp3(void)
{
	u32 temp;
	struct aper_size_info_16 *current_size;

	current_size = A_SIZE_16(agp_bridge->current_size);

	/* address to map to */
	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
						    AGP_APERTURE_BAR);

	/* attbase - aperture GATT base */
	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
		agp_bridge->gatt_bus_addr & 0xfffff000);

	/* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
	 *    translation table first.
	 * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
	 *    graphics AGP aperture for the AGP3.0 port.
	 */
	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7));
	return 0;
}


static void via_cleanup_agp3(void)
{
	struct aper_size_info_16 *previous_size;

	previous_size = A_SIZE_16(agp_bridge->previous_size);
	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
}


static void via_tlbflush_agp3(struct agp_memory *mem)
{
	u32 temp;

	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
}


static const struct agp_bridge_driver via_agp3_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= agp3_generic_sizes,
	.size_type		= U8_APER_SIZE,
	.num_aperture_sizes	= 10,
	.needs_scratch_page	= true,
	.configure		= via_configure_agp3,
	.fetch_size		= via_fetch_size_agp3,
	.cleanup		= via_cleanup_agp3,
	.tlb_flush		= via_tlbflush_agp3,
	.mask_memory		= agp_generic_mask_memory,
	.masks			= NULL,
	.agp_enable		= agp_generic_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= agp_generic_create_gatt_table,
	.free_gatt_table	= agp_generic_free_gatt_table,
	.insert_memory		= agp_generic_insert_memory,
	.remove_memory		= agp_generic_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_alloc_pages	= agp_generic_alloc_pages,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_destroy_pages	= agp_generic_destroy_pages,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
};

static const struct agp_bridge_driver via_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= via_generic_sizes,
	.size_type		= U8_APER_SIZE,
	.num_aperture_sizes	= 9,
	.needs_scratch_page	= true,
	.configure		= via_configure,
	.fetch_size		= via_fetch_size,
	.cleanup		= via_cleanup,
	.tlb_flush		= via_tlbflush,
	.mask_memory		= agp_generic_mask_memory,
	.masks			= NULL,
	.agp_enable		= agp_generic_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= agp_generic_create_gatt_table,
	.free_gatt_table	= agp_generic_free_gatt_table,
	.insert_memory		= agp_generic_insert_memory,
	.remove_memory		= agp_generic_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_alloc_pages	= agp_generic_alloc_pages,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_destroy_pages	= agp_generic_destroy_pages,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
};

static struct agp_device_ids via_agp_device_ids[] =
{
	{
		.device_id	= PCI_DEVICE_ID_VIA_82C597_0,
		.chipset_name	= "Apollo VP3",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_82C598_0,
		.chipset_name	= "Apollo MVP3",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_8501_0,
		.chipset_name	= "Apollo MVP4",
	},

	/* VT8601 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8601_0,
		.chipset_name	= "Apollo ProMedia/PLE133Ta",
	},

	/* VT82C693A / VT28C694T */
	{
		.device_id	= PCI_DEVICE_ID_VIA_82C691_0,
		.chipset_name	= "Apollo Pro 133",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_8371_0,
		.chipset_name	= "KX133",
	},

	/* VT8633 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8633_0,
		.chipset_name	= "Pro 266",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_XN266,
		.chipset_name	= "Apollo Pro266",
	},

	/* VT8361 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8361,
		.chipset_name	= "KLE133",
	},

	/* VT8365 / VT8362 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8363_0,
		.chipset_name	= "Twister-K/KT133x/KM133",
	},

	/* VT8753A */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8753_0,
		.chipset_name	= "P4X266",
	},

	/* VT8366 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8367_0,
		.chipset_name	= "KT266/KY266x/KT333",
	},

	/* VT8633 (for CuMine/ Celeron) */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8653_0,
		.chipset_name	= "Pro266T",
	},

	/* KM266 / PM266 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_XM266,
		.chipset_name	= "PM266/KM266",
	},

	/* CLE266 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_862X_0,
		.chipset_name	= "CLE266",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_8377_0,
		.chipset_name	= "KT400/KT400A/KT600",
	},

	/* VT8604 / VT8605 / VT8603
	 * (Apollo Pro133A chipset with S3 Savage4) */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8605_0,
		.chipset_name	= "ProSavage PM133/PL133/PN133"
	},

	/* P4M266x/P4N266 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8703_51_0,
		.chipset_name	= "P4M266x/P4N266",
	},

	/* VT8754 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8754C_0,
		.chipset_name	= "PT800",
	},

	/* P4X600 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8763_0,
		.chipset_name	= "P4X600"
	},

	/* KM400 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8378_0,
		.chipset_name	= "KM400/KM400A",
	},

	/* PT880 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_PT880,
		.chipset_name	= "PT880",
	},

	/* PT880 Ultra */
	{
		.device_id	= PCI_DEVICE_ID_VIA_PT880ULTRA,
		.chipset_name	= "PT880 Ultra",
	},

	/* PT890 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8783_0,
		.chipset_name	= "PT890",
	},

	/* PM800/PN800/PM880/PN880 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_PX8X0_0,
		.chipset_name	= "PM800/PN800/PM880/PN880",
	},
	/* KT880 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_3269_0,
		.chipset_name	= "KT880",
	},
	/* KTxxx/Px8xx */
	{
		.device_id	= PCI_DEVICE_ID_VIA_83_87XX_1,
		.chipset_name	= "VT83xx/VT87xx/KTxxx/Px8xx",
	},
	/* P4M800 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_3296_0,
		.chipset_name	= "P4M800",
	},
	/* P4M800CE */
	{
		.device_id	= PCI_DEVICE_ID_VIA_P4M800CE,
		.chipset_name	= "VT3314",
	},
	/* VT3324 / CX700 */
	{
		.device_id  = PCI_DEVICE_ID_VIA_VT3324,
		.chipset_name   = "CX700",
	},
	/* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
	 * architecture, the AGP resource and behavior are different from
	 * the traditional AGP which resides only in chipset. AGP is used
	 * by 3D driver which wasn't available for the VT3336 and VT3364
	 * generation until now.  Unfortunately, by testing, VT3364 works
	 * but VT3336 doesn't. - explanation from via, just leave this as
	 * as a placeholder to avoid future patches adding it back in.
	 */
#if 0
	{
		.device_id  = PCI_DEVICE_ID_VIA_VT3336,
		.chipset_name   = "VT3336",
	},
#endif
	/* P4M890 */
	{
		.device_id  = PCI_DEVICE_ID_VIA_P4M890,
		.chipset_name   = "P4M890",
	},
	/* P4M900 */
	{
		.device_id  = PCI_DEVICE_ID_VIA_VT3364,
		.chipset_name   = "P4M900",
	},
	{ }, /* dummy final entry, always present */
};


/*
 * VIA's AGP3 chipsets do magick to put the AGP bridge compliant
 * with the same standards version as the graphics card.
 */
static void check_via_agp3 (struct agp_bridge_data *bridge)
{
	u8 reg;

	pci_read_config_byte(bridge->dev, VIA_AGPSEL, &reg);
	/* Check AGP 2.0 compatibility mode. */
	if ((reg & (1<<1))==0)
		bridge->driver = &via_agp3_driver;
}


static int agp_via_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct agp_device_ids *devs = via_agp_device_ids;
	struct agp_bridge_data *bridge;
	int j = 0;
	u8 cap_ptr;

	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	if (!cap_ptr)
		return -ENODEV;

	j = ent - agp_via_pci_table;
	printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);

	bridge = agp_alloc_bridge();
	if (!bridge)
		return -ENOMEM;

	bridge->dev = pdev;
	bridge->capndx = cap_ptr;
	bridge->driver = &via_driver;

	/*
	 * Garg, there are KT400s with KT266 IDs.
	 */
	if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
		/* Is there a KT400 subsystem ? */
		if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
			printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
			check_via_agp3(bridge);
		}
	}

	/* If this is an AGP3 bridge, check which mode its in and adjust. */
	get_agp_version(bridge);
	if (bridge->major_version >= 3)
		check_via_agp3(bridge);

	/* Fill in the mode register */
	pci_read_config_dword(pdev,
			bridge->capndx+PCI_AGP_STATUS, &bridge->mode);

	pci_set_drvdata(pdev, bridge);
	return agp_add_bridge(bridge);
}

static void agp_via_remove(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

	agp_remove_bridge(bridge);
	agp_put_bridge(bridge);
}

#ifdef CONFIG_PM

static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state)
{
	pci_save_state (pdev);
	pci_set_power_state (pdev, PCI_D3hot);

	return 0;
}

static int agp_via_resume(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

	pci_set_power_state (pdev, PCI_D0);
	pci_restore_state(pdev);

	if (bridge->driver == &via_agp3_driver)
		return via_configure_agp3();
	else if (bridge->driver == &via_driver)
		return via_configure();

	return 0;
}

#endif /* CONFIG_PM */

/* must be the same order as name table above */
static const struct pci_device_id agp_via_pci_table[] = {
#define ID(x) \
	{						\
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),	\
	.class_mask	= ~0,				\
	.vendor		= PCI_VENDOR_ID_VIA,		\
	.device		= x,				\
	.subvendor	= PCI_ANY_ID,			\
	.subdevice	= PCI_ANY_ID,			\
	}
	ID(PCI_DEVICE_ID_VIA_82C597_0),
	ID(PCI_DEVICE_ID_VIA_82C598_0),
	ID(PCI_DEVICE_ID_VIA_8501_0),
	ID(PCI_DEVICE_ID_VIA_8601_0),
	ID(PCI_DEVICE_ID_VIA_82C691_0),
	ID(PCI_DEVICE_ID_VIA_8371_0),
	ID(PCI_DEVICE_ID_VIA_8633_0),
	ID(PCI_DEVICE_ID_VIA_XN266),
	ID(PCI_DEVICE_ID_VIA_8361),
	ID(PCI_DEVICE_ID_VIA_8363_0),
	ID(PCI_DEVICE_ID_VIA_8753_0),
	ID(PCI_DEVICE_ID_VIA_8367_0),
	ID(PCI_DEVICE_ID_VIA_8653_0),
	ID(PCI_DEVICE_ID_VIA_XM266),
	ID(PCI_DEVICE_ID_VIA_862X_0),
	ID(PCI_DEVICE_ID_VIA_8377_0),
	ID(PCI_DEVICE_ID_VIA_8605_0),
	ID(PCI_DEVICE_ID_VIA_8703_51_0),
	ID(PCI_DEVICE_ID_VIA_8754C_0),
	ID(PCI_DEVICE_ID_VIA_8763_0),
	ID(PCI_DEVICE_ID_VIA_8378_0),
	ID(PCI_DEVICE_ID_VIA_PT880),
	ID(PCI_DEVICE_ID_VIA_PT880ULTRA),
	ID(PCI_DEVICE_ID_VIA_8783_0),
	ID(PCI_DEVICE_ID_VIA_PX8X0_0),
	ID(PCI_DEVICE_ID_VIA_3269_0),
	ID(PCI_DEVICE_ID_VIA_83_87XX_1),
	ID(PCI_DEVICE_ID_VIA_3296_0),
	ID(PCI_DEVICE_ID_VIA_P4M800CE),
	ID(PCI_DEVICE_ID_VIA_VT3324),
	ID(PCI_DEVICE_ID_VIA_P4M890),
	ID(PCI_DEVICE_ID_VIA_VT3364),
	{ }
};

MODULE_DEVICE_TABLE(pci, agp_via_pci_table);


static struct pci_driver agp_via_pci_driver = {
	.name		= "agpgart-via",
	.id_table	= agp_via_pci_table,
	.probe		= agp_via_probe,
	.remove		= agp_via_remove,
#ifdef CONFIG_PM
	.suspend	= agp_via_suspend,
	.resume		= agp_via_resume,
#endif
};


static int __init agp_via_init(void)
{
	if (agp_off)
		return -EINVAL;
	return pci_register_driver(&agp_via_pci_driver);
}

static void __exit agp_via_cleanup(void)
{
	pci_unregister_driver(&agp_via_pci_driver);
}

module_init(agp_via_init);
module_exit(agp_via_cleanup);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Dave Jones");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* VIA AGPGART routines.
	3	*/
	4
	5	#include <linux/types.h>
	6	#include <linux/module.h>
	7	#include <linux/pci.h>
	8	#include <linux/init.h>
	9	#include <linux/agp_backend.h>
	10	#include "agp.h"
	11
b53e674a	12	static const struct pci_device_id agp_via_pci_table[];
1da177e4 LT	13
	14	#define VIA_GARTCTRL 0x80
	15	#define VIA_APSIZE 0x84
	16	#define VIA_ATTBASE 0x88
	17
	18	#define VIA_AGP3_GARTCTRL 0x90
	19	#define VIA_AGP3_APSIZE 0x94
	20	#define VIA_AGP3_ATTBASE 0x98
	21	#define VIA_AGPSEL 0xfd
	22
	23	static int via_fetch_size(void)
	24	{
	25	int i;
	26	u8 temp;
	27	struct aper_size_info_8 *values;
	28
	29	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
	30	pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
	31	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	32	if (temp == values[i].size_value) {
	33	agp_bridge->previous_size =
	34	agp_bridge->current_size = (void *) (values + i);
	35	agp_bridge->aperture_size_idx = i;
	36	return values[i].size;
	37	}
	38	}
	39	printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
	40	return 0;
	41	}
	42
	43
	44	static int via_configure(void)
	45	{
1da177e4 LT	46	struct aper_size_info_8 *current_size;
	47
	48	current_size = A_SIZE_8(agp_bridge->current_size);
	49	/* aperture size */
	50	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
	51	current_size->size_value);
e501b3d8 BH	52	/* address to map to */
	53	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
	54	AGP_APERTURE_BAR);
1da177e4 LT	55
	56	/* GART control register */
	57	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
	58
	59	/* attbase - aperture GATT base */
	60	pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
	61	(agp_bridge->gatt_bus_addr & 0xfffff000) \| 3);
	62	return 0;
	63	}
	64
	65
	66	static void via_cleanup(void)
	67	{
	68	struct aper_size_info_8 *previous_size;
	69
	70	previous_size = A_SIZE_8(agp_bridge->previous_size);
	71	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
	72	previous_size->size_value);
	73	/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
	74	* during reinitialization.
	75	*/
	76	}
	77
	78
	79	static void via_tlbflush(struct agp_memory *mem)
	80	{
	81	u32 temp;
	82
	83	pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp);
	84	temp \|= (1<<7);
	85	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
	86	temp &= ~(1<<7);
	87	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
	88	}
	89
	90
e5524f35	91	static const struct aper_size_info_8 via_generic_sizes[9] =
1da177e4 LT	92	{
	93	{256, 65536, 6, 0},
	94	{128, 32768, 5, 128},
	95	{64, 16384, 4, 192},
	96	{32, 8192, 3, 224},
	97	{16, 4096, 2, 240},
	98	{8, 2048, 1, 248},
	99	{4, 1024, 0, 252},
	100	{2, 512, 0, 254},
	101	{1, 256, 0, 255}
	102	};
	103
	104
	105	static int via_fetch_size_agp3(void)
	106	{
	107	int i;
	108	u16 temp;
	109	struct aper_size_info_16 *values;
	110
	111	values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
	112	pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
	113	temp &= 0xfff;
	114
	115	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	116	if (temp == values[i].size_value) {
	117	agp_bridge->previous_size =
	118	agp_bridge->current_size = (void *) (values + i);
	119	agp_bridge->aperture_size_idx = i;
	120	return values[i].size;
	121	}
	122	}
	123	return 0;
	124	}
	125
	126
	127	static int via_configure_agp3(void)
	128	{
	129	u32 temp;
	130	struct aper_size_info_16 *current_size;
	131
	132	current_size = A_SIZE_16(agp_bridge->current_size);
	133
e501b3d8 BH	134	/* address to map to */
	135	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
	136	AGP_APERTURE_BAR);
1da177e4 LT	137
	138	/* attbase - aperture GATT base */
	139	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
	140	agp_bridge->gatt_bus_addr & 0xfffff000);
	141
	142	/* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
	143	* translation table first.
	144	* 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
	145	* graphics AGP aperture for the AGP3.0 port.
	146	*/
	147	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
	148	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp \| (3<<7));
	149	return 0;
	150	}
	151
	152
	153	static void via_cleanup_agp3(void)
	154	{
	155	struct aper_size_info_16 *previous_size;
	156
	157	previous_size = A_SIZE_16(agp_bridge->previous_size);
	158	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
	159	}
	160
	161
	162	static void via_tlbflush_agp3(struct agp_memory *mem)
	163	{
	164	u32 temp;
	165
	166	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
	167	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
	168	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
	169	}
	170
	171
e5524f35	172	static const struct agp_bridge_driver via_agp3_driver = {
1da177e4 LT	173	.owner = THIS_MODULE,
	174	.aperture_sizes = agp3_generic_sizes,
	175	.size_type = U8_APER_SIZE,
	176	.num_aperture_sizes = 10,
61cf0593	177	.needs_scratch_page = true,
1da177e4 LT	178	.configure = via_configure_agp3,
	179	.fetch_size = via_fetch_size_agp3,
	180	.cleanup = via_cleanup_agp3,
	181	.tlb_flush = via_tlbflush_agp3,
	182	.mask_memory = agp_generic_mask_memory,
	183	.masks = NULL,
	184	.agp_enable = agp_generic_enable,
	185	.cache_flush = global_cache_flush,
	186	.create_gatt_table = agp_generic_create_gatt_table,
	187	.free_gatt_table = agp_generic_free_gatt_table,
	188	.insert_memory = agp_generic_insert_memory,
	189	.remove_memory = agp_generic_remove_memory,
	190	.alloc_by_type = agp_generic_alloc_by_type,
	191	.free_by_type = agp_generic_free_by_type,
	192	.agp_alloc_page = agp_generic_alloc_page,
5f310b63	193	.agp_alloc_pages = agp_generic_alloc_pages,
1da177e4	194	.agp_destroy_page = agp_generic_destroy_page,
5f310b63	195	.agp_destroy_pages = agp_generic_destroy_pages,
a030ce44	196	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4 LT	197	};
1da177e4 LT	198
e5524f35	199	static const struct agp_bridge_driver via_driver = {
1da177e4 LT	200	.owner = THIS_MODULE,
	201	.aperture_sizes = via_generic_sizes,
	202	.size_type = U8_APER_SIZE,
	203	.num_aperture_sizes = 9,
61cf0593	204	.needs_scratch_page = true,
1da177e4 LT	205	.configure = via_configure,
	206	.fetch_size = via_fetch_size,
	207	.cleanup = via_cleanup,
	208	.tlb_flush = via_tlbflush,
	209	.mask_memory = agp_generic_mask_memory,
	210	.masks = NULL,
	211	.agp_enable = agp_generic_enable,
	212	.cache_flush = global_cache_flush,
	213	.create_gatt_table = agp_generic_create_gatt_table,
	214	.free_gatt_table = agp_generic_free_gatt_table,
	215	.insert_memory = agp_generic_insert_memory,
	216	.remove_memory = agp_generic_remove_memory,
	217	.alloc_by_type = agp_generic_alloc_by_type,
	218	.free_by_type = agp_generic_free_by_type,
	219	.agp_alloc_page = agp_generic_alloc_page,
5f310b63	220	.agp_alloc_pages = agp_generic_alloc_pages,
1da177e4	221	.agp_destroy_page = agp_generic_destroy_page,
5f310b63	222	.agp_destroy_pages = agp_generic_destroy_pages,
a030ce44	223	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4 LT	224	};
1da177e4 LT	225
0bbed20e	226	static struct agp_device_ids via_agp_device_ids[] =
1da177e4 LT	227	{
	228	{
	229	.device_id = PCI_DEVICE_ID_VIA_82C597_0,
	230	.chipset_name = "Apollo VP3",
	231	},
	232
	233	{
	234	.device_id = PCI_DEVICE_ID_VIA_82C598_0,
	235	.chipset_name = "Apollo MVP3",
	236	},
	237
	238	{
	239	.device_id = PCI_DEVICE_ID_VIA_8501_0,
	240	.chipset_name = "Apollo MVP4",
	241	},
	242
	243	/* VT8601 */
	244	{
	245	.device_id = PCI_DEVICE_ID_VIA_8601_0,
	246	.chipset_name = "Apollo ProMedia/PLE133Ta",
	247	},
	248
	249	/* VT82C693A / VT28C694T */
	250	{
	251	.device_id = PCI_DEVICE_ID_VIA_82C691_0,
	252	.chipset_name = "Apollo Pro 133",
	253	},
	254
	255	{
	256	.device_id = PCI_DEVICE_ID_VIA_8371_0,
	257	.chipset_name = "KX133",
	258	},
	259
	260	/* VT8633 */
	261	{
	262	.device_id = PCI_DEVICE_ID_VIA_8633_0,
	263	.chipset_name = "Pro 266",
	264	},
	265
	266	{
	267	.device_id = PCI_DEVICE_ID_VIA_XN266,
	268	.chipset_name = "Apollo Pro266",
	269	},
	270
	271	/* VT8361 */
	272	{
	273	.device_id = PCI_DEVICE_ID_VIA_8361,
	274	.chipset_name = "KLE133",
	275	},
	276
	277	/* VT8365 / VT8362 */
	278	{
	279	.device_id = PCI_DEVICE_ID_VIA_8363_0,
	280	.chipset_name = "Twister-K/KT133x/KM133",
	281	},
	282
	283	/* VT8753A */
	284	{
	285	.device_id = PCI_DEVICE_ID_VIA_8753_0,
	286	.chipset_name = "P4X266",
	287	},
	288
	289	/* VT8366 */
	290	{
291	.device_id = PCI_DEVICE_ID_VIA_8367_0,
292	.chipset_name = "KT266/KY266x/KT333",
293	},
294
295	/* VT8633 (for CuMine/ Celeron) */
296	{
297	.device_id = PCI_DEVICE_ID_VIA_8653_0,
298	.chipset_name = "Pro266T",
299	},
300
301	/* KM266 / PM266 */
302	{
303	.device_id = PCI_DEVICE_ID_VIA_XM266,
304	.chipset_name = "PM266/KM266",
305	},
306
307	/* CLE266 */
308	{
309	.device_id = PCI_DEVICE_ID_VIA_862X_0,
310	.chipset_name = "CLE266",
311	},
312
313	{
314	.device_id = PCI_DEVICE_ID_VIA_8377_0,
315	.chipset_name = "KT400/KT400A/KT600",
316	},
317
318	/* VT8604 / VT8605 / VT8603
319	* (Apollo Pro133A chipset with S3 Savage4) */
320	{
321	.device_id = PCI_DEVICE_ID_VIA_8605_0,
322	.chipset_name = "ProSavage PM133/PL133/PN133"
323	},
324
325	/* P4M266x/P4N266 */
326	{
327	.device_id = PCI_DEVICE_ID_VIA_8703_51_0,
328	.chipset_name = "P4M266x/P4N266",
329	},
330
331	/* VT8754 */
332	{
333	.device_id = PCI_DEVICE_ID_VIA_8754C_0,
334	.chipset_name = "PT800",
335	},
336
337	/* P4X600 */
338	{
339	.device_id = PCI_DEVICE_ID_VIA_8763_0,
340	.chipset_name = "P4X600"
341	},
342
343	/* KM400 */
344	{
345	.device_id = PCI_DEVICE_ID_VIA_8378_0,
346	.chipset_name = "KM400/KM400A",
347	},
348
349	/* PT880 */
350	{
351	.device_id = PCI_DEVICE_ID_VIA_PT880,
352	.chipset_name = "PT880",
353	},
354
7dd1d9b8 MK	355	/* PT880 Ultra */
	356	{
	357	.device_id = PCI_DEVICE_ID_VIA_PT880ULTRA,
	358	.chipset_name = "PT880 Ultra",
	359	},
	360
1da177e4 LT	361	/* PT890 */
	362	{
	363	.device_id = PCI_DEVICE_ID_VIA_8783_0,
	364	.chipset_name = "PT890",
	365	},
	366
	367	/* PM800/PN800/PM880/PN880 */
	368	{
	369	.device_id = PCI_DEVICE_ID_VIA_PX8X0_0,
	370	.chipset_name = "PM800/PN800/PM880/PN880",
	371	},
	372	/* KT880 */
	373	{
	374	.device_id = PCI_DEVICE_ID_VIA_3269_0,
	375	.chipset_name = "KT880",
	376	},
	377	/* KTxxx/Px8xx */
	378	{
	379	.device_id = PCI_DEVICE_ID_VIA_83_87XX_1,
	380	.chipset_name = "VT83xx/VT87xx/KTxxx/Px8xx",
	381	},
	382	/* P4M800 */
	383	{
	384	.device_id = PCI_DEVICE_ID_VIA_3296_0,
	385	.chipset_name = "P4M800",
	386	},
c243f1f1 DJ	387	/* P4M800CE */
	388	{
	389	.device_id = PCI_DEVICE_ID_VIA_P4M800CE,
43ed41f6 DJ	390	.chipset_name = "VT3314",
43ed41f6 DJ	391	},
bbdfff86	392	/* VT3324 / CX700 */
43ed41f6	393	{
bbdfff86	394	.device_id = PCI_DEVICE_ID_VIA_VT3324,
43ed41f6 DJ	395	.chipset_name = "CX700",
43ed41f6 DJ	396	},
dcd981a7 GKH	397	/* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
	398	* architecture, the AGP resource and behavior are different from
	399	* the traditional AGP which resides only in chipset. AGP is used
	400	* by 3D driver which wasn't available for the VT3336 and VT3364
	401	* generation until now. Unfortunately, by testing, VT3364 works
25985edc	402	* but VT3336 doesn't. - explanation from via, just leave this as
dcd981a7 GKH	403	* as a placeholder to avoid future patches adding it back in.
	404	*/
	405	#if 0
43ed41f6 DJ	406	{
	407	.device_id = PCI_DEVICE_ID_VIA_VT3336,
	408	.chipset_name = "VT3336",
	409	},
dcd981a7	410	#endif
43ed41f6 DJ	411	/* P4M890 */
	412	{
	413	.device_id = PCI_DEVICE_ID_VIA_P4M890,
	414	.chipset_name = "P4M890",
c243f1f1	415	},
32ddef98 XB	416	/* P4M900 */
	417	{
	418	.device_id = PCI_DEVICE_ID_VIA_VT3364,
	419	.chipset_name = "P4M900",
	420	},
1da177e4 LT	421	{ }, /* dummy final entry, always present */
	422	};
	423
	424
	425	/*
	426	* VIA's AGP3 chipsets do magick to put the AGP bridge compliant
	427	* with the same standards version as the graphics card.
	428	*/
	429	static void check_via_agp3 (struct agp_bridge_data *bridge)
	430	{
	431	u8 reg;
	432
	433	pci_read_config_byte(bridge->dev, VIA_AGPSEL, &reg);
	434	/* Check AGP 2.0 compatibility mode. */
	435	if ((reg & (1<<1))==0)
	436	bridge->driver = &via_agp3_driver;
	437	}
	438
	439
bcd2982a	440	static int agp_via_probe(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4 LT	441	{
	442	struct agp_device_ids *devs = via_agp_device_ids;
	443	struct agp_bridge_data *bridge;
	444	int j = 0;
	445	u8 cap_ptr;
	446
	447	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	448	if (!cap_ptr)
	449	return -ENODEV;
	450
	451	j = ent - agp_via_pci_table;
	452	printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
	453
	454	bridge = agp_alloc_bridge();
	455	if (!bridge)
	456	return -ENOMEM;
	457
	458	bridge->dev = pdev;
	459	bridge->capndx = cap_ptr;
	460	bridge->driver = &via_driver;
	461
	462	/*
	463	* Garg, there are KT400s with KT266 IDs.
	464	*/
	465	if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
	466	/* Is there a KT400 subsystem ? */
	467	if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
	468	printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
	469	check_via_agp3(bridge);
	470	}
	471	}
	472
	473	/* If this is an AGP3 bridge, check which mode its in and adjust. */
	474	get_agp_version(bridge);
	475	if (bridge->major_version >= 3)
	476	check_via_agp3(bridge);
	477
	478	/* Fill in the mode register */
	479	pci_read_config_dword(pdev,
	480	bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
	481
	482	pci_set_drvdata(pdev, bridge);
	483	return agp_add_bridge(bridge);
	484	}
	485
39af33fc	486	static void agp_via_remove(struct pci_dev *pdev)
1da177e4 LT	487	{
	488	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
	489
	490	agp_remove_bridge(bridge);
	491	agp_put_bridge(bridge);
	492	}
	493
	494	#ifdef CONFIG_PM
	495
	496	static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state)
	497	{
	498	pci_save_state (pdev);
	499	pci_set_power_state (pdev, PCI_D3hot);
	500
	501	return 0;
	502	}
	503
	504	static int agp_via_resume(struct pci_dev *pdev)
	505	{
	506	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
	507
	508	pci_set_power_state (pdev, PCI_D0);
	509	pci_restore_state(pdev);
	510
	511	if (bridge->driver == &via_agp3_driver)
	512	return via_configure_agp3();
	513	else if (bridge->driver == &via_driver)
	514	return via_configure();
	515
	516	return 0;
	517	}
	518
	519	#endif /* CONFIG_PM */
	520
	521	/* must be the same order as name table above */
b53e674a	522	static const struct pci_device_id agp_via_pci_table[] = {
1da177e4 LT	523	#define ID(x) \
	524	{ \
	525	.class = (PCI_CLASS_BRIDGE_HOST << 8), \
	526	.class_mask = ~0, \
	527	.vendor = PCI_VENDOR_ID_VIA, \
	528	.device = x, \
	529	.subvendor = PCI_ANY_ID, \
	530	.subdevice = PCI_ANY_ID, \
	531	}
	532	ID(PCI_DEVICE_ID_VIA_82C597_0),
	533	ID(PCI_DEVICE_ID_VIA_82C598_0),
	534	ID(PCI_DEVICE_ID_VIA_8501_0),
	535	ID(PCI_DEVICE_ID_VIA_8601_0),
	536	ID(PCI_DEVICE_ID_VIA_82C691_0),
	537	ID(PCI_DEVICE_ID_VIA_8371_0),
	538	ID(PCI_DEVICE_ID_VIA_8633_0),
	539	ID(PCI_DEVICE_ID_VIA_XN266),
	540	ID(PCI_DEVICE_ID_VIA_8361),
	541	ID(PCI_DEVICE_ID_VIA_8363_0),
	542	ID(PCI_DEVICE_ID_VIA_8753_0),
	543	ID(PCI_DEVICE_ID_VIA_8367_0),
	544	ID(PCI_DEVICE_ID_VIA_8653_0),
	545	ID(PCI_DEVICE_ID_VIA_XM266),
	546	ID(PCI_DEVICE_ID_VIA_862X_0),
	547	ID(PCI_DEVICE_ID_VIA_8377_0),
	548	ID(PCI_DEVICE_ID_VIA_8605_0),
	549	ID(PCI_DEVICE_ID_VIA_8703_51_0),
	550	ID(PCI_DEVICE_ID_VIA_8754C_0),
	551	ID(PCI_DEVICE_ID_VIA_8763_0),
	552	ID(PCI_DEVICE_ID_VIA_8378_0),
	553	ID(PCI_DEVICE_ID_VIA_PT880),
7dd1d9b8	554	ID(PCI_DEVICE_ID_VIA_PT880ULTRA),
1da177e4 LT	555	ID(PCI_DEVICE_ID_VIA_8783_0),
	556	ID(PCI_DEVICE_ID_VIA_PX8X0_0),
	557	ID(PCI_DEVICE_ID_VIA_3269_0),
	558	ID(PCI_DEVICE_ID_VIA_83_87XX_1),
	559	ID(PCI_DEVICE_ID_VIA_3296_0),
c243f1f1	560	ID(PCI_DEVICE_ID_VIA_P4M800CE),
bbdfff86	561	ID(PCI_DEVICE_ID_VIA_VT3324),
43ed41f6	562	ID(PCI_DEVICE_ID_VIA_P4M890),
dcd981a7	563	ID(PCI_DEVICE_ID_VIA_VT3364),
1da177e4 LT	564	{ }
	565	};
	566
	567	MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
	568
	569
	570	static struct pci_driver agp_via_pci_driver = {
	571	.name = "agpgart-via",
	572	.id_table = agp_via_pci_table,
	573	.probe = agp_via_probe,
	574	.remove = agp_via_remove,
	575	#ifdef CONFIG_PM
	576	.suspend = agp_via_suspend,
	577	.resume = agp_via_resume,
	578	#endif
	579	};
	580
	581
	582	static int __init agp_via_init(void)
	583	{
	584	if (agp_off)
	585	return -EINVAL;
	586	return pci_register_driver(&agp_via_pci_driver);
	587	}
	588
	589	static void __exit agp_via_cleanup(void)
	590	{
	591	pci_unregister_driver(&agp_via_pci_driver);
	592	}
	593
	594	module_init(agp_via_init);
	595	module_exit(agp_via_cleanup);
	596
	597	MODULE_LICENSE("GPL");
bd8136d3	598	MODULE_AUTHOR("Dave Jones");