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1da177e4 LT |
1 | /** |
2 | * \file drm.h | |
3 | * Header for the Direct Rendering Manager | |
4 | * | |
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> | |
6 | * | |
7 | * \par Acknowledgments: | |
8 | * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
13 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
14 | * All rights reserved. | |
15 | * | |
16 | * Permission is hereby granted, free of charge, to any person obtaining a | |
17 | * copy of this software and associated documentation files (the "Software"), | |
18 | * to deal in the Software without restriction, including without limitation | |
19 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
20 | * and/or sell copies of the Software, and to permit persons to whom the | |
21 | * Software is furnished to do so, subject to the following conditions: | |
22 | * | |
23 | * The above copyright notice and this permission notice (including the next | |
24 | * paragraph) shall be included in all copies or substantial portions of the | |
25 | * Software. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
28 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
29 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
30 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
31 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
32 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
33 | * OTHER DEALINGS IN THE SOFTWARE. | |
34 | */ | |
35 | ||
36 | ||
37 | #ifndef _DRM_H_ | |
38 | #define _DRM_H_ | |
39 | ||
40 | #if defined(__linux__) | |
41 | #include <linux/config.h> | |
42 | #include <asm/ioctl.h> /* For _IO* macros */ | |
43 | #define DRM_IOCTL_NR(n) _IOC_NR(n) | |
44 | #define DRM_IOC_VOID _IOC_NONE | |
45 | #define DRM_IOC_READ _IOC_READ | |
46 | #define DRM_IOC_WRITE _IOC_WRITE | |
47 | #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE | |
48 | #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) | |
49 | #elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) | |
50 | #if defined(__FreeBSD__) && defined(IN_MODULE) | |
51 | /* Prevent name collision when including sys/ioccom.h */ | |
52 | #undef ioctl | |
53 | #include <sys/ioccom.h> | |
54 | #define ioctl(a,b,c) xf86ioctl(a,b,c) | |
55 | #else | |
56 | #include <sys/ioccom.h> | |
57 | #endif /* __FreeBSD__ && xf86ioctl */ | |
58 | #define DRM_IOCTL_NR(n) ((n) & 0xff) | |
59 | #define DRM_IOC_VOID IOC_VOID | |
60 | #define DRM_IOC_READ IOC_OUT | |
61 | #define DRM_IOC_WRITE IOC_IN | |
62 | #define DRM_IOC_READWRITE IOC_INOUT | |
63 | #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) | |
64 | #endif | |
65 | ||
66 | #define XFREE86_VERSION(major,minor,patch,snap) \ | |
67 | ((major << 16) | (minor << 8) | patch) | |
68 | ||
69 | #ifndef CONFIG_XFREE86_VERSION | |
70 | #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0) | |
71 | #endif | |
72 | ||
73 | #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) | |
74 | #define DRM_PROC_DEVICES "/proc/devices" | |
75 | #define DRM_PROC_MISC "/proc/misc" | |
76 | #define DRM_PROC_DRM "/proc/drm" | |
77 | #define DRM_DEV_DRM "/dev/drm" | |
78 | #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) | |
79 | #define DRM_DEV_UID 0 | |
80 | #define DRM_DEV_GID 0 | |
81 | #endif | |
82 | ||
83 | #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) | |
84 | #define DRM_MAJOR 226 | |
85 | #define DRM_MAX_MINOR 15 | |
86 | #endif | |
87 | #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ | |
88 | #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ | |
89 | #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ | |
90 | #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ | |
91 | ||
92 | #define _DRM_LOCK_HELD 0x80000000 /**< Hardware lock is held */ | |
93 | #define _DRM_LOCK_CONT 0x40000000 /**< Hardware lock is contended */ | |
94 | #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) | |
95 | #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) | |
96 | #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) | |
97 | ||
98 | ||
99 | typedef unsigned long drm_handle_t; | |
100 | typedef unsigned int drm_context_t; | |
101 | typedef unsigned int drm_drawable_t; | |
102 | typedef unsigned int drm_magic_t; | |
103 | ||
104 | ||
105 | /** | |
106 | * Cliprect. | |
107 | * | |
108 | * \warning: If you change this structure, make sure you change | |
109 | * XF86DRIClipRectRec in the server as well | |
110 | * | |
111 | * \note KW: Actually it's illegal to change either for | |
112 | * backwards-compatibility reasons. | |
113 | */ | |
114 | typedef struct drm_clip_rect { | |
115 | unsigned short x1; | |
116 | unsigned short y1; | |
117 | unsigned short x2; | |
118 | unsigned short y2; | |
119 | } drm_clip_rect_t; | |
120 | ||
121 | ||
122 | /** | |
123 | * Texture region, | |
124 | */ | |
125 | typedef struct drm_tex_region { | |
126 | unsigned char next; | |
127 | unsigned char prev; | |
128 | unsigned char in_use; | |
129 | unsigned char padding; | |
130 | unsigned int age; | |
131 | } drm_tex_region_t; | |
132 | ||
133 | /** | |
134 | * Hardware lock. | |
135 | * | |
136 | * The lock structure is a simple cache-line aligned integer. To avoid | |
137 | * processor bus contention on a multiprocessor system, there should not be any | |
138 | * other data stored in the same cache line. | |
139 | */ | |
140 | typedef struct drm_hw_lock { | |
141 | __volatile__ unsigned int lock; /**< lock variable */ | |
142 | char padding[60]; /**< Pad to cache line */ | |
143 | } drm_hw_lock_t; | |
144 | ||
145 | ||
146 | /** | |
147 | * DRM_IOCTL_VERSION ioctl argument type. | |
148 | * | |
149 | * \sa drmGetVersion(). | |
150 | */ | |
151 | typedef struct drm_version { | |
152 | int version_major; /**< Major version */ | |
153 | int version_minor; /**< Minor version */ | |
154 | int version_patchlevel;/**< Patch level */ | |
155 | size_t name_len; /**< Length of name buffer */ | |
156 | char __user *name; /**< Name of driver */ | |
157 | size_t date_len; /**< Length of date buffer */ | |
158 | char __user *date; /**< User-space buffer to hold date */ | |
159 | size_t desc_len; /**< Length of desc buffer */ | |
160 | char __user *desc; /**< User-space buffer to hold desc */ | |
161 | } drm_version_t; | |
162 | ||
163 | ||
164 | /** | |
165 | * DRM_IOCTL_GET_UNIQUE ioctl argument type. | |
166 | * | |
167 | * \sa drmGetBusid() and drmSetBusId(). | |
168 | */ | |
169 | typedef struct drm_unique { | |
170 | size_t unique_len; /**< Length of unique */ | |
171 | char __user *unique; /**< Unique name for driver instantiation */ | |
172 | } drm_unique_t; | |
173 | ||
174 | ||
175 | typedef struct drm_list { | |
176 | int count; /**< Length of user-space structures */ | |
177 | drm_version_t __user *version; | |
178 | } drm_list_t; | |
179 | ||
180 | ||
181 | typedef struct drm_block { | |
182 | int unused; | |
183 | } drm_block_t; | |
184 | ||
185 | ||
186 | /** | |
187 | * DRM_IOCTL_CONTROL ioctl argument type. | |
188 | * | |
189 | * \sa drmCtlInstHandler() and drmCtlUninstHandler(). | |
190 | */ | |
191 | typedef struct drm_control { | |
192 | enum { | |
193 | DRM_ADD_COMMAND, | |
194 | DRM_RM_COMMAND, | |
195 | DRM_INST_HANDLER, | |
196 | DRM_UNINST_HANDLER | |
197 | } func; | |
198 | int irq; | |
199 | } drm_control_t; | |
200 | ||
201 | ||
202 | /** | |
203 | * Type of memory to map. | |
204 | */ | |
205 | typedef enum drm_map_type { | |
206 | _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ | |
207 | _DRM_REGISTERS = 1, /**< no caching, no core dump */ | |
208 | _DRM_SHM = 2, /**< shared, cached */ | |
209 | _DRM_AGP = 3, /**< AGP/GART */ | |
210 | _DRM_SCATTER_GATHER = 4 /**< Scatter/gather memory for PCI DMA */ | |
211 | } drm_map_type_t; | |
212 | ||
213 | ||
214 | /** | |
215 | * Memory mapping flags. | |
216 | */ | |
217 | typedef enum drm_map_flags { | |
218 | _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ | |
219 | _DRM_READ_ONLY = 0x02, | |
220 | _DRM_LOCKED = 0x04, /**< shared, cached, locked */ | |
221 | _DRM_KERNEL = 0x08, /**< kernel requires access */ | |
222 | _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ | |
223 | _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ | |
224 | _DRM_REMOVABLE = 0x40 /**< Removable mapping */ | |
225 | } drm_map_flags_t; | |
226 | ||
227 | ||
228 | typedef struct drm_ctx_priv_map { | |
229 | unsigned int ctx_id; /**< Context requesting private mapping */ | |
230 | void *handle; /**< Handle of map */ | |
231 | } drm_ctx_priv_map_t; | |
232 | ||
233 | ||
234 | /** | |
235 | * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls | |
236 | * argument type. | |
237 | * | |
238 | * \sa drmAddMap(). | |
239 | */ | |
240 | typedef struct drm_map { | |
241 | unsigned long offset; /**< Requested physical address (0 for SAREA)*/ | |
242 | unsigned long size; /**< Requested physical size (bytes) */ | |
243 | drm_map_type_t type; /**< Type of memory to map */ | |
244 | drm_map_flags_t flags; /**< Flags */ | |
245 | void *handle; /**< User-space: "Handle" to pass to mmap() */ | |
246 | /**< Kernel-space: kernel-virtual address */ | |
247 | int mtrr; /**< MTRR slot used */ | |
248 | /* Private data */ | |
249 | } drm_map_t; | |
250 | ||
251 | ||
252 | /** | |
253 | * DRM_IOCTL_GET_CLIENT ioctl argument type. | |
254 | */ | |
255 | typedef struct drm_client { | |
256 | int idx; /**< Which client desired? */ | |
257 | int auth; /**< Is client authenticated? */ | |
258 | unsigned long pid; /**< Process ID */ | |
259 | unsigned long uid; /**< User ID */ | |
260 | unsigned long magic; /**< Magic */ | |
261 | unsigned long iocs; /**< Ioctl count */ | |
262 | } drm_client_t; | |
263 | ||
264 | ||
265 | typedef enum { | |
266 | _DRM_STAT_LOCK, | |
267 | _DRM_STAT_OPENS, | |
268 | _DRM_STAT_CLOSES, | |
269 | _DRM_STAT_IOCTLS, | |
270 | _DRM_STAT_LOCKS, | |
271 | _DRM_STAT_UNLOCKS, | |
272 | _DRM_STAT_VALUE, /**< Generic value */ | |
273 | _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ | |
274 | _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ | |
275 | ||
276 | _DRM_STAT_IRQ, /**< IRQ */ | |
277 | _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ | |
278 | _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ | |
279 | _DRM_STAT_DMA, /**< DMA */ | |
280 | _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ | |
281 | _DRM_STAT_MISSED /**< Missed DMA opportunity */ | |
282 | ||
283 | /* Add to the *END* of the list */ | |
284 | } drm_stat_type_t; | |
285 | ||
286 | ||
287 | /** | |
288 | * DRM_IOCTL_GET_STATS ioctl argument type. | |
289 | */ | |
290 | typedef struct drm_stats { | |
291 | unsigned long count; | |
292 | struct { | |
293 | unsigned long value; | |
294 | drm_stat_type_t type; | |
295 | } data[15]; | |
296 | } drm_stats_t; | |
297 | ||
298 | ||
299 | /** | |
300 | * Hardware locking flags. | |
301 | */ | |
302 | typedef enum drm_lock_flags { | |
303 | _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ | |
304 | _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ | |
305 | _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ | |
306 | _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ | |
307 | /* These *HALT* flags aren't supported yet | |
308 | -- they will be used to support the | |
309 | full-screen DGA-like mode. */ | |
310 | _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ | |
311 | _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ | |
312 | } drm_lock_flags_t; | |
313 | ||
314 | ||
315 | /** | |
316 | * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. | |
317 | * | |
318 | * \sa drmGetLock() and drmUnlock(). | |
319 | */ | |
320 | typedef struct drm_lock { | |
321 | int context; | |
322 | drm_lock_flags_t flags; | |
323 | } drm_lock_t; | |
324 | ||
325 | ||
326 | /** | |
327 | * DMA flags | |
328 | * | |
329 | * \warning | |
330 | * These values \e must match xf86drm.h. | |
331 | * | |
332 | * \sa drm_dma. | |
333 | */ | |
334 | typedef enum drm_dma_flags { | |
335 | /* Flags for DMA buffer dispatch */ | |
336 | _DRM_DMA_BLOCK = 0x01, /**< | |
337 | * Block until buffer dispatched. | |
338 | * | |
339 | * \note The buffer may not yet have | |
340 | * been processed by the hardware -- | |
341 | * getting a hardware lock with the | |
342 | * hardware quiescent will ensure | |
343 | * that the buffer has been | |
344 | * processed. | |
345 | */ | |
346 | _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ | |
347 | _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ | |
348 | ||
349 | /* Flags for DMA buffer request */ | |
350 | _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ | |
351 | _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ | |
352 | _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ | |
353 | } drm_dma_flags_t; | |
354 | ||
355 | ||
356 | /** | |
357 | * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. | |
358 | * | |
359 | * \sa drmAddBufs(). | |
360 | */ | |
361 | typedef struct drm_buf_desc { | |
362 | int count; /**< Number of buffers of this size */ | |
363 | int size; /**< Size in bytes */ | |
364 | int low_mark; /**< Low water mark */ | |
365 | int high_mark; /**< High water mark */ | |
366 | enum { | |
367 | _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ | |
368 | _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ | |
369 | _DRM_SG_BUFFER = 0x04 /**< Scatter/gather memory buffer */ | |
370 | } flags; | |
371 | unsigned long agp_start; /**< | |
372 | * Start address of where the AGP buffers are | |
373 | * in the AGP aperture | |
374 | */ | |
375 | } drm_buf_desc_t; | |
376 | ||
377 | ||
378 | /** | |
379 | * DRM_IOCTL_INFO_BUFS ioctl argument type. | |
380 | */ | |
381 | typedef struct drm_buf_info { | |
382 | int count; /**< Entries in list */ | |
383 | drm_buf_desc_t __user *list; | |
384 | } drm_buf_info_t; | |
385 | ||
386 | ||
387 | /** | |
388 | * DRM_IOCTL_FREE_BUFS ioctl argument type. | |
389 | */ | |
390 | typedef struct drm_buf_free { | |
391 | int count; | |
392 | int __user *list; | |
393 | } drm_buf_free_t; | |
394 | ||
395 | ||
396 | /** | |
397 | * Buffer information | |
398 | * | |
399 | * \sa drm_buf_map. | |
400 | */ | |
401 | typedef struct drm_buf_pub { | |
402 | int idx; /**< Index into the master buffer list */ | |
403 | int total; /**< Buffer size */ | |
404 | int used; /**< Amount of buffer in use (for DMA) */ | |
405 | void __user *address; /**< Address of buffer */ | |
406 | } drm_buf_pub_t; | |
407 | ||
408 | ||
409 | /** | |
410 | * DRM_IOCTL_MAP_BUFS ioctl argument type. | |
411 | */ | |
412 | typedef struct drm_buf_map { | |
413 | int count; /**< Length of the buffer list */ | |
414 | void __user *virtual; /**< Mmap'd area in user-virtual */ | |
415 | drm_buf_pub_t __user *list; /**< Buffer information */ | |
416 | } drm_buf_map_t; | |
417 | ||
418 | ||
419 | /** | |
420 | * DRM_IOCTL_DMA ioctl argument type. | |
421 | * | |
422 | * Indices here refer to the offset into the buffer list in drm_buf_get. | |
423 | * | |
424 | * \sa drmDMA(). | |
425 | */ | |
426 | typedef struct drm_dma { | |
427 | int context; /**< Context handle */ | |
428 | int send_count; /**< Number of buffers to send */ | |
429 | int __user *send_indices; /**< List of handles to buffers */ | |
430 | int __user *send_sizes; /**< Lengths of data to send */ | |
431 | drm_dma_flags_t flags; /**< Flags */ | |
432 | int request_count; /**< Number of buffers requested */ | |
433 | int request_size; /**< Desired size for buffers */ | |
434 | int __user *request_indices; /**< Buffer information */ | |
435 | int __user *request_sizes; | |
436 | int granted_count; /**< Number of buffers granted */ | |
437 | } drm_dma_t; | |
438 | ||
439 | ||
440 | typedef enum { | |
441 | _DRM_CONTEXT_PRESERVED = 0x01, | |
442 | _DRM_CONTEXT_2DONLY = 0x02 | |
443 | } drm_ctx_flags_t; | |
444 | ||
445 | ||
446 | /** | |
447 | * DRM_IOCTL_ADD_CTX ioctl argument type. | |
448 | * | |
449 | * \sa drmCreateContext() and drmDestroyContext(). | |
450 | */ | |
451 | typedef struct drm_ctx { | |
452 | drm_context_t handle; | |
453 | drm_ctx_flags_t flags; | |
454 | } drm_ctx_t; | |
455 | ||
456 | ||
457 | /** | |
458 | * DRM_IOCTL_RES_CTX ioctl argument type. | |
459 | */ | |
460 | typedef struct drm_ctx_res { | |
461 | int count; | |
462 | drm_ctx_t __user *contexts; | |
463 | } drm_ctx_res_t; | |
464 | ||
465 | ||
466 | /** | |
467 | * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. | |
468 | */ | |
469 | typedef struct drm_draw { | |
470 | drm_drawable_t handle; | |
471 | } drm_draw_t; | |
472 | ||
473 | ||
474 | /** | |
475 | * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. | |
476 | */ | |
477 | typedef struct drm_auth { | |
478 | drm_magic_t magic; | |
479 | } drm_auth_t; | |
480 | ||
481 | ||
482 | /** | |
483 | * DRM_IOCTL_IRQ_BUSID ioctl argument type. | |
484 | * | |
485 | * \sa drmGetInterruptFromBusID(). | |
486 | */ | |
487 | typedef struct drm_irq_busid { | |
488 | int irq; /**< IRQ number */ | |
489 | int busnum; /**< bus number */ | |
490 | int devnum; /**< device number */ | |
491 | int funcnum; /**< function number */ | |
492 | } drm_irq_busid_t; | |
493 | ||
494 | ||
495 | typedef enum { | |
496 | _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ | |
497 | _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ | |
498 | _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ | |
499 | } drm_vblank_seq_type_t; | |
500 | ||
501 | ||
502 | #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL | |
503 | ||
504 | ||
505 | struct drm_wait_vblank_request { | |
506 | drm_vblank_seq_type_t type; | |
507 | unsigned int sequence; | |
508 | unsigned long signal; | |
509 | }; | |
510 | ||
511 | ||
512 | struct drm_wait_vblank_reply { | |
513 | drm_vblank_seq_type_t type; | |
514 | unsigned int sequence; | |
515 | long tval_sec; | |
516 | long tval_usec; | |
517 | }; | |
518 | ||
519 | ||
520 | /** | |
521 | * DRM_IOCTL_WAIT_VBLANK ioctl argument type. | |
522 | * | |
523 | * \sa drmWaitVBlank(). | |
524 | */ | |
525 | typedef union drm_wait_vblank { | |
526 | struct drm_wait_vblank_request request; | |
527 | struct drm_wait_vblank_reply reply; | |
528 | } drm_wait_vblank_t; | |
529 | ||
530 | ||
531 | /** | |
532 | * DRM_IOCTL_AGP_ENABLE ioctl argument type. | |
533 | * | |
534 | * \sa drmAgpEnable(). | |
535 | */ | |
536 | typedef struct drm_agp_mode { | |
537 | unsigned long mode; /**< AGP mode */ | |
538 | } drm_agp_mode_t; | |
539 | ||
540 | ||
541 | /** | |
542 | * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. | |
543 | * | |
544 | * \sa drmAgpAlloc() and drmAgpFree(). | |
545 | */ | |
546 | typedef struct drm_agp_buffer { | |
547 | unsigned long size; /**< In bytes -- will round to page boundary */ | |
548 | unsigned long handle; /**< Used for binding / unbinding */ | |
549 | unsigned long type; /**< Type of memory to allocate */ | |
550 | unsigned long physical; /**< Physical used by i810 */ | |
551 | } drm_agp_buffer_t; | |
552 | ||
553 | ||
554 | /** | |
555 | * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. | |
556 | * | |
557 | * \sa drmAgpBind() and drmAgpUnbind(). | |
558 | */ | |
559 | typedef struct drm_agp_binding { | |
560 | unsigned long handle; /**< From drm_agp_buffer */ | |
561 | unsigned long offset; /**< In bytes -- will round to page boundary */ | |
562 | } drm_agp_binding_t; | |
563 | ||
564 | ||
565 | /** | |
566 | * DRM_IOCTL_AGP_INFO ioctl argument type. | |
567 | * | |
568 | * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), | |
569 | * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), | |
570 | * drmAgpVendorId() and drmAgpDeviceId(). | |
571 | */ | |
572 | typedef struct drm_agp_info { | |
573 | int agp_version_major; | |
574 | int agp_version_minor; | |
575 | unsigned long mode; | |
576 | unsigned long aperture_base; /* physical address */ | |
577 | unsigned long aperture_size; /* bytes */ | |
578 | unsigned long memory_allowed; /* bytes */ | |
579 | unsigned long memory_used; | |
580 | ||
581 | /* PCI information */ | |
582 | unsigned short id_vendor; | |
583 | unsigned short id_device; | |
584 | } drm_agp_info_t; | |
585 | ||
586 | ||
587 | /** | |
588 | * DRM_IOCTL_SG_ALLOC ioctl argument type. | |
589 | */ | |
590 | typedef struct drm_scatter_gather { | |
591 | unsigned long size; /**< In bytes -- will round to page boundary */ | |
592 | unsigned long handle; /**< Used for mapping / unmapping */ | |
593 | } drm_scatter_gather_t; | |
594 | ||
595 | /** | |
596 | * DRM_IOCTL_SET_VERSION ioctl argument type. | |
597 | */ | |
598 | typedef struct drm_set_version { | |
599 | int drm_di_major; | |
600 | int drm_di_minor; | |
601 | int drm_dd_major; | |
602 | int drm_dd_minor; | |
603 | } drm_set_version_t; | |
604 | ||
605 | ||
606 | #define DRM_IOCTL_BASE 'd' | |
607 | #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) | |
608 | #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) | |
609 | #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) | |
610 | #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) | |
611 | ||
612 | #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) | |
613 | #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) | |
614 | #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) | |
615 | #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) | |
616 | #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t) | |
617 | #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t) | |
618 | #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t) | |
619 | #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t) | |
620 | ||
621 | #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) | |
622 | #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) | |
623 | #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) | |
624 | #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) | |
625 | #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) | |
626 | #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) | |
627 | #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) | |
628 | #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) | |
629 | #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) | |
630 | #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) | |
631 | #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) | |
632 | ||
633 | #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t) | |
634 | ||
635 | #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t) | |
636 | #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t) | |
637 | ||
638 | #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) | |
639 | #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) | |
640 | #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) | |
641 | #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) | |
642 | #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) | |
643 | #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) | |
644 | #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) | |
645 | #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) | |
646 | #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) | |
647 | #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) | |
648 | #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) | |
649 | #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) | |
650 | #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) | |
651 | ||
652 | #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) | |
653 | #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) | |
654 | #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) | |
655 | #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) | |
656 | #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) | |
657 | #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) | |
658 | #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) | |
659 | #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) | |
660 | ||
661 | #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) | |
662 | #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) | |
663 | ||
664 | #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) | |
665 | ||
666 | /** | |
667 | * Device specific ioctls should only be in their respective headers | |
668 | * The device specific ioctl range is from 0x40 to 0x79. | |
669 | * | |
670 | * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and | |
671 | * drmCommandReadWrite(). | |
672 | */ | |
673 | #define DRM_COMMAND_BASE 0x40 | |
674 | ||
675 | #endif |