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1da177e4 LT |
1 | /* i810_dma.c -- DMA support for the i810 -*- linux-c -*- |
2 | * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com | |
3 | * | |
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: Rickard E. (Rik) Faith <faith@valinux.com> | |
28 | * Jeff Hartmann <jhartmann@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | * | |
31 | */ | |
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "i810_drm.h" | |
36 | #include "i810_drv.h" | |
37 | #include <linux/interrupt.h> /* For task queue support */ | |
38 | #include <linux/delay.h> | |
39 | #include <linux/pagemap.h> | |
40 | ||
41 | #define I810_BUF_FREE 2 | |
42 | #define I810_BUF_CLIENT 1 | |
43 | #define I810_BUF_HARDWARE 0 | |
44 | ||
45 | #define I810_BUF_UNMAPPED 0 | |
46 | #define I810_BUF_MAPPED 1 | |
47 | ||
b5e89ed5 | 48 | static drm_buf_t *i810_freelist_get(drm_device_t * dev) |
1da177e4 | 49 | { |
b5e89ed5 DA |
50 | drm_device_dma_t *dma = dev->dma; |
51 | int i; | |
52 | int used; | |
1da177e4 LT |
53 | |
54 | /* Linear search might not be the best solution */ | |
55 | ||
b5e89ed5 DA |
56 | for (i = 0; i < dma->buf_count; i++) { |
57 | drm_buf_t *buf = dma->buflist[i]; | |
58 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1da177e4 | 59 | /* In use is already a pointer */ |
b5e89ed5 | 60 | used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, |
1da177e4 LT |
61 | I810_BUF_CLIENT); |
62 | if (used == I810_BUF_FREE) { | |
63 | return buf; | |
64 | } | |
65 | } | |
b5e89ed5 | 66 | return NULL; |
1da177e4 LT |
67 | } |
68 | ||
69 | /* This should only be called if the buffer is not sent to the hardware | |
70 | * yet, the hardware updates in use for us once its on the ring buffer. | |
71 | */ | |
72 | ||
b5e89ed5 | 73 | static int i810_freelist_put(drm_device_t * dev, drm_buf_t * buf) |
1da177e4 | 74 | { |
b5e89ed5 DA |
75 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; |
76 | int used; | |
1da177e4 | 77 | |
b5e89ed5 DA |
78 | /* In use is already a pointer */ |
79 | used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); | |
1da177e4 | 80 | if (used != I810_BUF_CLIENT) { |
b5e89ed5 DA |
81 | DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); |
82 | return -EINVAL; | |
1da177e4 LT |
83 | } |
84 | ||
b5e89ed5 | 85 | return 0; |
1da177e4 LT |
86 | } |
87 | ||
c94f7029 | 88 | static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) |
1da177e4 | 89 | { |
b5e89ed5 DA |
90 | drm_file_t *priv = filp->private_data; |
91 | drm_device_t *dev; | |
92 | drm_i810_private_t *dev_priv; | |
93 | drm_buf_t *buf; | |
1da177e4 LT |
94 | drm_i810_buf_priv_t *buf_priv; |
95 | ||
96 | lock_kernel(); | |
b5e89ed5 | 97 | dev = priv->head->dev; |
1da177e4 | 98 | dev_priv = dev->dev_private; |
b5e89ed5 | 99 | buf = dev_priv->mmap_buffer; |
1da177e4 LT |
100 | buf_priv = buf->dev_private; |
101 | ||
102 | vma->vm_flags |= (VM_IO | VM_DONTCOPY); | |
103 | vma->vm_file = filp; | |
104 | ||
b5e89ed5 | 105 | buf_priv->currently_mapped = I810_BUF_MAPPED; |
1da177e4 LT |
106 | unlock_kernel(); |
107 | ||
108 | if (io_remap_pfn_range(vma, vma->vm_start, | |
3d77461e | 109 | vma->vm_pgoff, |
b5e89ed5 DA |
110 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
111 | return -EAGAIN; | |
1da177e4 LT |
112 | return 0; |
113 | } | |
114 | ||
c94f7029 | 115 | static struct file_operations i810_buffer_fops = { |
b5e89ed5 | 116 | .open = drm_open, |
c94f7029 | 117 | .release = drm_release, |
b5e89ed5 DA |
118 | .ioctl = drm_ioctl, |
119 | .mmap = i810_mmap_buffers, | |
120 | .fasync = drm_fasync, | |
c94f7029 DA |
121 | }; |
122 | ||
b5e89ed5 | 123 | static int i810_map_buffer(drm_buf_t * buf, struct file *filp) |
1da177e4 | 124 | { |
b5e89ed5 DA |
125 | drm_file_t *priv = filp->private_data; |
126 | drm_device_t *dev = priv->head->dev; | |
1da177e4 | 127 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; |
b5e89ed5 | 128 | drm_i810_private_t *dev_priv = dev->dev_private; |
99ac48f5 | 129 | const struct file_operations *old_fops; |
1da177e4 LT |
130 | int retcode = 0; |
131 | ||
b5e89ed5 | 132 | if (buf_priv->currently_mapped == I810_BUF_MAPPED) |
1da177e4 LT |
133 | return -EINVAL; |
134 | ||
b5e89ed5 | 135 | down_write(¤t->mm->mmap_sem); |
1da177e4 LT |
136 | old_fops = filp->f_op; |
137 | filp->f_op = &i810_buffer_fops; | |
138 | dev_priv->mmap_buffer = buf; | |
139 | buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, | |
b5e89ed5 DA |
140 | PROT_READ | PROT_WRITE, |
141 | MAP_SHARED, buf->bus_address); | |
1da177e4 LT |
142 | dev_priv->mmap_buffer = NULL; |
143 | filp->f_op = old_fops; | |
144 | if ((unsigned long)buf_priv->virtual > -1024UL) { | |
145 | /* Real error */ | |
146 | DRM_ERROR("mmap error\n"); | |
147 | retcode = (signed int)buf_priv->virtual; | |
148 | buf_priv->virtual = NULL; | |
149 | } | |
b5e89ed5 | 150 | up_write(¤t->mm->mmap_sem); |
1da177e4 LT |
151 | |
152 | return retcode; | |
153 | } | |
154 | ||
b5e89ed5 | 155 | static int i810_unmap_buffer(drm_buf_t * buf) |
1da177e4 LT |
156 | { |
157 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
158 | int retcode = 0; | |
159 | ||
160 | if (buf_priv->currently_mapped != I810_BUF_MAPPED) | |
161 | return -EINVAL; | |
162 | ||
163 | down_write(¤t->mm->mmap_sem); | |
164 | retcode = do_munmap(current->mm, | |
165 | (unsigned long)buf_priv->virtual, | |
166 | (size_t) buf->total); | |
167 | up_write(¤t->mm->mmap_sem); | |
168 | ||
b5e89ed5 DA |
169 | buf_priv->currently_mapped = I810_BUF_UNMAPPED; |
170 | buf_priv->virtual = NULL; | |
1da177e4 LT |
171 | |
172 | return retcode; | |
173 | } | |
174 | ||
b5e89ed5 | 175 | static int i810_dma_get_buffer(drm_device_t * dev, drm_i810_dma_t * d, |
1da177e4 LT |
176 | struct file *filp) |
177 | { | |
b5e89ed5 | 178 | drm_buf_t *buf; |
1da177e4 LT |
179 | drm_i810_buf_priv_t *buf_priv; |
180 | int retcode = 0; | |
181 | ||
182 | buf = i810_freelist_get(dev); | |
183 | if (!buf) { | |
184 | retcode = -ENOMEM; | |
b5e89ed5 | 185 | DRM_DEBUG("retcode=%d\n", retcode); |
1da177e4 LT |
186 | return retcode; |
187 | } | |
188 | ||
189 | retcode = i810_map_buffer(buf, filp); | |
190 | if (retcode) { | |
191 | i810_freelist_put(dev, buf); | |
b5e89ed5 | 192 | DRM_ERROR("mapbuf failed, retcode %d\n", retcode); |
1da177e4 LT |
193 | return retcode; |
194 | } | |
195 | buf->filp = filp; | |
196 | buf_priv = buf->dev_private; | |
197 | d->granted = 1; | |
b5e89ed5 DA |
198 | d->request_idx = buf->idx; |
199 | d->request_size = buf->total; | |
200 | d->virtual = buf_priv->virtual; | |
1da177e4 LT |
201 | |
202 | return retcode; | |
203 | } | |
204 | ||
b5e89ed5 | 205 | static int i810_dma_cleanup(drm_device_t * dev) |
1da177e4 LT |
206 | { |
207 | drm_device_dma_t *dma = dev->dma; | |
208 | ||
209 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
210 | * may not have been called from userspace and after dev_private | |
211 | * is freed, it's too late. | |
212 | */ | |
213 | if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled) | |
214 | drm_irq_uninstall(dev); | |
215 | ||
216 | if (dev->dev_private) { | |
217 | int i; | |
b5e89ed5 DA |
218 | drm_i810_private_t *dev_priv = |
219 | (drm_i810_private_t *) dev->dev_private; | |
1da177e4 LT |
220 | |
221 | if (dev_priv->ring.virtual_start) { | |
b5e89ed5 DA |
222 | drm_ioremapfree((void *)dev_priv->ring.virtual_start, |
223 | dev_priv->ring.Size, dev); | |
1da177e4 | 224 | } |
b5e89ed5 DA |
225 | if (dev_priv->hw_status_page) { |
226 | pci_free_consistent(dev->pdev, PAGE_SIZE, | |
1da177e4 LT |
227 | dev_priv->hw_status_page, |
228 | dev_priv->dma_status_page); | |
b5e89ed5 DA |
229 | /* Need to rewrite hardware status page */ |
230 | I810_WRITE(0x02080, 0x1ffff000); | |
1da177e4 | 231 | } |
b5e89ed5 | 232 | drm_free(dev->dev_private, sizeof(drm_i810_private_t), |
1da177e4 | 233 | DRM_MEM_DRIVER); |
b5e89ed5 | 234 | dev->dev_private = NULL; |
1da177e4 LT |
235 | |
236 | for (i = 0; i < dma->buf_count; i++) { | |
b5e89ed5 | 237 | drm_buf_t *buf = dma->buflist[i]; |
1da177e4 | 238 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; |
b5e89ed5 DA |
239 | if (buf_priv->kernel_virtual && buf->total) |
240 | drm_ioremapfree(buf_priv->kernel_virtual, | |
241 | buf->total, dev); | |
1da177e4 LT |
242 | } |
243 | } | |
b5e89ed5 | 244 | return 0; |
1da177e4 LT |
245 | } |
246 | ||
b5e89ed5 | 247 | static int i810_wait_ring(drm_device_t * dev, int n) |
1da177e4 | 248 | { |
b5e89ed5 DA |
249 | drm_i810_private_t *dev_priv = dev->dev_private; |
250 | drm_i810_ring_buffer_t *ring = &(dev_priv->ring); | |
251 | int iters = 0; | |
252 | unsigned long end; | |
1da177e4 LT |
253 | unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; |
254 | ||
b5e89ed5 DA |
255 | end = jiffies + (HZ * 3); |
256 | while (ring->space < n) { | |
257 | ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; | |
258 | ring->space = ring->head - (ring->tail + 8); | |
259 | if (ring->space < 0) | |
260 | ring->space += ring->Size; | |
261 | ||
1da177e4 | 262 | if (ring->head != last_head) { |
b5e89ed5 | 263 | end = jiffies + (HZ * 3); |
1da177e4 LT |
264 | last_head = ring->head; |
265 | } | |
b5e89ed5 DA |
266 | |
267 | iters++; | |
1da177e4 | 268 | if (time_before(end, jiffies)) { |
b5e89ed5 DA |
269 | DRM_ERROR("space: %d wanted %d\n", ring->space, n); |
270 | DRM_ERROR("lockup\n"); | |
271 | goto out_wait_ring; | |
1da177e4 LT |
272 | } |
273 | udelay(1); | |
274 | } | |
275 | ||
b5e89ed5 DA |
276 | out_wait_ring: |
277 | return iters; | |
1da177e4 LT |
278 | } |
279 | ||
b5e89ed5 | 280 | static void i810_kernel_lost_context(drm_device_t * dev) |
1da177e4 | 281 | { |
b5e89ed5 DA |
282 | drm_i810_private_t *dev_priv = dev->dev_private; |
283 | drm_i810_ring_buffer_t *ring = &(dev_priv->ring); | |
1da177e4 | 284 | |
b5e89ed5 DA |
285 | ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; |
286 | ring->tail = I810_READ(LP_RING + RING_TAIL); | |
287 | ring->space = ring->head - (ring->tail + 8); | |
288 | if (ring->space < 0) | |
289 | ring->space += ring->Size; | |
1da177e4 LT |
290 | } |
291 | ||
b5e89ed5 | 292 | static int i810_freelist_init(drm_device_t * dev, drm_i810_private_t * dev_priv) |
1da177e4 | 293 | { |
b5e89ed5 DA |
294 | drm_device_dma_t *dma = dev->dma; |
295 | int my_idx = 24; | |
296 | u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx); | |
297 | int i; | |
1da177e4 LT |
298 | |
299 | if (dma->buf_count > 1019) { | |
b5e89ed5 DA |
300 | /* Not enough space in the status page for the freelist */ |
301 | return -EINVAL; | |
1da177e4 LT |
302 | } |
303 | ||
b5e89ed5 DA |
304 | for (i = 0; i < dma->buf_count; i++) { |
305 | drm_buf_t *buf = dma->buflist[i]; | |
306 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1da177e4 | 307 | |
b5e89ed5 DA |
308 | buf_priv->in_use = hw_status++; |
309 | buf_priv->my_use_idx = my_idx; | |
310 | my_idx += 4; | |
1da177e4 | 311 | |
b5e89ed5 | 312 | *buf_priv->in_use = I810_BUF_FREE; |
1da177e4 LT |
313 | |
314 | buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, | |
b5e89ed5 | 315 | buf->total, dev); |
1da177e4 LT |
316 | } |
317 | return 0; | |
318 | } | |
319 | ||
b5e89ed5 DA |
320 | static int i810_dma_initialize(drm_device_t * dev, |
321 | drm_i810_private_t * dev_priv, | |
322 | drm_i810_init_t * init) | |
1da177e4 LT |
323 | { |
324 | struct list_head *list; | |
325 | ||
b5e89ed5 | 326 | memset(dev_priv, 0, sizeof(drm_i810_private_t)); |
1da177e4 LT |
327 | |
328 | list_for_each(list, &dev->maplist->head) { | |
329 | drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); | |
330 | if (r_list->map && | |
331 | r_list->map->type == _DRM_SHM && | |
b5e89ed5 | 332 | r_list->map->flags & _DRM_CONTAINS_LOCK) { |
1da177e4 | 333 | dev_priv->sarea_map = r_list->map; |
b5e89ed5 DA |
334 | break; |
335 | } | |
336 | } | |
1da177e4 LT |
337 | if (!dev_priv->sarea_map) { |
338 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 DA |
339 | i810_dma_cleanup(dev); |
340 | DRM_ERROR("can not find sarea!\n"); | |
341 | return -EINVAL; | |
1da177e4 LT |
342 | } |
343 | dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); | |
344 | if (!dev_priv->mmio_map) { | |
345 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 DA |
346 | i810_dma_cleanup(dev); |
347 | DRM_ERROR("can not find mmio map!\n"); | |
348 | return -EINVAL; | |
1da177e4 | 349 | } |
d1f2b55a | 350 | dev->agp_buffer_token = init->buffers_offset; |
1da177e4 LT |
351 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); |
352 | if (!dev->agp_buffer_map) { | |
353 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 DA |
354 | i810_dma_cleanup(dev); |
355 | DRM_ERROR("can not find dma buffer map!\n"); | |
356 | return -EINVAL; | |
1da177e4 LT |
357 | } |
358 | ||
359 | dev_priv->sarea_priv = (drm_i810_sarea_t *) | |
b5e89ed5 | 360 | ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset); |
1da177e4 | 361 | |
b5e89ed5 DA |
362 | dev_priv->ring.Start = init->ring_start; |
363 | dev_priv->ring.End = init->ring_end; | |
364 | dev_priv->ring.Size = init->ring_size; | |
1da177e4 | 365 | |
b5e89ed5 DA |
366 | dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + |
367 | init->ring_start, | |
368 | init->ring_size, dev); | |
1da177e4 | 369 | |
b5e89ed5 DA |
370 | if (dev_priv->ring.virtual_start == NULL) { |
371 | dev->dev_private = (void *)dev_priv; | |
372 | i810_dma_cleanup(dev); | |
373 | DRM_ERROR("can not ioremap virtual address for" | |
1da177e4 | 374 | " ring buffer\n"); |
b5e89ed5 | 375 | return -ENOMEM; |
1da177e4 LT |
376 | } |
377 | ||
b5e89ed5 | 378 | dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; |
1da177e4 LT |
379 | |
380 | dev_priv->w = init->w; | |
381 | dev_priv->h = init->h; | |
382 | dev_priv->pitch = init->pitch; | |
383 | dev_priv->back_offset = init->back_offset; | |
384 | dev_priv->depth_offset = init->depth_offset; | |
385 | dev_priv->front_offset = init->front_offset; | |
386 | ||
387 | dev_priv->overlay_offset = init->overlay_offset; | |
388 | dev_priv->overlay_physical = init->overlay_physical; | |
389 | ||
390 | dev_priv->front_di1 = init->front_offset | init->pitch_bits; | |
391 | dev_priv->back_di1 = init->back_offset | init->pitch_bits; | |
392 | dev_priv->zi1 = init->depth_offset | init->pitch_bits; | |
393 | ||
b5e89ed5 DA |
394 | /* Program Hardware Status Page */ |
395 | dev_priv->hw_status_page = | |
396 | pci_alloc_consistent(dev->pdev, PAGE_SIZE, | |
397 | &dev_priv->dma_status_page); | |
398 | if (!dev_priv->hw_status_page) { | |
1da177e4 LT |
399 | dev->dev_private = (void *)dev_priv; |
400 | i810_dma_cleanup(dev); | |
401 | DRM_ERROR("Can not allocate hardware status page\n"); | |
402 | return -ENOMEM; | |
403 | } | |
b5e89ed5 DA |
404 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
405 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | |
1da177e4 LT |
406 | |
407 | I810_WRITE(0x02080, dev_priv->dma_status_page); | |
b5e89ed5 | 408 | DRM_DEBUG("Enabled hardware status page\n"); |
1da177e4 | 409 | |
b5e89ed5 | 410 | /* Now we need to init our freelist */ |
1da177e4 LT |
411 | if (i810_freelist_init(dev, dev_priv) != 0) { |
412 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 DA |
413 | i810_dma_cleanup(dev); |
414 | DRM_ERROR("Not enough space in the status page for" | |
1da177e4 | 415 | " the freelist\n"); |
b5e89ed5 | 416 | return -ENOMEM; |
1da177e4 LT |
417 | } |
418 | dev->dev_private = (void *)dev_priv; | |
419 | ||
b5e89ed5 | 420 | return 0; |
1da177e4 LT |
421 | } |
422 | ||
423 | /* i810 DRM version 1.1 used a smaller init structure with different | |
424 | * ordering of values than is currently used (drm >= 1.2). There is | |
425 | * no defined way to detect the XFree version to correct this problem, | |
426 | * however by checking using this procedure we can detect the correct | |
427 | * thing to do. | |
428 | * | |
429 | * #1 Read the Smaller init structure from user-space | |
430 | * #2 Verify the overlay_physical is a valid physical address, or NULL | |
431 | * If it isn't then we have a v1.1 client. Fix up params. | |
432 | * If it is, then we have a 1.2 client... get the rest of the data. | |
433 | */ | |
b5e89ed5 | 434 | static int i810_dma_init_compat(drm_i810_init_t * init, unsigned long arg) |
1da177e4 LT |
435 | { |
436 | ||
437 | /* Get v1.1 init data */ | |
b5e89ed5 DA |
438 | if (copy_from_user(init, (drm_i810_pre12_init_t __user *) arg, |
439 | sizeof(drm_i810_pre12_init_t))) { | |
1da177e4 LT |
440 | return -EFAULT; |
441 | } | |
442 | ||
443 | if ((!init->overlay_physical) || (init->overlay_physical > 4096)) { | |
444 | ||
445 | /* This is a v1.2 client, just get the v1.2 init data */ | |
446 | DRM_INFO("Using POST v1.2 init.\n"); | |
b5e89ed5 | 447 | if (copy_from_user(init, (drm_i810_init_t __user *) arg, |
1da177e4 LT |
448 | sizeof(drm_i810_init_t))) { |
449 | return -EFAULT; | |
450 | } | |
451 | } else { | |
452 | ||
453 | /* This is a v1.1 client, fix the params */ | |
454 | DRM_INFO("Using PRE v1.2 init.\n"); | |
b5e89ed5 DA |
455 | init->pitch_bits = init->h; |
456 | init->pitch = init->w; | |
457 | init->h = init->overlay_physical; | |
458 | init->w = init->overlay_offset; | |
459 | init->overlay_physical = 0; | |
460 | init->overlay_offset = 0; | |
1da177e4 LT |
461 | } |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static int i810_dma_init(struct inode *inode, struct file *filp, | |
b5e89ed5 | 467 | unsigned int cmd, unsigned long arg) |
1da177e4 | 468 | { |
b5e89ed5 DA |
469 | drm_file_t *priv = filp->private_data; |
470 | drm_device_t *dev = priv->head->dev; | |
471 | drm_i810_private_t *dev_priv; | |
472 | drm_i810_init_t init; | |
473 | int retcode = 0; | |
1da177e4 LT |
474 | |
475 | /* Get only the init func */ | |
b5e89ed5 DA |
476 | if (copy_from_user |
477 | (&init, (void __user *)arg, sizeof(drm_i810_init_func_t))) | |
1da177e4 LT |
478 | return -EFAULT; |
479 | ||
b5e89ed5 DA |
480 | switch (init.func) { |
481 | case I810_INIT_DMA: | |
482 | /* This case is for backward compatibility. It | |
483 | * handles XFree 4.1.0 and 4.2.0, and has to | |
484 | * do some parameter checking as described below. | |
485 | * It will someday go away. | |
486 | */ | |
487 | retcode = i810_dma_init_compat(&init, arg); | |
488 | if (retcode) | |
489 | return retcode; | |
490 | ||
491 | dev_priv = drm_alloc(sizeof(drm_i810_private_t), | |
492 | DRM_MEM_DRIVER); | |
493 | if (dev_priv == NULL) | |
494 | return -ENOMEM; | |
495 | retcode = i810_dma_initialize(dev, dev_priv, &init); | |
496 | break; | |
497 | ||
498 | default: | |
499 | case I810_INIT_DMA_1_4: | |
500 | DRM_INFO("Using v1.4 init.\n"); | |
501 | if (copy_from_user(&init, (drm_i810_init_t __user *) arg, | |
502 | sizeof(drm_i810_init_t))) { | |
503 | return -EFAULT; | |
504 | } | |
505 | dev_priv = drm_alloc(sizeof(drm_i810_private_t), | |
506 | DRM_MEM_DRIVER); | |
507 | if (dev_priv == NULL) | |
508 | return -ENOMEM; | |
509 | retcode = i810_dma_initialize(dev, dev_priv, &init); | |
510 | break; | |
511 | ||
512 | case I810_CLEANUP_DMA: | |
513 | DRM_INFO("DMA Cleanup\n"); | |
514 | retcode = i810_dma_cleanup(dev); | |
515 | break; | |
1da177e4 LT |
516 | } |
517 | ||
b5e89ed5 | 518 | return retcode; |
1da177e4 LT |
519 | } |
520 | ||
1da177e4 LT |
521 | /* Most efficient way to verify state for the i810 is as it is |
522 | * emitted. Non-conformant state is silently dropped. | |
523 | * | |
524 | * Use 'volatile' & local var tmp to force the emitted values to be | |
525 | * identical to the verified ones. | |
526 | */ | |
b5e89ed5 DA |
527 | static void i810EmitContextVerified(drm_device_t * dev, |
528 | volatile unsigned int *code) | |
1da177e4 | 529 | { |
b5e89ed5 | 530 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
531 | int i, j = 0; |
532 | unsigned int tmp; | |
533 | RING_LOCALS; | |
534 | ||
b5e89ed5 | 535 | BEGIN_LP_RING(I810_CTX_SETUP_SIZE); |
1da177e4 | 536 | |
b5e89ed5 DA |
537 | OUT_RING(GFX_OP_COLOR_FACTOR); |
538 | OUT_RING(code[I810_CTXREG_CF1]); | |
1da177e4 | 539 | |
b5e89ed5 DA |
540 | OUT_RING(GFX_OP_STIPPLE); |
541 | OUT_RING(code[I810_CTXREG_ST1]); | |
1da177e4 | 542 | |
b5e89ed5 | 543 | for (i = 4; i < I810_CTX_SETUP_SIZE; i++) { |
1da177e4 LT |
544 | tmp = code[i]; |
545 | ||
b5e89ed5 DA |
546 | if ((tmp & (7 << 29)) == (3 << 29) && |
547 | (tmp & (0x1f << 24)) < (0x1d << 24)) { | |
548 | OUT_RING(tmp); | |
1da177e4 | 549 | j++; |
b5e89ed5 DA |
550 | } else |
551 | printk("constext state dropped!!!\n"); | |
1da177e4 LT |
552 | } |
553 | ||
554 | if (j & 1) | |
b5e89ed5 | 555 | OUT_RING(0); |
1da177e4 LT |
556 | |
557 | ADVANCE_LP_RING(); | |
558 | } | |
559 | ||
b5e89ed5 | 560 | static void i810EmitTexVerified(drm_device_t * dev, volatile unsigned int *code) |
1da177e4 | 561 | { |
b5e89ed5 | 562 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
563 | int i, j = 0; |
564 | unsigned int tmp; | |
565 | RING_LOCALS; | |
566 | ||
b5e89ed5 | 567 | BEGIN_LP_RING(I810_TEX_SETUP_SIZE); |
1da177e4 | 568 | |
b5e89ed5 DA |
569 | OUT_RING(GFX_OP_MAP_INFO); |
570 | OUT_RING(code[I810_TEXREG_MI1]); | |
571 | OUT_RING(code[I810_TEXREG_MI2]); | |
572 | OUT_RING(code[I810_TEXREG_MI3]); | |
1da177e4 | 573 | |
b5e89ed5 | 574 | for (i = 4; i < I810_TEX_SETUP_SIZE; i++) { |
1da177e4 LT |
575 | tmp = code[i]; |
576 | ||
b5e89ed5 DA |
577 | if ((tmp & (7 << 29)) == (3 << 29) && |
578 | (tmp & (0x1f << 24)) < (0x1d << 24)) { | |
579 | OUT_RING(tmp); | |
1da177e4 | 580 | j++; |
b5e89ed5 DA |
581 | } else |
582 | printk("texture state dropped!!!\n"); | |
1da177e4 LT |
583 | } |
584 | ||
585 | if (j & 1) | |
b5e89ed5 | 586 | OUT_RING(0); |
1da177e4 LT |
587 | |
588 | ADVANCE_LP_RING(); | |
589 | } | |
590 | ||
1da177e4 LT |
591 | /* Need to do some additional checking when setting the dest buffer. |
592 | */ | |
b5e89ed5 DA |
593 | static void i810EmitDestVerified(drm_device_t * dev, |
594 | volatile unsigned int *code) | |
1da177e4 | 595 | { |
b5e89ed5 | 596 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
597 | unsigned int tmp; |
598 | RING_LOCALS; | |
599 | ||
b5e89ed5 | 600 | BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2); |
1da177e4 LT |
601 | |
602 | tmp = code[I810_DESTREG_DI1]; | |
603 | if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { | |
b5e89ed5 DA |
604 | OUT_RING(CMD_OP_DESTBUFFER_INFO); |
605 | OUT_RING(tmp); | |
1da177e4 | 606 | } else |
b5e89ed5 DA |
607 | DRM_DEBUG("bad di1 %x (allow %x or %x)\n", |
608 | tmp, dev_priv->front_di1, dev_priv->back_di1); | |
1da177e4 LT |
609 | |
610 | /* invarient: | |
611 | */ | |
b5e89ed5 DA |
612 | OUT_RING(CMD_OP_Z_BUFFER_INFO); |
613 | OUT_RING(dev_priv->zi1); | |
1da177e4 | 614 | |
b5e89ed5 DA |
615 | OUT_RING(GFX_OP_DESTBUFFER_VARS); |
616 | OUT_RING(code[I810_DESTREG_DV1]); | |
1da177e4 | 617 | |
b5e89ed5 DA |
618 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
619 | OUT_RING(code[I810_DESTREG_DR1]); | |
620 | OUT_RING(code[I810_DESTREG_DR2]); | |
621 | OUT_RING(code[I810_DESTREG_DR3]); | |
622 | OUT_RING(code[I810_DESTREG_DR4]); | |
623 | OUT_RING(0); | |
1da177e4 LT |
624 | |
625 | ADVANCE_LP_RING(); | |
626 | } | |
627 | ||
b5e89ed5 | 628 | static void i810EmitState(drm_device_t * dev) |
1da177e4 | 629 | { |
b5e89ed5 DA |
630 | drm_i810_private_t *dev_priv = dev->dev_private; |
631 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1da177e4 | 632 | unsigned int dirty = sarea_priv->dirty; |
b5e89ed5 | 633 | |
1da177e4 LT |
634 | DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); |
635 | ||
636 | if (dirty & I810_UPLOAD_BUFFERS) { | |
b5e89ed5 | 637 | i810EmitDestVerified(dev, sarea_priv->BufferState); |
1da177e4 LT |
638 | sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; |
639 | } | |
640 | ||
641 | if (dirty & I810_UPLOAD_CTX) { | |
b5e89ed5 | 642 | i810EmitContextVerified(dev, sarea_priv->ContextState); |
1da177e4 LT |
643 | sarea_priv->dirty &= ~I810_UPLOAD_CTX; |
644 | } | |
645 | ||
646 | if (dirty & I810_UPLOAD_TEX0) { | |
b5e89ed5 | 647 | i810EmitTexVerified(dev, sarea_priv->TexState[0]); |
1da177e4 LT |
648 | sarea_priv->dirty &= ~I810_UPLOAD_TEX0; |
649 | } | |
650 | ||
651 | if (dirty & I810_UPLOAD_TEX1) { | |
b5e89ed5 | 652 | i810EmitTexVerified(dev, sarea_priv->TexState[1]); |
1da177e4 LT |
653 | sarea_priv->dirty &= ~I810_UPLOAD_TEX1; |
654 | } | |
655 | } | |
656 | ||
1da177e4 LT |
657 | /* need to verify |
658 | */ | |
b5e89ed5 DA |
659 | static void i810_dma_dispatch_clear(drm_device_t * dev, int flags, |
660 | unsigned int clear_color, | |
661 | unsigned int clear_zval) | |
1da177e4 | 662 | { |
b5e89ed5 DA |
663 | drm_i810_private_t *dev_priv = dev->dev_private; |
664 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1da177e4 LT |
665 | int nbox = sarea_priv->nbox; |
666 | drm_clip_rect_t *pbox = sarea_priv->boxes; | |
667 | int pitch = dev_priv->pitch; | |
668 | int cpp = 2; | |
669 | int i; | |
670 | RING_LOCALS; | |
b5e89ed5 DA |
671 | |
672 | if (dev_priv->current_page == 1) { | |
673 | unsigned int tmp = flags; | |
674 | ||
1da177e4 | 675 | flags &= ~(I810_FRONT | I810_BACK); |
b5e89ed5 DA |
676 | if (tmp & I810_FRONT) |
677 | flags |= I810_BACK; | |
678 | if (tmp & I810_BACK) | |
679 | flags |= I810_FRONT; | |
1da177e4 LT |
680 | } |
681 | ||
b5e89ed5 | 682 | i810_kernel_lost_context(dev); |
1da177e4 | 683 | |
b5e89ed5 DA |
684 | if (nbox > I810_NR_SAREA_CLIPRECTS) |
685 | nbox = I810_NR_SAREA_CLIPRECTS; | |
1da177e4 | 686 | |
b5e89ed5 | 687 | for (i = 0; i < nbox; i++, pbox++) { |
1da177e4 LT |
688 | unsigned int x = pbox->x1; |
689 | unsigned int y = pbox->y1; | |
690 | unsigned int width = (pbox->x2 - x) * cpp; | |
691 | unsigned int height = pbox->y2 - y; | |
692 | unsigned int start = y * pitch + x * cpp; | |
693 | ||
694 | if (pbox->x1 > pbox->x2 || | |
695 | pbox->y1 > pbox->y2 || | |
b5e89ed5 | 696 | pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) |
1da177e4 LT |
697 | continue; |
698 | ||
b5e89ed5 DA |
699 | if (flags & I810_FRONT) { |
700 | BEGIN_LP_RING(6); | |
701 | OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); | |
702 | OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); | |
703 | OUT_RING((height << 16) | width); | |
704 | OUT_RING(start); | |
705 | OUT_RING(clear_color); | |
706 | OUT_RING(0); | |
1da177e4 LT |
707 | ADVANCE_LP_RING(); |
708 | } | |
709 | ||
b5e89ed5 DA |
710 | if (flags & I810_BACK) { |
711 | BEGIN_LP_RING(6); | |
712 | OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); | |
713 | OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); | |
714 | OUT_RING((height << 16) | width); | |
715 | OUT_RING(dev_priv->back_offset + start); | |
716 | OUT_RING(clear_color); | |
717 | OUT_RING(0); | |
1da177e4 LT |
718 | ADVANCE_LP_RING(); |
719 | } | |
720 | ||
b5e89ed5 DA |
721 | if (flags & I810_DEPTH) { |
722 | BEGIN_LP_RING(6); | |
723 | OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); | |
724 | OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); | |
725 | OUT_RING((height << 16) | width); | |
726 | OUT_RING(dev_priv->depth_offset + start); | |
727 | OUT_RING(clear_zval); | |
728 | OUT_RING(0); | |
1da177e4 LT |
729 | ADVANCE_LP_RING(); |
730 | } | |
731 | } | |
732 | } | |
733 | ||
b5e89ed5 | 734 | static void i810_dma_dispatch_swap(drm_device_t * dev) |
1da177e4 | 735 | { |
b5e89ed5 DA |
736 | drm_i810_private_t *dev_priv = dev->dev_private; |
737 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1da177e4 LT |
738 | int nbox = sarea_priv->nbox; |
739 | drm_clip_rect_t *pbox = sarea_priv->boxes; | |
740 | int pitch = dev_priv->pitch; | |
741 | int cpp = 2; | |
742 | int i; | |
743 | RING_LOCALS; | |
744 | ||
745 | DRM_DEBUG("swapbuffers\n"); | |
746 | ||
b5e89ed5 | 747 | i810_kernel_lost_context(dev); |
1da177e4 | 748 | |
b5e89ed5 DA |
749 | if (nbox > I810_NR_SAREA_CLIPRECTS) |
750 | nbox = I810_NR_SAREA_CLIPRECTS; | |
1da177e4 | 751 | |
b5e89ed5 | 752 | for (i = 0; i < nbox; i++, pbox++) { |
1da177e4 LT |
753 | unsigned int w = pbox->x2 - pbox->x1; |
754 | unsigned int h = pbox->y2 - pbox->y1; | |
b5e89ed5 | 755 | unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch; |
1da177e4 LT |
756 | unsigned int start = dst; |
757 | ||
758 | if (pbox->x1 > pbox->x2 || | |
759 | pbox->y1 > pbox->y2 || | |
b5e89ed5 | 760 | pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) |
1da177e4 LT |
761 | continue; |
762 | ||
b5e89ed5 DA |
763 | BEGIN_LP_RING(6); |
764 | OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4); | |
765 | OUT_RING(pitch | (0xCC << 16)); | |
766 | OUT_RING((h << 16) | (w * cpp)); | |
1da177e4 | 767 | if (dev_priv->current_page == 0) |
b5e89ed5 | 768 | OUT_RING(dev_priv->front_offset + start); |
1da177e4 | 769 | else |
b5e89ed5 DA |
770 | OUT_RING(dev_priv->back_offset + start); |
771 | OUT_RING(pitch); | |
1da177e4 | 772 | if (dev_priv->current_page == 0) |
b5e89ed5 | 773 | OUT_RING(dev_priv->back_offset + start); |
1da177e4 | 774 | else |
b5e89ed5 | 775 | OUT_RING(dev_priv->front_offset + start); |
1da177e4 LT |
776 | ADVANCE_LP_RING(); |
777 | } | |
778 | } | |
779 | ||
b5e89ed5 DA |
780 | static void i810_dma_dispatch_vertex(drm_device_t * dev, |
781 | drm_buf_t * buf, int discard, int used) | |
1da177e4 | 782 | { |
b5e89ed5 | 783 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 | 784 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; |
b5e89ed5 DA |
785 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; |
786 | drm_clip_rect_t *box = sarea_priv->boxes; | |
787 | int nbox = sarea_priv->nbox; | |
1da177e4 LT |
788 | unsigned long address = (unsigned long)buf->bus_address; |
789 | unsigned long start = address - dev->agp->base; | |
790 | int i = 0; | |
b5e89ed5 | 791 | RING_LOCALS; |
1da177e4 | 792 | |
b5e89ed5 | 793 | i810_kernel_lost_context(dev); |
1da177e4 | 794 | |
b5e89ed5 | 795 | if (nbox > I810_NR_SAREA_CLIPRECTS) |
1da177e4 LT |
796 | nbox = I810_NR_SAREA_CLIPRECTS; |
797 | ||
b5e89ed5 | 798 | if (used > 4 * 1024) |
1da177e4 LT |
799 | used = 0; |
800 | ||
801 | if (sarea_priv->dirty) | |
b5e89ed5 | 802 | i810EmitState(dev); |
1da177e4 LT |
803 | |
804 | if (buf_priv->currently_mapped == I810_BUF_MAPPED) { | |
805 | unsigned int prim = (sarea_priv->vertex_prim & PR_MASK); | |
806 | ||
b5e89ed5 DA |
807 | *(u32 *) buf_priv->kernel_virtual = |
808 | ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2))); | |
1da177e4 LT |
809 | |
810 | if (used & 4) { | |
b5e89ed5 | 811 | *(u32 *) ((u32) buf_priv->kernel_virtual + used) = 0; |
1da177e4 LT |
812 | used += 4; |
813 | } | |
814 | ||
815 | i810_unmap_buffer(buf); | |
816 | } | |
817 | ||
818 | if (used) { | |
819 | do { | |
820 | if (i < nbox) { | |
821 | BEGIN_LP_RING(4); | |
b5e89ed5 DA |
822 | OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | |
823 | SC_ENABLE); | |
824 | OUT_RING(GFX_OP_SCISSOR_INFO); | |
825 | OUT_RING(box[i].x1 | (box[i].y1 << 16)); | |
826 | OUT_RING((box[i].x2 - | |
827 | 1) | ((box[i].y2 - 1) << 16)); | |
1da177e4 LT |
828 | ADVANCE_LP_RING(); |
829 | } | |
830 | ||
831 | BEGIN_LP_RING(4); | |
b5e89ed5 DA |
832 | OUT_RING(CMD_OP_BATCH_BUFFER); |
833 | OUT_RING(start | BB1_PROTECTED); | |
834 | OUT_RING(start + used - 4); | |
835 | OUT_RING(0); | |
1da177e4 LT |
836 | ADVANCE_LP_RING(); |
837 | ||
838 | } while (++i < nbox); | |
839 | } | |
840 | ||
841 | if (discard) { | |
842 | dev_priv->counter++; | |
843 | ||
b5e89ed5 DA |
844 | (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, |
845 | I810_BUF_HARDWARE); | |
1da177e4 LT |
846 | |
847 | BEGIN_LP_RING(8); | |
b5e89ed5 DA |
848 | OUT_RING(CMD_STORE_DWORD_IDX); |
849 | OUT_RING(20); | |
850 | OUT_RING(dev_priv->counter); | |
851 | OUT_RING(CMD_STORE_DWORD_IDX); | |
852 | OUT_RING(buf_priv->my_use_idx); | |
853 | OUT_RING(I810_BUF_FREE); | |
854 | OUT_RING(CMD_REPORT_HEAD); | |
855 | OUT_RING(0); | |
1da177e4 LT |
856 | ADVANCE_LP_RING(); |
857 | } | |
858 | } | |
859 | ||
b5e89ed5 | 860 | static void i810_dma_dispatch_flip(drm_device_t * dev) |
1da177e4 | 861 | { |
b5e89ed5 | 862 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
863 | int pitch = dev_priv->pitch; |
864 | RING_LOCALS; | |
865 | ||
b5e89ed5 DA |
866 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
867 | __FUNCTION__, | |
868 | dev_priv->current_page, | |
869 | dev_priv->sarea_priv->pf_current_page); | |
870 | ||
871 | i810_kernel_lost_context(dev); | |
1da177e4 | 872 | |
b5e89ed5 DA |
873 | BEGIN_LP_RING(2); |
874 | OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); | |
875 | OUT_RING(0); | |
1da177e4 LT |
876 | ADVANCE_LP_RING(); |
877 | ||
b5e89ed5 | 878 | BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2); |
1da177e4 LT |
879 | /* On i815 at least ASYNC is buggy */ |
880 | /* pitch<<5 is from 11.2.8 p158, | |
881 | its the pitch / 8 then left shifted 8, | |
882 | so (pitch >> 3) << 8 */ | |
b5e89ed5 DA |
883 | OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ ); |
884 | if (dev_priv->current_page == 0) { | |
885 | OUT_RING(dev_priv->back_offset); | |
1da177e4 LT |
886 | dev_priv->current_page = 1; |
887 | } else { | |
b5e89ed5 | 888 | OUT_RING(dev_priv->front_offset); |
1da177e4 LT |
889 | dev_priv->current_page = 0; |
890 | } | |
891 | OUT_RING(0); | |
892 | ADVANCE_LP_RING(); | |
893 | ||
894 | BEGIN_LP_RING(2); | |
b5e89ed5 DA |
895 | OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP); |
896 | OUT_RING(0); | |
1da177e4 LT |
897 | ADVANCE_LP_RING(); |
898 | ||
899 | /* Increment the frame counter. The client-side 3D driver must | |
900 | * throttle the framerate by waiting for this value before | |
901 | * performing the swapbuffer ioctl. | |
902 | */ | |
903 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
904 | ||
905 | } | |
906 | ||
b5e89ed5 | 907 | static void i810_dma_quiescent(drm_device_t * dev) |
1da177e4 | 908 | { |
b5e89ed5 DA |
909 | drm_i810_private_t *dev_priv = dev->dev_private; |
910 | RING_LOCALS; | |
1da177e4 LT |
911 | |
912 | /* printk("%s\n", __FUNCTION__); */ | |
913 | ||
b5e89ed5 | 914 | i810_kernel_lost_context(dev); |
1da177e4 | 915 | |
b5e89ed5 DA |
916 | BEGIN_LP_RING(4); |
917 | OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); | |
918 | OUT_RING(CMD_REPORT_HEAD); | |
919 | OUT_RING(0); | |
920 | OUT_RING(0); | |
921 | ADVANCE_LP_RING(); | |
1da177e4 | 922 | |
b5e89ed5 | 923 | i810_wait_ring(dev, dev_priv->ring.Size - 8); |
1da177e4 LT |
924 | } |
925 | ||
b5e89ed5 | 926 | static int i810_flush_queue(drm_device_t * dev) |
1da177e4 | 927 | { |
b5e89ed5 | 928 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 | 929 | drm_device_dma_t *dma = dev->dma; |
b5e89ed5 DA |
930 | int i, ret = 0; |
931 | RING_LOCALS; | |
932 | ||
1da177e4 LT |
933 | /* printk("%s\n", __FUNCTION__); */ |
934 | ||
b5e89ed5 | 935 | i810_kernel_lost_context(dev); |
1da177e4 | 936 | |
b5e89ed5 DA |
937 | BEGIN_LP_RING(2); |
938 | OUT_RING(CMD_REPORT_HEAD); | |
939 | OUT_RING(0); | |
940 | ADVANCE_LP_RING(); | |
1da177e4 | 941 | |
b5e89ed5 | 942 | i810_wait_ring(dev, dev_priv->ring.Size - 8); |
1da177e4 | 943 | |
b5e89ed5 DA |
944 | for (i = 0; i < dma->buf_count; i++) { |
945 | drm_buf_t *buf = dma->buflist[i]; | |
946 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1da177e4 LT |
947 | |
948 | int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE, | |
949 | I810_BUF_FREE); | |
950 | ||
951 | if (used == I810_BUF_HARDWARE) | |
952 | DRM_DEBUG("reclaimed from HARDWARE\n"); | |
953 | if (used == I810_BUF_CLIENT) | |
954 | DRM_DEBUG("still on client\n"); | |
955 | } | |
956 | ||
b5e89ed5 | 957 | return ret; |
1da177e4 LT |
958 | } |
959 | ||
960 | /* Must be called with the lock held */ | |
ce60fe02 | 961 | static void i810_reclaim_buffers(drm_device_t * dev, struct file *filp) |
1da177e4 LT |
962 | { |
963 | drm_device_dma_t *dma = dev->dma; | |
b5e89ed5 | 964 | int i; |
1da177e4 | 965 | |
b5e89ed5 DA |
966 | if (!dma) |
967 | return; | |
968 | if (!dev->dev_private) | |
969 | return; | |
970 | if (!dma->buflist) | |
971 | return; | |
1da177e4 | 972 | |
b5e89ed5 | 973 | i810_flush_queue(dev); |
1da177e4 LT |
974 | |
975 | for (i = 0; i < dma->buf_count; i++) { | |
b5e89ed5 DA |
976 | drm_buf_t *buf = dma->buflist[i]; |
977 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1da177e4 LT |
978 | |
979 | if (buf->filp == filp && buf_priv) { | |
980 | int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, | |
981 | I810_BUF_FREE); | |
982 | ||
983 | if (used == I810_BUF_CLIENT) | |
984 | DRM_DEBUG("reclaimed from client\n"); | |
985 | if (buf_priv->currently_mapped == I810_BUF_MAPPED) | |
b5e89ed5 | 986 | buf_priv->currently_mapped = I810_BUF_UNMAPPED; |
1da177e4 LT |
987 | } |
988 | } | |
989 | } | |
990 | ||
c94f7029 DA |
991 | static int i810_flush_ioctl(struct inode *inode, struct file *filp, |
992 | unsigned int cmd, unsigned long arg) | |
1da177e4 | 993 | { |
b5e89ed5 DA |
994 | drm_file_t *priv = filp->private_data; |
995 | drm_device_t *dev = priv->head->dev; | |
1da177e4 LT |
996 | |
997 | LOCK_TEST_WITH_RETURN(dev, filp); | |
998 | ||
b5e89ed5 DA |
999 | i810_flush_queue(dev); |
1000 | return 0; | |
1da177e4 LT |
1001 | } |
1002 | ||
1da177e4 | 1003 | static int i810_dma_vertex(struct inode *inode, struct file *filp, |
b5e89ed5 | 1004 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1005 | { |
1006 | drm_file_t *priv = filp->private_data; | |
1007 | drm_device_t *dev = priv->head->dev; | |
1008 | drm_device_dma_t *dma = dev->dma; | |
b5e89ed5 DA |
1009 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1010 | u32 *hw_status = dev_priv->hw_status_page; | |
1011 | drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) | |
1012 | dev_priv->sarea_priv; | |
1da177e4 LT |
1013 | drm_i810_vertex_t vertex; |
1014 | ||
b5e89ed5 DA |
1015 | if (copy_from_user |
1016 | (&vertex, (drm_i810_vertex_t __user *) arg, sizeof(vertex))) | |
1da177e4 LT |
1017 | return -EFAULT; |
1018 | ||
1019 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1020 | ||
1021 | DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n", | |
1022 | vertex.idx, vertex.used, vertex.discard); | |
1023 | ||
b5e89ed5 | 1024 | if (vertex.idx < 0 || vertex.idx > dma->buf_count) |
1da177e4 LT |
1025 | return -EINVAL; |
1026 | ||
b5e89ed5 DA |
1027 | i810_dma_dispatch_vertex(dev, |
1028 | dma->buflist[vertex.idx], | |
1029 | vertex.discard, vertex.used); | |
1da177e4 | 1030 | |
b5e89ed5 | 1031 | atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]); |
1da177e4 | 1032 | atomic_inc(&dev->counts[_DRM_STAT_DMA]); |
b5e89ed5 DA |
1033 | sarea_priv->last_enqueue = dev_priv->counter - 1; |
1034 | sarea_priv->last_dispatch = (int)hw_status[5]; | |
1da177e4 LT |
1035 | |
1036 | return 0; | |
1037 | } | |
1038 | ||
1da177e4 | 1039 | static int i810_clear_bufs(struct inode *inode, struct file *filp, |
b5e89ed5 | 1040 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1041 | { |
1042 | drm_file_t *priv = filp->private_data; | |
1043 | drm_device_t *dev = priv->head->dev; | |
1044 | drm_i810_clear_t clear; | |
1045 | ||
b5e89ed5 DA |
1046 | if (copy_from_user |
1047 | (&clear, (drm_i810_clear_t __user *) arg, sizeof(clear))) | |
1da177e4 LT |
1048 | return -EFAULT; |
1049 | ||
1050 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1051 | ||
b5e89ed5 DA |
1052 | /* GH: Someone's doing nasty things... */ |
1053 | if (!dev->dev_private) { | |
1054 | return -EINVAL; | |
1055 | } | |
1da177e4 | 1056 | |
b5e89ed5 DA |
1057 | i810_dma_dispatch_clear(dev, clear.flags, |
1058 | clear.clear_color, clear.clear_depth); | |
1059 | return 0; | |
1da177e4 LT |
1060 | } |
1061 | ||
1062 | static int i810_swap_bufs(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1063 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1064 | { |
1065 | drm_file_t *priv = filp->private_data; | |
1066 | drm_device_t *dev = priv->head->dev; | |
1067 | ||
1068 | DRM_DEBUG("i810_swap_bufs\n"); | |
1069 | ||
1070 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1071 | ||
b5e89ed5 DA |
1072 | i810_dma_dispatch_swap(dev); |
1073 | return 0; | |
1da177e4 LT |
1074 | } |
1075 | ||
1076 | static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, | |
b5e89ed5 | 1077 | unsigned long arg) |
1da177e4 | 1078 | { |
b5e89ed5 DA |
1079 | drm_file_t *priv = filp->private_data; |
1080 | drm_device_t *dev = priv->head->dev; | |
1081 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; | |
1082 | u32 *hw_status = dev_priv->hw_status_page; | |
1083 | drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) | |
1084 | dev_priv->sarea_priv; | |
1085 | ||
1086 | sarea_priv->last_dispatch = (int)hw_status[5]; | |
1da177e4 LT |
1087 | return 0; |
1088 | } | |
1089 | ||
1090 | static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, | |
b5e89ed5 | 1091 | unsigned long arg) |
1da177e4 | 1092 | { |
b5e89ed5 DA |
1093 | drm_file_t *priv = filp->private_data; |
1094 | drm_device_t *dev = priv->head->dev; | |
1095 | int retcode = 0; | |
1096 | drm_i810_dma_t d; | |
1097 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; | |
1098 | u32 *hw_status = dev_priv->hw_status_page; | |
1099 | drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) | |
1100 | dev_priv->sarea_priv; | |
1101 | ||
1102 | if (copy_from_user(&d, (drm_i810_dma_t __user *) arg, sizeof(d))) | |
1da177e4 LT |
1103 | return -EFAULT; |
1104 | ||
1105 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1106 | ||
1107 | d.granted = 0; | |
1108 | ||
1109 | retcode = i810_dma_get_buffer(dev, &d, filp); | |
1110 | ||
1111 | DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n", | |
1112 | current->pid, retcode, d.granted); | |
1113 | ||
b5e89ed5 | 1114 | if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d))) |
1da177e4 | 1115 | return -EFAULT; |
b5e89ed5 | 1116 | sarea_priv->last_dispatch = (int)hw_status[5]; |
1da177e4 LT |
1117 | |
1118 | return retcode; | |
1119 | } | |
1120 | ||
1121 | static int i810_copybuf(struct inode *inode, | |
b5e89ed5 | 1122 | struct file *filp, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1123 | { |
1124 | /* Never copy - 2.4.x doesn't need it */ | |
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd, | |
b5e89ed5 | 1129 | unsigned long arg) |
1da177e4 LT |
1130 | { |
1131 | /* Never copy - 2.4.x doesn't need it */ | |
1132 | return 0; | |
1133 | } | |
1134 | ||
b5e89ed5 DA |
1135 | static void i810_dma_dispatch_mc(drm_device_t * dev, drm_buf_t * buf, int used, |
1136 | unsigned int last_render) | |
1da177e4 LT |
1137 | { |
1138 | drm_i810_private_t *dev_priv = dev->dev_private; | |
1139 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1140 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1141 | unsigned long address = (unsigned long)buf->bus_address; | |
1142 | unsigned long start = address - dev->agp->base; | |
1143 | int u; | |
1144 | RING_LOCALS; | |
1145 | ||
1146 | i810_kernel_lost_context(dev); | |
1147 | ||
b5e89ed5 | 1148 | u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE); |
1da177e4 LT |
1149 | if (u != I810_BUF_CLIENT) { |
1150 | DRM_DEBUG("MC found buffer that isn't mine!\n"); | |
1151 | } | |
1152 | ||
b5e89ed5 | 1153 | if (used > 4 * 1024) |
1da177e4 LT |
1154 | used = 0; |
1155 | ||
1156 | sarea_priv->dirty = 0x7f; | |
1157 | ||
b5e89ed5 | 1158 | DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used); |
1da177e4 LT |
1159 | |
1160 | dev_priv->counter++; | |
1161 | DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); | |
1162 | DRM_DEBUG("i810_dma_dispatch_mc\n"); | |
1163 | DRM_DEBUG("start : %lx\n", start); | |
1164 | DRM_DEBUG("used : %d\n", used); | |
1165 | DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4); | |
1166 | ||
1167 | if (buf_priv->currently_mapped == I810_BUF_MAPPED) { | |
1168 | if (used & 4) { | |
b5e89ed5 | 1169 | *(u32 *) ((u32) buf_priv->virtual + used) = 0; |
1da177e4 LT |
1170 | used += 4; |
1171 | } | |
1172 | ||
1173 | i810_unmap_buffer(buf); | |
1174 | } | |
1175 | BEGIN_LP_RING(4); | |
b5e89ed5 DA |
1176 | OUT_RING(CMD_OP_BATCH_BUFFER); |
1177 | OUT_RING(start | BB1_PROTECTED); | |
1178 | OUT_RING(start + used - 4); | |
1179 | OUT_RING(0); | |
1da177e4 LT |
1180 | ADVANCE_LP_RING(); |
1181 | ||
1da177e4 | 1182 | BEGIN_LP_RING(8); |
b5e89ed5 DA |
1183 | OUT_RING(CMD_STORE_DWORD_IDX); |
1184 | OUT_RING(buf_priv->my_use_idx); | |
1185 | OUT_RING(I810_BUF_FREE); | |
1186 | OUT_RING(0); | |
1187 | ||
1188 | OUT_RING(CMD_STORE_DWORD_IDX); | |
1189 | OUT_RING(16); | |
1190 | OUT_RING(last_render); | |
1191 | OUT_RING(0); | |
1da177e4 LT |
1192 | ADVANCE_LP_RING(); |
1193 | } | |
1194 | ||
1195 | static int i810_dma_mc(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1196 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1197 | { |
1198 | drm_file_t *priv = filp->private_data; | |
1199 | drm_device_t *dev = priv->head->dev; | |
1200 | drm_device_dma_t *dma = dev->dma; | |
b5e89ed5 | 1201 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 LT |
1202 | u32 *hw_status = dev_priv->hw_status_page; |
1203 | drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) | |
b5e89ed5 | 1204 | dev_priv->sarea_priv; |
1da177e4 LT |
1205 | drm_i810_mc_t mc; |
1206 | ||
b5e89ed5 | 1207 | if (copy_from_user(&mc, (drm_i810_mc_t __user *) arg, sizeof(mc))) |
1da177e4 LT |
1208 | return -EFAULT; |
1209 | ||
1210 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1211 | ||
1212 | if (mc.idx >= dma->buf_count || mc.idx < 0) | |
1213 | return -EINVAL; | |
1214 | ||
1215 | i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used, | |
b5e89ed5 | 1216 | mc.last_render); |
1da177e4 LT |
1217 | |
1218 | atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]); | |
1219 | atomic_inc(&dev->counts[_DRM_STAT_DMA]); | |
b5e89ed5 DA |
1220 | sarea_priv->last_enqueue = dev_priv->counter - 1; |
1221 | sarea_priv->last_dispatch = (int)hw_status[5]; | |
1da177e4 LT |
1222 | |
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | static int i810_rstatus(struct inode *inode, struct file *filp, | |
1227 | unsigned int cmd, unsigned long arg) | |
1228 | { | |
1229 | drm_file_t *priv = filp->private_data; | |
1230 | drm_device_t *dev = priv->head->dev; | |
b5e89ed5 | 1231 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 | 1232 | |
b5e89ed5 | 1233 | return (int)(((u32 *) (dev_priv->hw_status_page))[4]); |
1da177e4 LT |
1234 | } |
1235 | ||
1236 | static int i810_ov0_info(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1237 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1238 | { |
1239 | drm_file_t *priv = filp->private_data; | |
1240 | drm_device_t *dev = priv->head->dev; | |
b5e89ed5 | 1241 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 LT |
1242 | drm_i810_overlay_t data; |
1243 | ||
1244 | data.offset = dev_priv->overlay_offset; | |
1245 | data.physical = dev_priv->overlay_physical; | |
b5e89ed5 DA |
1246 | if (copy_to_user |
1247 | ((drm_i810_overlay_t __user *) arg, &data, sizeof(data))) | |
1da177e4 LT |
1248 | return -EFAULT; |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static int i810_fstatus(struct inode *inode, struct file *filp, | |
1253 | unsigned int cmd, unsigned long arg) | |
1254 | { | |
1255 | drm_file_t *priv = filp->private_data; | |
1256 | drm_device_t *dev = priv->head->dev; | |
b5e89ed5 | 1257 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 LT |
1258 | |
1259 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1260 | ||
1261 | return I810_READ(0x30008); | |
1262 | } | |
1263 | ||
1264 | static int i810_ov0_flip(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1265 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1266 | { |
1267 | drm_file_t *priv = filp->private_data; | |
1268 | drm_device_t *dev = priv->head->dev; | |
b5e89ed5 | 1269 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 LT |
1270 | |
1271 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1272 | ||
1273 | //Tell the overlay to update | |
b5e89ed5 | 1274 | I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000); |
1da177e4 LT |
1275 | |
1276 | return 0; | |
1277 | } | |
1278 | ||
1da177e4 | 1279 | /* Not sure why this isn't set all the time: |
b5e89ed5 DA |
1280 | */ |
1281 | static void i810_do_init_pageflip(drm_device_t * dev) | |
1da177e4 LT |
1282 | { |
1283 | drm_i810_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1284 | |
1da177e4 LT |
1285 | DRM_DEBUG("%s\n", __FUNCTION__); |
1286 | dev_priv->page_flipping = 1; | |
1287 | dev_priv->current_page = 0; | |
1288 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
1289 | } | |
1290 | ||
b5e89ed5 | 1291 | static int i810_do_cleanup_pageflip(drm_device_t * dev) |
1da177e4 LT |
1292 | { |
1293 | drm_i810_private_t *dev_priv = dev->dev_private; | |
1294 | ||
1295 | DRM_DEBUG("%s\n", __FUNCTION__); | |
1296 | if (dev_priv->current_page != 0) | |
b5e89ed5 | 1297 | i810_dma_dispatch_flip(dev); |
1da177e4 LT |
1298 | |
1299 | dev_priv->page_flipping = 0; | |
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | static int i810_flip_bufs(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1304 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1305 | { |
1306 | drm_file_t *priv = filp->private_data; | |
1307 | drm_device_t *dev = priv->head->dev; | |
1308 | drm_i810_private_t *dev_priv = dev->dev_private; | |
1309 | ||
1310 | DRM_DEBUG("%s\n", __FUNCTION__); | |
1311 | ||
1312 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1313 | ||
b5e89ed5 DA |
1314 | if (!dev_priv->page_flipping) |
1315 | i810_do_init_pageflip(dev); | |
1da177e4 | 1316 | |
b5e89ed5 DA |
1317 | i810_dma_dispatch_flip(dev); |
1318 | return 0; | |
1da177e4 LT |
1319 | } |
1320 | ||
22eae947 DA |
1321 | int i810_driver_load(drm_device_t *dev, unsigned long flags) |
1322 | { | |
1323 | /* i810 has 4 more counters */ | |
1324 | dev->counters += 4; | |
1325 | dev->types[6] = _DRM_STAT_IRQ; | |
1326 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1327 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1328 | dev->types[9] = _DRM_STAT_DMA; | |
1329 | ||
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | void i810_driver_lastclose(drm_device_t * dev) | |
1da177e4 | 1334 | { |
b5e89ed5 | 1335 | i810_dma_cleanup(dev); |
1da177e4 LT |
1336 | } |
1337 | ||
22eae947 | 1338 | void i810_driver_preclose(drm_device_t * dev, DRMFILE filp) |
1da177e4 LT |
1339 | { |
1340 | if (dev->dev_private) { | |
1341 | drm_i810_private_t *dev_priv = dev->dev_private; | |
1342 | if (dev_priv->page_flipping) { | |
1343 | i810_do_cleanup_pageflip(dev); | |
1344 | } | |
1345 | } | |
1346 | } | |
1347 | ||
22eae947 | 1348 | void i810_driver_reclaim_buffers_locked(drm_device_t * dev, struct file *filp) |
1da177e4 LT |
1349 | { |
1350 | i810_reclaim_buffers(dev, filp); | |
1351 | } | |
1352 | ||
b5e89ed5 | 1353 | int i810_driver_dma_quiescent(drm_device_t * dev) |
1da177e4 | 1354 | { |
b5e89ed5 | 1355 | i810_dma_quiescent(dev); |
1da177e4 LT |
1356 | return 0; |
1357 | } | |
1358 | ||
1359 | drm_ioctl_desc_t i810_ioctls[] = { | |
a7a2cc31 DA |
1360 | [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, |
1361 | [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, DRM_AUTH}, | |
1362 | [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, DRM_AUTH}, | |
1363 | [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, DRM_AUTH}, | |
1364 | [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, DRM_AUTH}, | |
1365 | [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, DRM_AUTH}, | |
1366 | [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, DRM_AUTH}, | |
1367 | [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, DRM_AUTH}, | |
1368 | [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, DRM_AUTH}, | |
1369 | [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, DRM_AUTH}, | |
1370 | [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, DRM_AUTH}, | |
1371 | [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, DRM_AUTH}, | |
1372 | [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | |
1373 | [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, DRM_AUTH}, | |
1374 | [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, DRM_AUTH} | |
1da177e4 LT |
1375 | }; |
1376 | ||
1377 | int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls); | |
cda17380 DA |
1378 | |
1379 | /** | |
1380 | * Determine if the device really is AGP or not. | |
1381 | * | |
1382 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
1383 | * PCI-e. | |
1384 | * | |
1385 | * \param dev The device to be tested. | |
1386 | * | |
1387 | * \returns | |
1388 | * A value of 1 is always retured to indictate every i810 is AGP. | |
1389 | */ | |
1390 | int i810_driver_device_is_agp(drm_device_t * dev) | |
1391 | { | |
1392 | return 1; | |
1393 | } |