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1da177e4 LT |
1 | #ifndef _I830_DRM_H_ |
2 | #define _I830_DRM_H_ | |
3 | ||
4 | /* WARNING: These defines must be the same as what the Xserver uses. | |
5 | * if you change them, you must change the defines in the Xserver. | |
6 | * | |
7 | * KW: Actually, you can't ever change them because doing so would | |
8 | * break backwards compatibility. | |
9 | */ | |
10 | ||
11 | #ifndef _I830_DEFINES_ | |
12 | #define _I830_DEFINES_ | |
13 | ||
14 | #define I830_DMA_BUF_ORDER 12 | |
bc5f4523 DA |
15 | #define I830_DMA_BUF_SZ (1<<I830_DMA_BUF_ORDER) |
16 | #define I830_DMA_BUF_NR 256 | |
17 | #define I830_NR_SAREA_CLIPRECTS 8 | |
1da177e4 LT |
18 | |
19 | /* Each region is a minimum of 64k, and there are at most 64 of them. | |
20 | */ | |
21 | #define I830_NR_TEX_REGIONS 64 | |
22 | #define I830_LOG_MIN_TEX_REGION_SIZE 16 | |
23 | ||
24 | /* KW: These aren't correct but someone set them to two and then | |
25 | * released the module. Now we can't change them as doing so would | |
26 | * break backwards compatibility. | |
27 | */ | |
28 | #define I830_TEXTURE_COUNT 2 | |
29 | #define I830_TEXBLEND_COUNT I830_TEXTURE_COUNT | |
30 | ||
31 | #define I830_TEXBLEND_SIZE 12 /* (4 args + op) * 2 + COLOR_FACTOR */ | |
32 | ||
33 | #define I830_UPLOAD_CTX 0x1 | |
34 | #define I830_UPLOAD_BUFFERS 0x2 | |
35 | #define I830_UPLOAD_CLIPRECTS 0x4 | |
b5e89ed5 DA |
36 | #define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ |
37 | #define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ | |
38 | #define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ | |
39 | #define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ | |
40 | #define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ | |
41 | #define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ | |
42 | #define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ | |
43 | #define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ | |
1da177e4 LT |
44 | #define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2)) |
45 | #define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2)) | |
46 | #define I830_UPLOAD_TEXIMAGE_MASK 0xff00 | |
47 | #define I830_UPLOAD_TEX0 0x10000 | |
48 | #define I830_UPLOAD_TEX1 0x20000 | |
49 | #define I830_UPLOAD_TEX2 0x40000 | |
50 | #define I830_UPLOAD_TEX3 0x80000 | |
51 | #define I830_UPLOAD_TEX_N(n) (0x10000 << (n)) | |
52 | #define I830_UPLOAD_TEX_MASK 0xf0000 | |
53 | #define I830_UPLOAD_TEXBLEND0 0x100000 | |
54 | #define I830_UPLOAD_TEXBLEND1 0x200000 | |
55 | #define I830_UPLOAD_TEXBLEND2 0x400000 | |
56 | #define I830_UPLOAD_TEXBLEND3 0x800000 | |
57 | #define I830_UPLOAD_TEXBLEND_N(n) (0x100000 << (n)) | |
58 | #define I830_UPLOAD_TEXBLEND_MASK 0xf00000 | |
59 | #define I830_UPLOAD_TEX_PALETTE_N(n) (0x1000000 << (n)) | |
60 | #define I830_UPLOAD_TEX_PALETTE_SHARED 0x4000000 | |
bc5f4523 | 61 | #define I830_UPLOAD_STIPPLE 0x8000000 |
1da177e4 LT |
62 | |
63 | /* Indices into buf.Setup where various bits of state are mirrored per | |
64 | * context and per buffer. These can be fired at the card as a unit, | |
65 | * or in a piecewise fashion as required. | |
66 | */ | |
67 | ||
b5e89ed5 | 68 | /* Destbuffer state |
1da177e4 LT |
69 | * - backbuffer linear offset and pitch -- invarient in the current dri |
70 | * - zbuffer linear offset and pitch -- also invarient | |
71 | * - drawing origin in back and depth buffers. | |
72 | * | |
73 | * Keep the depth/back buffer state here to accommodate private buffers | |
74 | * in the future. | |
75 | */ | |
76 | ||
77 | #define I830_DESTREG_CBUFADDR 0 | |
78 | #define I830_DESTREG_DBUFADDR 1 | |
79 | #define I830_DESTREG_DV0 2 | |
80 | #define I830_DESTREG_DV1 3 | |
81 | #define I830_DESTREG_SENABLE 4 | |
82 | #define I830_DESTREG_SR0 5 | |
83 | #define I830_DESTREG_SR1 6 | |
84 | #define I830_DESTREG_SR2 7 | |
85 | #define I830_DESTREG_DR0 8 | |
86 | #define I830_DESTREG_DR1 9 | |
87 | #define I830_DESTREG_DR2 10 | |
88 | #define I830_DESTREG_DR3 11 | |
89 | #define I830_DESTREG_DR4 12 | |
90 | #define I830_DEST_SETUP_SIZE 13 | |
91 | ||
92 | /* Context state | |
93 | */ | |
94 | #define I830_CTXREG_STATE1 0 | |
95 | #define I830_CTXREG_STATE2 1 | |
96 | #define I830_CTXREG_STATE3 2 | |
97 | #define I830_CTXREG_STATE4 3 | |
98 | #define I830_CTXREG_STATE5 4 | |
99 | #define I830_CTXREG_IALPHAB 5 | |
100 | #define I830_CTXREG_STENCILTST 6 | |
101 | #define I830_CTXREG_ENABLES_1 7 | |
102 | #define I830_CTXREG_ENABLES_2 8 | |
103 | #define I830_CTXREG_AA 9 | |
104 | #define I830_CTXREG_FOGCOLOR 10 | |
105 | #define I830_CTXREG_BLENDCOLR0 11 | |
b5e89ed5 | 106 | #define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ |
1da177e4 LT |
107 | #define I830_CTXREG_VF 13 |
108 | #define I830_CTXREG_VF2 14 | |
109 | #define I830_CTXREG_MCSB0 15 | |
110 | #define I830_CTXREG_MCSB1 16 | |
111 | #define I830_CTX_SETUP_SIZE 17 | |
112 | ||
113 | /* 1.3: Stipple state | |
b5e89ed5 | 114 | */ |
1da177e4 LT |
115 | #define I830_STPREG_ST0 0 |
116 | #define I830_STPREG_ST1 1 | |
117 | #define I830_STP_SETUP_SIZE 2 | |
118 | ||
1da177e4 LT |
119 | /* Texture state (per tex unit) |
120 | */ | |
121 | ||
122 | #define I830_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (6 dwords) */ | |
123 | #define I830_TEXREG_MI1 1 | |
124 | #define I830_TEXREG_MI2 2 | |
125 | #define I830_TEXREG_MI3 3 | |
126 | #define I830_TEXREG_MI4 4 | |
127 | #define I830_TEXREG_MI5 5 | |
128 | #define I830_TEXREG_MF 6 /* GFX_OP_MAP_FILTER */ | |
129 | #define I830_TEXREG_MLC 7 /* GFX_OP_MAP_LOD_CTL */ | |
130 | #define I830_TEXREG_MLL 8 /* GFX_OP_MAP_LOD_LIMITS */ | |
131 | #define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */ | |
132 | #define I830_TEX_SETUP_SIZE 10 | |
133 | ||
b5e89ed5 | 134 | #define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ |
1da177e4 LT |
135 | #define I830_TEXREG_TM0S0 1 |
136 | #define I830_TEXREG_TM0S1 2 | |
137 | #define I830_TEXREG_TM0S2 3 | |
138 | #define I830_TEXREG_TM0S3 4 | |
139 | #define I830_TEXREG_TM0S4 5 | |
b5e89ed5 DA |
140 | #define I830_TEXREG_NOP0 6 /* noop */ |
141 | #define I830_TEXREG_NOP1 7 /* noop */ | |
142 | #define I830_TEXREG_NOP2 8 /* noop */ | |
143 | #define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ | |
1da177e4 LT |
144 | #define __I830_TEX_SETUP_SIZE 10 |
145 | ||
146 | #define I830_FRONT 0x1 | |
147 | #define I830_BACK 0x2 | |
148 | #define I830_DEPTH 0x4 | |
149 | ||
b5e89ed5 | 150 | #endif /* _I830_DEFINES_ */ |
1da177e4 LT |
151 | |
152 | typedef struct _drm_i830_init { | |
153 | enum { | |
154 | I830_INIT_DMA = 0x01, | |
155 | I830_CLEANUP_DMA = 0x02 | |
156 | } func; | |
157 | unsigned int mmio_offset; | |
158 | unsigned int buffers_offset; | |
159 | int sarea_priv_offset; | |
160 | unsigned int ring_start; | |
161 | unsigned int ring_end; | |
162 | unsigned int ring_size; | |
163 | unsigned int front_offset; | |
164 | unsigned int back_offset; | |
165 | unsigned int depth_offset; | |
166 | unsigned int w; | |
167 | unsigned int h; | |
168 | unsigned int pitch; | |
169 | unsigned int pitch_bits; | |
170 | unsigned int back_pitch; | |
171 | unsigned int depth_pitch; | |
172 | unsigned int cpp; | |
173 | } drm_i830_init_t; | |
174 | ||
175 | /* Warning: If you change the SAREA structure you must change the Xserver | |
176 | * structure as well */ | |
177 | ||
178 | typedef struct _drm_i830_tex_region { | |
b5e89ed5 | 179 | unsigned char next, prev; /* indices to form a circular LRU */ |
1da177e4 LT |
180 | unsigned char in_use; /* owned by a client, or free? */ |
181 | int age; /* tracked by clients to update local LRU's */ | |
182 | } drm_i830_tex_region_t; | |
183 | ||
184 | typedef struct _drm_i830_sarea { | |
185 | unsigned int ContextState[I830_CTX_SETUP_SIZE]; | |
b5e89ed5 | 186 | unsigned int BufferState[I830_DEST_SETUP_SIZE]; |
1da177e4 LT |
187 | unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; |
188 | unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; | |
189 | unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; | |
190 | unsigned int Palette[2][256]; | |
b5e89ed5 | 191 | unsigned int dirty; |
1da177e4 LT |
192 | |
193 | unsigned int nbox; | |
eddca551 | 194 | struct drm_clip_rect boxes[I830_NR_SAREA_CLIPRECTS]; |
1da177e4 LT |
195 | |
196 | /* Maintain an LRU of contiguous regions of texture space. If | |
197 | * you think you own a region of texture memory, and it has an | |
198 | * age different to the one you set, then you are mistaken and | |
199 | * it has been stolen by another client. If global texAge | |
200 | * hasn't changed, there is no need to walk the list. | |
201 | * | |
202 | * These regions can be used as a proxy for the fine-grained | |
203 | * texture information of other clients - by maintaining them | |
204 | * in the same lru which is used to age their own textures, | |
205 | * clients have an approximate lru for the whole of global | |
206 | * texture space, and can make informed decisions as to which | |
207 | * areas to kick out. There is no need to choose whether to | |
208 | * kick out your own texture or someone else's - simply eject | |
b5e89ed5 | 209 | * them all in LRU order. |
1da177e4 LT |
210 | */ |
211 | ||
b5e89ed5 DA |
212 | drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1]; |
213 | /* Last elt is sentinal */ | |
214 | int texAge; /* last time texture was uploaded */ | |
215 | int last_enqueue; /* last time a buffer was enqueued */ | |
1da177e4 | 216 | int last_dispatch; /* age of the most recently dispatched buffer */ |
b5e89ed5 | 217 | int last_quiescent; /* */ |
1da177e4 LT |
218 | int ctxOwner; /* last context to upload state */ |
219 | ||
220 | int vertex_prim; | |
221 | ||
b5e89ed5 DA |
222 | int pf_enabled; /* is pageflipping allowed? */ |
223 | int pf_active; | |
224 | int pf_current_page; /* which buffer is being displayed? */ | |
225 | ||
226 | int perf_boxes; /* performance boxes to be displayed */ | |
1da177e4 | 227 | |
b5e89ed5 | 228 | /* Here's the state for texunits 2,3: |
1da177e4 LT |
229 | */ |
230 | unsigned int TexState2[I830_TEX_SETUP_SIZE]; | |
231 | unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; | |
232 | unsigned int TexBlendStateWordsUsed2; | |
233 | ||
234 | unsigned int TexState3[I830_TEX_SETUP_SIZE]; | |
235 | unsigned int TexBlendState3[I830_TEXBLEND_SIZE]; | |
236 | unsigned int TexBlendStateWordsUsed3; | |
237 | ||
238 | unsigned int StippleState[I830_STP_SETUP_SIZE]; | |
239 | } drm_i830_sarea_t; | |
240 | ||
241 | /* Flags for perf_boxes | |
242 | */ | |
b5e89ed5 DA |
243 | #define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ |
244 | #define I830_BOX_FLIP 0x2 /* populated by kernel */ | |
245 | #define I830_BOX_WAIT 0x4 /* populated by kernel & client */ | |
246 | #define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ | |
247 | #define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ | |
1da177e4 LT |
248 | |
249 | /* I830 specific ioctls | |
250 | * The device specific ioctl range is 0x40 to 0x79. | |
251 | */ | |
252 | #define DRM_I830_INIT 0x00 | |
253 | #define DRM_I830_VERTEX 0x01 | |
254 | #define DRM_I830_CLEAR 0x02 | |
255 | #define DRM_I830_FLUSH 0x03 | |
256 | #define DRM_I830_GETAGE 0x04 | |
257 | #define DRM_I830_GETBUF 0x05 | |
258 | #define DRM_I830_SWAP 0x06 | |
259 | #define DRM_I830_COPY 0x07 | |
260 | #define DRM_I830_DOCOPY 0x08 | |
261 | #define DRM_I830_FLIP 0x09 | |
262 | #define DRM_I830_IRQ_EMIT 0x0a | |
263 | #define DRM_I830_IRQ_WAIT 0x0b | |
264 | #define DRM_I830_GETPARAM 0x0c | |
265 | #define DRM_I830_SETPARAM 0x0d | |
266 | ||
267 | #define DRM_IOCTL_I830_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_INIT, drm_i830_init_t) | |
268 | #define DRM_IOCTL_I830_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_VERTEX, drm_i830_vertex_t) | |
269 | #define DRM_IOCTL_I830_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_CLEAR, drm_i830_clear_t) | |
270 | #define DRM_IOCTL_I830_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLUSH) | |
271 | #define DRM_IOCTL_I830_GETAGE DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_GETAGE) | |
272 | #define DRM_IOCTL_I830_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETBUF, drm_i830_dma_t) | |
273 | #define DRM_IOCTL_I830_SWAP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_SWAP) | |
274 | #define DRM_IOCTL_I830_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_COPY, drm_i830_copy_t) | |
275 | #define DRM_IOCTL_I830_DOCOPY DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_DOCOPY) | |
276 | #define DRM_IOCTL_I830_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLIP) | |
277 | #define DRM_IOCTL_I830_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_EMIT, drm_i830_irq_emit_t) | |
278 | #define DRM_IOCTL_I830_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_WAIT, drm_i830_irq_wait_t) | |
279 | #define DRM_IOCTL_I830_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETPARAM, drm_i830_getparam_t) | |
280 | #define DRM_IOCTL_I830_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_SETPARAM, drm_i830_setparam_t) | |
281 | ||
282 | typedef struct _drm_i830_clear { | |
283 | int clear_color; | |
284 | int clear_depth; | |
285 | int flags; | |
286 | unsigned int clear_colormask; | |
287 | unsigned int clear_depthmask; | |
288 | } drm_i830_clear_t; | |
289 | ||
1da177e4 LT |
290 | /* These may be placeholders if we have more cliprects than |
291 | * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to | |
292 | * false, indicating that the buffer will be dispatched again with a | |
293 | * new set of cliprects. | |
294 | */ | |
295 | typedef struct _drm_i830_vertex { | |
b5e89ed5 | 296 | int idx; /* buffer index */ |
1da177e4 LT |
297 | int used; /* nr bytes in use */ |
298 | int discard; /* client is finished with the buffer? */ | |
299 | } drm_i830_vertex_t; | |
300 | ||
301 | typedef struct _drm_i830_copy_t { | |
b5e89ed5 | 302 | int idx; /* buffer index */ |
1da177e4 | 303 | int used; /* nr bytes in use */ |
b5e89ed5 | 304 | void __user *address; /* Address to copy from */ |
1da177e4 LT |
305 | } drm_i830_copy_t; |
306 | ||
307 | typedef struct drm_i830_dma { | |
308 | void __user *virtual; | |
309 | int request_idx; | |
310 | int request_size; | |
311 | int granted; | |
312 | } drm_i830_dma_t; | |
313 | ||
1da177e4 LT |
314 | /* 1.3: Userspace can request & wait on irq's: |
315 | */ | |
316 | typedef struct drm_i830_irq_emit { | |
317 | int __user *irq_seq; | |
318 | } drm_i830_irq_emit_t; | |
319 | ||
320 | typedef struct drm_i830_irq_wait { | |
321 | int irq_seq; | |
322 | } drm_i830_irq_wait_t; | |
323 | ||
1da177e4 LT |
324 | /* 1.3: New ioctl to query kernel params: |
325 | */ | |
326 | #define I830_PARAM_IRQ_ACTIVE 1 | |
327 | ||
328 | typedef struct drm_i830_getparam { | |
329 | int param; | |
330 | int __user *value; | |
331 | } drm_i830_getparam_t; | |
332 | ||
1da177e4 LT |
333 | /* 1.3: New ioctl to set kernel params: |
334 | */ | |
335 | #define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 | |
336 | ||
337 | typedef struct drm_i830_setparam { | |
338 | int param; | |
339 | int value; | |
340 | } drm_i830_setparam_t; | |
341 | ||
b5e89ed5 | 342 | #endif /* _I830_DRM_H_ */ |