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Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | ||
2f02cc3f EA |
34 | #define IS_I965G(dev) (dev->pci_device == 0x2972 || \ |
35 | dev->pci_device == 0x2982 || \ | |
36 | dev->pci_device == 0x2992 || \ | |
ce7dd063 | 37 | dev->pci_device == 0x29A2 || \ |
2f4042b1 WZ |
38 | dev->pci_device == 0x2A02 || \ |
39 | dev->pci_device == 0x2A12) | |
c29b669c | 40 | |
dc7a9319 WZ |
41 | #define IS_G33(dev) (dev->pci_device == 0x29b2 || \ |
42 | dev->pci_device == 0x29c2 || \ | |
43 | dev->pci_device == 0x29d2) | |
44 | ||
1da177e4 LT |
45 | /* Really want an OS-independent resettable timer. Would like to have |
46 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
47 | * the head pointer changes, so that EBUSY only happens if the ring | |
48 | * actually stalls for (eg) 3 seconds. | |
49 | */ | |
84b1fd10 | 50 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
51 | { |
52 | drm_i915_private_t *dev_priv = dev->dev_private; | |
53 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
54 | u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; | |
55 | int i; | |
56 | ||
57 | for (i = 0; i < 10000; i++) { | |
58 | ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; | |
59 | ring->space = ring->head - (ring->tail + 8); | |
60 | if (ring->space < 0) | |
61 | ring->space += ring->Size; | |
62 | if (ring->space >= n) | |
63 | return 0; | |
64 | ||
65 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
66 | ||
67 | if (ring->head != last_head) | |
68 | i = 0; | |
69 | ||
70 | last_head = ring->head; | |
71 | } | |
72 | ||
73 | return DRM_ERR(EBUSY); | |
74 | } | |
75 | ||
84b1fd10 | 76 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
77 | { |
78 | drm_i915_private_t *dev_priv = dev->dev_private; | |
79 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
80 | ||
81 | ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; | |
82 | ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR; | |
83 | ring->space = ring->head - (ring->tail + 8); | |
84 | if (ring->space < 0) | |
85 | ring->space += ring->Size; | |
86 | ||
87 | if (ring->head == ring->tail) | |
88 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
89 | } | |
90 | ||
84b1fd10 | 91 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 LT |
92 | { |
93 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
94 | * may not have been called from userspace and after dev_private | |
95 | * is freed, it's too late. | |
96 | */ | |
97 | if (dev->irq) | |
b5e89ed5 | 98 | drm_irq_uninstall(dev); |
1da177e4 LT |
99 | |
100 | if (dev->dev_private) { | |
101 | drm_i915_private_t *dev_priv = | |
102 | (drm_i915_private_t *) dev->dev_private; | |
103 | ||
104 | if (dev_priv->ring.virtual_start) { | |
b5e89ed5 | 105 | drm_core_ioremapfree(&dev_priv->ring.map, dev); |
1da177e4 LT |
106 | } |
107 | ||
9c8da5eb DA |
108 | if (dev_priv->status_page_dmah) { |
109 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
1da177e4 LT |
110 | /* Need to rewrite hardware status page */ |
111 | I915_WRITE(0x02080, 0x1ffff000); | |
112 | } | |
113 | ||
dc7a9319 WZ |
114 | if (dev_priv->status_gfx_addr) { |
115 | dev_priv->status_gfx_addr = 0; | |
116 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
117 | I915_WRITE(0x2080, 0x1ffff000); | |
118 | } | |
119 | ||
b5e89ed5 DA |
120 | drm_free(dev->dev_private, sizeof(drm_i915_private_t), |
121 | DRM_MEM_DRIVER); | |
1da177e4 LT |
122 | |
123 | dev->dev_private = NULL; | |
124 | } | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
84b1fd10 | 129 | static int i915_initialize(struct drm_device * dev, |
1da177e4 LT |
130 | drm_i915_private_t * dev_priv, |
131 | drm_i915_init_t * init) | |
132 | { | |
133 | memset(dev_priv, 0, sizeof(drm_i915_private_t)); | |
134 | ||
da509d7a | 135 | dev_priv->sarea = drm_getsarea(dev); |
1da177e4 LT |
136 | if (!dev_priv->sarea) { |
137 | DRM_ERROR("can not find sarea!\n"); | |
138 | dev->dev_private = (void *)dev_priv; | |
139 | i915_dma_cleanup(dev); | |
140 | return DRM_ERR(EINVAL); | |
141 | } | |
142 | ||
143 | dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); | |
144 | if (!dev_priv->mmio_map) { | |
145 | dev->dev_private = (void *)dev_priv; | |
146 | i915_dma_cleanup(dev); | |
147 | DRM_ERROR("can not find mmio map!\n"); | |
148 | return DRM_ERR(EINVAL); | |
149 | } | |
150 | ||
151 | dev_priv->sarea_priv = (drm_i915_sarea_t *) | |
152 | ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); | |
153 | ||
154 | dev_priv->ring.Start = init->ring_start; | |
155 | dev_priv->ring.End = init->ring_end; | |
156 | dev_priv->ring.Size = init->ring_size; | |
157 | dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; | |
158 | ||
159 | dev_priv->ring.map.offset = init->ring_start; | |
160 | dev_priv->ring.map.size = init->ring_size; | |
161 | dev_priv->ring.map.type = 0; | |
162 | dev_priv->ring.map.flags = 0; | |
163 | dev_priv->ring.map.mtrr = 0; | |
164 | ||
b5e89ed5 | 165 | drm_core_ioremap(&dev_priv->ring.map, dev); |
1da177e4 LT |
166 | |
167 | if (dev_priv->ring.map.handle == NULL) { | |
168 | dev->dev_private = (void *)dev_priv; | |
169 | i915_dma_cleanup(dev); | |
170 | DRM_ERROR("can not ioremap virtual address for" | |
171 | " ring buffer\n"); | |
172 | return DRM_ERR(ENOMEM); | |
173 | } | |
174 | ||
175 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
176 | ||
a6b54f3f | 177 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
178 | dev_priv->back_offset = init->back_offset; |
179 | dev_priv->front_offset = init->front_offset; | |
180 | dev_priv->current_page = 0; | |
181 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
182 | ||
183 | /* We are using separate values as placeholders for mechanisms for | |
184 | * private backbuffer/depthbuffer usage. | |
185 | */ | |
186 | dev_priv->use_mi_batchbuffer_start = 0; | |
187 | ||
188 | /* Allow hardware batchbuffers unless told otherwise. | |
189 | */ | |
190 | dev_priv->allow_batchbuffer = 1; | |
191 | ||
192 | /* Program Hardware Status Page */ | |
dc7a9319 WZ |
193 | if (!IS_G33(dev)) { |
194 | dev_priv->status_page_dmah = | |
195 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); | |
196 | ||
197 | if (!dev_priv->status_page_dmah) { | |
198 | dev->dev_private = (void *)dev_priv; | |
199 | i915_dma_cleanup(dev); | |
200 | DRM_ERROR("Can not allocate hardware status page\n"); | |
201 | return DRM_ERR(ENOMEM); | |
202 | } | |
203 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
204 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
1da177e4 | 205 | |
dc7a9319 WZ |
206 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
207 | I915_WRITE(0x02080, dev_priv->dma_status_page); | |
1da177e4 | 208 | } |
1da177e4 | 209 | DRM_DEBUG("Enabled hardware status page\n"); |
1da177e4 | 210 | dev->dev_private = (void *)dev_priv; |
1da177e4 LT |
211 | return 0; |
212 | } | |
213 | ||
84b1fd10 | 214 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
215 | { |
216 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
217 | ||
218 | DRM_DEBUG("%s\n", __FUNCTION__); | |
219 | ||
220 | if (!dev_priv->sarea) { | |
221 | DRM_ERROR("can not find sarea!\n"); | |
222 | return DRM_ERR(EINVAL); | |
223 | } | |
224 | ||
225 | if (!dev_priv->mmio_map) { | |
226 | DRM_ERROR("can not find mmio map!\n"); | |
227 | return DRM_ERR(EINVAL); | |
228 | } | |
229 | ||
230 | if (dev_priv->ring.map.handle == NULL) { | |
231 | DRM_ERROR("can not ioremap virtual address for" | |
232 | " ring buffer\n"); | |
233 | return DRM_ERR(ENOMEM); | |
234 | } | |
235 | ||
236 | /* Program Hardware Status Page */ | |
237 | if (!dev_priv->hw_status_page) { | |
238 | DRM_ERROR("Can not find hardware status page\n"); | |
239 | return DRM_ERR(EINVAL); | |
240 | } | |
241 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | |
242 | ||
dc7a9319 WZ |
243 | if (dev_priv->status_gfx_addr != 0) |
244 | I915_WRITE(0x02080, dev_priv->status_gfx_addr); | |
245 | else | |
246 | I915_WRITE(0x02080, dev_priv->dma_status_page); | |
1da177e4 LT |
247 | DRM_DEBUG("Enabled hardware status page\n"); |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
c94f7029 | 252 | static int i915_dma_init(DRM_IOCTL_ARGS) |
1da177e4 LT |
253 | { |
254 | DRM_DEVICE; | |
255 | drm_i915_private_t *dev_priv; | |
256 | drm_i915_init_t init; | |
257 | int retcode = 0; | |
258 | ||
259 | DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data, | |
260 | sizeof(init)); | |
261 | ||
262 | switch (init.func) { | |
263 | case I915_INIT_DMA: | |
b5e89ed5 DA |
264 | dev_priv = drm_alloc(sizeof(drm_i915_private_t), |
265 | DRM_MEM_DRIVER); | |
1da177e4 LT |
266 | if (dev_priv == NULL) |
267 | return DRM_ERR(ENOMEM); | |
268 | retcode = i915_initialize(dev, dev_priv, &init); | |
269 | break; | |
270 | case I915_CLEANUP_DMA: | |
271 | retcode = i915_dma_cleanup(dev); | |
272 | break; | |
273 | case I915_RESUME_DMA: | |
0d6aa60b | 274 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
275 | break; |
276 | default: | |
46acbf13 | 277 | retcode = DRM_ERR(EINVAL); |
1da177e4 LT |
278 | break; |
279 | } | |
280 | ||
281 | return retcode; | |
282 | } | |
283 | ||
284 | /* Implement basically the same security restrictions as hardware does | |
285 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
286 | * | |
287 | * Most of the calculations below involve calculating the size of a | |
288 | * particular instruction. It's important to get the size right as | |
289 | * that tells us where the next instruction to check is. Any illegal | |
290 | * instruction detected will be given a size of zero, which is a | |
291 | * signal to abort the rest of the buffer. | |
292 | */ | |
293 | static int do_validate_cmd(int cmd) | |
294 | { | |
295 | switch (((cmd >> 29) & 0x7)) { | |
296 | case 0x0: | |
297 | switch ((cmd >> 23) & 0x3f) { | |
298 | case 0x0: | |
299 | return 1; /* MI_NOOP */ | |
300 | case 0x4: | |
301 | return 1; /* MI_FLUSH */ | |
302 | default: | |
303 | return 0; /* disallow everything else */ | |
304 | } | |
305 | break; | |
306 | case 0x1: | |
307 | return 0; /* reserved */ | |
308 | case 0x2: | |
309 | return (cmd & 0xff) + 2; /* 2d commands */ | |
310 | case 0x3: | |
311 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
312 | return 1; | |
313 | ||
314 | switch ((cmd >> 24) & 0x1f) { | |
315 | case 0x1c: | |
316 | return 1; | |
317 | case 0x1d: | |
b5e89ed5 | 318 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
319 | case 0x3: |
320 | return (cmd & 0x1f) + 2; | |
321 | case 0x4: | |
322 | return (cmd & 0xf) + 2; | |
323 | default: | |
324 | return (cmd & 0xffff) + 2; | |
325 | } | |
326 | case 0x1e: | |
327 | if (cmd & (1 << 23)) | |
328 | return (cmd & 0xffff) + 1; | |
329 | else | |
330 | return 1; | |
331 | case 0x1f: | |
332 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
333 | return (cmd & 0x1ffff) + 2; | |
334 | else if (cmd & (1 << 17)) /* indirect random */ | |
335 | if ((cmd & 0xffff) == 0) | |
336 | return 0; /* unknown length, too hard */ | |
337 | else | |
338 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
339 | else | |
340 | return 2; /* indirect sequential */ | |
341 | default: | |
342 | return 0; | |
343 | } | |
344 | default: | |
345 | return 0; | |
346 | } | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | static int validate_cmd(int cmd) | |
352 | { | |
353 | int ret = do_validate_cmd(cmd); | |
354 | ||
355 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ | |
356 | ||
357 | return ret; | |
358 | } | |
359 | ||
84b1fd10 | 360 | static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords) |
1da177e4 LT |
361 | { |
362 | drm_i915_private_t *dev_priv = dev->dev_private; | |
363 | int i; | |
364 | RING_LOCALS; | |
365 | ||
de227f5f DA |
366 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
367 | return DRM_ERR(EINVAL); | |
368 | ||
c29b669c | 369 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 370 | |
1da177e4 LT |
371 | for (i = 0; i < dwords;) { |
372 | int cmd, sz; | |
373 | ||
374 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) | |
375 | return DRM_ERR(EINVAL); | |
376 | ||
1da177e4 LT |
377 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
378 | return DRM_ERR(EINVAL); | |
379 | ||
1da177e4 LT |
380 | OUT_RING(cmd); |
381 | ||
382 | while (++i, --sz) { | |
383 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], | |
384 | sizeof(cmd))) { | |
385 | return DRM_ERR(EINVAL); | |
386 | } | |
387 | OUT_RING(cmd); | |
388 | } | |
1da177e4 LT |
389 | } |
390 | ||
de227f5f DA |
391 | if (dwords & 1) |
392 | OUT_RING(0); | |
393 | ||
394 | ADVANCE_LP_RING(); | |
395 | ||
1da177e4 LT |
396 | return 0; |
397 | } | |
398 | ||
84b1fd10 | 399 | static int i915_emit_box(struct drm_device * dev, |
c60ce623 | 400 | struct drm_clip_rect __user * boxes, |
1da177e4 LT |
401 | int i, int DR1, int DR4) |
402 | { | |
403 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 404 | struct drm_clip_rect box; |
1da177e4 LT |
405 | RING_LOCALS; |
406 | ||
407 | if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { | |
46acbf13 | 408 | return DRM_ERR(EFAULT); |
1da177e4 LT |
409 | } |
410 | ||
411 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { | |
412 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
413 | box.x1, box.y1, box.x2, box.y2); | |
414 | return DRM_ERR(EINVAL); | |
415 | } | |
416 | ||
c29b669c AH |
417 | if (IS_I965G(dev)) { |
418 | BEGIN_LP_RING(4); | |
419 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
420 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 421 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
422 | OUT_RING(DR4); |
423 | ADVANCE_LP_RING(); | |
424 | } else { | |
425 | BEGIN_LP_RING(6); | |
426 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
427 | OUT_RING(DR1); | |
428 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
429 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
430 | OUT_RING(DR4); | |
431 | OUT_RING(0); | |
432 | ADVANCE_LP_RING(); | |
433 | } | |
1da177e4 LT |
434 | |
435 | return 0; | |
436 | } | |
437 | ||
c29b669c AH |
438 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
439 | * emit. For now, do it in both places: | |
440 | */ | |
441 | ||
84b1fd10 | 442 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
443 | { |
444 | drm_i915_private_t *dev_priv = dev->dev_private; | |
445 | RING_LOCALS; | |
446 | ||
c29b669c AH |
447 | dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter; |
448 | ||
449 | if (dev_priv->counter > 0x7FFFFFFFUL) | |
450 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; | |
de227f5f DA |
451 | |
452 | BEGIN_LP_RING(4); | |
453 | OUT_RING(CMD_STORE_DWORD_IDX); | |
454 | OUT_RING(20); | |
455 | OUT_RING(dev_priv->counter); | |
456 | OUT_RING(0); | |
457 | ADVANCE_LP_RING(); | |
458 | } | |
459 | ||
84b1fd10 | 460 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
1da177e4 LT |
461 | drm_i915_cmdbuffer_t * cmd) |
462 | { | |
463 | int nbox = cmd->num_cliprects; | |
464 | int i = 0, count, ret; | |
465 | ||
466 | if (cmd->sz & 0x3) { | |
467 | DRM_ERROR("alignment"); | |
468 | return DRM_ERR(EINVAL); | |
469 | } | |
470 | ||
471 | i915_kernel_lost_context(dev); | |
472 | ||
473 | count = nbox ? nbox : 1; | |
474 | ||
475 | for (i = 0; i < count; i++) { | |
476 | if (i < nbox) { | |
477 | ret = i915_emit_box(dev, cmd->cliprects, i, | |
478 | cmd->DR1, cmd->DR4); | |
479 | if (ret) | |
480 | return ret; | |
481 | } | |
482 | ||
483 | ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); | |
484 | if (ret) | |
485 | return ret; | |
486 | } | |
487 | ||
de227f5f | 488 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
489 | return 0; |
490 | } | |
491 | ||
84b1fd10 | 492 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
1da177e4 LT |
493 | drm_i915_batchbuffer_t * batch) |
494 | { | |
495 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 496 | struct drm_clip_rect __user *boxes = batch->cliprects; |
1da177e4 LT |
497 | int nbox = batch->num_cliprects; |
498 | int i = 0, count; | |
499 | RING_LOCALS; | |
500 | ||
501 | if ((batch->start | batch->used) & 0x7) { | |
502 | DRM_ERROR("alignment"); | |
503 | return DRM_ERR(EINVAL); | |
504 | } | |
505 | ||
506 | i915_kernel_lost_context(dev); | |
507 | ||
508 | count = nbox ? nbox : 1; | |
509 | ||
510 | for (i = 0; i < count; i++) { | |
511 | if (i < nbox) { | |
512 | int ret = i915_emit_box(dev, boxes, i, | |
513 | batch->DR1, batch->DR4); | |
514 | if (ret) | |
515 | return ret; | |
516 | } | |
517 | ||
518 | if (dev_priv->use_mi_batchbuffer_start) { | |
519 | BEGIN_LP_RING(2); | |
520 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
521 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
522 | ADVANCE_LP_RING(); | |
523 | } else { | |
524 | BEGIN_LP_RING(4); | |
525 | OUT_RING(MI_BATCH_BUFFER); | |
526 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
527 | OUT_RING(batch->start + batch->used - 4); | |
528 | OUT_RING(0); | |
529 | ADVANCE_LP_RING(); | |
530 | } | |
531 | } | |
532 | ||
de227f5f | 533 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
534 | |
535 | return 0; | |
536 | } | |
537 | ||
84b1fd10 | 538 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
539 | { |
540 | drm_i915_private_t *dev_priv = dev->dev_private; | |
541 | RING_LOCALS; | |
542 | ||
543 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", | |
544 | __FUNCTION__, | |
545 | dev_priv->current_page, | |
546 | dev_priv->sarea_priv->pf_current_page); | |
547 | ||
548 | i915_kernel_lost_context(dev); | |
549 | ||
550 | BEGIN_LP_RING(2); | |
551 | OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); | |
552 | OUT_RING(0); | |
553 | ADVANCE_LP_RING(); | |
554 | ||
555 | BEGIN_LP_RING(6); | |
556 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
557 | OUT_RING(0); | |
558 | if (dev_priv->current_page == 0) { | |
559 | OUT_RING(dev_priv->back_offset); | |
560 | dev_priv->current_page = 1; | |
561 | } else { | |
562 | OUT_RING(dev_priv->front_offset); | |
563 | dev_priv->current_page = 0; | |
564 | } | |
565 | OUT_RING(0); | |
566 | ADVANCE_LP_RING(); | |
567 | ||
568 | BEGIN_LP_RING(2); | |
569 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
570 | OUT_RING(0); | |
571 | ADVANCE_LP_RING(); | |
572 | ||
573 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; | |
574 | ||
575 | BEGIN_LP_RING(4); | |
576 | OUT_RING(CMD_STORE_DWORD_IDX); | |
577 | OUT_RING(20); | |
578 | OUT_RING(dev_priv->counter); | |
579 | OUT_RING(0); | |
580 | ADVANCE_LP_RING(); | |
581 | ||
582 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
583 | return 0; | |
584 | } | |
585 | ||
84b1fd10 | 586 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
587 | { |
588 | drm_i915_private_t *dev_priv = dev->dev_private; | |
589 | ||
590 | i915_kernel_lost_context(dev); | |
591 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); | |
592 | } | |
593 | ||
c94f7029 | 594 | static int i915_flush_ioctl(DRM_IOCTL_ARGS) |
1da177e4 LT |
595 | { |
596 | DRM_DEVICE; | |
597 | ||
598 | LOCK_TEST_WITH_RETURN(dev, filp); | |
599 | ||
600 | return i915_quiescent(dev); | |
601 | } | |
602 | ||
c94f7029 | 603 | static int i915_batchbuffer(DRM_IOCTL_ARGS) |
1da177e4 LT |
604 | { |
605 | DRM_DEVICE; | |
606 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
607 | u32 *hw_status = dev_priv->hw_status_page; | |
608 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) | |
609 | dev_priv->sarea_priv; | |
610 | drm_i915_batchbuffer_t batch; | |
611 | int ret; | |
612 | ||
613 | if (!dev_priv->allow_batchbuffer) { | |
614 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
615 | return DRM_ERR(EINVAL); | |
616 | } | |
617 | ||
618 | DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data, | |
619 | sizeof(batch)); | |
620 | ||
621 | DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", | |
622 | batch.start, batch.used, batch.num_cliprects); | |
623 | ||
624 | LOCK_TEST_WITH_RETURN(dev, filp); | |
625 | ||
626 | if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, | |
627 | batch.num_cliprects * | |
c60ce623 | 628 | sizeof(struct drm_clip_rect))) |
1da177e4 LT |
629 | return DRM_ERR(EFAULT); |
630 | ||
631 | ret = i915_dispatch_batchbuffer(dev, &batch); | |
632 | ||
633 | sarea_priv->last_dispatch = (int)hw_status[5]; | |
634 | return ret; | |
635 | } | |
636 | ||
c94f7029 | 637 | static int i915_cmdbuffer(DRM_IOCTL_ARGS) |
1da177e4 LT |
638 | { |
639 | DRM_DEVICE; | |
640 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
641 | u32 *hw_status = dev_priv->hw_status_page; | |
642 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) | |
643 | dev_priv->sarea_priv; | |
644 | drm_i915_cmdbuffer_t cmdbuf; | |
645 | int ret; | |
646 | ||
647 | DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data, | |
648 | sizeof(cmdbuf)); | |
649 | ||
650 | DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", | |
651 | cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects); | |
652 | ||
653 | LOCK_TEST_WITH_RETURN(dev, filp); | |
654 | ||
655 | if (cmdbuf.num_cliprects && | |
656 | DRM_VERIFYAREA_READ(cmdbuf.cliprects, | |
657 | cmdbuf.num_cliprects * | |
c60ce623 | 658 | sizeof(struct drm_clip_rect))) { |
1da177e4 LT |
659 | DRM_ERROR("Fault accessing cliprects\n"); |
660 | return DRM_ERR(EFAULT); | |
661 | } | |
662 | ||
663 | ret = i915_dispatch_cmdbuffer(dev, &cmdbuf); | |
664 | if (ret) { | |
665 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
666 | return ret; | |
667 | } | |
668 | ||
669 | sarea_priv->last_dispatch = (int)hw_status[5]; | |
670 | return 0; | |
671 | } | |
672 | ||
c94f7029 | 673 | static int i915_flip_bufs(DRM_IOCTL_ARGS) |
1da177e4 LT |
674 | { |
675 | DRM_DEVICE; | |
676 | ||
677 | DRM_DEBUG("%s\n", __FUNCTION__); | |
678 | ||
679 | LOCK_TEST_WITH_RETURN(dev, filp); | |
680 | ||
681 | return i915_dispatch_flip(dev); | |
682 | } | |
683 | ||
c94f7029 | 684 | static int i915_getparam(DRM_IOCTL_ARGS) |
1da177e4 LT |
685 | { |
686 | DRM_DEVICE; | |
687 | drm_i915_private_t *dev_priv = dev->dev_private; | |
688 | drm_i915_getparam_t param; | |
689 | int value; | |
690 | ||
691 | if (!dev_priv) { | |
692 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
693 | return DRM_ERR(EINVAL); | |
694 | } | |
695 | ||
696 | DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data, | |
697 | sizeof(param)); | |
698 | ||
699 | switch (param.param) { | |
700 | case I915_PARAM_IRQ_ACTIVE: | |
701 | value = dev->irq ? 1 : 0; | |
702 | break; | |
703 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
704 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
705 | break; | |
0d6aa60b DA |
706 | case I915_PARAM_LAST_DISPATCH: |
707 | value = READ_BREADCRUMB(dev_priv); | |
708 | break; | |
1da177e4 | 709 | default: |
de227f5f | 710 | DRM_ERROR("Unknown parameter %d\n", param.param); |
1da177e4 LT |
711 | return DRM_ERR(EINVAL); |
712 | } | |
713 | ||
714 | if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { | |
715 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); | |
716 | return DRM_ERR(EFAULT); | |
717 | } | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
c94f7029 | 722 | static int i915_setparam(DRM_IOCTL_ARGS) |
1da177e4 LT |
723 | { |
724 | DRM_DEVICE; | |
725 | drm_i915_private_t *dev_priv = dev->dev_private; | |
726 | drm_i915_setparam_t param; | |
727 | ||
728 | if (!dev_priv) { | |
729 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
730 | return DRM_ERR(EINVAL); | |
731 | } | |
732 | ||
733 | DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data, | |
734 | sizeof(param)); | |
735 | ||
736 | switch (param.param) { | |
737 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: | |
738 | dev_priv->use_mi_batchbuffer_start = param.value; | |
739 | break; | |
740 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
741 | dev_priv->tex_lru_log_granularity = param.value; | |
742 | break; | |
743 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
744 | dev_priv->allow_batchbuffer = param.value; | |
745 | break; | |
746 | default: | |
747 | DRM_ERROR("unknown parameter %d\n", param.param); | |
748 | return DRM_ERR(EINVAL); | |
749 | } | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
dc7a9319 WZ |
754 | static int i915_set_status_page(DRM_IOCTL_ARGS) |
755 | { | |
756 | DRM_DEVICE; | |
757 | drm_i915_private_t *dev_priv = dev->dev_private; | |
758 | drm_i915_hws_addr_t hws; | |
759 | ||
760 | if (!dev_priv) { | |
761 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
762 | return DRM_ERR(EINVAL); | |
763 | } | |
764 | DRM_COPY_FROM_USER_IOCTL(hws, (drm_i915_hws_addr_t __user *) data, | |
765 | sizeof(hws)); | |
766 | printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws.addr); | |
767 | ||
768 | dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12); | |
769 | ||
770 | dev_priv->hws_map.offset = dev->agp->agp_info.aper_base + hws.addr; | |
771 | dev_priv->hws_map.size = 4*1024; | |
772 | dev_priv->hws_map.type = 0; | |
773 | dev_priv->hws_map.flags = 0; | |
774 | dev_priv->hws_map.mtrr = 0; | |
775 | ||
776 | drm_core_ioremap(&dev_priv->hws_map, dev); | |
777 | if (dev_priv->hws_map.handle == NULL) { | |
778 | dev->dev_private = (void *)dev_priv; | |
779 | i915_dma_cleanup(dev); | |
780 | dev_priv->status_gfx_addr = 0; | |
781 | DRM_ERROR("can not ioremap virtual address for" | |
782 | " G33 hw status page\n"); | |
783 | return DRM_ERR(ENOMEM); | |
784 | } | |
785 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
786 | ||
787 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
788 | I915_WRITE(0x02080, dev_priv->status_gfx_addr); | |
789 | DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n", | |
790 | dev_priv->status_gfx_addr); | |
791 | DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); | |
792 | return 0; | |
793 | } | |
794 | ||
84b1fd10 | 795 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 DA |
796 | { |
797 | /* i915 has 4 more counters */ | |
798 | dev->counters += 4; | |
799 | dev->types[6] = _DRM_STAT_IRQ; | |
800 | dev->types[7] = _DRM_STAT_PRIMARY; | |
801 | dev->types[8] = _DRM_STAT_SECONDARY; | |
802 | dev->types[9] = _DRM_STAT_DMA; | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
84b1fd10 | 807 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 808 | { |
b5e89ed5 | 809 | if (dev->dev_private) { |
1da177e4 | 810 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e89ed5 DA |
811 | i915_mem_takedown(&(dev_priv->agp_heap)); |
812 | } | |
813 | i915_dma_cleanup(dev); | |
1da177e4 LT |
814 | } |
815 | ||
84b1fd10 | 816 | void i915_driver_preclose(struct drm_device * dev, DRMFILE filp) |
1da177e4 | 817 | { |
b5e89ed5 | 818 | if (dev->dev_private) { |
1da177e4 | 819 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 820 | i915_mem_release(dev, filp, dev_priv->agp_heap); |
1da177e4 LT |
821 | } |
822 | } | |
823 | ||
c94f7029 | 824 | drm_ioctl_desc_t i915_ioctls[] = { |
a7a2cc31 DA |
825 | [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, |
826 | [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH}, | |
827 | [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH}, | |
828 | [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH}, | |
829 | [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH}, | |
830 | [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH}, | |
831 | [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH}, | |
832 | [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | |
833 | [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH}, | |
834 | [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH}, | |
835 | [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | |
de227f5f | 836 | [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH}, |
702880f2 DA |
837 | [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY }, |
838 | [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY }, | |
839 | [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH }, | |
a6b54f3f | 840 | [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH}, |
dc7a9319 | 841 | [DRM_IOCTL_NR(DRM_I915_HWS_ADDR)] = {i915_set_status_page, DRM_AUTH}, |
c94f7029 DA |
842 | }; |
843 | ||
844 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
845 | |
846 | /** | |
847 | * Determine if the device really is AGP or not. | |
848 | * | |
849 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
850 | * PCI-e. | |
851 | * | |
852 | * \param dev The device to be tested. | |
853 | * | |
854 | * \returns | |
855 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
856 | */ | |
84b1fd10 | 857 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
858 | { |
859 | return 1; | |
860 | } |