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0d6aa60b | 1 | /* |
bc54fd1a DA |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial portions | |
15 | * of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
0d6aa60b | 25 | */ |
bc54fd1a | 26 | |
1da177e4 LT |
27 | #ifndef _I915_DRM_H_ |
28 | #define _I915_DRM_H_ | |
29 | ||
30 | /* Please note that modifications to all structs defined here are | |
31 | * subject to backwards-compatibility constraints. | |
32 | */ | |
33 | ||
34 | #include "drm.h" | |
35 | ||
36 | /* Each region is a minimum of 16k, and there are at most 255 of them. | |
37 | */ | |
38 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use | |
39 | * of chars for next/prev indices */ | |
40 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 | |
41 | ||
42 | typedef struct _drm_i915_init { | |
43 | enum { | |
44 | I915_INIT_DMA = 0x01, | |
45 | I915_CLEANUP_DMA = 0x02, | |
46 | I915_RESUME_DMA = 0x03 | |
47 | } func; | |
48 | unsigned int mmio_offset; | |
49 | int sarea_priv_offset; | |
50 | unsigned int ring_start; | |
51 | unsigned int ring_end; | |
52 | unsigned int ring_size; | |
53 | unsigned int front_offset; | |
54 | unsigned int back_offset; | |
55 | unsigned int depth_offset; | |
56 | unsigned int w; | |
57 | unsigned int h; | |
58 | unsigned int pitch; | |
59 | unsigned int pitch_bits; | |
60 | unsigned int back_pitch; | |
61 | unsigned int depth_pitch; | |
62 | unsigned int cpp; | |
63 | unsigned int chipset; | |
64 | } drm_i915_init_t; | |
65 | ||
66 | typedef struct _drm_i915_sarea { | |
67 | drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1]; | |
68 | int last_upload; /* last time texture was uploaded */ | |
69 | int last_enqueue; /* last time a buffer was enqueued */ | |
70 | int last_dispatch; /* age of the most recently dispatched buffer */ | |
71 | int ctxOwner; /* last context to upload state */ | |
72 | int texAge; | |
73 | int pf_enabled; /* is pageflipping allowed? */ | |
74 | int pf_active; | |
75 | int pf_current_page; /* which buffer is being displayed? */ | |
76 | int perf_boxes; /* performance boxes to be displayed */ | |
de227f5f DA |
77 | int width, height; /* screen size in pixels */ |
78 | ||
79 | drm_handle_t front_handle; | |
80 | int front_offset; | |
81 | int front_size; | |
82 | ||
83 | drm_handle_t back_handle; | |
84 | int back_offset; | |
85 | int back_size; | |
86 | ||
87 | drm_handle_t depth_handle; | |
88 | int depth_offset; | |
89 | int depth_size; | |
90 | ||
91 | drm_handle_t tex_handle; | |
92 | int tex_offset; | |
93 | int tex_size; | |
94 | int log_tex_granularity; | |
95 | int pitch; | |
96 | int rotation; /* 0, 90, 180 or 270 */ | |
97 | int rotated_offset; | |
98 | int rotated_size; | |
99 | int rotated_pitch; | |
100 | int virtualX, virtualY; | |
1da177e4 LT |
101 | } drm_i915_sarea_t; |
102 | ||
103 | /* Flags for perf_boxes | |
104 | */ | |
105 | #define I915_BOX_RING_EMPTY 0x1 | |
106 | #define I915_BOX_FLIP 0x2 | |
107 | #define I915_BOX_WAIT 0x4 | |
108 | #define I915_BOX_TEXTURE_LOAD 0x8 | |
109 | #define I915_BOX_LOST_CONTEXT 0x10 | |
110 | ||
111 | /* I915 specific ioctls | |
112 | * The device specific ioctl range is 0x40 to 0x79. | |
113 | */ | |
114 | #define DRM_I915_INIT 0x00 | |
115 | #define DRM_I915_FLUSH 0x01 | |
116 | #define DRM_I915_FLIP 0x02 | |
117 | #define DRM_I915_BATCHBUFFER 0x03 | |
118 | #define DRM_I915_IRQ_EMIT 0x04 | |
119 | #define DRM_I915_IRQ_WAIT 0x05 | |
120 | #define DRM_I915_GETPARAM 0x06 | |
121 | #define DRM_I915_SETPARAM 0x07 | |
122 | #define DRM_I915_ALLOC 0x08 | |
123 | #define DRM_I915_FREE 0x09 | |
124 | #define DRM_I915_INIT_HEAP 0x0a | |
125 | #define DRM_I915_CMDBUFFER 0x0b | |
de227f5f | 126 | #define DRM_I915_DESTROY_HEAP 0x0c |
1da177e4 LT |
127 | |
128 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
129 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | |
130 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) | |
131 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) | |
132 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) | |
133 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) | |
134 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) | |
135 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) | |
136 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) | |
137 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) | |
138 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | |
139 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | |
de227f5f | 140 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) |
1da177e4 LT |
141 | |
142 | /* Allow drivers to submit batchbuffers directly to hardware, relying | |
143 | * on the security mechanisms provided by hardware. | |
144 | */ | |
145 | typedef struct _drm_i915_batchbuffer { | |
146 | int start; /* agp offset */ | |
147 | int used; /* nr bytes in use */ | |
148 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
149 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
150 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
151 | drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ | |
152 | } drm_i915_batchbuffer_t; | |
153 | ||
154 | /* As above, but pass a pointer to userspace buffer which can be | |
155 | * validated by the kernel prior to sending to hardware. | |
156 | */ | |
157 | typedef struct _drm_i915_cmdbuffer { | |
158 | char __user *buf; /* pointer to userspace command buffer */ | |
159 | int sz; /* nr bytes in buf */ | |
160 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
161 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
162 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
163 | drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ | |
164 | } drm_i915_cmdbuffer_t; | |
165 | ||
166 | /* Userspace can request & wait on irq's: | |
167 | */ | |
168 | typedef struct drm_i915_irq_emit { | |
169 | int __user *irq_seq; | |
170 | } drm_i915_irq_emit_t; | |
171 | ||
172 | typedef struct drm_i915_irq_wait { | |
173 | int irq_seq; | |
174 | } drm_i915_irq_wait_t; | |
175 | ||
176 | /* Ioctl to query kernel params: | |
177 | */ | |
178 | #define I915_PARAM_IRQ_ACTIVE 1 | |
179 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 | |
0d6aa60b | 180 | #define I915_PARAM_LAST_DISPATCH 3 |
1da177e4 LT |
181 | |
182 | typedef struct drm_i915_getparam { | |
183 | int param; | |
184 | int __user *value; | |
185 | } drm_i915_getparam_t; | |
186 | ||
187 | /* Ioctl to set kernel params: | |
188 | */ | |
189 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 | |
190 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 | |
191 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 | |
192 | ||
193 | typedef struct drm_i915_setparam { | |
194 | int param; | |
195 | int value; | |
196 | } drm_i915_setparam_t; | |
197 | ||
198 | /* A memory manager for regions of shared memory: | |
199 | */ | |
200 | #define I915_MEM_REGION_AGP 1 | |
201 | ||
202 | typedef struct drm_i915_mem_alloc { | |
203 | int region; | |
204 | int alignment; | |
205 | int size; | |
206 | int __user *region_offset; /* offset from start of fb or agp */ | |
207 | } drm_i915_mem_alloc_t; | |
208 | ||
209 | typedef struct drm_i915_mem_free { | |
210 | int region; | |
211 | int region_offset; | |
212 | } drm_i915_mem_free_t; | |
213 | ||
214 | typedef struct drm_i915_mem_init_heap { | |
215 | int region; | |
216 | int size; | |
217 | int start; | |
218 | } drm_i915_mem_init_heap_t; | |
219 | ||
de227f5f DA |
220 | /* Allow memory manager to be torn down and re-initialized (eg on |
221 | * rotate): | |
222 | */ | |
223 | typedef struct drm_i915_mem_destroy_heap { | |
224 | int region; | |
225 | } drm_i915_mem_destroy_heap_t; | |
226 | ||
1da177e4 | 227 | #endif /* _I915_DRM_H_ */ |