[mirror_ubuntu-artful-kernel.git] / drivers / char / drm / i915_drv.c

/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
/*
 *
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"

#include "drm_pciids.h"

static struct pci_device_id pciidlist[] = {
	i915_PCI_IDS
};

enum pipe {
    PIPE_A = 0,
    PIPE_B,
};

static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (pipe == PIPE_A)
		return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
	else
		return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
}

static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
	u32 *array;
	int i;

	if (!i915_pipe_enabled(dev, pipe))
		return;

	if (pipe == PIPE_A)
		array = dev_priv->save_palette_a;
	else
		array = dev_priv->save_palette_b;

	for(i = 0; i < 256; i++)
		array[i] = I915_READ(reg + (i << 2));
}

static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
	u32 *array;
	int i;

	if (!i915_pipe_enabled(dev, pipe))
		return;

	if (pipe == PIPE_A)
		array = dev_priv->save_palette_a;
	else
		array = dev_priv->save_palette_b;

	for(i = 0; i < 256; i++)
		I915_WRITE(reg + (i << 2), array[i]);
}

static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
{
	outb(reg, index_port);
	return inb(data_port);
}

static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
{
	inb(st01);
	outb(palette_enable | reg, VGA_AR_INDEX);
	return inb(VGA_AR_DATA_READ);
}

static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
{
	inb(st01);
	outb(palette_enable | reg, VGA_AR_INDEX);
	outb(val, VGA_AR_DATA_WRITE);
}

static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
{
	outb(reg, index_port);
	outb(val, data_port);
}

static void i915_save_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
	u16 cr_index, cr_data, st01;

	/* VGA color palette registers */
	dev_priv->saveDACMASK = inb(VGA_DACMASK);
	/* DACCRX automatically increments during read */
	outb(0, VGA_DACRX);
	/* Read 3 bytes of color data from each index */
	for (i = 0; i < 256 * 3; i++)
		dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);

	/* MSR bits */
	dev_priv->saveMSR = inb(VGA_MSR_READ);
	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
		cr_index = VGA_CR_INDEX_CGA;
		cr_data = VGA_CR_DATA_CGA;
		st01 = VGA_ST01_CGA;
	} else {
		cr_index = VGA_CR_INDEX_MDA;
		cr_data = VGA_CR_DATA_MDA;
		st01 = VGA_ST01_MDA;
	}

	/* CRT controller regs */
	i915_write_indexed(cr_index, cr_data, 0x11,
			   i915_read_indexed(cr_index, cr_data, 0x11) &
			   (~0x80));
	for (i = 0; i < 0x24; i++)
		dev_priv->saveCR[i] =
			i915_read_indexed(cr_index, cr_data, i);
	/* Make sure we don't turn off CR group 0 writes */
	dev_priv->saveCR[0x11] &= ~0x80;

	/* Attribute controller registers */
	inb(st01);
	dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
	for (i = 0; i < 20; i++)
		dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
	inb(st01);
	outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
	inb(st01);

	/* Graphics controller registers */
	for (i = 0; i < 9; i++)
		dev_priv->saveGR[i] =
			i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);

	dev_priv->saveGR[0x10] =
		i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
	dev_priv->saveGR[0x11] =
		i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
	dev_priv->saveGR[0x18] =
		i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);

	/* Sequencer registers */
	for (i = 0; i < 8; i++)
		dev_priv->saveSR[i] =
			i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
}

static void i915_restore_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
	u16 cr_index, cr_data, st01;

	/* MSR bits */
	outb(dev_priv->saveMSR, VGA_MSR_WRITE);
	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
		cr_index = VGA_CR_INDEX_CGA;
		cr_data = VGA_CR_DATA_CGA;
		st01 = VGA_ST01_CGA;
	} else {
		cr_index = VGA_CR_INDEX_MDA;
		cr_data = VGA_CR_DATA_MDA;
		st01 = VGA_ST01_MDA;
	}

	/* Sequencer registers, don't write SR07 */
	for (i = 0; i < 7; i++)
		i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
				   dev_priv->saveSR[i]);

	/* CRT controller regs */
	/* Enable CR group 0 writes */
	i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
	for (i = 0; i < 0x24; i++)
		i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);

	/* Graphics controller regs */
	for (i = 0; i < 9; i++)
		i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
				   dev_priv->saveGR[i]);

	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
			   dev_priv->saveGR[0x10]);
	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
			   dev_priv->saveGR[0x11]);
	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
			   dev_priv->saveGR[0x18]);

	/* Attribute controller registers */
	for (i = 0; i < 20; i++)
		i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
	inb(st01); /* switch back to index mode */
	outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
	inb(st01);

	/* VGA color palette registers */
	outb(dev_priv->saveDACMASK, VGA_DACMASK);
	/* DACCRX automatically increments during read */
	outb(0, VGA_DACWX);
	/* Read 3 bytes of color data from each index */
	for (i = 0; i < 256 * 3; i++)
		outb(dev_priv->saveDACDATA[i], VGA_DACDATA);

}

static int i915_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	if (!dev || !dev_priv) {
		printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
		printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

	pci_save_state(dev->pdev);
	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);

	/* Pipe & plane A info */
	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
	dev_priv->saveFPA0 = I915_READ(FPA0);
	dev_priv->saveFPA1 = I915_READ(FPA1);
	dev_priv->saveDPLL_A = I915_READ(DPLL_A);
	if (IS_I965G(dev))
		dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
	dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
	dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
	dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
	dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
	dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
	dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);

	dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
	dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
	dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
	dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
	dev_priv->saveDSPABASE = I915_READ(DSPABASE);
	if (IS_I965G(dev)) {
		dev_priv->saveDSPASURF = I915_READ(DSPASURF);
		dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
	}
	i915_save_palette(dev, PIPE_A);
	dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);

	/* Pipe & plane B info */
	dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
	dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
	dev_priv->saveFPB0 = I915_READ(FPB0);
	dev_priv->saveFPB1 = I915_READ(FPB1);
	dev_priv->saveDPLL_B = I915_READ(DPLL_B);
	if (IS_I965G(dev))
		dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
	dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
	dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
	dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
	dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
	dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
	dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);

	dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
	dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
	dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
	dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
	dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
	if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
		dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
		dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
	}
	i915_save_palette(dev, PIPE_B);
	dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);

	/* CRT state */
	dev_priv->saveADPA = I915_READ(ADPA);

	/* LVDS state */
	dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
	dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
	dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
	if (IS_I965G(dev))
		dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
	if (IS_MOBILE(dev) && !IS_I830(dev))
		dev_priv->saveLVDS = I915_READ(LVDS);
	if (!IS_I830(dev) && !IS_845G(dev))
		dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
	dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
	dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
	dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);

	/* FIXME: save TV & SDVO state */

	/* FBC state */
	dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
	dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
	dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
	dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);

	/* Interrupt state */
	dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
	dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
	dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);

	/* VGA state */
	dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
	dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
	dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);

	/* Clock gating state */
	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);

	/* Cache mode state */
	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);

	/* Memory Arbitration state */
	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);

	/* Scratch space */
	for (i = 0; i < 16; i++) {
		dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
	}
	for (i = 0; i < 3; i++)
		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));

	i915_save_vga(dev);

	/* Shut down the device */
	pci_disable_device(dev->pdev);
	pci_set_power_state(dev->pdev, PCI_D3hot);

	return 0;
}

static int i915_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	pci_set_power_state(dev->pdev, PCI_D0);
	pci_restore_state(dev->pdev);
	if (pci_enable_device(dev->pdev))
		return -1;

	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);

	/* Pipe & plane A info */
	/* Prime the clock */
	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
		I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
			   ~DPLL_VCO_ENABLE);
		udelay(150);
	}
	I915_WRITE(FPA0, dev_priv->saveFPA0);
	I915_WRITE(FPA1, dev_priv->saveFPA1);
	/* Actually enable it */
	I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
	udelay(150);
	if (IS_I965G(dev))
		I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
	udelay(150);

	/* Restore mode */
	I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
	I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
	I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
	I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
	I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
	I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
	I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);

	/* Restore plane info */
	I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
	I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
	I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
	I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
	I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
	if (IS_I965G(dev)) {
		I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
		I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
	}

	I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);

	i915_restore_palette(dev, PIPE_A);
	/* Enable the plane */
	I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
	I915_WRITE(DSPABASE, I915_READ(DSPABASE));

	/* Pipe & plane B info */
	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
		I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
			   ~DPLL_VCO_ENABLE);
		udelay(150);
	}
	I915_WRITE(FPB0, dev_priv->saveFPB0);
	I915_WRITE(FPB1, dev_priv->saveFPB1);
	/* Actually enable it */
	I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
	udelay(150);
	if (IS_I965G(dev))
		I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
	udelay(150);

	/* Restore mode */
	I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
	I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
	I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
	I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
	I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
	I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
	I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);

	/* Restore plane info */
	I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
	I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
	I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
	I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
	I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
	if (IS_I965G(dev)) {
		I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
		I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
	}

	I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);

	i915_restore_palette(dev, PIPE_B);
	/* Enable the plane */
	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
	I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));

	/* CRT state */
	I915_WRITE(ADPA, dev_priv->saveADPA);

	/* LVDS state */
	if (IS_I965G(dev))
		I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
	if (IS_MOBILE(dev) && !IS_I830(dev))
		I915_WRITE(LVDS, dev_priv->saveLVDS);
	if (!IS_I830(dev) && !IS_845G(dev))
		I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);

	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
	I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
	I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
	I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
	I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
	I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);

	/* FIXME: restore TV & SDVO state */

	/* FBC info */
	I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
	I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
	I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
	I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);

	/* VGA state */
	I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
	I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
	I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
	I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
	udelay(150);

	/* Clock gating state */
	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);

	/* Cache mode state */
	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);

	/* Memory arbitration state */
	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);

	for (i = 0; i < 16; i++) {
		I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
		I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
	}
	for (i = 0; i < 3; i++)
		I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);

	i915_restore_vga(dev);

	return 0;
}

static struct drm_driver driver = {
	/* don't use mtrr's here, the Xserver or user space app should
	 * deal with them for intel hardware.
	 */
	.driver_features =
	    DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
	    DRIVER_IRQ_VBL2,
	.load = i915_driver_load,
	.unload = i915_driver_unload,
	.lastclose = i915_driver_lastclose,
	.preclose = i915_driver_preclose,
	.suspend = i915_suspend,
	.resume = i915_resume,
	.device_is_agp = i915_driver_device_is_agp,
	.vblank_wait = i915_driver_vblank_wait,
	.vblank_wait2 = i915_driver_vblank_wait2,
	.irq_preinstall = i915_driver_irq_preinstall,
	.irq_postinstall = i915_driver_irq_postinstall,
	.irq_uninstall = i915_driver_irq_uninstall,
	.irq_handler = i915_driver_irq_handler,
	.reclaim_buffers = drm_core_reclaim_buffers,
	.get_map_ofs = drm_core_get_map_ofs,
	.get_reg_ofs = drm_core_get_reg_ofs,
	.ioctls = i915_ioctls,
	.fops = {
		 .owner = THIS_MODULE,
		 .open = drm_open,
		 .release = drm_release,
		 .ioctl = drm_ioctl,
		 .mmap = drm_mmap,
		 .poll = drm_poll,
		 .fasync = drm_fasync,
#ifdef CONFIG_COMPAT
		 .compat_ioctl = i915_compat_ioctl,
#endif
	},

	.pci_driver = {
		 .name = DRIVER_NAME,
		 .id_table = pciidlist,
	},

	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
	.date = DRIVER_DATE,
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
};

static int __init i915_init(void)
{
	driver.num_ioctls = i915_max_ioctl;
	return drm_init(&driver);
}

static void __exit i915_exit(void)
{
	drm_exit(&driver);
}

module_init(i915_init);
module_exit(i915_exit);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
1da177e4 LT	1	/* i915_drv.c -- i830,i845,i855,i865,i915 driver -- linux-c --
1da177e4 LT	2	*/
0d6aa60b	3	/*
bc54fd1a	4	*
1da177e4 LT	5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
1da177e4 LT	6	* All Rights Reserved.
bc54fd1a DA	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the
	10	* "Software"), to deal in the Software without restriction, including
	11	* without limitation the rights to use, copy, modify, merge, publish,
	12	* distribute, sub license, and/or sell copies of the Software, and to
	13	* permit persons to whom the Software is furnished to do so, subject to
	14	* the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the
	17	* next paragraph) shall be included in all copies or substantial portions
	18	* of the Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	27	*
0d6aa60b	28	*/
1da177e4 LT	29
	30	#include "drmP.h"
	31	#include "drm.h"
	32	#include "i915_drm.h"
	33	#include "i915_drv.h"
	34
	35	#include "drm_pciids.h"
	36
1da177e4 LT	37	static struct pci_device_id pciidlist[] = {
	38	i915_PCI_IDS
	39	};
	40
ba8bbcf6 JB	41	enum pipe {
	42	PIPE_A = 0,
	43	PIPE_B,
	44	};
	45
	46	static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
	47	{
	48	struct drm_i915_private *dev_priv = dev->dev_private;
	49
	50	if (pipe == PIPE_A)
	51	return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
	52	else
	53	return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
	54	}
	55
	56	static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
	57	{
	58	struct drm_i915_private *dev_priv = dev->dev_private;
	59	unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
	60	u32 *array;
	61	int i;
	62
	63	if (!i915_pipe_enabled(dev, pipe))
	64	return;
	65
	66	if (pipe == PIPE_A)
	67	array = dev_priv->save_palette_a;
	68	else
	69	array = dev_priv->save_palette_b;
	70
	71	for(i = 0; i < 256; i++)
	72	array[i] = I915_READ(reg + (i << 2));
	73	}
	74
	75	static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
	76	{
	77	struct drm_i915_private *dev_priv = dev->dev_private;
	78	unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
	79	u32 *array;
	80	int i;
	81
	82	if (!i915_pipe_enabled(dev, pipe))
	83	return;
	84
	85	if (pipe == PIPE_A)
	86	array = dev_priv->save_palette_a;
	87	else
	88	array = dev_priv->save_palette_b;
	89
	90	for(i = 0; i < 256; i++)
	91	I915_WRITE(reg + (i << 2), array[i]);
	92	}
	93
	94	static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
	95	{
	96	outb(reg, index_port);
	97	return inb(data_port);
	98	}
	99
	100	static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
	101	{
	102	inb(st01);
	103	outb(palette_enable \| reg, VGA_AR_INDEX);
	104	return inb(VGA_AR_DATA_READ);
105	}
106
107	static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
108	{
109	inb(st01);
110	outb(palette_enable \| reg, VGA_AR_INDEX);
111	outb(val, VGA_AR_DATA_WRITE);
112	}
113
114	static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
115	{
116	outb(reg, index_port);
117	outb(val, data_port);
118	}
119
120	static void i915_save_vga(struct drm_device *dev)
121	{
122	struct drm_i915_private *dev_priv = dev->dev_private;
123	int i;
124	u16 cr_index, cr_data, st01;
125
126	/* VGA color palette registers */
127	dev_priv->saveDACMASK = inb(VGA_DACMASK);
128	/* DACCRX automatically increments during read */
129	outb(0, VGA_DACRX);
130	/* Read 3 bytes of color data from each index */
131	for (i = 0; i < 256 * 3; i++)
132	dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
133
134	/* MSR bits */
135	dev_priv->saveMSR = inb(VGA_MSR_READ);
136	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
137	cr_index = VGA_CR_INDEX_CGA;
138	cr_data = VGA_CR_DATA_CGA;
139	st01 = VGA_ST01_CGA;
140	} else {
141	cr_index = VGA_CR_INDEX_MDA;
142	cr_data = VGA_CR_DATA_MDA;
143	st01 = VGA_ST01_MDA;
144	}
145
146	/* CRT controller regs */
147	i915_write_indexed(cr_index, cr_data, 0x11,
148	i915_read_indexed(cr_index, cr_data, 0x11) &
149	(~0x80));
150	for (i = 0; i < 0x24; i++)
151	dev_priv->saveCR[i] =
152	i915_read_indexed(cr_index, cr_data, i);
153	/* Make sure we don't turn off CR group 0 writes */
154	dev_priv->saveCR[0x11] &= ~0x80;
155
156	/* Attribute controller registers */
157	inb(st01);
158	dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
159	for (i = 0; i < 20; i++)
160	dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
161	inb(st01);
162	outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
da636ad6	163	inb(st01);
ba8bbcf6 JB	164
	165	/* Graphics controller registers */
	166	for (i = 0; i < 9; i++)
	167	dev_priv->saveGR[i] =
	168	i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
	169
	170	dev_priv->saveGR[0x10] =
	171	i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
	172	dev_priv->saveGR[0x11] =
	173	i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
	174	dev_priv->saveGR[0x18] =
	175	i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
	176
	177	/* Sequencer registers */
	178	for (i = 0; i < 8; i++)
	179	dev_priv->saveSR[i] =
	180	i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
	181	}
	182
	183	static void i915_restore_vga(struct drm_device *dev)
	184	{
	185	struct drm_i915_private *dev_priv = dev->dev_private;
	186	int i;
	187	u16 cr_index, cr_data, st01;
	188
	189	/* MSR bits */
	190	outb(dev_priv->saveMSR, VGA_MSR_WRITE);
	191	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
	192	cr_index = VGA_CR_INDEX_CGA;
	193	cr_data = VGA_CR_DATA_CGA;
	194	st01 = VGA_ST01_CGA;
	195	} else {
	196	cr_index = VGA_CR_INDEX_MDA;
	197	cr_data = VGA_CR_DATA_MDA;
	198	st01 = VGA_ST01_MDA;
	199	}
	200
	201	/* Sequencer registers, don't write SR07 */
	202	for (i = 0; i < 7; i++)
	203	i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
	204	dev_priv->saveSR[i]);
	205
	206	/* CRT controller regs */
	207	/* Enable CR group 0 writes */
	208	i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
	209	for (i = 0; i < 0x24; i++)
	210	i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
	211
	212	/* Graphics controller regs */
	213	for (i = 0; i < 9; i++)
	214	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
	215	dev_priv->saveGR[i]);
	216
	217	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
	218	dev_priv->saveGR[0x10]);
	219	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
	220	dev_priv->saveGR[0x11]);
	221	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
	222	dev_priv->saveGR[0x18]);
	223
	224	/* Attribute controller registers */
	225	for (i = 0; i < 20; i++)
	226	i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
	227	inb(st01); /* switch back to index mode */
228	outb(dev_priv->saveAR_INDEX \| 0x20, VGA_AR_INDEX);
da636ad6	229	inb(st01);
ba8bbcf6 JB	230
	231	/* VGA color palette registers */
	232	outb(dev_priv->saveDACMASK, VGA_DACMASK);
	233	/* DACCRX automatically increments during read */
	234	outb(0, VGA_DACWX);
	235	/* Read 3 bytes of color data from each index */
	236	for (i = 0; i < 256 * 3; i++)
	237	outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
	238
	239	}
	240
	241	static int i915_suspend(struct drm_device *dev)
	242	{
	243	struct drm_i915_private *dev_priv = dev->dev_private;
	244	int i;
	245
	246	if (!dev \|\| !dev_priv) {
	247	printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
	248	printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
	249	return -ENODEV;
	250	}
	251
	252	pci_save_state(dev->pdev);
	253	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
	254
	255	/* Pipe & plane A info */
	256	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
	257	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
	258	dev_priv->saveFPA0 = I915_READ(FPA0);
	259	dev_priv->saveFPA1 = I915_READ(FPA1);
	260	dev_priv->saveDPLL_A = I915_READ(DPLL_A);
	261	if (IS_I965G(dev))
	262	dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
	263	dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
	264	dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
	265	dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
	266	dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
	267	dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
	268	dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
	269	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
	270
	271	dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
	272	dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
	273	dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
	274	dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
	275	dev_priv->saveDSPABASE = I915_READ(DSPABASE);
	276	if (IS_I965G(dev)) {
	277	dev_priv->saveDSPASURF = I915_READ(DSPASURF);
	278	dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
	279	}
	280	i915_save_palette(dev, PIPE_A);
0da3ea12	281	dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
ba8bbcf6 JB	282
	283	/* Pipe & plane B info */
	284	dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
	285	dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
	286	dev_priv->saveFPB0 = I915_READ(FPB0);
	287	dev_priv->saveFPB1 = I915_READ(FPB1);
	288	dev_priv->saveDPLL_B = I915_READ(DPLL_B);
	289	if (IS_I965G(dev))
	290	dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
	291	dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
	292	dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
	293	dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
	294	dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
	295	dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
	296	dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
	297	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
	298
	299	dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
	300	dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
	301	dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
	302	dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
	303	dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
5f5f9d4c	304	if (IS_I965GM(dev) \|\| IS_IGD_GM(dev)) {
ba8bbcf6 JB	305	dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
	306	dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
	307	}
	308	i915_save_palette(dev, PIPE_B);
0da3ea12	309	dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
ba8bbcf6 JB	310
	311	/* CRT state */
	312	dev_priv->saveADPA = I915_READ(ADPA);
	313
	314	/* LVDS state */
	315	dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
	316	dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
	317	dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
	318	if (IS_I965G(dev))
	319	dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
	320	if (IS_MOBILE(dev) && !IS_I830(dev))
	321	dev_priv->saveLVDS = I915_READ(LVDS);
	322	if (!IS_I830(dev) && !IS_845G(dev))
	323	dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
	324	dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
	325	dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
	326	dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
	327
	328	/* FIXME: save TV & SDVO state */
	329
	330	/* FBC state */
	331	dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
	332	dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
	333	dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
	334	dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
	335
0da3ea12 JB	336	/* Interrupt state */
	337	dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
	338	dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
	339	dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
	340
ba8bbcf6 JB	341	/* VGA state */
	342	dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
	343	dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
	344	dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
	345	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
	346
1f84e550 KP	347	/* Clock gating state */
	348	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
	349
	350	/* Cache mode state */
	351	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
	352
	353	/* Memory Arbitration state */
	354	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
	355
ba8bbcf6 JB	356	/* Scratch space */
	357	for (i = 0; i < 16; i++) {
	358	dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
	359	dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
	360	}
	361	for (i = 0; i < 3; i++)
	362	dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
	363
	364	i915_save_vga(dev);
	365
	366	/* Shut down the device */
	367	pci_disable_device(dev->pdev);
	368	pci_set_power_state(dev->pdev, PCI_D3hot);
	369
	370	return 0;
	371	}
	372
	373	static int i915_resume(struct drm_device *dev)
	374	{
	375	struct drm_i915_private *dev_priv = dev->dev_private;
	376	int i;
	377
	378	pci_set_power_state(dev->pdev, PCI_D0);
	379	pci_restore_state(dev->pdev);
	380	if (pci_enable_device(dev->pdev))
	381	return -1;
	382
	383	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
	384
	385	/* Pipe & plane A info */
	386	/* Prime the clock */
	387	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
	388	I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
	389	~DPLL_VCO_ENABLE);
	390	udelay(150);
	391	}
	392	I915_WRITE(FPA0, dev_priv->saveFPA0);
	393	I915_WRITE(FPA1, dev_priv->saveFPA1);
	394	/* Actually enable it */
	395	I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
	396	udelay(150);
	397	if (IS_I965G(dev))
	398	I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
	399	udelay(150);
	400
	401	/* Restore mode */
	402	I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
	403	I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
	404	I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
	405	I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
	406	I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
	407	I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
	408	I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
	409
	410	/* Restore plane info */
	411	I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
	412	I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
	413	I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
	414	I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
	415	I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
	416	if (IS_I965G(dev)) {
	417	I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
	418	I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
	419	}
420
c0c4261b	421	I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
ba8bbcf6 JB	422
	423	i915_restore_palette(dev, PIPE_A);
	424	/* Enable the plane */
	425	I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
	426	I915_WRITE(DSPABASE, I915_READ(DSPABASE));
	427
	428	/* Pipe & plane B info */
	429	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
	430	I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
	431	~DPLL_VCO_ENABLE);
	432	udelay(150);
	433	}
	434	I915_WRITE(FPB0, dev_priv->saveFPB0);
	435	I915_WRITE(FPB1, dev_priv->saveFPB1);
	436	/* Actually enable it */
	437	I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
	438	udelay(150);
	439	if (IS_I965G(dev))
	440	I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
	441	udelay(150);
	442
	443	/* Restore mode */
	444	I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
	445	I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
	446	I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
	447	I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
	448	I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
	449	I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
	450	I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
	451
	452	/* Restore plane info */
	453	I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
	454	I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
	455	I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
	456	I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
	457	I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
	458	if (IS_I965G(dev)) {
	459	I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
	460	I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
	461	}
	462
c0c4261b JB	463	I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
	464
	465	i915_restore_palette(dev, PIPE_B);
ba8bbcf6 JB	466	/* Enable the plane */
	467	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
	468	I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
	469
	470	/* CRT state */
	471	I915_WRITE(ADPA, dev_priv->saveADPA);
	472
	473	/* LVDS state */
	474	if (IS_I965G(dev))
	475	I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
	476	if (IS_MOBILE(dev) && !IS_I830(dev))
	477	I915_WRITE(LVDS, dev_priv->saveLVDS);
	478	if (!IS_I830(dev) && !IS_845G(dev))
	479	I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
	480
	481	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
	482	I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
	483	I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
	484	I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
	485	I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
	486	I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
	487
	488	/* FIXME: restore TV & SDVO state */
	489
	490	/* FBC info */
	491	I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
	492	I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
	493	I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
	494	I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
	495
	496	/* VGA state */
	497	I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
	498	I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
	499	I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
	500	I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
	501	udelay(150);
	502
1f84e550 KP	503	/* Clock gating state */
	504	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
	505
	506	/* Cache mode state */
	507	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 \| 0xffff0000);
	508
	509	/* Memory arbitration state */
	510	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE \| 0xffff0000);
	511
ba8bbcf6 JB	512	for (i = 0; i < 16; i++) {
	513	I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
	514	I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
	515	}
	516	for (i = 0; i < 3; i++)
	517	I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
	518
	519	i915_restore_vga(dev);
	520
	521	return 0;
	522	}
	523
1da177e4	524	static struct drm_driver driver = {
792d2b9a DA	525	/* don't use mtrr's here, the Xserver or user space app should
	526	* deal with them for intel hardware.
	527	*/
b5e89ed5	528	.driver_features =
792d2b9a	529	DRIVER_USE_AGP \| DRIVER_REQUIRE_AGP \| /* DRIVER_USE_MTRR \|*/
68815bad MD	530	DRIVER_HAVE_IRQ \| DRIVER_IRQ_SHARED \| DRIVER_IRQ_VBL \|
68815bad MD	531	DRIVER_IRQ_VBL2,
22eae947	532	.load = i915_driver_load,
ba8bbcf6	533	.unload = i915_driver_unload,
22eae947 DA	534	.lastclose = i915_driver_lastclose,
22eae947 DA	535	.preclose = i915_driver_preclose,
ba8bbcf6 JB	536	.suspend = i915_suspend,
ba8bbcf6 JB	537	.resume = i915_resume,
cda17380	538	.device_is_agp = i915_driver_device_is_agp,
0d6aa60b	539	.vblank_wait = i915_driver_vblank_wait,
68815bad	540	.vblank_wait2 = i915_driver_vblank_wait2,
1da177e4 LT	541	.irq_preinstall = i915_driver_irq_preinstall,
	542	.irq_postinstall = i915_driver_irq_postinstall,
	543	.irq_uninstall = i915_driver_irq_uninstall,
	544	.irq_handler = i915_driver_irq_handler,
	545	.reclaim_buffers = drm_core_reclaim_buffers,
	546	.get_map_ofs = drm_core_get_map_ofs,
	547	.get_reg_ofs = drm_core_get_reg_ofs,
1da177e4 LT	548	.ioctls = i915_ioctls,
1da177e4 LT	549	.fops = {
b5e89ed5 DA	550	.owner = THIS_MODULE,
	551	.open = drm_open,
	552	.release = drm_release,
	553	.ioctl = drm_ioctl,
	554	.mmap = drm_mmap,
	555	.poll = drm_poll,
	556	.fasync = drm_fasync,
8ca7c1df	557	#ifdef CONFIG_COMPAT
b5e89ed5	558	.compat_ioctl = i915_compat_ioctl,
8ca7c1df	559	#endif
22eae947 DA	560	},
22eae947 DA	561
1da177e4	562	.pci_driver = {
22eae947 DA	563	.name = DRIVER_NAME,
	564	.id_table = pciidlist,
	565	},
bc5f4523	566
22eae947 DA	567	.name = DRIVER_NAME,
	568	.desc = DRIVER_DESC,
	569	.date = DRIVER_DATE,
	570	.major = DRIVER_MAJOR,
	571	.minor = DRIVER_MINOR,
	572	.patchlevel = DRIVER_PATCHLEVEL,
1da177e4 LT	573	};
	574
	575	static int __init i915_init(void)
	576	{
	577	driver.num_ioctls = i915_max_ioctl;
	578	return drm_init(&driver);
	579	}
	580
	581	static void __exit i915_exit(void)
	582	{
	583	drm_exit(&driver);
	584	}
	585
	586	module_init(i915_init);
	587	module_exit(i915_exit);
	588
b5e89ed5 DA	589	MODULE_AUTHOR(DRIVER_AUTHOR);
b5e89ed5 DA	590	MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4	591	MODULE_LICENSE("GPL and additional rights");