[mirror_ubuntu-bionic-kernel.git] / drivers / char / drm / i915_drv.h

/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
/**************************************************************************
 *
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/

#ifndef _I915_DRV_H_
#define _I915_DRV_H_

/* General customization:
 */

#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
#define DRIVER_DATE		"20040405"

/* Interface history:
 *
 * 1.1: Original.
 */
#define DRIVER_MAJOR		1
#define DRIVER_MINOR		1
#define DRIVER_PATCHLEVEL	0

/* We use our own dma mechanisms, not the drm template code.  However,
 * the shared IRQ code is useful to us:
 */
#define __HAVE_PM		1

typedef struct _drm_i915_ring_buffer {
	int tail_mask;
	unsigned long Start;
	unsigned long End;
	unsigned long Size;
	u8 *virtual_start;
	int head;
	int tail;
	int space;
	drm_local_map_t map;
} drm_i915_ring_buffer_t;

struct mem_block {
	struct mem_block *next;
	struct mem_block *prev;
	int start;
	int size;
	DRMFILE filp;		/* 0: free, -1: heap, other: real files */
};

typedef struct drm_i915_private {
	drm_local_map_t *sarea;
	drm_local_map_t *mmio_map;

	drm_i915_sarea_t *sarea_priv;
	drm_i915_ring_buffer_t ring;

	drm_dma_handle_t *status_page_dmah;
	void *hw_status_page;
	dma_addr_t dma_status_page;
	unsigned long counter;

	int back_offset;
	int front_offset;
	int current_page;
	int page_flipping;
	int use_mi_batchbuffer_start;

	wait_queue_head_t irq_queue;
	atomic_t irq_received;
	atomic_t irq_emitted;

	int tex_lru_log_granularity;
	int allow_batchbuffer;
	struct mem_block *agp_heap;
} drm_i915_private_t;

				/* i915_dma.c */
extern void i915_kernel_lost_context(drm_device_t * dev);
extern void i915_driver_pretakedown(drm_device_t *dev);
extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp);
extern int i915_driver_device_is_agp(drm_device_t *dev);

/* i915_irq.c */
extern int i915_irq_emit(DRM_IOCTL_ARGS);
extern int i915_irq_wait(DRM_IOCTL_ARGS);

extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
extern void i915_driver_irq_preinstall(drm_device_t *dev);
extern void i915_driver_irq_postinstall(drm_device_t *dev);
extern void i915_driver_irq_uninstall(drm_device_t *dev);

/* i915_mem.c */
extern int i915_mem_alloc(DRM_IOCTL_ARGS);
extern int i915_mem_free(DRM_IOCTL_ARGS);
extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
extern void i915_mem_takedown(struct mem_block **heap);
extern void i915_mem_release(drm_device_t * dev,
			     DRMFILE filp, struct mem_block *heap);

extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);


#define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, reg)
#define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, reg, val)
#define I915_READ16(reg) 	DRM_READ16(dev_priv->mmio_map, reg)
#define I915_WRITE16(reg,val)	DRM_WRITE16(dev_priv->mmio_map, reg, val)

#define I915_VERBOSE 0

#define RING_LOCALS	unsigned int outring, ringmask, outcount; \
                        volatile char *virt;

#define BEGIN_LP_RING(n) do {				\
	if (I915_VERBOSE)				\
		DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",	\
			  n, __FUNCTION__);		\
	if (dev_priv->ring.space < n*4)			\
		i915_wait_ring(dev, n*4, __FUNCTION__);		\
	outcount = 0;					\
	outring = dev_priv->ring.tail;			\
	ringmask = dev_priv->ring.tail_mask;		\
	virt = dev_priv->ring.virtual_start;		\
} while (0)

#define OUT_RING(n) do {					\
	if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
	*(volatile unsigned int *)(virt + outring) = n;		\
        outcount++;						\
	outring += 4;						\
	outring &= ringmask;					\
} while (0)

#define ADVANCE_LP_RING() do {						\
	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
	dev_priv->ring.tail = outring;					\
	dev_priv->ring.space -= outcount * 4;				\
	I915_WRITE(LP_RING + RING_TAIL, outring);			\
} while(0)

extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);

#define GFX_OP_USER_INTERRUPT 		((0<<29)|(2<<23))
#define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
#define CMD_REPORT_HEAD			(7<<23)
#define CMD_STORE_DWORD_IDX		((0x21<<23) | 0x1)
#define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)

#define INST_PARSER_CLIENT   0x00000000
#define INST_OP_FLUSH        0x02000000
#define INST_FLUSH_MAP_CACHE 0x00000001

#define BB1_START_ADDR_MASK   (~0x7)
#define BB1_PROTECTED         (1<<0)
#define BB1_UNPROTECTED       (0<<0)
#define BB2_END_ADDR_MASK     (~0x7)

#define I915REG_HWSTAM		0x02098
#define I915REG_INT_IDENTITY_R	0x020a4
#define I915REG_INT_MASK_R 	0x020a8
#define I915REG_INT_ENABLE_R	0x020a0

#define SRX_INDEX		0x3c4
#define SRX_DATA		0x3c5
#define SR01			1
#define SR01_SCREEN_OFF 	(1<<5)

#define PPCR			0x61204
#define PPCR_ON			(1<<0)

#define ADPA			0x61100
#define ADPA_DPMS_MASK		(~(3<<10))
#define ADPA_DPMS_ON		(0<<10)
#define ADPA_DPMS_SUSPEND	(1<<10)
#define ADPA_DPMS_STANDBY	(2<<10)
#define ADPA_DPMS_OFF		(3<<10)

#define NOPID                   0x2094
#define LP_RING     		0x2030
#define HP_RING     		0x2040
#define RING_TAIL      		0x00
#define TAIL_ADDR		0x001FFFF8
#define RING_HEAD      		0x04
#define HEAD_WRAP_COUNT     	0xFFE00000
#define HEAD_WRAP_ONE       	0x00200000
#define HEAD_ADDR           	0x001FFFFC
#define RING_START     		0x08
#define START_ADDR          	0x0xFFFFF000
#define RING_LEN       		0x0C
#define RING_NR_PAGES       	0x001FF000
#define RING_REPORT_MASK    	0x00000006
#define RING_REPORT_64K     	0x00000002
#define RING_REPORT_128K    	0x00000004
#define RING_NO_REPORT      	0x00000000
#define RING_VALID_MASK     	0x00000001
#define RING_VALID          	0x00000001
#define RING_INVALID        	0x00000000

#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define SC_UPDATE_SCISSOR       (0x1<<1)
#define SC_ENABLE_MASK          (0x1<<0)
#define SC_ENABLE               (0x1<<0)

#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
#define SCI_YMIN_MASK      (0xffff<<16)
#define SCI_XMIN_MASK      (0xffff<<0)
#define SCI_YMAX_MASK      (0xffff<<16)
#define SCI_XMAX_MASK      (0xffff<<0)

#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))

#define MI_BATCH_BUFFER 	((0x30<<23)|1)
#define MI_BATCH_BUFFER_START 	(0x31<<23)
#define MI_BATCH_BUFFER_END 	(0xA<<23)
#define MI_BATCH_NON_SECURE	(1)

#define MI_WAIT_FOR_EVENT       ((0x3<<23))
#define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)

#define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))

#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
#define ASYNC_FLIP                (1<<22)

#define CMD_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)

#endif
Commit	Line	Data
1da177e4 LT	1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --
	2	*/
	3	/**************************************************************************
bc54fd1a	4	*
1da177e4 LT	5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
1da177e4 LT	6	* All Rights Reserved.
bc54fd1a DA	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the
	10	* "Software"), to deal in the Software without restriction, including
	11	* without limitation the rights to use, copy, modify, merge, publish,
	12	* distribute, sub license, and/or sell copies of the Software, and to
	13	* permit persons to whom the Software is furnished to do so, subject to
	14	* the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the
	17	* next paragraph) shall be included in all copies or substantial portions
	18	* of the Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	27	*
1da177e4 LT	28	**************************************************************************/
	29
	30	#ifndef _I915_DRV_H_
	31	#define _I915_DRV_H_
	32
	33	/* General customization:
	34	*/
	35
	36	#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
	37
	38	#define DRIVER_NAME "i915"
	39	#define DRIVER_DESC "Intel Graphics"
	40	#define DRIVER_DATE "20040405"
	41
	42	/* Interface history:
	43	*
	44	* 1.1: Original.
	45	*/
	46	#define DRIVER_MAJOR 1
	47	#define DRIVER_MINOR 1
	48	#define DRIVER_PATCHLEVEL 0
	49
	50	/* We use our own dma mechanisms, not the drm template code. However,
	51	* the shared IRQ code is useful to us:
	52	*/
	53	#define __HAVE_PM 1
	54
	55	typedef struct _drm_i915_ring_buffer {
	56	int tail_mask;
	57	unsigned long Start;
	58	unsigned long End;
	59	unsigned long Size;
	60	u8 *virtual_start;
	61	int head;
	62	int tail;
	63	int space;
	64	drm_local_map_t map;
	65	} drm_i915_ring_buffer_t;
	66
	67	struct mem_block {
	68	struct mem_block *next;
	69	struct mem_block *prev;
	70	int start;
	71	int size;
	72	DRMFILE filp; /* 0: free, -1: heap, other: real files */
	73	};
	74
	75	typedef struct drm_i915_private {
	76	drm_local_map_t *sarea;
	77	drm_local_map_t *mmio_map;
	78
	79	drm_i915_sarea_t *sarea_priv;
	80	drm_i915_ring_buffer_t ring;
	81
9c8da5eb	82	drm_dma_handle_t *status_page_dmah;
1da177e4	83	void *hw_status_page;
1da177e4	84	dma_addr_t dma_status_page;
9c8da5eb	85	unsigned long counter;
1da177e4 LT	86
	87	int back_offset;
	88	int front_offset;
	89	int current_page;
	90	int page_flipping;
	91	int use_mi_batchbuffer_start;
	92
	93	wait_queue_head_t irq_queue;
	94	atomic_t irq_received;
	95	atomic_t irq_emitted;
	96
	97	int tex_lru_log_granularity;
	98	int allow_batchbuffer;
	99	struct mem_block *agp_heap;
	100	} drm_i915_private_t;
	101
	102	/* i915_dma.c */
1da177e4 LT	103	extern void i915_kernel_lost_context(drm_device_t * dev);
	104	extern void i915_driver_pretakedown(drm_device_t *dev);
	105	extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp);
cda17380	106	extern int i915_driver_device_is_agp(drm_device_t *dev);
1da177e4 LT	107
	108	/* i915_irq.c */
	109	extern int i915_irq_emit(DRM_IOCTL_ARGS);
	110	extern int i915_irq_wait(DRM_IOCTL_ARGS);
1da177e4 LT	111
	112	extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
	113	extern void i915_driver_irq_preinstall(drm_device_t *dev);
	114	extern void i915_driver_irq_postinstall(drm_device_t *dev);
	115	extern void i915_driver_irq_uninstall(drm_device_t *dev);
	116
	117	/* i915_mem.c */
	118	extern int i915_mem_alloc(DRM_IOCTL_ARGS);
	119	extern int i915_mem_free(DRM_IOCTL_ARGS);
	120	extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
	121	extern void i915_mem_takedown(struct mem_block **heap);
	122	extern void i915_mem_release(drm_device_t * dev,
	123	DRMFILE filp, struct mem_block *heap);
	124
8ca7c1df	125	extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
f179bc77	126	unsigned long arg);
8ca7c1df DA	127
8ca7c1df DA	128
1da177e4 LT	129	#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
	130	#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
	131	#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
	132	#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val)
	133
	134	#define I915_VERBOSE 0
	135
	136	#define RING_LOCALS unsigned int outring, ringmask, outcount; \
	137	volatile char *virt;
	138
	139	#define BEGIN_LP_RING(n) do { \
	140	if (I915_VERBOSE) \
	141	DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
	142	n, __FUNCTION__); \
	143	if (dev_priv->ring.space < n*4) \
	144	i915_wait_ring(dev, n*4, __FUNCTION__); \
	145	outcount = 0; \
	146	outring = dev_priv->ring.tail; \
	147	ringmask = dev_priv->ring.tail_mask; \
	148	virt = dev_priv->ring.virtual_start; \
	149	} while (0)
	150
	151	#define OUT_RING(n) do { \
	152	if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
	153	(volatile unsigned int )(virt + outring) = n; \
	154	outcount++; \
	155	outring += 4; \
	156	outring &= ringmask; \
	157	} while (0)
	158
	159	#define ADVANCE_LP_RING() do { \
	160	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
	161	dev_priv->ring.tail = outring; \
	162	dev_priv->ring.space -= outcount * 4; \
	163	I915_WRITE(LP_RING + RING_TAIL, outring); \
	164	} while(0)
	165
	166	extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
	167
	168	#define GFX_OP_USER_INTERRUPT ((0<<29)\|(2<<23))
	169	#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)\|(1<<23))
	170	#define CMD_REPORT_HEAD (7<<23)
	171	#define CMD_STORE_DWORD_IDX ((0x21<<23) \| 0x1)
	172	#define CMD_OP_BATCH_BUFFER ((0x0<<29)\|(0x30<<23)\|0x1)
	173
	174	#define INST_PARSER_CLIENT 0x00000000
	175	#define INST_OP_FLUSH 0x02000000
	176	#define INST_FLUSH_MAP_CACHE 0x00000001
	177
	178	#define BB1_START_ADDR_MASK (~0x7)
	179	#define BB1_PROTECTED (1<<0)
	180	#define BB1_UNPROTECTED (0<<0)
	181	#define BB2_END_ADDR_MASK (~0x7)
	182
	183	#define I915REG_HWSTAM 0x02098
	184	#define I915REG_INT_IDENTITY_R 0x020a4
	185	#define I915REG_INT_MASK_R 0x020a8
	186	#define I915REG_INT_ENABLE_R 0x020a0
	187
	188	#define SRX_INDEX 0x3c4
	189	#define SRX_DATA 0x3c5
	190	#define SR01 1
	191	#define SR01_SCREEN_OFF (1<<5)
	192
193	#define PPCR 0x61204
194	#define PPCR_ON (1<<0)
195
196	#define ADPA 0x61100
197	#define ADPA_DPMS_MASK (~(3<<10))
198	#define ADPA_DPMS_ON (0<<10)
199	#define ADPA_DPMS_SUSPEND (1<<10)
200	#define ADPA_DPMS_STANDBY (2<<10)
201	#define ADPA_DPMS_OFF (3<<10)
202
203	#define NOPID 0x2094
204	#define LP_RING 0x2030
205	#define HP_RING 0x2040
206	#define RING_TAIL 0x00
207	#define TAIL_ADDR 0x001FFFF8
208	#define RING_HEAD 0x04
209	#define HEAD_WRAP_COUNT 0xFFE00000
210	#define HEAD_WRAP_ONE 0x00200000
211	#define HEAD_ADDR 0x001FFFFC
212	#define RING_START 0x08
213	#define START_ADDR 0x0xFFFFF000
214	#define RING_LEN 0x0C
215	#define RING_NR_PAGES 0x001FF000
216	#define RING_REPORT_MASK 0x00000006
217	#define RING_REPORT_64K 0x00000002
218	#define RING_REPORT_128K 0x00000004
219	#define RING_NO_REPORT 0x00000000
220	#define RING_VALID_MASK 0x00000001
221	#define RING_VALID 0x00000001
222	#define RING_INVALID 0x00000000
223
224	#define GFX_OP_SCISSOR ((0x3<<29)\|(0x1c<<24)\|(0x10<<19))
225	#define SC_UPDATE_SCISSOR (0x1<<1)
226	#define SC_ENABLE_MASK (0x1<<0)
227	#define SC_ENABLE (0x1<<0)
228
229	#define GFX_OP_SCISSOR_INFO ((0x3<<29)\|(0x1d<<24)\|(0x81<<16)\|(0x1))
230	#define SCI_YMIN_MASK (0xffff<<16)
231	#define SCI_XMIN_MASK (0xffff<<0)
232	#define SCI_YMAX_MASK (0xffff<<16)
233	#define SCI_XMAX_MASK (0xffff<<0)
234
235	#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)\|(0x1c<<24)\|(0x10<<19))
236	#define GFX_OP_SCISSOR_RECT ((0x3<<29)\|(0x1d<<24)\|(0x81<<16)\|1)
237	#define GFX_OP_COLOR_FACTOR ((0x3<<29)\|(0x1d<<24)\|(0x1<<16)\|0x0)
238	#define GFX_OP_STIPPLE ((0x3<<29)\|(0x1d<<24)\|(0x83<<16))
239	#define GFX_OP_MAP_INFO ((0x3<<29)\|(0x1d<<24)\|0x4)
240	#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)\|(0x1d<<24)\|(0x85<<16)\|0x0)
241	#define GFX_OP_DRAWRECT_INFO ((0x3<<29)\|(0x1d<<24)\|(0x80<<16)\|(0x3))
242
243	#define MI_BATCH_BUFFER ((0x30<<23)\|1)
244	#define MI_BATCH_BUFFER_START (0x31<<23)
245	#define MI_BATCH_BUFFER_END (0xA<<23)
246	#define MI_BATCH_NON_SECURE (1)
247
248	#define MI_WAIT_FOR_EVENT ((0x3<<23))
249	#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
250	#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
251
252	#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
253
254	#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)\|(0x14<<23)\|2)
255	#define ASYNC_FLIP (1<<22)
256
257	#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)\|(0x1d<<24)\|(0x8e<<16)\|1)
258
259	#endif