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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
33 | /* General customization: | |
34 | */ | |
35 | ||
36 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
37 | ||
38 | #define DRIVER_NAME "i915" | |
39 | #define DRIVER_DESC "Intel Graphics" | |
de227f5f | 40 | #define DRIVER_DATE "20060119" |
1da177e4 LT |
41 | |
42 | /* Interface history: | |
43 | * | |
44 | * 1.1: Original. | |
0d6aa60b DA |
45 | * 1.2: Add Power Management |
46 | * 1.3: Add vblank support | |
de227f5f | 47 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 48 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
49 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
50 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
51 | */ |
52 | #define DRIVER_MAJOR 1 | |
2228ed67 | 53 | #define DRIVER_MINOR 6 |
1da177e4 LT |
54 | #define DRIVER_PATCHLEVEL 0 |
55 | ||
1da177e4 LT |
56 | typedef struct _drm_i915_ring_buffer { |
57 | int tail_mask; | |
58 | unsigned long Start; | |
59 | unsigned long End; | |
60 | unsigned long Size; | |
61 | u8 *virtual_start; | |
62 | int head; | |
63 | int tail; | |
64 | int space; | |
65 | drm_local_map_t map; | |
66 | } drm_i915_ring_buffer_t; | |
67 | ||
68 | struct mem_block { | |
69 | struct mem_block *next; | |
70 | struct mem_block *prev; | |
71 | int start; | |
72 | int size; | |
6c340eac | 73 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
74 | }; |
75 | ||
a6b54f3f MD |
76 | typedef struct _drm_i915_vbl_swap { |
77 | struct list_head head; | |
78 | drm_drawable_t drw_id; | |
79 | unsigned int pipe; | |
80 | unsigned int sequence; | |
81 | } drm_i915_vbl_swap_t; | |
82 | ||
1da177e4 LT |
83 | typedef struct drm_i915_private { |
84 | drm_local_map_t *sarea; | |
85 | drm_local_map_t *mmio_map; | |
86 | ||
87 | drm_i915_sarea_t *sarea_priv; | |
88 | drm_i915_ring_buffer_t ring; | |
89 | ||
9c8da5eb | 90 | drm_dma_handle_t *status_page_dmah; |
1da177e4 | 91 | void *hw_status_page; |
1da177e4 | 92 | dma_addr_t dma_status_page; |
9c8da5eb | 93 | unsigned long counter; |
dc7a9319 WZ |
94 | unsigned int status_gfx_addr; |
95 | drm_local_map_t hws_map; | |
1da177e4 | 96 | |
a6b54f3f | 97 | unsigned int cpp; |
1da177e4 LT |
98 | int back_offset; |
99 | int front_offset; | |
100 | int current_page; | |
101 | int page_flipping; | |
102 | int use_mi_batchbuffer_start; | |
103 | ||
104 | wait_queue_head_t irq_queue; | |
105 | atomic_t irq_received; | |
106 | atomic_t irq_emitted; | |
107 | ||
108 | int tex_lru_log_granularity; | |
109 | int allow_batchbuffer; | |
110 | struct mem_block *agp_heap; | |
0d6aa60b | 111 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 112 | int vblank_pipe; |
a6b54f3f MD |
113 | |
114 | spinlock_t swaps_lock; | |
115 | drm_i915_vbl_swap_t vbl_swaps; | |
116 | unsigned int swaps_pending; | |
1da177e4 LT |
117 | } drm_i915_private_t; |
118 | ||
b3a83639 DA |
119 | extern drm_ioctl_desc_t i915_ioctls[]; |
120 | extern int i915_max_ioctl; | |
121 | ||
1da177e4 | 122 | /* i915_dma.c */ |
84b1fd10 | 123 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 124 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
84b1fd10 | 125 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
126 | extern void i915_driver_preclose(struct drm_device *dev, |
127 | struct drm_file *file_priv); | |
84b1fd10 | 128 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
129 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
130 | unsigned long arg); | |
1da177e4 LT |
131 | |
132 | /* i915_irq.c */ | |
133 | extern int i915_irq_emit(DRM_IOCTL_ARGS); | |
134 | extern int i915_irq_wait(DRM_IOCTL_ARGS); | |
1da177e4 | 135 | |
84b1fd10 DA |
136 | extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence); |
137 | extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); | |
1da177e4 | 138 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); |
84b1fd10 DA |
139 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
140 | extern void i915_driver_irq_postinstall(struct drm_device * dev); | |
141 | extern void i915_driver_irq_uninstall(struct drm_device * dev); | |
702880f2 DA |
142 | extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS); |
143 | extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS); | |
a6b54f3f | 144 | extern int i915_vblank_swap(DRM_IOCTL_ARGS); |
1da177e4 LT |
145 | |
146 | /* i915_mem.c */ | |
147 | extern int i915_mem_alloc(DRM_IOCTL_ARGS); | |
148 | extern int i915_mem_free(DRM_IOCTL_ARGS); | |
149 | extern int i915_mem_init_heap(DRM_IOCTL_ARGS); | |
de227f5f | 150 | extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); |
1da177e4 | 151 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 152 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 153 | struct drm_file *file_priv, struct mem_block *heap); |
1da177e4 | 154 | |
0d6aa60b DA |
155 | #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) |
156 | #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) | |
157 | #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) | |
158 | #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) | |
1da177e4 LT |
159 | |
160 | #define I915_VERBOSE 0 | |
161 | ||
162 | #define RING_LOCALS unsigned int outring, ringmask, outcount; \ | |
163 | volatile char *virt; | |
164 | ||
165 | #define BEGIN_LP_RING(n) do { \ | |
166 | if (I915_VERBOSE) \ | |
167 | DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \ | |
c29b669c AH |
168 | (n), __FUNCTION__); \ |
169 | if (dev_priv->ring.space < (n)*4) \ | |
170 | i915_wait_ring(dev, (n)*4, __FUNCTION__); \ | |
1da177e4 LT |
171 | outcount = 0; \ |
172 | outring = dev_priv->ring.tail; \ | |
173 | ringmask = dev_priv->ring.tail_mask; \ | |
174 | virt = dev_priv->ring.virtual_start; \ | |
175 | } while (0) | |
176 | ||
177 | #define OUT_RING(n) do { \ | |
178 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ | |
c29b669c | 179 | *(volatile unsigned int *)(virt + outring) = (n); \ |
1da177e4 LT |
180 | outcount++; \ |
181 | outring += 4; \ | |
182 | outring &= ringmask; \ | |
183 | } while (0) | |
184 | ||
185 | #define ADVANCE_LP_RING() do { \ | |
186 | if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ | |
187 | dev_priv->ring.tail = outring; \ | |
188 | dev_priv->ring.space -= outcount * 4; \ | |
189 | I915_WRITE(LP_RING + RING_TAIL, outring); \ | |
190 | } while(0) | |
191 | ||
84b1fd10 | 192 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
1da177e4 LT |
193 | |
194 | #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) | |
195 | #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) | |
196 | #define CMD_REPORT_HEAD (7<<23) | |
197 | #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) | |
198 | #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) | |
199 | ||
200 | #define INST_PARSER_CLIENT 0x00000000 | |
201 | #define INST_OP_FLUSH 0x02000000 | |
202 | #define INST_FLUSH_MAP_CACHE 0x00000001 | |
203 | ||
204 | #define BB1_START_ADDR_MASK (~0x7) | |
205 | #define BB1_PROTECTED (1<<0) | |
206 | #define BB1_UNPROTECTED (0<<0) | |
207 | #define BB2_END_ADDR_MASK (~0x7) | |
208 | ||
209 | #define I915REG_HWSTAM 0x02098 | |
210 | #define I915REG_INT_IDENTITY_R 0x020a4 | |
211 | #define I915REG_INT_MASK_R 0x020a8 | |
212 | #define I915REG_INT_ENABLE_R 0x020a0 | |
213 | ||
e4a7b1d1 DA |
214 | #define I915REG_PIPEASTAT 0x70024 |
215 | #define I915REG_PIPEBSTAT 0x71024 | |
216 | ||
217 | #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) | |
218 | #define I915_VBLANK_CLEAR (1UL<<1) | |
219 | ||
1da177e4 LT |
220 | #define SRX_INDEX 0x3c4 |
221 | #define SRX_DATA 0x3c5 | |
222 | #define SR01 1 | |
223 | #define SR01_SCREEN_OFF (1<<5) | |
224 | ||
225 | #define PPCR 0x61204 | |
226 | #define PPCR_ON (1<<0) | |
227 | ||
0d6aa60b DA |
228 | #define DVOB 0x61140 |
229 | #define DVOB_ON (1<<31) | |
230 | #define DVOC 0x61160 | |
231 | #define DVOC_ON (1<<31) | |
232 | #define LVDS 0x61180 | |
233 | #define LVDS_ON (1<<31) | |
234 | ||
1da177e4 LT |
235 | #define ADPA 0x61100 |
236 | #define ADPA_DPMS_MASK (~(3<<10)) | |
237 | #define ADPA_DPMS_ON (0<<10) | |
238 | #define ADPA_DPMS_SUSPEND (1<<10) | |
239 | #define ADPA_DPMS_STANDBY (2<<10) | |
240 | #define ADPA_DPMS_OFF (3<<10) | |
241 | ||
242 | #define NOPID 0x2094 | |
243 | #define LP_RING 0x2030 | |
244 | #define HP_RING 0x2040 | |
245 | #define RING_TAIL 0x00 | |
246 | #define TAIL_ADDR 0x001FFFF8 | |
247 | #define RING_HEAD 0x04 | |
248 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
249 | #define HEAD_WRAP_ONE 0x00200000 | |
250 | #define HEAD_ADDR 0x001FFFFC | |
251 | #define RING_START 0x08 | |
252 | #define START_ADDR 0x0xFFFFF000 | |
253 | #define RING_LEN 0x0C | |
254 | #define RING_NR_PAGES 0x001FF000 | |
255 | #define RING_REPORT_MASK 0x00000006 | |
256 | #define RING_REPORT_64K 0x00000002 | |
257 | #define RING_REPORT_128K 0x00000004 | |
258 | #define RING_NO_REPORT 0x00000000 | |
259 | #define RING_VALID_MASK 0x00000001 | |
260 | #define RING_VALID 0x00000001 | |
261 | #define RING_INVALID 0x00000000 | |
262 | ||
263 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
264 | #define SC_UPDATE_SCISSOR (0x1<<1) | |
265 | #define SC_ENABLE_MASK (0x1<<0) | |
266 | #define SC_ENABLE (0x1<<0) | |
267 | ||
268 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) | |
269 | #define SCI_YMIN_MASK (0xffff<<16) | |
270 | #define SCI_XMIN_MASK (0xffff<<0) | |
271 | #define SCI_YMAX_MASK (0xffff<<16) | |
272 | #define SCI_XMAX_MASK (0xffff<<0) | |
273 | ||
274 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
275 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) | |
276 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) | |
277 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) | |
278 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) | |
279 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) | |
280 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) | |
281 | ||
c29b669c AH |
282 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) |
283 | ||
a6b54f3f MD |
284 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
285 | #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) | |
286 | #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) | |
287 | ||
1da177e4 LT |
288 | #define MI_BATCH_BUFFER ((0x30<<23)|1) |
289 | #define MI_BATCH_BUFFER_START (0x31<<23) | |
290 | #define MI_BATCH_BUFFER_END (0xA<<23) | |
291 | #define MI_BATCH_NON_SECURE (1) | |
21f16289 | 292 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
1da177e4 LT |
293 | |
294 | #define MI_WAIT_FOR_EVENT ((0x3<<23)) | |
295 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) | |
296 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) | |
297 | ||
298 | #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) | |
299 | ||
300 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) | |
301 | #define ASYNC_FLIP (1<<22) | |
302 | ||
303 | #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) | |
304 | ||
0d6aa60b DA |
305 | #define READ_BREADCRUMB(dev_priv) (((u32 *)(dev_priv->hw_status_page))[5]) |
306 | ||
1da177e4 | 307 | #endif |