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1da177e4 LT |
1 | /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- |
2 | * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com | |
3 | * | |
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
6795c985 DA |
26 | */ |
27 | ||
28 | /** | |
29 | * \file mga_dma.c | |
30 | * DMA support for MGA G200 / G400. | |
b5e89ed5 | 31 | * |
6795c985 DA |
32 | * \author Rickard E. (Rik) Faith <faith@valinux.com> |
33 | * \author Jeff Hartmann <jhartmann@valinux.com> | |
34 | * \author Keith Whitwell <keith@tungstengraphics.com> | |
35 | * \author Gareth Hughes <gareth@valinux.com> | |
1da177e4 LT |
36 | */ |
37 | ||
38 | #include "drmP.h" | |
39 | #include "drm.h" | |
6795c985 | 40 | #include "drm_sarea.h" |
1da177e4 LT |
41 | #include "mga_drm.h" |
42 | #include "mga_drv.h" | |
43 | ||
44 | #define MGA_DEFAULT_USEC_TIMEOUT 10000 | |
45 | #define MGA_FREELIST_DEBUG 0 | |
46 | ||
b5e89ed5 | 47 | static int mga_do_cleanup_dma(drm_device_t * dev); |
1da177e4 LT |
48 | |
49 | /* ================================================================ | |
50 | * Engine control | |
51 | */ | |
52 | ||
b5e89ed5 | 53 | int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) |
1da177e4 LT |
54 | { |
55 | u32 status = 0; | |
56 | int i; | |
b5e89ed5 | 57 | DRM_DEBUG("\n"); |
1da177e4 | 58 | |
b5e89ed5 DA |
59 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
60 | status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; | |
61 | if (status == MGA_ENDPRDMASTS) { | |
62 | MGA_WRITE8(MGA_CRTC_INDEX, 0); | |
1da177e4 LT |
63 | return 0; |
64 | } | |
b5e89ed5 | 65 | DRM_UDELAY(1); |
1da177e4 LT |
66 | } |
67 | ||
68 | #if MGA_DMA_DEBUG | |
b5e89ed5 DA |
69 | DRM_ERROR("failed!\n"); |
70 | DRM_INFO(" status=0x%08x\n", status); | |
1da177e4 LT |
71 | #endif |
72 | return DRM_ERR(EBUSY); | |
73 | } | |
74 | ||
b5e89ed5 | 75 | static int mga_do_dma_reset(drm_mga_private_t * dev_priv) |
1da177e4 LT |
76 | { |
77 | drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
78 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
79 | ||
b5e89ed5 | 80 | DRM_DEBUG("\n"); |
1da177e4 LT |
81 | |
82 | /* The primary DMA stream should look like new right about now. | |
83 | */ | |
84 | primary->tail = 0; | |
85 | primary->space = primary->size; | |
86 | primary->last_flush = 0; | |
87 | ||
88 | sarea_priv->last_wrap = 0; | |
89 | ||
90 | /* FIXME: Reset counters, buffer ages etc... | |
91 | */ | |
92 | ||
93 | /* FIXME: What else do we need to reinitialize? WARP stuff? | |
94 | */ | |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | /* ================================================================ | |
100 | * Primary DMA stream | |
101 | */ | |
102 | ||
b5e89ed5 | 103 | void mga_do_dma_flush(drm_mga_private_t * dev_priv) |
1da177e4 LT |
104 | { |
105 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
106 | u32 head, tail; | |
107 | u32 status = 0; | |
108 | int i; | |
b5e89ed5 DA |
109 | DMA_LOCALS; |
110 | DRM_DEBUG("\n"); | |
111 | ||
112 | /* We need to wait so that we can do an safe flush */ | |
113 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
114 | status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; | |
115 | if (status == MGA_ENDPRDMASTS) | |
116 | break; | |
117 | DRM_UDELAY(1); | |
1da177e4 LT |
118 | } |
119 | ||
b5e89ed5 DA |
120 | if (primary->tail == primary->last_flush) { |
121 | DRM_DEBUG(" bailing out...\n"); | |
1da177e4 LT |
122 | return; |
123 | } | |
124 | ||
125 | tail = primary->tail + dev_priv->primary->offset; | |
126 | ||
127 | /* We need to pad the stream between flushes, as the card | |
128 | * actually (partially?) reads the first of these commands. | |
129 | * See page 4-16 in the G400 manual, middle of the page or so. | |
130 | */ | |
b5e89ed5 | 131 | BEGIN_DMA(1); |
1da177e4 | 132 | |
b5e89ed5 DA |
133 | DMA_BLOCK(MGA_DMAPAD, 0x00000000, |
134 | MGA_DMAPAD, 0x00000000, | |
135 | MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); | |
1da177e4 LT |
136 | |
137 | ADVANCE_DMA(); | |
138 | ||
139 | primary->last_flush = primary->tail; | |
140 | ||
b5e89ed5 | 141 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 | 142 | |
b5e89ed5 | 143 | if (head <= tail) { |
1da177e4 LT |
144 | primary->space = primary->size - primary->tail; |
145 | } else { | |
146 | primary->space = head - tail; | |
147 | } | |
148 | ||
b5e89ed5 DA |
149 | DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); |
150 | DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset); | |
151 | DRM_DEBUG(" space = 0x%06x\n", primary->space); | |
1da177e4 LT |
152 | |
153 | mga_flush_write_combine(); | |
6795c985 | 154 | MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); |
1da177e4 | 155 | |
b5e89ed5 | 156 | DRM_DEBUG("done.\n"); |
1da177e4 LT |
157 | } |
158 | ||
b5e89ed5 | 159 | void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv) |
1da177e4 LT |
160 | { |
161 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
162 | u32 head, tail; | |
163 | DMA_LOCALS; | |
b5e89ed5 | 164 | DRM_DEBUG("\n"); |
1da177e4 LT |
165 | |
166 | BEGIN_DMA_WRAP(); | |
167 | ||
b5e89ed5 DA |
168 | DMA_BLOCK(MGA_DMAPAD, 0x00000000, |
169 | MGA_DMAPAD, 0x00000000, | |
170 | MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); | |
1da177e4 LT |
171 | |
172 | ADVANCE_DMA(); | |
173 | ||
174 | tail = primary->tail + dev_priv->primary->offset; | |
175 | ||
176 | primary->tail = 0; | |
177 | primary->last_flush = 0; | |
178 | primary->last_wrap++; | |
179 | ||
b5e89ed5 | 180 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 | 181 | |
b5e89ed5 | 182 | if (head == dev_priv->primary->offset) { |
1da177e4 LT |
183 | primary->space = primary->size; |
184 | } else { | |
185 | primary->space = head - dev_priv->primary->offset; | |
186 | } | |
187 | ||
b5e89ed5 DA |
188 | DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); |
189 | DRM_DEBUG(" tail = 0x%06x\n", primary->tail); | |
190 | DRM_DEBUG(" wrap = %d\n", primary->last_wrap); | |
191 | DRM_DEBUG(" space = 0x%06x\n", primary->space); | |
1da177e4 LT |
192 | |
193 | mga_flush_write_combine(); | |
6795c985 | 194 | MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); |
1da177e4 | 195 | |
b5e89ed5 DA |
196 | set_bit(0, &primary->wrapped); |
197 | DRM_DEBUG("done.\n"); | |
1da177e4 LT |
198 | } |
199 | ||
b5e89ed5 | 200 | void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv) |
1da177e4 LT |
201 | { |
202 | drm_mga_primary_buffer_t *primary = &dev_priv->prim; | |
203 | drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
204 | u32 head = dev_priv->primary->offset; | |
b5e89ed5 | 205 | DRM_DEBUG("\n"); |
1da177e4 LT |
206 | |
207 | sarea_priv->last_wrap++; | |
b5e89ed5 | 208 | DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); |
1da177e4 LT |
209 | |
210 | mga_flush_write_combine(); | |
b5e89ed5 | 211 | MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL); |
1da177e4 | 212 | |
b5e89ed5 DA |
213 | clear_bit(0, &primary->wrapped); |
214 | DRM_DEBUG("done.\n"); | |
1da177e4 LT |
215 | } |
216 | ||
1da177e4 LT |
217 | /* ================================================================ |
218 | * Freelist management | |
219 | */ | |
220 | ||
221 | #define MGA_BUFFER_USED ~0 | |
222 | #define MGA_BUFFER_FREE 0 | |
223 | ||
224 | #if MGA_FREELIST_DEBUG | |
b5e89ed5 | 225 | static void mga_freelist_print(drm_device_t * dev) |
1da177e4 LT |
226 | { |
227 | drm_mga_private_t *dev_priv = dev->dev_private; | |
228 | drm_mga_freelist_t *entry; | |
229 | ||
b5e89ed5 DA |
230 | DRM_INFO("\n"); |
231 | DRM_INFO("current dispatch: last=0x%x done=0x%x\n", | |
232 | dev_priv->sarea_priv->last_dispatch, | |
233 | (unsigned int)(MGA_READ(MGA_PRIMADDRESS) - | |
234 | dev_priv->primary->offset)); | |
235 | DRM_INFO("current freelist:\n"); | |
236 | ||
237 | for (entry = dev_priv->head->next; entry; entry = entry->next) { | |
238 | DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n", | |
239 | entry, entry->buf->idx, entry->age.head, | |
240 | entry->age.head - dev_priv->primary->offset); | |
1da177e4 | 241 | } |
b5e89ed5 | 242 | DRM_INFO("\n"); |
1da177e4 LT |
243 | } |
244 | #endif | |
245 | ||
b5e89ed5 | 246 | static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv) |
1da177e4 LT |
247 | { |
248 | drm_device_dma_t *dma = dev->dma; | |
249 | drm_buf_t *buf; | |
250 | drm_mga_buf_priv_t *buf_priv; | |
251 | drm_mga_freelist_t *entry; | |
252 | int i; | |
b5e89ed5 | 253 | DRM_DEBUG("count=%d\n", dma->buf_count); |
1da177e4 | 254 | |
b5e89ed5 DA |
255 | dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); |
256 | if (dev_priv->head == NULL) | |
1da177e4 LT |
257 | return DRM_ERR(ENOMEM); |
258 | ||
b5e89ed5 DA |
259 | memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); |
260 | SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); | |
1da177e4 | 261 | |
b5e89ed5 | 262 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 | 263 | buf = dma->buflist[i]; |
b5e89ed5 | 264 | buf_priv = buf->dev_private; |
1da177e4 | 265 | |
b5e89ed5 DA |
266 | entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); |
267 | if (entry == NULL) | |
1da177e4 LT |
268 | return DRM_ERR(ENOMEM); |
269 | ||
b5e89ed5 | 270 | memset(entry, 0, sizeof(drm_mga_freelist_t)); |
1da177e4 LT |
271 | |
272 | entry->next = dev_priv->head->next; | |
273 | entry->prev = dev_priv->head; | |
b5e89ed5 | 274 | SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); |
1da177e4 LT |
275 | entry->buf = buf; |
276 | ||
b5e89ed5 | 277 | if (dev_priv->head->next != NULL) |
1da177e4 | 278 | dev_priv->head->next->prev = entry; |
b5e89ed5 | 279 | if (entry->next == NULL) |
1da177e4 LT |
280 | dev_priv->tail = entry; |
281 | ||
282 | buf_priv->list_entry = entry; | |
283 | buf_priv->discard = 0; | |
284 | buf_priv->dispatched = 0; | |
285 | ||
286 | dev_priv->head->next = entry; | |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
b5e89ed5 | 292 | static void mga_freelist_cleanup(drm_device_t * dev) |
1da177e4 LT |
293 | { |
294 | drm_mga_private_t *dev_priv = dev->dev_private; | |
295 | drm_mga_freelist_t *entry; | |
296 | drm_mga_freelist_t *next; | |
b5e89ed5 | 297 | DRM_DEBUG("\n"); |
1da177e4 LT |
298 | |
299 | entry = dev_priv->head; | |
b5e89ed5 | 300 | while (entry) { |
1da177e4 | 301 | next = entry->next; |
b5e89ed5 | 302 | drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); |
1da177e4 LT |
303 | entry = next; |
304 | } | |
305 | ||
306 | dev_priv->head = dev_priv->tail = NULL; | |
307 | } | |
308 | ||
309 | #if 0 | |
310 | /* FIXME: Still needed? | |
311 | */ | |
b5e89ed5 | 312 | static void mga_freelist_reset(drm_device_t * dev) |
1da177e4 LT |
313 | { |
314 | drm_device_dma_t *dma = dev->dma; | |
315 | drm_buf_t *buf; | |
316 | drm_mga_buf_priv_t *buf_priv; | |
317 | int i; | |
318 | ||
b5e89ed5 | 319 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 | 320 | buf = dma->buflist[i]; |
b5e89ed5 DA |
321 | buf_priv = buf->dev_private; |
322 | SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0); | |
1da177e4 LT |
323 | } |
324 | } | |
325 | #endif | |
326 | ||
b5e89ed5 | 327 | static drm_buf_t *mga_freelist_get(drm_device_t * dev) |
1da177e4 LT |
328 | { |
329 | drm_mga_private_t *dev_priv = dev->dev_private; | |
330 | drm_mga_freelist_t *next; | |
331 | drm_mga_freelist_t *prev; | |
332 | drm_mga_freelist_t *tail = dev_priv->tail; | |
333 | u32 head, wrap; | |
b5e89ed5 | 334 | DRM_DEBUG("\n"); |
1da177e4 | 335 | |
b5e89ed5 | 336 | head = MGA_READ(MGA_PRIMADDRESS); |
1da177e4 LT |
337 | wrap = dev_priv->sarea_priv->last_wrap; |
338 | ||
b5e89ed5 DA |
339 | DRM_DEBUG(" tail=0x%06lx %d\n", |
340 | tail->age.head ? | |
341 | tail->age.head - dev_priv->primary->offset : 0, | |
342 | tail->age.wrap); | |
343 | DRM_DEBUG(" head=0x%06lx %d\n", | |
344 | head - dev_priv->primary->offset, wrap); | |
1da177e4 | 345 | |
b5e89ed5 | 346 | if (TEST_AGE(&tail->age, head, wrap)) { |
1da177e4 LT |
347 | prev = dev_priv->tail->prev; |
348 | next = dev_priv->tail; | |
349 | prev->next = NULL; | |
350 | next->prev = next->next = NULL; | |
351 | dev_priv->tail = prev; | |
b5e89ed5 | 352 | SET_AGE(&next->age, MGA_BUFFER_USED, 0); |
1da177e4 LT |
353 | return next->buf; |
354 | } | |
355 | ||
b5e89ed5 | 356 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
357 | return NULL; |
358 | } | |
359 | ||
b5e89ed5 | 360 | int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf) |
1da177e4 LT |
361 | { |
362 | drm_mga_private_t *dev_priv = dev->dev_private; | |
363 | drm_mga_buf_priv_t *buf_priv = buf->dev_private; | |
364 | drm_mga_freelist_t *head, *entry, *prev; | |
365 | ||
b5e89ed5 DA |
366 | DRM_DEBUG("age=0x%06lx wrap=%d\n", |
367 | buf_priv->list_entry->age.head - | |
368 | dev_priv->primary->offset, buf_priv->list_entry->age.wrap); | |
1da177e4 LT |
369 | |
370 | entry = buf_priv->list_entry; | |
371 | head = dev_priv->head; | |
372 | ||
b5e89ed5 DA |
373 | if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) { |
374 | SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); | |
1da177e4 LT |
375 | prev = dev_priv->tail; |
376 | prev->next = entry; | |
377 | entry->prev = prev; | |
378 | entry->next = NULL; | |
379 | } else { | |
380 | prev = head->next; | |
381 | head->next = entry; | |
382 | prev->prev = entry; | |
383 | entry->prev = head; | |
384 | entry->next = prev; | |
385 | } | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
1da177e4 LT |
390 | /* ================================================================ |
391 | * DMA initialization, cleanup | |
392 | */ | |
393 | ||
b5e89ed5 | 394 | int mga_driver_preinit(drm_device_t * dev, unsigned long flags) |
6795c985 | 395 | { |
b5e89ed5 | 396 | drm_mga_private_t *dev_priv; |
6795c985 DA |
397 | |
398 | dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); | |
399 | if (!dev_priv) | |
400 | return DRM_ERR(ENOMEM); | |
401 | ||
402 | dev->dev_private = (void *)dev_priv; | |
403 | memset(dev_priv, 0, sizeof(drm_mga_private_t)); | |
404 | ||
405 | dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; | |
406 | dev_priv->chipset = flags; | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
908f9c48 | 411 | #if __OS_HAS_AGP |
6795c985 DA |
412 | /** |
413 | * Bootstrap the driver for AGP DMA. | |
b5e89ed5 | 414 | * |
6795c985 DA |
415 | * \todo |
416 | * Investigate whether there is any benifit to storing the WARP microcode in | |
417 | * AGP memory. If not, the microcode may as well always be put in PCI | |
418 | * memory. | |
419 | * | |
420 | * \todo | |
421 | * This routine needs to set dma_bs->agp_mode to the mode actually configured | |
422 | * in the hardware. Looking just at the Linux AGP driver code, I don't see | |
423 | * an easy way to determine this. | |
424 | * | |
425 | * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap | |
426 | */ | |
427 | static int mga_do_agp_dma_bootstrap(drm_device_t * dev, | |
428 | drm_mga_dma_bootstrap_t * dma_bs) | |
429 | { | |
b5e89ed5 DA |
430 | drm_mga_private_t *const dev_priv = |
431 | (drm_mga_private_t *) dev->dev_private; | |
6795c985 DA |
432 | const unsigned int warp_size = mga_warp_microcode_size(dev_priv); |
433 | int err; | |
b5e89ed5 | 434 | unsigned offset; |
6795c985 | 435 | const unsigned secondary_size = dma_bs->secondary_bin_count |
b5e89ed5 | 436 | * dma_bs->secondary_bin_size; |
6795c985 DA |
437 | const unsigned agp_size = (dma_bs->agp_size << 20); |
438 | drm_buf_desc_t req; | |
439 | drm_agp_mode_t mode; | |
440 | drm_agp_info_t info; | |
441 | ||
6795c985 DA |
442 | /* Acquire AGP. */ |
443 | err = drm_agp_acquire(dev); | |
444 | if (err) { | |
445 | DRM_ERROR("Unable to acquire AGP\n"); | |
446 | return err; | |
447 | } | |
448 | ||
449 | err = drm_agp_info(dev, &info); | |
450 | if (err) { | |
451 | DRM_ERROR("Unable to get AGP info\n"); | |
452 | return err; | |
453 | } | |
454 | ||
455 | mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode; | |
456 | err = drm_agp_enable(dev, mode); | |
457 | if (err) { | |
458 | DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); | |
459 | return err; | |
460 | } | |
461 | ||
6795c985 DA |
462 | /* In addition to the usual AGP mode configuration, the G200 AGP cards |
463 | * need to have the AGP mode "manually" set. | |
464 | */ | |
465 | ||
466 | if (dev_priv->chipset == MGA_CARD_TYPE_G200) { | |
467 | if (mode.mode & 0x02) { | |
468 | MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); | |
b5e89ed5 | 469 | } else { |
6795c985 DA |
470 | MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); |
471 | } | |
472 | } | |
473 | ||
6795c985 DA |
474 | /* Allocate and bind AGP memory. */ |
475 | dev_priv->agp_pages = agp_size / PAGE_SIZE; | |
b5e89ed5 | 476 | dev_priv->agp_mem = drm_alloc_agp(dev, dev_priv->agp_pages, 0); |
6795c985 DA |
477 | if (dev_priv->agp_mem == NULL) { |
478 | dev_priv->agp_pages = 0; | |
479 | DRM_ERROR("Unable to allocate %uMB AGP memory\n", | |
480 | dma_bs->agp_size); | |
481 | return DRM_ERR(ENOMEM); | |
482 | } | |
b5e89ed5 DA |
483 | |
484 | err = drm_bind_agp(dev_priv->agp_mem, 0); | |
6795c985 DA |
485 | if (err) { |
486 | DRM_ERROR("Unable to bind AGP memory\n"); | |
487 | return err; | |
488 | } | |
489 | ||
490 | offset = 0; | |
b5e89ed5 DA |
491 | err = drm_addmap(dev, offset, warp_size, |
492 | _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp); | |
6795c985 DA |
493 | if (err) { |
494 | DRM_ERROR("Unable to map WARP microcode\n"); | |
495 | return err; | |
496 | } | |
497 | ||
498 | offset += warp_size; | |
b5e89ed5 DA |
499 | err = drm_addmap(dev, offset, dma_bs->primary_size, |
500 | _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary); | |
6795c985 DA |
501 | if (err) { |
502 | DRM_ERROR("Unable to map primary DMA region\n"); | |
503 | return err; | |
504 | } | |
505 | ||
506 | offset += dma_bs->primary_size; | |
b5e89ed5 DA |
507 | err = drm_addmap(dev, offset, secondary_size, |
508 | _DRM_AGP, 0, &dev->agp_buffer_map); | |
6795c985 DA |
509 | if (err) { |
510 | DRM_ERROR("Unable to map secondary DMA region\n"); | |
511 | return err; | |
512 | } | |
513 | ||
b5e89ed5 | 514 | (void)memset(&req, 0, sizeof(req)); |
6795c985 DA |
515 | req.count = dma_bs->secondary_bin_count; |
516 | req.size = dma_bs->secondary_bin_size; | |
517 | req.flags = _DRM_AGP_BUFFER; | |
518 | req.agp_start = offset; | |
519 | ||
b5e89ed5 | 520 | err = drm_addbufs_agp(dev, &req); |
6795c985 DA |
521 | if (err) { |
522 | DRM_ERROR("Unable to add secondary DMA buffers\n"); | |
523 | return err; | |
524 | } | |
525 | ||
526 | offset += secondary_size; | |
b5e89ed5 DA |
527 | err = drm_addmap(dev, offset, agp_size - offset, |
528 | _DRM_AGP, 0, &dev_priv->agp_textures); | |
6795c985 DA |
529 | if (err) { |
530 | DRM_ERROR("Unable to map AGP texture region\n"); | |
531 | return err; | |
532 | } | |
533 | ||
534 | drm_core_ioremap(dev_priv->warp, dev); | |
535 | drm_core_ioremap(dev_priv->primary, dev); | |
536 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
537 | ||
538 | if (!dev_priv->warp->handle || | |
539 | !dev_priv->primary->handle || !dev->agp_buffer_map->handle) { | |
540 | DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n", | |
541 | dev_priv->warp->handle, dev_priv->primary->handle, | |
542 | dev->agp_buffer_map->handle); | |
543 | return DRM_ERR(ENOMEM); | |
544 | } | |
545 | ||
546 | dev_priv->dma_access = MGA_PAGPXFER; | |
547 | dev_priv->wagp_enable = MGA_WAGP_ENABLE; | |
548 | ||
549 | DRM_INFO("Initialized card for AGP DMA.\n"); | |
550 | return 0; | |
551 | } | |
908f9c48 DA |
552 | #else |
553 | static int mga_do_agp_dma_bootstrap(drm_device_t * dev, | |
554 | drm_mga_dma_bootstrap_t * dma_bs) | |
555 | { | |
556 | return -EINVAL; | |
557 | } | |
558 | #endif | |
6795c985 DA |
559 | |
560 | /** | |
561 | * Bootstrap the driver for PCI DMA. | |
b5e89ed5 | 562 | * |
6795c985 DA |
563 | * \todo |
564 | * The algorithm for decreasing the size of the primary DMA buffer could be | |
565 | * better. The size should be rounded up to the nearest page size, then | |
566 | * decrease the request size by a single page each pass through the loop. | |
567 | * | |
568 | * \todo | |
569 | * Determine whether the maximum address passed to drm_pci_alloc is correct. | |
570 | * The same goes for drm_addbufs_pci. | |
b5e89ed5 | 571 | * |
6795c985 DA |
572 | * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap |
573 | */ | |
574 | static int mga_do_pci_dma_bootstrap(drm_device_t * dev, | |
575 | drm_mga_dma_bootstrap_t * dma_bs) | |
576 | { | |
b5e89ed5 DA |
577 | drm_mga_private_t *const dev_priv = |
578 | (drm_mga_private_t *) dev->dev_private; | |
6795c985 DA |
579 | const unsigned int warp_size = mga_warp_microcode_size(dev_priv); |
580 | unsigned int primary_size; | |
581 | unsigned int bin_count; | |
582 | int err; | |
583 | drm_buf_desc_t req; | |
584 | ||
6795c985 DA |
585 | if (dev->dma == NULL) { |
586 | DRM_ERROR("dev->dma is NULL\n"); | |
587 | return DRM_ERR(EFAULT); | |
588 | } | |
589 | ||
590 | /* The proper alignment is 0x100 for this mapping */ | |
591 | err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT, | |
592 | _DRM_READ_ONLY, &dev_priv->warp); | |
593 | if (err != 0) { | |
594 | DRM_ERROR("Unable to create mapping for WARP microcode\n"); | |
595 | return err; | |
596 | } | |
597 | ||
598 | /* Other than the bottom two bits being used to encode other | |
599 | * information, there don't appear to be any restrictions on the | |
600 | * alignment of the primary or secondary DMA buffers. | |
601 | */ | |
602 | ||
b5e89ed5 DA |
603 | for (primary_size = dma_bs->primary_size; primary_size != 0; |
604 | primary_size >>= 1) { | |
6795c985 DA |
605 | /* The proper alignment for this mapping is 0x04 */ |
606 | err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT, | |
607 | _DRM_READ_ONLY, &dev_priv->primary); | |
608 | if (!err) | |
609 | break; | |
610 | } | |
611 | ||
612 | if (err != 0) { | |
613 | DRM_ERROR("Unable to allocate primary DMA region\n"); | |
614 | return DRM_ERR(ENOMEM); | |
615 | } | |
616 | ||
617 | if (dev_priv->primary->size != dma_bs->primary_size) { | |
618 | DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", | |
b5e89ed5 DA |
619 | dma_bs->primary_size, |
620 | (unsigned)dev_priv->primary->size); | |
6795c985 DA |
621 | dma_bs->primary_size = dev_priv->primary->size; |
622 | } | |
623 | ||
b5e89ed5 DA |
624 | for (bin_count = dma_bs->secondary_bin_count; bin_count > 0; |
625 | bin_count--) { | |
626 | (void)memset(&req, 0, sizeof(req)); | |
6795c985 DA |
627 | req.count = bin_count; |
628 | req.size = dma_bs->secondary_bin_size; | |
629 | ||
b5e89ed5 | 630 | err = drm_addbufs_pci(dev, &req); |
6795c985 DA |
631 | if (!err) { |
632 | break; | |
633 | } | |
634 | } | |
b5e89ed5 | 635 | |
6795c985 DA |
636 | if (bin_count == 0) { |
637 | DRM_ERROR("Unable to add secondary DMA buffers\n"); | |
638 | return err; | |
639 | } | |
640 | ||
641 | if (bin_count != dma_bs->secondary_bin_count) { | |
642 | DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u " | |
643 | "to %u.\n", dma_bs->secondary_bin_count, bin_count); | |
644 | ||
645 | dma_bs->secondary_bin_count = bin_count; | |
646 | } | |
647 | ||
648 | dev_priv->dma_access = 0; | |
649 | dev_priv->wagp_enable = 0; | |
650 | ||
651 | dma_bs->agp_mode = 0; | |
652 | ||
653 | DRM_INFO("Initialized card for PCI DMA.\n"); | |
654 | return 0; | |
655 | } | |
656 | ||
6795c985 DA |
657 | static int mga_do_dma_bootstrap(drm_device_t * dev, |
658 | drm_mga_dma_bootstrap_t * dma_bs) | |
659 | { | |
660 | const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); | |
661 | int err; | |
b5e89ed5 DA |
662 | drm_mga_private_t *const dev_priv = |
663 | (drm_mga_private_t *) dev->dev_private; | |
6795c985 DA |
664 | |
665 | dev_priv->used_new_dma_init = 1; | |
666 | ||
667 | /* The first steps are the same for both PCI and AGP based DMA. Map | |
668 | * the cards MMIO registers and map a status page. | |
669 | */ | |
b5e89ed5 DA |
670 | err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, |
671 | _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio); | |
6795c985 DA |
672 | if (err) { |
673 | DRM_ERROR("Unable to map MMIO region\n"); | |
674 | return err; | |
675 | } | |
676 | ||
b5e89ed5 DA |
677 | err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM, |
678 | _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, | |
679 | &dev_priv->status); | |
6795c985 DA |
680 | if (err) { |
681 | DRM_ERROR("Unable to map status region\n"); | |
682 | return err; | |
683 | } | |
684 | ||
6795c985 DA |
685 | /* The DMA initialization procedure is slightly different for PCI and |
686 | * AGP cards. AGP cards just allocate a large block of AGP memory and | |
687 | * carve off portions of it for internal uses. The remaining memory | |
688 | * is returned to user-mode to be used for AGP textures. | |
689 | */ | |
6795c985 DA |
690 | if (is_agp) { |
691 | err = mga_do_agp_dma_bootstrap(dev, dma_bs); | |
692 | } | |
b5e89ed5 | 693 | |
6795c985 DA |
694 | /* If we attempted to initialize the card for AGP DMA but failed, |
695 | * clean-up any mess that may have been created. | |
696 | */ | |
697 | ||
698 | if (err) { | |
699 | mga_do_cleanup_dma(dev); | |
700 | } | |
701 | ||
6795c985 DA |
702 | /* Not only do we want to try and initialized PCI cards for PCI DMA, |
703 | * but we also try to initialized AGP cards that could not be | |
704 | * initialized for AGP DMA. This covers the case where we have an AGP | |
705 | * card in a system with an unsupported AGP chipset. In that case the | |
706 | * card will be detected as AGP, but we won't be able to allocate any | |
707 | * AGP memory, etc. | |
708 | */ | |
709 | ||
710 | if (!is_agp || err) { | |
711 | err = mga_do_pci_dma_bootstrap(dev, dma_bs); | |
712 | } | |
713 | ||
6795c985 DA |
714 | return err; |
715 | } | |
716 | ||
717 | int mga_dma_bootstrap(DRM_IOCTL_ARGS) | |
718 | { | |
719 | DRM_DEVICE; | |
720 | drm_mga_dma_bootstrap_t bootstrap; | |
721 | int err; | |
722 | ||
6795c985 DA |
723 | DRM_COPY_FROM_USER_IOCTL(bootstrap, |
724 | (drm_mga_dma_bootstrap_t __user *) data, | |
725 | sizeof(bootstrap)); | |
726 | ||
b5e89ed5 DA |
727 | err = mga_do_dma_bootstrap(dev, &bootstrap); |
728 | if (!err) { | |
6795c985 | 729 | static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; |
b5e89ed5 DA |
730 | const drm_mga_private_t *const dev_priv = |
731 | (drm_mga_private_t *) dev->dev_private; | |
6795c985 DA |
732 | |
733 | if (dev_priv->agp_textures != NULL) { | |
b5e89ed5 DA |
734 | bootstrap.texture_handle = |
735 | dev_priv->agp_textures->offset; | |
6795c985 | 736 | bootstrap.texture_size = dev_priv->agp_textures->size; |
b5e89ed5 | 737 | } else { |
6795c985 DA |
738 | bootstrap.texture_handle = 0; |
739 | bootstrap.texture_size = 0; | |
740 | } | |
741 | ||
b5e89ed5 DA |
742 | bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07]; |
743 | if (DRM_COPY_TO_USER((void __user *)data, &bootstrap, | |
6795c985 DA |
744 | sizeof(bootstrap))) { |
745 | err = DRM_ERR(EFAULT); | |
746 | } | |
b5e89ed5 | 747 | } else { |
6795c985 DA |
748 | mga_do_cleanup_dma(dev); |
749 | } | |
750 | ||
751 | return err; | |
752 | } | |
753 | ||
b5e89ed5 | 754 | static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init) |
1da177e4 LT |
755 | { |
756 | drm_mga_private_t *dev_priv; | |
757 | int ret; | |
b5e89ed5 | 758 | DRM_DEBUG("\n"); |
1da177e4 | 759 | |
6795c985 | 760 | dev_priv = dev->dev_private; |
1da177e4 | 761 | |
6795c985 | 762 | if (init->sgram) { |
1da177e4 LT |
763 | dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; |
764 | } else { | |
765 | dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; | |
766 | } | |
b5e89ed5 | 767 | dev_priv->maccess = init->maccess; |
1da177e4 | 768 | |
b5e89ed5 DA |
769 | dev_priv->fb_cpp = init->fb_cpp; |
770 | dev_priv->front_offset = init->front_offset; | |
771 | dev_priv->front_pitch = init->front_pitch; | |
772 | dev_priv->back_offset = init->back_offset; | |
773 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 774 | |
b5e89ed5 DA |
775 | dev_priv->depth_cpp = init->depth_cpp; |
776 | dev_priv->depth_offset = init->depth_offset; | |
777 | dev_priv->depth_pitch = init->depth_pitch; | |
1da177e4 LT |
778 | |
779 | /* FIXME: Need to support AGP textures... | |
780 | */ | |
781 | dev_priv->texture_offset = init->texture_offset[0]; | |
782 | dev_priv->texture_size = init->texture_size[0]; | |
783 | ||
784 | DRM_GETSAREA(); | |
785 | ||
6795c985 DA |
786 | if (!dev_priv->sarea) { |
787 | DRM_ERROR("failed to find sarea!\n"); | |
1da177e4 LT |
788 | return DRM_ERR(EINVAL); |
789 | } | |
790 | ||
b5e89ed5 | 791 | if (!dev_priv->used_new_dma_init) { |
6795c985 DA |
792 | dev_priv->status = drm_core_findmap(dev, init->status_offset); |
793 | if (!dev_priv->status) { | |
794 | DRM_ERROR("failed to find status page!\n"); | |
795 | return DRM_ERR(EINVAL); | |
796 | } | |
797 | dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); | |
798 | if (!dev_priv->mmio) { | |
799 | DRM_ERROR("failed to find mmio region!\n"); | |
800 | return DRM_ERR(EINVAL); | |
801 | } | |
802 | dev_priv->warp = drm_core_findmap(dev, init->warp_offset); | |
803 | if (!dev_priv->warp) { | |
804 | DRM_ERROR("failed to find warp microcode region!\n"); | |
805 | return DRM_ERR(EINVAL); | |
806 | } | |
807 | dev_priv->primary = drm_core_findmap(dev, init->primary_offset); | |
808 | if (!dev_priv->primary) { | |
809 | DRM_ERROR("failed to find primary dma region!\n"); | |
810 | return DRM_ERR(EINVAL); | |
811 | } | |
d1f2b55a | 812 | dev->agp_buffer_token = init->buffers_offset; |
b5e89ed5 DA |
813 | dev->agp_buffer_map = |
814 | drm_core_findmap(dev, init->buffers_offset); | |
6795c985 DA |
815 | if (!dev->agp_buffer_map) { |
816 | DRM_ERROR("failed to find dma buffer region!\n"); | |
817 | return DRM_ERR(EINVAL); | |
818 | } | |
819 | ||
820 | drm_core_ioremap(dev_priv->warp, dev); | |
821 | drm_core_ioremap(dev_priv->primary, dev); | |
822 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
1da177e4 LT |
823 | } |
824 | ||
825 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
826 | (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
827 | init->sarea_priv_offset); | |
1da177e4 | 828 | |
6795c985 DA |
829 | if (!dev_priv->warp->handle || |
830 | !dev_priv->primary->handle || | |
831 | ((dev_priv->dma_access != 0) && | |
832 | ((dev->agp_buffer_map == NULL) || | |
833 | (dev->agp_buffer_map->handle == NULL)))) { | |
834 | DRM_ERROR("failed to ioremap agp regions!\n"); | |
1da177e4 LT |
835 | return DRM_ERR(ENOMEM); |
836 | } | |
837 | ||
6795c985 DA |
838 | ret = mga_warp_install_microcode(dev_priv); |
839 | if (ret < 0) { | |
840 | DRM_ERROR("failed to install WARP ucode!\n"); | |
1da177e4 LT |
841 | return ret; |
842 | } | |
843 | ||
6795c985 DA |
844 | ret = mga_warp_init(dev_priv); |
845 | if (ret < 0) { | |
846 | DRM_ERROR("failed to init WARP engine!\n"); | |
1da177e4 LT |
847 | return ret; |
848 | } | |
849 | ||
b5e89ed5 | 850 | dev_priv->prim.status = (u32 *) dev_priv->status->handle; |
1da177e4 | 851 | |
b5e89ed5 | 852 | mga_do_wait_for_idle(dev_priv); |
1da177e4 LT |
853 | |
854 | /* Init the primary DMA registers. | |
855 | */ | |
b5e89ed5 | 856 | MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); |
1da177e4 | 857 | #if 0 |
b5e89ed5 DA |
858 | MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ |
859 | MGA_PRIMPTREN1); /* DWGSYNC */ | |
1da177e4 LT |
860 | #endif |
861 | ||
b5e89ed5 DA |
862 | dev_priv->prim.start = (u8 *) dev_priv->primary->handle; |
863 | dev_priv->prim.end = ((u8 *) dev_priv->primary->handle | |
1da177e4 LT |
864 | + dev_priv->primary->size); |
865 | dev_priv->prim.size = dev_priv->primary->size; | |
866 | ||
867 | dev_priv->prim.tail = 0; | |
868 | dev_priv->prim.space = dev_priv->prim.size; | |
869 | dev_priv->prim.wrapped = 0; | |
870 | ||
871 | dev_priv->prim.last_flush = 0; | |
872 | dev_priv->prim.last_wrap = 0; | |
873 | ||
874 | dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; | |
875 | ||
876 | dev_priv->prim.status[0] = dev_priv->primary->offset; | |
877 | dev_priv->prim.status[1] = 0; | |
878 | ||
879 | dev_priv->sarea_priv->last_wrap = 0; | |
880 | dev_priv->sarea_priv->last_frame.head = 0; | |
881 | dev_priv->sarea_priv->last_frame.wrap = 0; | |
882 | ||
6795c985 DA |
883 | if (mga_freelist_init(dev, dev_priv) < 0) { |
884 | DRM_ERROR("could not initialize freelist\n"); | |
1da177e4 LT |
885 | return DRM_ERR(ENOMEM); |
886 | } | |
887 | ||
1da177e4 LT |
888 | return 0; |
889 | } | |
890 | ||
b5e89ed5 | 891 | static int mga_do_cleanup_dma(drm_device_t * dev) |
1da177e4 | 892 | { |
6795c985 DA |
893 | int err = 0; |
894 | DRM_DEBUG("\n"); | |
1da177e4 LT |
895 | |
896 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
897 | * may not have been called from userspace and after dev_private | |
898 | * is freed, it's too late. | |
899 | */ | |
b5e89ed5 DA |
900 | if (dev->irq_enabled) |
901 | drm_irq_uninstall(dev); | |
1da177e4 | 902 | |
b5e89ed5 | 903 | if (dev->dev_private) { |
1da177e4 LT |
904 | drm_mga_private_t *dev_priv = dev->dev_private; |
905 | ||
b5e89ed5 | 906 | if ((dev_priv->warp != NULL) |
6795c985 DA |
907 | && (dev_priv->mmio->type != _DRM_CONSISTENT)) |
908 | drm_core_ioremapfree(dev_priv->warp, dev); | |
909 | ||
b5e89ed5 | 910 | if ((dev_priv->primary != NULL) |
6795c985 DA |
911 | && (dev_priv->primary->type != _DRM_CONSISTENT)) |
912 | drm_core_ioremapfree(dev_priv->primary, dev); | |
1da177e4 | 913 | |
6795c985 DA |
914 | if (dev->agp_buffer_map != NULL) |
915 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
916 | ||
917 | if (dev_priv->used_new_dma_init) { | |
908f9c48 | 918 | #if __OS_HAS_AGP |
6795c985 DA |
919 | if (dev_priv->agp_mem != NULL) { |
920 | dev_priv->agp_textures = NULL; | |
921 | drm_unbind_agp(dev_priv->agp_mem); | |
922 | ||
b5e89ed5 DA |
923 | drm_free_agp(dev_priv->agp_mem, |
924 | dev_priv->agp_pages); | |
6795c985 DA |
925 | dev_priv->agp_pages = 0; |
926 | dev_priv->agp_mem = NULL; | |
927 | } | |
928 | ||
929 | if ((dev->agp != NULL) && dev->agp->acquired) { | |
930 | err = drm_agp_release(dev); | |
931 | } | |
908f9c48 | 932 | #endif |
6795c985 | 933 | dev_priv->used_new_dma_init = 0; |
1da177e4 LT |
934 | } |
935 | ||
6795c985 DA |
936 | dev_priv->warp = NULL; |
937 | dev_priv->primary = NULL; | |
938 | dev_priv->mmio = NULL; | |
939 | dev_priv->status = NULL; | |
940 | dev_priv->sarea = NULL; | |
941 | dev_priv->sarea_priv = NULL; | |
942 | dev->agp_buffer_map = NULL; | |
943 | ||
944 | memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); | |
945 | dev_priv->warp_pipe = 0; | |
b5e89ed5 DA |
946 | memset(dev_priv->warp_pipe_phys, 0, |
947 | sizeof(dev_priv->warp_pipe_phys)); | |
6795c985 DA |
948 | |
949 | if (dev_priv->head != NULL) { | |
950 | mga_freelist_cleanup(dev); | |
951 | } | |
1da177e4 LT |
952 | } |
953 | ||
908f9c48 | 954 | return err; |
1da177e4 LT |
955 | } |
956 | ||
b5e89ed5 | 957 | int mga_dma_init(DRM_IOCTL_ARGS) |
1da177e4 LT |
958 | { |
959 | DRM_DEVICE; | |
960 | drm_mga_init_t init; | |
6795c985 | 961 | int err; |
1da177e4 | 962 | |
b5e89ed5 | 963 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 964 | |
6795c985 DA |
965 | DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, |
966 | sizeof(init)); | |
1da177e4 | 967 | |
b5e89ed5 | 968 | switch (init.func) { |
1da177e4 | 969 | case MGA_INIT_DMA: |
6795c985 DA |
970 | err = mga_do_init_dma(dev, &init); |
971 | if (err) { | |
b5e89ed5 | 972 | (void)mga_do_cleanup_dma(dev); |
6795c985 DA |
973 | } |
974 | return err; | |
1da177e4 | 975 | case MGA_CLEANUP_DMA: |
b5e89ed5 | 976 | return mga_do_cleanup_dma(dev); |
1da177e4 LT |
977 | } |
978 | ||
979 | return DRM_ERR(EINVAL); | |
980 | } | |
981 | ||
1da177e4 LT |
982 | /* ================================================================ |
983 | * Primary DMA stream management | |
984 | */ | |
985 | ||
b5e89ed5 | 986 | int mga_dma_flush(DRM_IOCTL_ARGS) |
1da177e4 LT |
987 | { |
988 | DRM_DEVICE; | |
b5e89ed5 | 989 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
1da177e4 LT |
990 | drm_lock_t lock; |
991 | ||
b5e89ed5 | 992 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 993 | |
b5e89ed5 DA |
994 | DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data, |
995 | sizeof(lock)); | |
1da177e4 | 996 | |
b5e89ed5 DA |
997 | DRM_DEBUG("%s%s%s\n", |
998 | (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", | |
999 | (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", | |
1000 | (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); | |
1da177e4 | 1001 | |
b5e89ed5 | 1002 | WRAP_WAIT_WITH_RETURN(dev_priv); |
1da177e4 | 1003 | |
b5e89ed5 DA |
1004 | if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) { |
1005 | mga_do_dma_flush(dev_priv); | |
1da177e4 LT |
1006 | } |
1007 | ||
b5e89ed5 | 1008 | if (lock.flags & _DRM_LOCK_QUIESCENT) { |
1da177e4 | 1009 | #if MGA_DMA_DEBUG |
b5e89ed5 DA |
1010 | int ret = mga_do_wait_for_idle(dev_priv); |
1011 | if (ret < 0) | |
1012 | DRM_INFO("%s: -EBUSY\n", __FUNCTION__); | |
1da177e4 LT |
1013 | return ret; |
1014 | #else | |
b5e89ed5 | 1015 | return mga_do_wait_for_idle(dev_priv); |
1da177e4 LT |
1016 | #endif |
1017 | } else { | |
1018 | return 0; | |
1019 | } | |
1020 | } | |
1021 | ||
b5e89ed5 | 1022 | int mga_dma_reset(DRM_IOCTL_ARGS) |
1da177e4 LT |
1023 | { |
1024 | DRM_DEVICE; | |
b5e89ed5 | 1025 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
1da177e4 | 1026 | |
b5e89ed5 | 1027 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1028 | |
b5e89ed5 | 1029 | return mga_do_dma_reset(dev_priv); |
1da177e4 LT |
1030 | } |
1031 | ||
1da177e4 LT |
1032 | /* ================================================================ |
1033 | * DMA buffer management | |
1034 | */ | |
1035 | ||
b5e89ed5 | 1036 | static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) |
1da177e4 LT |
1037 | { |
1038 | drm_buf_t *buf; | |
1039 | int i; | |
1040 | ||
b5e89ed5 DA |
1041 | for (i = d->granted_count; i < d->request_count; i++) { |
1042 | buf = mga_freelist_get(dev); | |
1043 | if (!buf) | |
1044 | return DRM_ERR(EAGAIN); | |
1da177e4 LT |
1045 | |
1046 | buf->filp = filp; | |
1047 | ||
b5e89ed5 DA |
1048 | if (DRM_COPY_TO_USER(&d->request_indices[i], |
1049 | &buf->idx, sizeof(buf->idx))) | |
1da177e4 | 1050 | return DRM_ERR(EFAULT); |
b5e89ed5 DA |
1051 | if (DRM_COPY_TO_USER(&d->request_sizes[i], |
1052 | &buf->total, sizeof(buf->total))) | |
1da177e4 LT |
1053 | return DRM_ERR(EFAULT); |
1054 | ||
1055 | d->granted_count++; | |
1056 | } | |
1057 | return 0; | |
1058 | } | |
1059 | ||
b5e89ed5 | 1060 | int mga_dma_buffers(DRM_IOCTL_ARGS) |
1da177e4 LT |
1061 | { |
1062 | DRM_DEVICE; | |
1063 | drm_device_dma_t *dma = dev->dma; | |
b5e89ed5 | 1064 | drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; |
1da177e4 LT |
1065 | drm_dma_t __user *argp = (void __user *)data; |
1066 | drm_dma_t d; | |
1067 | int ret = 0; | |
1068 | ||
b5e89ed5 | 1069 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1070 | |
b5e89ed5 | 1071 | DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); |
1da177e4 LT |
1072 | |
1073 | /* Please don't send us buffers. | |
1074 | */ | |
b5e89ed5 DA |
1075 | if (d.send_count != 0) { |
1076 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", | |
1077 | DRM_CURRENTPID, d.send_count); | |
1da177e4 LT |
1078 | return DRM_ERR(EINVAL); |
1079 | } | |
1080 | ||
1081 | /* We'll send you buffers. | |
1082 | */ | |
b5e89ed5 DA |
1083 | if (d.request_count < 0 || d.request_count > dma->buf_count) { |
1084 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", | |
1085 | DRM_CURRENTPID, d.request_count, dma->buf_count); | |
1da177e4 LT |
1086 | return DRM_ERR(EINVAL); |
1087 | } | |
1088 | ||
b5e89ed5 | 1089 | WRAP_TEST_WITH_RETURN(dev_priv); |
1da177e4 LT |
1090 | |
1091 | d.granted_count = 0; | |
1092 | ||
b5e89ed5 DA |
1093 | if (d.request_count) { |
1094 | ret = mga_dma_get_buffers(filp, dev, &d); | |
1da177e4 LT |
1095 | } |
1096 | ||
b5e89ed5 | 1097 | DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); |
1da177e4 LT |
1098 | |
1099 | return ret; | |
1100 | } | |
1101 | ||
6795c985 DA |
1102 | /** |
1103 | * Called just before the module is unloaded. | |
1104 | */ | |
1105 | int mga_driver_postcleanup(drm_device_t * dev) | |
1106 | { | |
1107 | drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER); | |
1108 | dev->dev_private = NULL; | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | /** | |
1114 | * Called when the last opener of the device is closed. | |
1115 | */ | |
1116 | void mga_driver_pretakedown(drm_device_t * dev) | |
1da177e4 | 1117 | { |
b5e89ed5 | 1118 | mga_do_cleanup_dma(dev); |
1da177e4 LT |
1119 | } |
1120 | ||
b5e89ed5 | 1121 | int mga_driver_dma_quiescent(drm_device_t * dev) |
1da177e4 LT |
1122 | { |
1123 | drm_mga_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1124 | return mga_do_wait_for_idle(dev_priv); |
1da177e4 | 1125 | } |