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414ed537 DA |
1 | /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*- |
2 | * | |
3 | * Copyright (C) The Weather Channel, Inc. 2002. | |
4 | * Copyright (C) 2004 Nicolai Haehnle. | |
5 | * All Rights Reserved. | |
6 | * | |
7 | * The Weather Channel (TM) funded Tungsten Graphics to develop the | |
8 | * initial release of the Radeon 8500 driver under the XFree86 license. | |
9 | * This notice must be preserved. | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the next | |
19 | * paragraph) shall be included in all copies or substantial portions of the | |
20 | * Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
26 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
27 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | * | |
30 | * Authors: | |
31 | * Nicolai Haehnle <prefect_@gmx.net> | |
32 | */ | |
33 | ||
34 | #include "drmP.h" | |
35 | #include "drm.h" | |
36 | #include "radeon_drm.h" | |
37 | #include "radeon_drv.h" | |
38 | #include "r300_reg.h" | |
39 | ||
414ed537 DA |
40 | #define R300_SIMULTANEOUS_CLIPRECTS 4 |
41 | ||
42 | /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects | |
43 | */ | |
44 | static const int r300_cliprect_cntl[4] = { | |
45 | 0xAAAA, | |
46 | 0xEEEE, | |
47 | 0xFEFE, | |
48 | 0xFFFE | |
49 | }; | |
50 | ||
414ed537 DA |
51 | /** |
52 | * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command | |
53 | * buffer, starting with index n. | |
54 | */ | |
d985c108 DA |
55 | static int r300_emit_cliprects(drm_radeon_private_t *dev_priv, |
56 | drm_radeon_kcmd_buffer_t *cmdbuf, int n) | |
414ed537 | 57 | { |
c60ce623 | 58 | struct drm_clip_rect box; |
414ed537 DA |
59 | int nr; |
60 | int i; | |
61 | RING_LOCALS; | |
62 | ||
63 | nr = cmdbuf->nbox - n; | |
64 | if (nr > R300_SIMULTANEOUS_CLIPRECTS) | |
65 | nr = R300_SIMULTANEOUS_CLIPRECTS; | |
66 | ||
67 | DRM_DEBUG("%i cliprects\n", nr); | |
68 | ||
69 | if (nr) { | |
b5e89ed5 DA |
70 | BEGIN_RING(6 + nr * 2); |
71 | OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); | |
414ed537 | 72 | |
b5e89ed5 DA |
73 | for (i = 0; i < nr; ++i) { |
74 | if (DRM_COPY_FROM_USER_UNCHECKED | |
75 | (&box, &cmdbuf->boxes[n + i], sizeof(box))) { | |
414ed537 DA |
76 | DRM_ERROR("copy cliprect faulted\n"); |
77 | return DRM_ERR(EFAULT); | |
78 | } | |
79 | ||
b5e89ed5 DA |
80 | box.x1 = |
81 | (box.x1 + | |
82 | R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; | |
83 | box.y1 = | |
84 | (box.y1 + | |
85 | R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; | |
86 | box.x2 = | |
87 | (box.x2 + | |
88 | R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; | |
89 | box.y2 = | |
90 | (box.y2 + | |
91 | R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; | |
414ed537 DA |
92 | |
93 | OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | | |
b5e89ed5 | 94 | (box.y1 << R300_CLIPRECT_Y_SHIFT)); |
414ed537 | 95 | OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | |
b5e89ed5 | 96 | (box.y2 << R300_CLIPRECT_Y_SHIFT)); |
414ed537 DA |
97 | } |
98 | ||
b5e89ed5 | 99 | OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]); |
414ed537 DA |
100 | |
101 | /* TODO/SECURITY: Force scissors to a safe value, otherwise the | |
b5e89ed5 DA |
102 | * client might be able to trample over memory. |
103 | * The impact should be very limited, but I'd rather be safe than | |
104 | * sorry. | |
105 | */ | |
106 | OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); | |
107 | OUT_RING(0); | |
108 | OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); | |
414ed537 | 109 | ADVANCE_RING(); |
b5e89ed5 | 110 | } else { |
414ed537 DA |
111 | /* Why we allow zero cliprect rendering: |
112 | * There are some commands in a command buffer that must be submitted | |
113 | * even when there are no cliprects, e.g. DMA buffer discard | |
114 | * or state setting (though state setting could be avoided by | |
115 | * simulating a loss of context). | |
116 | * | |
117 | * Now since the cmdbuf interface is so chaotic right now (and is | |
118 | * bound to remain that way for a bit until things settle down), | |
119 | * it is basically impossible to filter out the commands that are | |
120 | * necessary and those that aren't. | |
121 | * | |
122 | * So I choose the safe way and don't do any filtering at all; | |
123 | * instead, I simply set up the engine so that all rendering | |
124 | * can't produce any fragments. | |
125 | */ | |
126 | BEGIN_RING(2); | |
b5e89ed5 | 127 | OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0); |
414ed537 | 128 | ADVANCE_RING(); |
b5e89ed5 | 129 | } |
414ed537 DA |
130 | |
131 | return 0; | |
132 | } | |
133 | ||
b3a83639 | 134 | static u8 r300_reg_flags[0x10000 >> 2]; |
414ed537 DA |
135 | |
136 | void r300_init_reg_flags(void) | |
137 | { | |
138 | int i; | |
b5e89ed5 DA |
139 | memset(r300_reg_flags, 0, 0x10000 >> 2); |
140 | #define ADD_RANGE_MARK(reg, count,mark) \ | |
414ed537 DA |
141 | for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\ |
142 | r300_reg_flags[i]|=(mark); | |
b5e89ed5 DA |
143 | |
144 | #define MARK_SAFE 1 | |
145 | #define MARK_CHECK_OFFSET 2 | |
146 | ||
147 | #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) | |
414ed537 DA |
148 | |
149 | /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */ | |
150 | ADD_RANGE(R300_SE_VPORT_XSCALE, 6); | |
c6c656b4 | 151 | ADD_RANGE(R300_VAP_CNTL, 1); |
414ed537 DA |
152 | ADD_RANGE(R300_SE_VTE_CNTL, 2); |
153 | ADD_RANGE(0x2134, 2); | |
c6c656b4 | 154 | ADD_RANGE(R300_VAP_CNTL_STATUS, 1); |
414ed537 DA |
155 | ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2); |
156 | ADD_RANGE(0x21DC, 1); | |
c6c656b4 OM |
157 | ADD_RANGE(R300_VAP_UNKNOWN_221C, 1); |
158 | ADD_RANGE(R300_VAP_CLIP_X_0, 4); | |
159 | ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1); | |
160 | ADD_RANGE(R300_VAP_UNKNOWN_2288, 1); | |
414ed537 DA |
161 | ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2); |
162 | ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); | |
163 | ADD_RANGE(R300_GB_ENABLE, 1); | |
164 | ADD_RANGE(R300_GB_MSPOS0, 5); | |
4e5e2e25 | 165 | ADD_RANGE(R300_TX_CNTL, 1); |
414ed537 DA |
166 | ADD_RANGE(R300_TX_ENABLE, 1); |
167 | ADD_RANGE(0x4200, 4); | |
168 | ADD_RANGE(0x4214, 1); | |
169 | ADD_RANGE(R300_RE_POINTSIZE, 1); | |
170 | ADD_RANGE(0x4230, 3); | |
171 | ADD_RANGE(R300_RE_LINE_CNT, 1); | |
c6c656b4 | 172 | ADD_RANGE(R300_RE_UNK4238, 1); |
414ed537 | 173 | ADD_RANGE(0x4260, 3); |
c6c656b4 OM |
174 | ADD_RANGE(R300_RE_SHADE, 4); |
175 | ADD_RANGE(R300_RE_POLYGON_MODE, 5); | |
176 | ADD_RANGE(R300_RE_ZBIAS_CNTL, 1); | |
414ed537 | 177 | ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4); |
c6c656b4 | 178 | ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1); |
414ed537 DA |
179 | ADD_RANGE(R300_RE_CULL_CNTL, 1); |
180 | ADD_RANGE(0x42C0, 2); | |
181 | ADD_RANGE(R300_RS_CNTL_0, 2); | |
182 | ADD_RANGE(R300_RS_INTERP_0, 8); | |
183 | ADD_RANGE(R300_RS_ROUTE_0, 8); | |
184 | ADD_RANGE(0x43A4, 2); | |
185 | ADD_RANGE(0x43E8, 1); | |
186 | ADD_RANGE(R300_PFS_CNTL_0, 3); | |
187 | ADD_RANGE(R300_PFS_NODE_0, 4); | |
188 | ADD_RANGE(R300_PFS_TEXI_0, 64); | |
189 | ADD_RANGE(0x46A4, 5); | |
190 | ADD_RANGE(R300_PFS_INSTR0_0, 64); | |
191 | ADD_RANGE(R300_PFS_INSTR1_0, 64); | |
192 | ADD_RANGE(R300_PFS_INSTR2_0, 64); | |
193 | ADD_RANGE(R300_PFS_INSTR3_0, 64); | |
c6c656b4 OM |
194 | ADD_RANGE(R300_RE_FOG_STATE, 1); |
195 | ADD_RANGE(R300_FOG_COLOR_R, 3); | |
414ed537 DA |
196 | ADD_RANGE(R300_PP_ALPHA_TEST, 2); |
197 | ADD_RANGE(0x4BD8, 1); | |
198 | ADD_RANGE(R300_PFS_PARAM_0_X, 64); | |
199 | ADD_RANGE(0x4E00, 1); | |
200 | ADD_RANGE(R300_RB3D_CBLEND, 2); | |
201 | ADD_RANGE(R300_RB3D_COLORMASK, 1); | |
c6c656b4 | 202 | ADD_RANGE(R300_RB3D_BLEND_COLOR, 3); |
b5e89ed5 | 203 | ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */ |
414ed537 DA |
204 | ADD_RANGE(R300_RB3D_COLORPITCH0, 1); |
205 | ADD_RANGE(0x4E50, 9); | |
206 | ADD_RANGE(0x4E88, 1); | |
207 | ADD_RANGE(0x4EA0, 2); | |
208 | ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); | |
c6c656b4 | 209 | ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4); |
b5e89ed5 DA |
210 | ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ |
211 | ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); | |
414ed537 DA |
212 | ADD_RANGE(0x4F28, 1); |
213 | ADD_RANGE(0x4F30, 2); | |
214 | ADD_RANGE(0x4F44, 1); | |
215 | ADD_RANGE(0x4F54, 1); | |
216 | ||
217 | ADD_RANGE(R300_TX_FILTER_0, 16); | |
45f17100 | 218 | ADD_RANGE(R300_TX_FILTER1_0, 16); |
414ed537 DA |
219 | ADD_RANGE(R300_TX_SIZE_0, 16); |
220 | ADD_RANGE(R300_TX_FORMAT_0, 16); | |
d985c108 | 221 | ADD_RANGE(R300_TX_PITCH_0, 16); |
b5e89ed5 | 222 | /* Texture offset is dangerous and needs more checking */ |
414ed537 | 223 | ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET); |
45f17100 | 224 | ADD_RANGE(R300_TX_CHROMA_KEY_0, 16); |
414ed537 DA |
225 | ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); |
226 | ||
227 | /* Sporadic registers used as primitives are emitted */ | |
c6c656b4 | 228 | ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1); |
414ed537 DA |
229 | ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); |
230 | ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); | |
231 | ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); | |
232 | ||
233 | } | |
234 | ||
b5e89ed5 | 235 | static __inline__ int r300_check_range(unsigned reg, int count) |
414ed537 DA |
236 | { |
237 | int i; | |
b5e89ed5 DA |
238 | if (reg & ~0xffff) |
239 | return -1; | |
240 | for (i = (reg >> 2); i < (reg >> 2) + count; i++) | |
241 | if (r300_reg_flags[i] != MARK_SAFE) | |
242 | return 1; | |
414ed537 DA |
243 | return 0; |
244 | } | |
245 | ||
b5e89ed5 DA |
246 | static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * |
247 | dev_priv, | |
b3a83639 | 248 | drm_radeon_kcmd_buffer_t |
b5e89ed5 DA |
249 | * cmdbuf, |
250 | drm_r300_cmd_header_t | |
251 | header) | |
414ed537 DA |
252 | { |
253 | int reg; | |
254 | int sz; | |
255 | int i; | |
256 | int values[64]; | |
257 | RING_LOCALS; | |
258 | ||
259 | sz = header.packet0.count; | |
260 | reg = (header.packet0.reghi << 8) | header.packet0.reglo; | |
b5e89ed5 DA |
261 | |
262 | if ((sz > 64) || (sz < 0)) { | |
263 | DRM_ERROR | |
264 | ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", | |
265 | reg, sz); | |
414ed537 | 266 | return DRM_ERR(EINVAL); |
b5e89ed5 DA |
267 | } |
268 | for (i = 0; i < sz; i++) { | |
b3a83639 | 269 | values[i] = ((int *)cmdbuf->buf)[i]; |
b5e89ed5 | 270 | switch (r300_reg_flags[(reg >> 2) + i]) { |
414ed537 DA |
271 | case MARK_SAFE: |
272 | break; | |
273 | case MARK_CHECK_OFFSET: | |
1d6bb8e5 | 274 | if (!radeon_check_offset(dev_priv, (u32) values[i])) { |
b5e89ed5 DA |
275 | DRM_ERROR |
276 | ("Offset failed range check (reg=%04x sz=%d)\n", | |
277 | reg, sz); | |
414ed537 | 278 | return DRM_ERR(EINVAL); |
b5e89ed5 | 279 | } |
414ed537 DA |
280 | break; |
281 | default: | |
b5e89ed5 DA |
282 | DRM_ERROR("Register %04x failed check as flag=%02x\n", |
283 | reg + i * 4, r300_reg_flags[(reg >> 2) + i]); | |
414ed537 | 284 | return DRM_ERR(EINVAL); |
414ed537 | 285 | } |
b5e89ed5 DA |
286 | } |
287 | ||
288 | BEGIN_RING(1 + sz); | |
289 | OUT_RING(CP_PACKET0(reg, sz - 1)); | |
290 | OUT_RING_TABLE(values, sz); | |
414ed537 DA |
291 | ADVANCE_RING(); |
292 | ||
b5e89ed5 DA |
293 | cmdbuf->buf += sz * 4; |
294 | cmdbuf->bufsz -= sz * 4; | |
414ed537 DA |
295 | |
296 | return 0; | |
297 | } | |
298 | ||
299 | /** | |
300 | * Emits a packet0 setting arbitrary registers. | |
301 | * Called by r300_do_cp_cmdbuf. | |
302 | * | |
303 | * Note that checks are performed on contents and addresses of the registers | |
304 | */ | |
d985c108 DA |
305 | static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv, |
306 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
b5e89ed5 | 307 | drm_r300_cmd_header_t header) |
414ed537 DA |
308 | { |
309 | int reg; | |
310 | int sz; | |
311 | RING_LOCALS; | |
312 | ||
313 | sz = header.packet0.count; | |
314 | reg = (header.packet0.reghi << 8) | header.packet0.reglo; | |
315 | ||
316 | if (!sz) | |
317 | return 0; | |
318 | ||
b5e89ed5 | 319 | if (sz * 4 > cmdbuf->bufsz) |
414ed537 | 320 | return DRM_ERR(EINVAL); |
b5e89ed5 DA |
321 | |
322 | if (reg + sz * 4 >= 0x10000) { | |
323 | DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, | |
324 | sz); | |
414ed537 | 325 | return DRM_ERR(EINVAL); |
b5e89ed5 | 326 | } |
414ed537 | 327 | |
b5e89ed5 | 328 | if (r300_check_range(reg, sz)) { |
414ed537 | 329 | /* go and check everything */ |
b5e89ed5 DA |
330 | return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, |
331 | header); | |
332 | } | |
414ed537 DA |
333 | /* the rest of the data is safe to emit, whatever the values the user passed */ |
334 | ||
b5e89ed5 DA |
335 | BEGIN_RING(1 + sz); |
336 | OUT_RING(CP_PACKET0(reg, sz - 1)); | |
b3a83639 | 337 | OUT_RING_TABLE((int *)cmdbuf->buf, sz); |
414ed537 DA |
338 | ADVANCE_RING(); |
339 | ||
b5e89ed5 DA |
340 | cmdbuf->buf += sz * 4; |
341 | cmdbuf->bufsz -= sz * 4; | |
414ed537 DA |
342 | |
343 | return 0; | |
344 | } | |
345 | ||
414ed537 DA |
346 | /** |
347 | * Uploads user-supplied vertex program instructions or parameters onto | |
348 | * the graphics card. | |
349 | * Called by r300_do_cp_cmdbuf. | |
350 | */ | |
d985c108 DA |
351 | static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv, |
352 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
414ed537 DA |
353 | drm_r300_cmd_header_t header) |
354 | { | |
355 | int sz; | |
356 | int addr; | |
357 | RING_LOCALS; | |
358 | ||
359 | sz = header.vpu.count; | |
360 | addr = (header.vpu.adrhi << 8) | header.vpu.adrlo; | |
361 | ||
362 | if (!sz) | |
363 | return 0; | |
b5e89ed5 | 364 | if (sz * 16 > cmdbuf->bufsz) |
414ed537 DA |
365 | return DRM_ERR(EINVAL); |
366 | ||
b5e89ed5 | 367 | BEGIN_RING(5 + sz * 4); |
414ed537 DA |
368 | /* Wait for VAP to come to senses.. */ |
369 | /* there is no need to emit it multiple times, (only once before VAP is programmed, | |
370 | but this optimization is for later */ | |
b5e89ed5 DA |
371 | OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0); |
372 | OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr); | |
373 | OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); | |
b3a83639 | 374 | OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4); |
414ed537 DA |
375 | |
376 | ADVANCE_RING(); | |
377 | ||
b5e89ed5 DA |
378 | cmdbuf->buf += sz * 16; |
379 | cmdbuf->bufsz -= sz * 16; | |
414ed537 DA |
380 | |
381 | return 0; | |
382 | } | |
383 | ||
414ed537 DA |
384 | /** |
385 | * Emit a clear packet from userspace. | |
386 | * Called by r300_emit_packet3. | |
387 | */ | |
d985c108 DA |
388 | static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv, |
389 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
414ed537 DA |
390 | { |
391 | RING_LOCALS; | |
392 | ||
b5e89ed5 | 393 | if (8 * 4 > cmdbuf->bufsz) |
414ed537 DA |
394 | return DRM_ERR(EINVAL); |
395 | ||
396 | BEGIN_RING(10); | |
b5e89ed5 DA |
397 | OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); |
398 | OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | | |
399 | (1 << R300_PRIM_NUM_VERTICES_SHIFT)); | |
b3a83639 | 400 | OUT_RING_TABLE((int *)cmdbuf->buf, 8); |
414ed537 DA |
401 | ADVANCE_RING(); |
402 | ||
b5e89ed5 DA |
403 | cmdbuf->buf += 8 * 4; |
404 | cmdbuf->bufsz -= 8 * 4; | |
414ed537 DA |
405 | |
406 | return 0; | |
407 | } | |
408 | ||
d985c108 DA |
409 | static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, |
410 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
b5e89ed5 | 411 | u32 header) |
414ed537 | 412 | { |
b5e89ed5 DA |
413 | int count, i, k; |
414 | #define MAX_ARRAY_PACKET 64 | |
414ed537 DA |
415 | u32 payload[MAX_ARRAY_PACKET]; |
416 | u32 narrays; | |
417 | RING_LOCALS; | |
418 | ||
b5e89ed5 DA |
419 | count = (header >> 16) & 0x3fff; |
420 | ||
421 | if ((count + 1) > MAX_ARRAY_PACKET) { | |
422 | DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", | |
423 | count); | |
414ed537 | 424 | return DRM_ERR(EINVAL); |
b5e89ed5 DA |
425 | } |
426 | memset(payload, 0, MAX_ARRAY_PACKET * 4); | |
427 | memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4); | |
428 | ||
414ed537 | 429 | /* carefully check packet contents */ |
b5e89ed5 DA |
430 | |
431 | narrays = payload[0]; | |
432 | k = 0; | |
433 | i = 1; | |
434 | while ((k < narrays) && (i < (count + 1))) { | |
435 | i++; /* skip attribute field */ | |
1d6bb8e5 | 436 | if (!radeon_check_offset(dev_priv, payload[i])) { |
b5e89ed5 DA |
437 | DRM_ERROR |
438 | ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", | |
439 | k, i); | |
414ed537 | 440 | return DRM_ERR(EINVAL); |
b5e89ed5 | 441 | } |
414ed537 DA |
442 | k++; |
443 | i++; | |
b5e89ed5 DA |
444 | if (k == narrays) |
445 | break; | |
414ed537 | 446 | /* have one more to process, they come in pairs */ |
1d6bb8e5 | 447 | if (!radeon_check_offset(dev_priv, payload[i])) { |
b5e89ed5 DA |
448 | DRM_ERROR |
449 | ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", | |
450 | k, i); | |
414ed537 | 451 | return DRM_ERR(EINVAL); |
414ed537 | 452 | } |
b5e89ed5 DA |
453 | k++; |
454 | i++; | |
455 | } | |
414ed537 | 456 | /* do the counts match what we expect ? */ |
b5e89ed5 DA |
457 | if ((k != narrays) || (i != (count + 1))) { |
458 | DRM_ERROR | |
459 | ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", | |
460 | k, i, narrays, count + 1); | |
414ed537 | 461 | return DRM_ERR(EINVAL); |
b5e89ed5 | 462 | } |
414ed537 DA |
463 | |
464 | /* all clear, output packet */ | |
465 | ||
b5e89ed5 | 466 | BEGIN_RING(count + 2); |
414ed537 | 467 | OUT_RING(header); |
b5e89ed5 | 468 | OUT_RING_TABLE(payload, count + 1); |
414ed537 DA |
469 | ADVANCE_RING(); |
470 | ||
b5e89ed5 DA |
471 | cmdbuf->buf += (count + 2) * 4; |
472 | cmdbuf->bufsz -= (count + 2) * 4; | |
414ed537 DA |
473 | |
474 | return 0; | |
475 | } | |
d5ea702f | 476 | |
4e5e2e25 DA |
477 | static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, |
478 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
479 | { | |
480 | u32 *cmd = (u32 *) cmdbuf->buf; | |
481 | int count, ret; | |
482 | RING_LOCALS; | |
483 | ||
484 | count=(cmd[0]>>16) & 0x3fff; | |
485 | ||
486 | if (cmd[0] & 0x8000) { | |
487 | u32 offset; | |
488 | ||
489 | if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
490 | | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { | |
491 | offset = cmd[2] << 10; | |
1d6bb8e5 | 492 | ret = !radeon_check_offset(dev_priv, offset); |
73d72cff | 493 | if (ret) { |
4e5e2e25 DA |
494 | DRM_ERROR("Invalid bitblt first offset is %08X\n", offset); |
495 | return DRM_ERR(EINVAL); | |
496 | } | |
497 | } | |
498 | ||
499 | if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && | |
500 | (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { | |
501 | offset = cmd[3] << 10; | |
1d6bb8e5 | 502 | ret = !radeon_check_offset(dev_priv, offset); |
73d72cff | 503 | if (ret) { |
4e5e2e25 DA |
504 | DRM_ERROR("Invalid bitblt second offset is %08X\n", offset); |
505 | return DRM_ERR(EINVAL); | |
506 | } | |
507 | ||
508 | } | |
509 | } | |
510 | ||
511 | BEGIN_RING(count+2); | |
512 | OUT_RING(cmd[0]); | |
513 | OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); | |
514 | ADVANCE_RING(); | |
515 | ||
516 | cmdbuf->buf += (count+2)*4; | |
517 | cmdbuf->bufsz -= (count+2)*4; | |
518 | ||
519 | return 0; | |
520 | } | |
414ed537 | 521 | |
a1aa2897 RS |
522 | static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv, |
523 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
524 | { | |
525 | u32 *cmd = (u32 *) cmdbuf->buf; | |
526 | int count, ret; | |
527 | RING_LOCALS; | |
528 | ||
529 | count=(cmd[0]>>16) & 0x3fff; | |
530 | ||
531 | if ((cmd[1] & 0x8000ffff) != 0x80000810) { | |
532 | DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); | |
533 | return DRM_ERR(EINVAL); | |
534 | } | |
1d6bb8e5 | 535 | ret = !radeon_check_offset(dev_priv, cmd[2]); |
a1aa2897 RS |
536 | if (ret) { |
537 | DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); | |
538 | return DRM_ERR(EINVAL); | |
539 | } | |
540 | ||
541 | BEGIN_RING(count+2); | |
542 | OUT_RING(cmd[0]); | |
543 | OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); | |
544 | ADVANCE_RING(); | |
545 | ||
546 | cmdbuf->buf += (count+2)*4; | |
547 | cmdbuf->bufsz -= (count+2)*4; | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
d985c108 DA |
552 | static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, |
553 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
414ed537 DA |
554 | { |
555 | u32 header; | |
556 | int count; | |
557 | RING_LOCALS; | |
558 | ||
559 | if (4 > cmdbuf->bufsz) | |
560 | return DRM_ERR(EINVAL); | |
561 | ||
b5e89ed5 | 562 | /* Fixme !! This simply emits a packet without much checking. |
414ed537 DA |
563 | We need to be smarter. */ |
564 | ||
565 | /* obtain first word - actual packet3 header */ | |
b3a83639 | 566 | header = *(u32 *) cmdbuf->buf; |
414ed537 DA |
567 | |
568 | /* Is it packet 3 ? */ | |
b5e89ed5 | 569 | if ((header >> 30) != 0x3) { |
414ed537 DA |
570 | DRM_ERROR("Not a packet3 header (0x%08x)\n", header); |
571 | return DRM_ERR(EINVAL); | |
b5e89ed5 | 572 | } |
414ed537 | 573 | |
b5e89ed5 | 574 | count = (header >> 16) & 0x3fff; |
414ed537 DA |
575 | |
576 | /* Check again now that we know how much data to expect */ | |
b5e89ed5 DA |
577 | if ((count + 2) * 4 > cmdbuf->bufsz) { |
578 | DRM_ERROR | |
579 | ("Expected packet3 of length %d but have only %d bytes left\n", | |
580 | (count + 2) * 4, cmdbuf->bufsz); | |
414ed537 | 581 | return DRM_ERR(EINVAL); |
b5e89ed5 | 582 | } |
414ed537 DA |
583 | |
584 | /* Is it a packet type we know about ? */ | |
b5e89ed5 DA |
585 | switch (header & 0xff00) { |
586 | case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ | |
414ed537 DA |
587 | return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header); |
588 | ||
4e5e2e25 DA |
589 | case RADEON_CNTL_BITBLT_MULTI: |
590 | return r300_emit_bitblt_multi(dev_priv, cmdbuf); | |
591 | ||
a1aa2897 RS |
592 | case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */ |
593 | return r300_emit_indx_buffer(dev_priv, cmdbuf); | |
b5e89ed5 DA |
594 | case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */ |
595 | case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */ | |
596 | case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */ | |
414ed537 DA |
597 | case RADEON_WAIT_FOR_IDLE: |
598 | case RADEON_CP_NOP: | |
599 | /* these packets are safe */ | |
600 | break; | |
601 | default: | |
602 | DRM_ERROR("Unknown packet3 header (0x%08x)\n", header); | |
603 | return DRM_ERR(EINVAL); | |
b5e89ed5 | 604 | } |
414ed537 | 605 | |
b5e89ed5 | 606 | BEGIN_RING(count + 2); |
414ed537 | 607 | OUT_RING(header); |
b3a83639 | 608 | OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); |
414ed537 DA |
609 | ADVANCE_RING(); |
610 | ||
b5e89ed5 DA |
611 | cmdbuf->buf += (count + 2) * 4; |
612 | cmdbuf->bufsz -= (count + 2) * 4; | |
414ed537 DA |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
414ed537 DA |
617 | /** |
618 | * Emit a rendering packet3 from userspace. | |
619 | * Called by r300_do_cp_cmdbuf. | |
620 | */ | |
d985c108 DA |
621 | static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, |
622 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
414ed537 DA |
623 | drm_r300_cmd_header_t header) |
624 | { | |
625 | int n; | |
626 | int ret; | |
b3a83639 | 627 | char *orig_buf = cmdbuf->buf; |
414ed537 DA |
628 | int orig_bufsz = cmdbuf->bufsz; |
629 | ||
630 | /* This is a do-while-loop so that we run the interior at least once, | |
631 | * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale. | |
632 | */ | |
633 | n = 0; | |
634 | do { | |
635 | if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) { | |
636 | ret = r300_emit_cliprects(dev_priv, cmdbuf, n); | |
637 | if (ret) | |
638 | return ret; | |
639 | ||
640 | cmdbuf->buf = orig_buf; | |
641 | cmdbuf->bufsz = orig_bufsz; | |
b5e89ed5 | 642 | } |
414ed537 | 643 | |
b5e89ed5 | 644 | switch (header.packet3.packet) { |
414ed537 DA |
645 | case R300_CMD_PACKET3_CLEAR: |
646 | DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n"); | |
647 | ret = r300_emit_clear(dev_priv, cmdbuf); | |
648 | if (ret) { | |
649 | DRM_ERROR("r300_emit_clear failed\n"); | |
650 | return ret; | |
b5e89ed5 | 651 | } |
414ed537 DA |
652 | break; |
653 | ||
654 | case R300_CMD_PACKET3_RAW: | |
655 | DRM_DEBUG("R300_CMD_PACKET3_RAW\n"); | |
656 | ret = r300_emit_raw_packet3(dev_priv, cmdbuf); | |
657 | if (ret) { | |
658 | DRM_ERROR("r300_emit_raw_packet3 failed\n"); | |
659 | return ret; | |
b5e89ed5 | 660 | } |
414ed537 DA |
661 | break; |
662 | ||
663 | default: | |
664 | DRM_ERROR("bad packet3 type %i at %p\n", | |
b5e89ed5 DA |
665 | header.packet3.packet, |
666 | cmdbuf->buf - sizeof(header)); | |
414ed537 | 667 | return DRM_ERR(EINVAL); |
b5e89ed5 | 668 | } |
414ed537 DA |
669 | |
670 | n += R300_SIMULTANEOUS_CLIPRECTS; | |
b5e89ed5 | 671 | } while (n < cmdbuf->nbox); |
414ed537 DA |
672 | |
673 | return 0; | |
674 | } | |
675 | ||
676 | /* Some of the R300 chips seem to be extremely touchy about the two registers | |
677 | * that are configured in r300_pacify. | |
678 | * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace | |
679 | * sends a command buffer that contains only state setting commands and a | |
680 | * vertex program/parameter upload sequence, this will eventually lead to a | |
681 | * lockup, unless the sequence is bracketed by calls to r300_pacify. | |
682 | * So we should take great care to *always* call r300_pacify before | |
683 | * *anything* 3D related, and again afterwards. This is what the | |
684 | * call bracket in r300_do_cp_cmdbuf is for. | |
685 | */ | |
686 | ||
687 | /** | |
688 | * Emit the sequence to pacify R300. | |
689 | */ | |
d985c108 | 690 | static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv) |
414ed537 DA |
691 | { |
692 | RING_LOCALS; | |
693 | ||
694 | BEGIN_RING(6); | |
b5e89ed5 | 695 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
c6c656b4 OM |
696 | OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); |
697 | OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
698 | OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03); | |
b5e89ed5 DA |
699 | OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); |
700 | OUT_RING(0x0); | |
414ed537 DA |
701 | ADVANCE_RING(); |
702 | } | |
703 | ||
414ed537 DA |
704 | /** |
705 | * Called by r300_do_cp_cmdbuf to update the internal buffer age and state. | |
706 | * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must | |
707 | * be careful about how this function is called. | |
708 | */ | |
84b1fd10 | 709 | static void r300_discard_buffer(struct drm_device * dev, drm_buf_t * buf) |
414ed537 DA |
710 | { |
711 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
712 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; | |
713 | ||
714 | buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; | |
715 | buf->pending = 1; | |
716 | buf->used = 0; | |
717 | } | |
718 | ||
ee4621f0 DA |
719 | static int r300_scratch(drm_radeon_private_t *dev_priv, |
720 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
721 | drm_r300_cmd_header_t header) | |
722 | { | |
723 | u32 *ref_age_base; | |
724 | u32 i, buf_idx, h_pending; | |
725 | RING_LOCALS; | |
726 | ||
727 | if (cmdbuf->bufsz < | |
728 | (sizeof(u64) + header.scratch.n_bufs * sizeof(buf_idx))) { | |
729 | return DRM_ERR(EINVAL); | |
730 | } | |
731 | ||
732 | if (header.scratch.reg >= 5) { | |
733 | return DRM_ERR(EINVAL); | |
734 | } | |
735 | ||
736 | dev_priv->scratch_ages[header.scratch.reg]++; | |
737 | ||
caa98c41 | 738 | ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf); |
ee4621f0 DA |
739 | |
740 | cmdbuf->buf += sizeof(u64); | |
741 | cmdbuf->bufsz -= sizeof(u64); | |
742 | ||
743 | for (i=0; i < header.scratch.n_bufs; i++) { | |
744 | buf_idx = *(u32 *)cmdbuf->buf; | |
745 | buf_idx *= 2; /* 8 bytes per buf */ | |
746 | ||
747 | if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) { | |
748 | return DRM_ERR(EINVAL); | |
749 | } | |
750 | ||
751 | if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) { | |
752 | return DRM_ERR(EINVAL); | |
753 | } | |
754 | ||
755 | if (h_pending == 0) { | |
756 | return DRM_ERR(EINVAL); | |
757 | } | |
758 | ||
759 | h_pending--; | |
760 | ||
761 | if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) { | |
762 | return DRM_ERR(EINVAL); | |
763 | } | |
764 | ||
765 | cmdbuf->buf += sizeof(buf_idx); | |
766 | cmdbuf->bufsz -= sizeof(buf_idx); | |
767 | } | |
768 | ||
769 | BEGIN_RING(2); | |
c6c656b4 OM |
770 | OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) ); |
771 | OUT_RING( dev_priv->scratch_ages[header.scratch.reg] ); | |
ee4621f0 DA |
772 | ADVANCE_RING(); |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
414ed537 DA |
777 | /** |
778 | * Parses and validates a user-supplied command buffer and emits appropriate | |
779 | * commands on the DMA ring buffer. | |
780 | * Called by the ioctl handler function radeon_cp_cmdbuf. | |
781 | */ | |
84b1fd10 | 782 | int r300_do_cp_cmdbuf(struct drm_device *dev, |
b5e89ed5 | 783 | DRMFILE filp, |
84b1fd10 | 784 | struct drm_file *filp_priv, |
d985c108 | 785 | drm_radeon_kcmd_buffer_t *cmdbuf) |
414ed537 DA |
786 | { |
787 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 DA |
788 | drm_device_dma_t *dma = dev->dma; |
789 | drm_buf_t *buf = NULL; | |
414ed537 DA |
790 | int emit_dispatch_age = 0; |
791 | int ret = 0; | |
792 | ||
793 | DRM_DEBUG("\n"); | |
794 | ||
795 | /* See the comment above r300_emit_begin3d for why this call must be here, | |
796 | * and what the cleanup gotos are for. */ | |
797 | r300_pacify(dev_priv); | |
798 | ||
799 | if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) { | |
800 | ret = r300_emit_cliprects(dev_priv, cmdbuf, 0); | |
801 | if (ret) | |
802 | goto cleanup; | |
b5e89ed5 | 803 | } |
414ed537 | 804 | |
b5e89ed5 | 805 | while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) { |
414ed537 DA |
806 | int idx; |
807 | drm_r300_cmd_header_t header; | |
808 | ||
809 | header.u = *(unsigned int *)cmdbuf->buf; | |
810 | ||
811 | cmdbuf->buf += sizeof(header); | |
812 | cmdbuf->bufsz -= sizeof(header); | |
813 | ||
b5e89ed5 DA |
814 | switch (header.header.cmd_type) { |
815 | case R300_CMD_PACKET0: | |
414ed537 DA |
816 | DRM_DEBUG("R300_CMD_PACKET0\n"); |
817 | ret = r300_emit_packet0(dev_priv, cmdbuf, header); | |
818 | if (ret) { | |
819 | DRM_ERROR("r300_emit_packet0 failed\n"); | |
820 | goto cleanup; | |
b5e89ed5 | 821 | } |
414ed537 DA |
822 | break; |
823 | ||
824 | case R300_CMD_VPU: | |
825 | DRM_DEBUG("R300_CMD_VPU\n"); | |
826 | ret = r300_emit_vpu(dev_priv, cmdbuf, header); | |
827 | if (ret) { | |
828 | DRM_ERROR("r300_emit_vpu failed\n"); | |
829 | goto cleanup; | |
b5e89ed5 | 830 | } |
414ed537 DA |
831 | break; |
832 | ||
833 | case R300_CMD_PACKET3: | |
834 | DRM_DEBUG("R300_CMD_PACKET3\n"); | |
835 | ret = r300_emit_packet3(dev_priv, cmdbuf, header); | |
836 | if (ret) { | |
837 | DRM_ERROR("r300_emit_packet3 failed\n"); | |
838 | goto cleanup; | |
b5e89ed5 | 839 | } |
414ed537 DA |
840 | break; |
841 | ||
842 | case R300_CMD_END3D: | |
843 | DRM_DEBUG("R300_CMD_END3D\n"); | |
b5e89ed5 DA |
844 | /* TODO: |
845 | Ideally userspace driver should not need to issue this call, | |
846 | i.e. the drm driver should issue it automatically and prevent | |
847 | lockups. | |
848 | ||
849 | In practice, we do not understand why this call is needed and what | |
850 | it does (except for some vague guesses that it has to do with cache | |
851 | coherence) and so the user space driver does it. | |
852 | ||
853 | Once we are sure which uses prevent lockups the code could be moved | |
854 | into the kernel and the userspace driver will not | |
855 | need to use this command. | |
856 | ||
857 | Note that issuing this command does not hurt anything | |
858 | except, possibly, performance */ | |
414ed537 DA |
859 | r300_pacify(dev_priv); |
860 | break; | |
861 | ||
862 | case R300_CMD_CP_DELAY: | |
863 | /* simple enough, we can do it here */ | |
864 | DRM_DEBUG("R300_CMD_CP_DELAY\n"); | |
865 | { | |
866 | int i; | |
867 | RING_LOCALS; | |
868 | ||
869 | BEGIN_RING(header.delay.count); | |
b5e89ed5 | 870 | for (i = 0; i < header.delay.count; i++) |
414ed537 DA |
871 | OUT_RING(RADEON_CP_PACKET2); |
872 | ADVANCE_RING(); | |
873 | } | |
874 | break; | |
875 | ||
876 | case R300_CMD_DMA_DISCARD: | |
877 | DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); | |
b5e89ed5 DA |
878 | idx = header.dma.buf_idx; |
879 | if (idx < 0 || idx >= dma->buf_count) { | |
880 | DRM_ERROR("buffer index %d (of %d max)\n", | |
881 | idx, dma->buf_count - 1); | |
414ed537 | 882 | ret = DRM_ERR(EINVAL); |
414ed537 | 883 | goto cleanup; |
b5e89ed5 DA |
884 | } |
885 | ||
886 | buf = dma->buflist[idx]; | |
887 | if (buf->filp != filp || buf->pending) { | |
888 | DRM_ERROR("bad buffer %p %p %d\n", | |
889 | buf->filp, filp, buf->pending); | |
890 | ret = DRM_ERR(EINVAL); | |
891 | goto cleanup; | |
892 | } | |
414ed537 DA |
893 | |
894 | emit_dispatch_age = 1; | |
895 | r300_discard_buffer(dev, buf); | |
b5e89ed5 | 896 | break; |
414ed537 DA |
897 | |
898 | case R300_CMD_WAIT: | |
899 | /* simple enough, we can do it here */ | |
900 | DRM_DEBUG("R300_CMD_WAIT\n"); | |
b5e89ed5 DA |
901 | if (header.wait.flags == 0) |
902 | break; /* nothing to do */ | |
414ed537 DA |
903 | |
904 | { | |
905 | RING_LOCALS; | |
906 | ||
907 | BEGIN_RING(2); | |
b5e89ed5 DA |
908 | OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); |
909 | OUT_RING((header.wait.flags & 0xf) << 14); | |
414ed537 DA |
910 | ADVANCE_RING(); |
911 | } | |
912 | break; | |
913 | ||
ee4621f0 DA |
914 | case R300_CMD_SCRATCH: |
915 | DRM_DEBUG("R300_CMD_SCRATCH\n"); | |
916 | ret = r300_scratch(dev_priv, cmdbuf, header); | |
917 | if (ret) { | |
918 | DRM_ERROR("r300_scratch failed\n"); | |
919 | goto cleanup; | |
920 | } | |
921 | break; | |
922 | ||
414ed537 DA |
923 | default: |
924 | DRM_ERROR("bad cmd_type %i at %p\n", | |
b5e89ed5 | 925 | header.header.cmd_type, |
414ed537 DA |
926 | cmdbuf->buf - sizeof(header)); |
927 | ret = DRM_ERR(EINVAL); | |
928 | goto cleanup; | |
b5e89ed5 | 929 | } |
414ed537 DA |
930 | } |
931 | ||
932 | DRM_DEBUG("END\n"); | |
933 | ||
b5e89ed5 | 934 | cleanup: |
414ed537 DA |
935 | r300_pacify(dev_priv); |
936 | ||
937 | /* We emit the vertex buffer age here, outside the pacifier "brackets" | |
938 | * for two reasons: | |
939 | * (1) This may coalesce multiple age emissions into a single one and | |
940 | * (2) more importantly, some chips lock up hard when scratch registers | |
941 | * are written inside the pacifier bracket. | |
942 | */ | |
943 | if (emit_dispatch_age) { | |
944 | RING_LOCALS; | |
945 | ||
946 | /* Emit the vertex buffer age */ | |
947 | BEGIN_RING(2); | |
948 | RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch); | |
949 | ADVANCE_RING(); | |
b5e89ed5 | 950 | } |
414ed537 DA |
951 | |
952 | COMMIT_RING(); | |
953 | ||
954 | return ret; | |
955 | } |