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f26c473c DA |
1 | /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ |
2 | /* | |
1da177e4 LT |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
45e51905 | 5 | * Copyright 2007 Advanced Micro Devices, Inc. |
1da177e4 LT |
6 | * All Rights Reserved. |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: | |
28 | * Kevin E. Martin <martin@valinux.com> | |
29 | * Gareth Hughes <gareth@valinux.com> | |
30 | */ | |
31 | ||
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "radeon_drm.h" | |
35 | #include "radeon_drv.h" | |
414ed537 | 36 | #include "r300_reg.h" |
1da177e4 | 37 | |
9f18409e AD |
38 | #include "radeon_microcode.h" |
39 | ||
1da177e4 LT |
40 | #define RADEON_FIFO_DEBUG 0 |
41 | ||
84b1fd10 | 42 | static int radeon_do_cleanup_cp(struct drm_device * dev); |
1da177e4 | 43 | |
45e51905 | 44 | static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
3d5e2c13 DA |
45 | { |
46 | u32 ret; | |
47 | RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); | |
48 | ret = RADEON_READ(R520_MC_IND_DATA); | |
49 | RADEON_WRITE(R520_MC_IND_INDEX, 0); | |
50 | return ret; | |
51 | } | |
52 | ||
45e51905 AD |
53 | static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
54 | { | |
55 | u32 ret; | |
56 | RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); | |
57 | ret = RADEON_READ(RS480_NB_MC_DATA); | |
58 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); | |
59 | return ret; | |
60 | } | |
61 | ||
60f92683 MC |
62 | static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
63 | { | |
45e51905 | 64 | u32 ret; |
60f92683 | 65 | RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
45e51905 AD |
66 | ret = RADEON_READ(RS690_MC_DATA); |
67 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); | |
68 | return ret; | |
69 | } | |
70 | ||
71 | static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | |
72 | { | |
73 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | |
74 | return RS690_READ_MCIND(dev_priv, addr); | |
75 | else | |
76 | return RS480_READ_MCIND(dev_priv, addr); | |
60f92683 MC |
77 | } |
78 | ||
3d5e2c13 DA |
79 | u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) |
80 | { | |
81 | ||
82 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 83 | return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); |
60f92683 MC |
84 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
85 | return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); | |
3d5e2c13 | 86 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 87 | return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); |
3d5e2c13 DA |
88 | else |
89 | return RADEON_READ(RADEON_MC_FB_LOCATION); | |
90 | } | |
91 | ||
92 | static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) | |
93 | { | |
94 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 95 | R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); |
60f92683 MC |
96 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
97 | RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); | |
3d5e2c13 | 98 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 99 | R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); |
3d5e2c13 DA |
100 | else |
101 | RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); | |
102 | } | |
103 | ||
104 | static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) | |
105 | { | |
106 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 107 | R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); |
60f92683 MC |
108 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
109 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); | |
3d5e2c13 | 110 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 111 | R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); |
3d5e2c13 DA |
112 | else |
113 | RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); | |
114 | } | |
115 | ||
84b1fd10 | 116 | static int RADEON_READ_PLL(struct drm_device * dev, int addr) |
1da177e4 LT |
117 | { |
118 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
119 | ||
120 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); | |
121 | return RADEON_READ(RADEON_CLOCK_CNTL_DATA); | |
122 | } | |
123 | ||
3d5e2c13 | 124 | static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) |
ea98a92f DA |
125 | { |
126 | RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); | |
127 | return RADEON_READ(RADEON_PCIE_DATA); | |
128 | } | |
129 | ||
1da177e4 | 130 | #if RADEON_FIFO_DEBUG |
b5e89ed5 | 131 | static void radeon_status(drm_radeon_private_t * dev_priv) |
1da177e4 | 132 | { |
bf9d8929 | 133 | printk("%s:\n", __func__); |
b5e89ed5 DA |
134 | printk("RBBM_STATUS = 0x%08x\n", |
135 | (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); | |
136 | printk("CP_RB_RTPR = 0x%08x\n", | |
137 | (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); | |
138 | printk("CP_RB_WTPR = 0x%08x\n", | |
139 | (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); | |
140 | printk("AIC_CNTL = 0x%08x\n", | |
141 | (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); | |
142 | printk("AIC_STAT = 0x%08x\n", | |
143 | (unsigned int)RADEON_READ(RADEON_AIC_STAT)); | |
144 | printk("AIC_PT_BASE = 0x%08x\n", | |
145 | (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); | |
146 | printk("TLB_ADDR = 0x%08x\n", | |
147 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); | |
148 | printk("TLB_DATA = 0x%08x\n", | |
149 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); | |
1da177e4 LT |
150 | } |
151 | #endif | |
152 | ||
1da177e4 LT |
153 | /* ================================================================ |
154 | * Engine, FIFO control | |
155 | */ | |
156 | ||
b5e89ed5 | 157 | static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
158 | { |
159 | u32 tmp; | |
160 | int i; | |
161 | ||
162 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
163 | ||
b9b603dd MD |
164 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); |
165 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | |
166 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); | |
1da177e4 | 167 | |
b5e89ed5 | 168 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
b9b603dd MD |
169 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) |
170 | & RADEON_RB3D_DC_BUSY)) { | |
1da177e4 LT |
171 | return 0; |
172 | } | |
b5e89ed5 | 173 | DRM_UDELAY(1); |
1da177e4 LT |
174 | } |
175 | ||
176 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
177 | DRM_ERROR("failed!\n"); |
178 | radeon_status(dev_priv); | |
1da177e4 | 179 | #endif |
20caafa6 | 180 | return -EBUSY; |
1da177e4 LT |
181 | } |
182 | ||
b5e89ed5 | 183 | static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) |
1da177e4 LT |
184 | { |
185 | int i; | |
186 | ||
187 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
188 | ||
b5e89ed5 DA |
189 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
190 | int slots = (RADEON_READ(RADEON_RBBM_STATUS) | |
191 | & RADEON_RBBM_FIFOCNT_MASK); | |
192 | if (slots >= entries) | |
193 | return 0; | |
194 | DRM_UDELAY(1); | |
1da177e4 LT |
195 | } |
196 | ||
197 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
198 | DRM_ERROR("failed!\n"); |
199 | radeon_status(dev_priv); | |
1da177e4 | 200 | #endif |
20caafa6 | 201 | return -EBUSY; |
1da177e4 LT |
202 | } |
203 | ||
b5e89ed5 | 204 | static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
205 | { |
206 | int i, ret; | |
207 | ||
208 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
209 | ||
b5e89ed5 DA |
210 | ret = radeon_do_wait_for_fifo(dev_priv, 64); |
211 | if (ret) | |
212 | return ret; | |
1da177e4 | 213 | |
b5e89ed5 DA |
214 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
215 | if (!(RADEON_READ(RADEON_RBBM_STATUS) | |
216 | & RADEON_RBBM_ACTIVE)) { | |
217 | radeon_do_pixcache_flush(dev_priv); | |
1da177e4 LT |
218 | return 0; |
219 | } | |
b5e89ed5 | 220 | DRM_UDELAY(1); |
1da177e4 LT |
221 | } |
222 | ||
223 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
224 | DRM_ERROR("failed!\n"); |
225 | radeon_status(dev_priv); | |
1da177e4 | 226 | #endif |
20caafa6 | 227 | return -EBUSY; |
1da177e4 LT |
228 | } |
229 | ||
1da177e4 LT |
230 | /* ================================================================ |
231 | * CP control, initialization | |
232 | */ | |
233 | ||
234 | /* Load the microcode for the CP */ | |
b5e89ed5 | 235 | static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
236 | { |
237 | int i; | |
b5e89ed5 | 238 | DRM_DEBUG("\n"); |
1da177e4 | 239 | |
b5e89ed5 | 240 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 241 | |
b5e89ed5 | 242 | RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); |
9f18409e AD |
243 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || |
244 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || | |
245 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || | |
246 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || | |
247 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { | |
248 | DRM_INFO("Loading R100 Microcode\n"); | |
249 | for (i = 0; i < 256; i++) { | |
250 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
251 | R100_cp_microcode[i][1]); | |
252 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
253 | R100_cp_microcode[i][0]); | |
254 | } | |
255 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || | |
256 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || | |
257 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || | |
258 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { | |
1da177e4 | 259 | DRM_INFO("Loading R200 Microcode\n"); |
b5e89ed5 DA |
260 | for (i = 0; i < 256; i++) { |
261 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
262 | R200_cp_microcode[i][1]); | |
263 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
264 | R200_cp_microcode[i][0]); | |
1da177e4 | 265 | } |
9f18409e AD |
266 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || |
267 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || | |
268 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || | |
269 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || | |
45e51905 | 270 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { |
1da177e4 | 271 | DRM_INFO("Loading R300 Microcode\n"); |
b5e89ed5 DA |
272 | for (i = 0; i < 256; i++) { |
273 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
274 | R300_cp_microcode[i][1]); | |
275 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
276 | R300_cp_microcode[i][0]); | |
1da177e4 | 277 | } |
9f18409e AD |
278 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || |
279 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { | |
280 | DRM_INFO("Loading R400 Microcode\n"); | |
281 | for (i = 0; i < 256; i++) { | |
282 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
283 | R420_cp_microcode[i][1]); | |
284 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
285 | R420_cp_microcode[i][0]); | |
286 | } | |
287 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | |
288 | DRM_INFO("Loading RS690 Microcode\n"); | |
289 | for (i = 0; i < 256; i++) { | |
290 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
291 | RS690_cp_microcode[i][1]); | |
292 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
293 | RS690_cp_microcode[i][0]); | |
294 | } | |
295 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || | |
296 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || | |
297 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || | |
298 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || | |
299 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || | |
300 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { | |
301 | DRM_INFO("Loading R500 Microcode\n"); | |
b5e89ed5 DA |
302 | for (i = 0; i < 256; i++) { |
303 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
9f18409e | 304 | R520_cp_microcode[i][1]); |
b5e89ed5 | 305 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
9f18409e | 306 | R520_cp_microcode[i][0]); |
1da177e4 LT |
307 | } |
308 | } | |
309 | } | |
310 | ||
311 | /* Flush any pending commands to the CP. This should only be used just | |
312 | * prior to a wait for idle, as it informs the engine that the command | |
313 | * stream is ending. | |
314 | */ | |
b5e89ed5 | 315 | static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) |
1da177e4 | 316 | { |
b5e89ed5 | 317 | DRM_DEBUG("\n"); |
1da177e4 LT |
318 | #if 0 |
319 | u32 tmp; | |
320 | ||
b5e89ed5 DA |
321 | tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); |
322 | RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); | |
1da177e4 LT |
323 | #endif |
324 | } | |
325 | ||
326 | /* Wait for the CP to go idle. | |
327 | */ | |
b5e89ed5 | 328 | int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
329 | { |
330 | RING_LOCALS; | |
b5e89ed5 | 331 | DRM_DEBUG("\n"); |
1da177e4 | 332 | |
b5e89ed5 | 333 | BEGIN_RING(6); |
1da177e4 LT |
334 | |
335 | RADEON_PURGE_CACHE(); | |
336 | RADEON_PURGE_ZCACHE(); | |
337 | RADEON_WAIT_UNTIL_IDLE(); | |
338 | ||
339 | ADVANCE_RING(); | |
340 | COMMIT_RING(); | |
341 | ||
b5e89ed5 | 342 | return radeon_do_wait_for_idle(dev_priv); |
1da177e4 LT |
343 | } |
344 | ||
345 | /* Start the Command Processor. | |
346 | */ | |
b5e89ed5 | 347 | static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
348 | { |
349 | RING_LOCALS; | |
b5e89ed5 | 350 | DRM_DEBUG("\n"); |
1da177e4 | 351 | |
b5e89ed5 | 352 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 353 | |
b5e89ed5 | 354 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); |
1da177e4 LT |
355 | |
356 | dev_priv->cp_running = 1; | |
357 | ||
b5e89ed5 | 358 | BEGIN_RING(6); |
1da177e4 LT |
359 | |
360 | RADEON_PURGE_CACHE(); | |
361 | RADEON_PURGE_ZCACHE(); | |
362 | RADEON_WAIT_UNTIL_IDLE(); | |
363 | ||
364 | ADVANCE_RING(); | |
365 | COMMIT_RING(); | |
366 | } | |
367 | ||
368 | /* Reset the Command Processor. This will not flush any pending | |
369 | * commands, so you must wait for the CP command stream to complete | |
370 | * before calling this routine. | |
371 | */ | |
b5e89ed5 | 372 | static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
373 | { |
374 | u32 cur_read_ptr; | |
b5e89ed5 | 375 | DRM_DEBUG("\n"); |
1da177e4 | 376 | |
b5e89ed5 DA |
377 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
378 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
379 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
380 | dev_priv->ring.tail = cur_read_ptr; |
381 | } | |
382 | ||
383 | /* Stop the Command Processor. This will not flush any pending | |
384 | * commands, so you must flush the command stream and wait for the CP | |
385 | * to go idle before calling this routine. | |
386 | */ | |
b5e89ed5 | 387 | static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) |
1da177e4 | 388 | { |
b5e89ed5 | 389 | DRM_DEBUG("\n"); |
1da177e4 | 390 | |
b5e89ed5 | 391 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); |
1da177e4 LT |
392 | |
393 | dev_priv->cp_running = 0; | |
394 | } | |
395 | ||
396 | /* Reset the engine. This will stop the CP if it is running. | |
397 | */ | |
84b1fd10 | 398 | static int radeon_do_engine_reset(struct drm_device * dev) |
1da177e4 LT |
399 | { |
400 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
401 | u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; | |
b5e89ed5 | 402 | DRM_DEBUG("\n"); |
1da177e4 | 403 | |
b5e89ed5 DA |
404 | radeon_do_pixcache_flush(dev_priv); |
405 | ||
3d5e2c13 DA |
406 | if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { |
407 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); | |
408 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); | |
409 | ||
410 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | | |
411 | RADEON_FORCEON_MCLKA | | |
412 | RADEON_FORCEON_MCLKB | | |
413 | RADEON_FORCEON_YCLKA | | |
414 | RADEON_FORCEON_YCLKB | | |
415 | RADEON_FORCEON_MC | | |
416 | RADEON_FORCEON_AIC)); | |
417 | ||
418 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
419 | ||
420 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | | |
421 | RADEON_SOFT_RESET_CP | | |
422 | RADEON_SOFT_RESET_HI | | |
423 | RADEON_SOFT_RESET_SE | | |
424 | RADEON_SOFT_RESET_RE | | |
425 | RADEON_SOFT_RESET_PP | | |
426 | RADEON_SOFT_RESET_E2 | | |
427 | RADEON_SOFT_RESET_RB)); | |
428 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
429 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & | |
430 | ~(RADEON_SOFT_RESET_CP | | |
431 | RADEON_SOFT_RESET_HI | | |
432 | RADEON_SOFT_RESET_SE | | |
433 | RADEON_SOFT_RESET_RE | | |
434 | RADEON_SOFT_RESET_PP | | |
435 | RADEON_SOFT_RESET_E2 | | |
436 | RADEON_SOFT_RESET_RB))); | |
437 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
438 | ||
439 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); | |
440 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); | |
441 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); | |
442 | } | |
1da177e4 LT |
443 | |
444 | /* Reset the CP ring */ | |
b5e89ed5 | 445 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
446 | |
447 | /* The CP is no longer running after an engine reset */ | |
448 | dev_priv->cp_running = 0; | |
449 | ||
450 | /* Reset any pending vertex, indirect buffers */ | |
b5e89ed5 | 451 | radeon_freelist_reset(dev); |
1da177e4 LT |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
84b1fd10 | 456 | static void radeon_cp_init_ring_buffer(struct drm_device * dev, |
b5e89ed5 | 457 | drm_radeon_private_t * dev_priv) |
1da177e4 LT |
458 | { |
459 | u32 ring_start, cur_read_ptr; | |
460 | u32 tmp; | |
bc5f4523 | 461 | |
d5ea702f DA |
462 | /* Initialize the memory controller. With new memory map, the fb location |
463 | * is not changed, it should have been properly initialized already. Part | |
464 | * of the problem is that the code below is bogus, assuming the GART is | |
465 | * always appended to the fb which is not necessarily the case | |
466 | */ | |
467 | if (!dev_priv->new_memmap) | |
3d5e2c13 | 468 | radeon_write_fb_location(dev_priv, |
d5ea702f DA |
469 | ((dev_priv->gart_vm_start - 1) & 0xffff0000) |
470 | | (dev_priv->fb_location >> 16)); | |
1da177e4 LT |
471 | |
472 | #if __OS_HAS_AGP | |
54a56ac5 | 473 | if (dev_priv->flags & RADEON_IS_AGP) { |
d5ea702f | 474 | RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); |
3d5e2c13 | 475 | radeon_write_agp_location(dev_priv, |
b5e89ed5 DA |
476 | (((dev_priv->gart_vm_start - 1 + |
477 | dev_priv->gart_size) & 0xffff0000) | | |
478 | (dev_priv->gart_vm_start >> 16))); | |
1da177e4 LT |
479 | |
480 | ring_start = (dev_priv->cp_ring->offset | |
481 | - dev->agp->base | |
482 | + dev_priv->gart_vm_start); | |
b0917bd9 | 483 | } else |
1da177e4 LT |
484 | #endif |
485 | ring_start = (dev_priv->cp_ring->offset | |
b0917bd9 | 486 | - (unsigned long)dev->sg->virtual |
1da177e4 LT |
487 | + dev_priv->gart_vm_start); |
488 | ||
b5e89ed5 | 489 | RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); |
1da177e4 LT |
490 | |
491 | /* Set the write pointer delay */ | |
b5e89ed5 | 492 | RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); |
1da177e4 LT |
493 | |
494 | /* Initialize the ring buffer's read and write pointers */ | |
b5e89ed5 DA |
495 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
496 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
497 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
498 | dev_priv->ring.tail = cur_read_ptr; |
499 | ||
500 | #if __OS_HAS_AGP | |
54a56ac5 | 501 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
502 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, |
503 | dev_priv->ring_rptr->offset | |
504 | - dev->agp->base + dev_priv->gart_vm_start); | |
1da177e4 LT |
505 | } else |
506 | #endif | |
507 | { | |
55910517 | 508 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
509 | unsigned long tmp_ofs, page_ofs; |
510 | ||
b0917bd9 IK |
511 | tmp_ofs = dev_priv->ring_rptr->offset - |
512 | (unsigned long)dev->sg->virtual; | |
1da177e4 LT |
513 | page_ofs = tmp_ofs >> PAGE_SHIFT; |
514 | ||
b5e89ed5 DA |
515 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); |
516 | DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", | |
517 | (unsigned long)entry->busaddr[page_ofs], | |
518 | entry->handle + tmp_ofs); | |
1da177e4 LT |
519 | } |
520 | ||
d5ea702f DA |
521 | /* Set ring buffer size */ |
522 | #ifdef __BIG_ENDIAN | |
523 | RADEON_WRITE(RADEON_CP_RB_CNTL, | |
576cc458 RS |
524 | RADEON_BUF_SWAP_32BIT | |
525 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
526 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
527 | dev_priv->ring.size_l2qw); | |
d5ea702f | 528 | #else |
576cc458 RS |
529 | RADEON_WRITE(RADEON_CP_RB_CNTL, |
530 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
531 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
532 | dev_priv->ring.size_l2qw); | |
d5ea702f DA |
533 | #endif |
534 | ||
535 | /* Start with assuming that writeback doesn't work */ | |
536 | dev_priv->writeback_works = 0; | |
537 | ||
1da177e4 LT |
538 | /* Initialize the scratch register pointer. This will cause |
539 | * the scratch register values to be written out to memory | |
540 | * whenever they are updated. | |
541 | * | |
542 | * We simply put this behind the ring read pointer, this works | |
543 | * with PCI GART as well as (whatever kind of) AGP GART | |
544 | */ | |
b5e89ed5 DA |
545 | RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) |
546 | + RADEON_SCRATCH_REG_OFFSET); | |
1da177e4 LT |
547 | |
548 | dev_priv->scratch = ((__volatile__ u32 *) | |
549 | dev_priv->ring_rptr->handle + | |
550 | (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); | |
551 | ||
b5e89ed5 | 552 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); |
1da177e4 | 553 | |
d5ea702f DA |
554 | /* Turn on bus mastering */ |
555 | tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
556 | RADEON_WRITE(RADEON_BUS_CNTL, tmp); | |
1da177e4 LT |
557 | |
558 | dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; | |
b5e89ed5 | 559 | RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); |
1da177e4 LT |
560 | |
561 | dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; | |
b5e89ed5 DA |
562 | RADEON_WRITE(RADEON_LAST_DISPATCH_REG, |
563 | dev_priv->sarea_priv->last_dispatch); | |
1da177e4 LT |
564 | |
565 | dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; | |
b5e89ed5 | 566 | RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); |
1da177e4 | 567 | |
b5e89ed5 | 568 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 569 | |
1da177e4 | 570 | /* Sync everything up */ |
b5e89ed5 DA |
571 | RADEON_WRITE(RADEON_ISYNC_CNTL, |
572 | (RADEON_ISYNC_ANY2D_IDLE3D | | |
573 | RADEON_ISYNC_ANY3D_IDLE2D | | |
574 | RADEON_ISYNC_WAIT_IDLEGUI | | |
575 | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); | |
d5ea702f DA |
576 | |
577 | } | |
578 | ||
579 | static void radeon_test_writeback(drm_radeon_private_t * dev_priv) | |
580 | { | |
581 | u32 tmp; | |
582 | ||
583 | /* Writeback doesn't seem to work everywhere, test it here and possibly | |
584 | * enable it if it appears to work | |
585 | */ | |
586 | DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); | |
587 | RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); | |
588 | ||
589 | for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { | |
590 | if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == | |
591 | 0xdeadbeef) | |
592 | break; | |
593 | DRM_UDELAY(1); | |
594 | } | |
595 | ||
596 | if (tmp < dev_priv->usec_timeout) { | |
597 | dev_priv->writeback_works = 1; | |
598 | DRM_INFO("writeback test succeeded in %d usecs\n", tmp); | |
599 | } else { | |
600 | dev_priv->writeback_works = 0; | |
601 | DRM_INFO("writeback test failed\n"); | |
602 | } | |
603 | if (radeon_no_wb == 1) { | |
604 | dev_priv->writeback_works = 0; | |
605 | DRM_INFO("writeback forced off\n"); | |
606 | } | |
ae1b1a48 MD |
607 | |
608 | if (!dev_priv->writeback_works) { | |
609 | /* Disable writeback to avoid unnecessary bus master transfer */ | |
610 | RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | | |
611 | RADEON_RB_NO_UPDATE); | |
612 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); | |
613 | } | |
1da177e4 LT |
614 | } |
615 | ||
f2b04cd2 DA |
616 | /* Enable or disable IGP GART on the chip */ |
617 | static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) | |
60f92683 MC |
618 | { |
619 | u32 temp; | |
620 | ||
621 | if (on) { | |
45e51905 | 622 | DRM_DEBUG("programming igp gart %08X %08lX %08X\n", |
60f92683 MC |
623 | dev_priv->gart_vm_start, |
624 | (long)dev_priv->gart_info.bus_addr, | |
625 | dev_priv->gart_size); | |
626 | ||
45e51905 AD |
627 | temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); |
628 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | |
629 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | | |
630 | RS690_BLOCK_GFX_D3_EN)); | |
631 | else | |
632 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); | |
60f92683 | 633 | |
45e51905 AD |
634 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | |
635 | RS480_VA_SIZE_32MB)); | |
60f92683 | 636 | |
45e51905 AD |
637 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); |
638 | IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | | |
639 | RS480_TLB_ENABLE | | |
640 | RS480_GTW_LAC_EN | | |
641 | RS480_1LEVEL_GART)); | |
60f92683 | 642 | |
fa0d71b9 DA |
643 | temp = dev_priv->gart_info.bus_addr & 0xfffff000; |
644 | temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; | |
45e51905 AD |
645 | IGP_WRITE_MCIND(RS480_GART_BASE, temp); |
646 | ||
647 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); | |
648 | IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | | |
649 | RS480_REQ_TYPE_SNOOP_DIS)); | |
650 | ||
651 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | |
652 | IGP_WRITE_MCIND(RS690_MC_AGP_BASE, | |
653 | (unsigned int)dev_priv->gart_vm_start); | |
654 | IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0); | |
655 | } else { | |
656 | RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); | |
657 | RADEON_WRITE(RS480_AGP_BASE_2, 0); | |
658 | } | |
3722bfc6 | 659 | |
60f92683 MC |
660 | dev_priv->gart_size = 32*1024*1024; |
661 | temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & | |
662 | 0xffff0000) | (dev_priv->gart_vm_start >> 16)); | |
663 | ||
45e51905 | 664 | radeon_write_agp_location(dev_priv, temp); |
60f92683 | 665 | |
45e51905 AD |
666 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); |
667 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | | |
668 | RS480_VA_SIZE_32MB)); | |
60f92683 MC |
669 | |
670 | do { | |
45e51905 AD |
671 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
672 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) | |
60f92683 MC |
673 | break; |
674 | DRM_UDELAY(1); | |
675 | } while (1); | |
676 | ||
45e51905 AD |
677 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, |
678 | RS480_GART_CACHE_INVALIDATE); | |
2735977b | 679 | |
60f92683 | 680 | do { |
45e51905 AD |
681 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
682 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) | |
60f92683 MC |
683 | break; |
684 | DRM_UDELAY(1); | |
685 | } while (1); | |
686 | ||
45e51905 | 687 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); |
60f92683 | 688 | } else { |
45e51905 | 689 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
60f92683 MC |
690 | } |
691 | } | |
692 | ||
ea98a92f DA |
693 | static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) |
694 | { | |
695 | u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); | |
696 | if (on) { | |
697 | ||
698 | DRM_DEBUG("programming pcie %08X %08lX %08X\n", | |
b5e89ed5 DA |
699 | dev_priv->gart_vm_start, |
700 | (long)dev_priv->gart_info.bus_addr, | |
ea98a92f | 701 | dev_priv->gart_size); |
b5e89ed5 DA |
702 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
703 | dev_priv->gart_vm_start); | |
704 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, | |
705 | dev_priv->gart_info.bus_addr); | |
706 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, | |
707 | dev_priv->gart_vm_start); | |
708 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, | |
709 | dev_priv->gart_vm_start + | |
710 | dev_priv->gart_size - 1); | |
711 | ||
3d5e2c13 | 712 | radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
b5e89ed5 DA |
713 | |
714 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, | |
715 | RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 716 | } else { |
b5e89ed5 DA |
717 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
718 | tmp & ~RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 719 | } |
1da177e4 LT |
720 | } |
721 | ||
722 | /* Enable or disable PCI GART on the chip */ | |
b5e89ed5 | 723 | static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) |
1da177e4 | 724 | { |
d985c108 | 725 | u32 tmp; |
1da177e4 | 726 | |
45e51905 AD |
727 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
728 | (dev_priv->flags & RADEON_IS_IGPGART)) { | |
f2b04cd2 DA |
729 | radeon_set_igpgart(dev_priv, on); |
730 | return; | |
731 | } | |
732 | ||
54a56ac5 | 733 | if (dev_priv->flags & RADEON_IS_PCIE) { |
ea98a92f DA |
734 | radeon_set_pciegart(dev_priv, on); |
735 | return; | |
736 | } | |
1da177e4 | 737 | |
bc5f4523 | 738 | tmp = RADEON_READ(RADEON_AIC_CNTL); |
d985c108 | 739 | |
b5e89ed5 DA |
740 | if (on) { |
741 | RADEON_WRITE(RADEON_AIC_CNTL, | |
742 | tmp | RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
743 | |
744 | /* set PCI GART page-table base address | |
745 | */ | |
ea98a92f | 746 | RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); |
1da177e4 LT |
747 | |
748 | /* set address range for PCI address translate | |
749 | */ | |
b5e89ed5 DA |
750 | RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); |
751 | RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start | |
752 | + dev_priv->gart_size - 1); | |
1da177e4 LT |
753 | |
754 | /* Turn off AGP aperture -- is this required for PCI GART? | |
755 | */ | |
3d5e2c13 | 756 | radeon_write_agp_location(dev_priv, 0xffffffc0); |
b5e89ed5 | 757 | RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
1da177e4 | 758 | } else { |
b5e89ed5 DA |
759 | RADEON_WRITE(RADEON_AIC_CNTL, |
760 | tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
761 | } |
762 | } | |
763 | ||
84b1fd10 | 764 | static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) |
1da177e4 | 765 | { |
d985c108 DA |
766 | drm_radeon_private_t *dev_priv = dev->dev_private; |
767 | ||
b5e89ed5 | 768 | DRM_DEBUG("\n"); |
1da177e4 | 769 | |
f3dd5c37 | 770 | /* if we require new memory map but we don't have it fail */ |
54a56ac5 | 771 | if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { |
b15ec368 | 772 | DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); |
f3dd5c37 | 773 | radeon_do_cleanup_cp(dev); |
20caafa6 | 774 | return -EINVAL; |
f3dd5c37 DA |
775 | } |
776 | ||
54a56ac5 | 777 | if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { |
d985c108 | 778 | DRM_DEBUG("Forcing AGP card to PCI mode\n"); |
54a56ac5 DA |
779 | dev_priv->flags &= ~RADEON_IS_AGP; |
780 | } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) | |
b15ec368 DA |
781 | && !init->is_pci) { |
782 | DRM_DEBUG("Restoring AGP flag\n"); | |
54a56ac5 | 783 | dev_priv->flags |= RADEON_IS_AGP; |
d985c108 | 784 | } |
1da177e4 | 785 | |
54a56ac5 | 786 | if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { |
b5e89ed5 | 787 | DRM_ERROR("PCI GART memory not allocated!\n"); |
1da177e4 | 788 | radeon_do_cleanup_cp(dev); |
20caafa6 | 789 | return -EINVAL; |
1da177e4 LT |
790 | } |
791 | ||
792 | dev_priv->usec_timeout = init->usec_timeout; | |
b5e89ed5 DA |
793 | if (dev_priv->usec_timeout < 1 || |
794 | dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { | |
795 | DRM_DEBUG("TIMEOUT problem!\n"); | |
1da177e4 | 796 | radeon_do_cleanup_cp(dev); |
20caafa6 | 797 | return -EINVAL; |
1da177e4 LT |
798 | } |
799 | ||
ddbee333 DA |
800 | /* Enable vblank on CRTC1 for older X servers |
801 | */ | |
802 | dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; | |
803 | ||
d985c108 | 804 | switch(init->func) { |
1da177e4 | 805 | case RADEON_INIT_R200_CP: |
b5e89ed5 | 806 | dev_priv->microcode_version = UCODE_R200; |
1da177e4 LT |
807 | break; |
808 | case RADEON_INIT_R300_CP: | |
b5e89ed5 | 809 | dev_priv->microcode_version = UCODE_R300; |
1da177e4 LT |
810 | break; |
811 | default: | |
b5e89ed5 | 812 | dev_priv->microcode_version = UCODE_R100; |
1da177e4 | 813 | } |
b5e89ed5 | 814 | |
1da177e4 LT |
815 | dev_priv->do_boxes = 0; |
816 | dev_priv->cp_mode = init->cp_mode; | |
817 | ||
818 | /* We don't support anything other than bus-mastering ring mode, | |
819 | * but the ring can be in either AGP or PCI space for the ring | |
820 | * read pointer. | |
821 | */ | |
b5e89ed5 DA |
822 | if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && |
823 | (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { | |
824 | DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); | |
1da177e4 | 825 | radeon_do_cleanup_cp(dev); |
20caafa6 | 826 | return -EINVAL; |
1da177e4 LT |
827 | } |
828 | ||
b5e89ed5 | 829 | switch (init->fb_bpp) { |
1da177e4 LT |
830 | case 16: |
831 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; | |
832 | break; | |
833 | case 32: | |
834 | default: | |
835 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; | |
836 | break; | |
837 | } | |
b5e89ed5 DA |
838 | dev_priv->front_offset = init->front_offset; |
839 | dev_priv->front_pitch = init->front_pitch; | |
840 | dev_priv->back_offset = init->back_offset; | |
841 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 842 | |
b5e89ed5 | 843 | switch (init->depth_bpp) { |
1da177e4 LT |
844 | case 16: |
845 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; | |
846 | break; | |
847 | case 32: | |
848 | default: | |
849 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; | |
850 | break; | |
851 | } | |
b5e89ed5 DA |
852 | dev_priv->depth_offset = init->depth_offset; |
853 | dev_priv->depth_pitch = init->depth_pitch; | |
1da177e4 LT |
854 | |
855 | /* Hardware state for depth clears. Remove this if/when we no | |
856 | * longer clear the depth buffer with a 3D rectangle. Hard-code | |
857 | * all values to prevent unwanted 3D state from slipping through | |
858 | * and screwing with the clear operation. | |
859 | */ | |
860 | dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | | |
861 | (dev_priv->color_fmt << 10) | | |
b5e89ed5 DA |
862 | (dev_priv->microcode_version == |
863 | UCODE_R100 ? RADEON_ZBLOCK16 : 0)); | |
1da177e4 | 864 | |
b5e89ed5 DA |
865 | dev_priv->depth_clear.rb3d_zstencilcntl = |
866 | (dev_priv->depth_fmt | | |
867 | RADEON_Z_TEST_ALWAYS | | |
868 | RADEON_STENCIL_TEST_ALWAYS | | |
869 | RADEON_STENCIL_S_FAIL_REPLACE | | |
870 | RADEON_STENCIL_ZPASS_REPLACE | | |
871 | RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); | |
1da177e4 LT |
872 | |
873 | dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | | |
874 | RADEON_BFACE_SOLID | | |
875 | RADEON_FFACE_SOLID | | |
876 | RADEON_FLAT_SHADE_VTX_LAST | | |
877 | RADEON_DIFFUSE_SHADE_FLAT | | |
878 | RADEON_ALPHA_SHADE_FLAT | | |
879 | RADEON_SPECULAR_SHADE_FLAT | | |
880 | RADEON_FOG_SHADE_FLAT | | |
881 | RADEON_VTX_PIX_CENTER_OGL | | |
882 | RADEON_ROUND_MODE_TRUNC | | |
883 | RADEON_ROUND_PREC_8TH_PIX); | |
884 | ||
1da177e4 | 885 | |
1da177e4 LT |
886 | dev_priv->ring_offset = init->ring_offset; |
887 | dev_priv->ring_rptr_offset = init->ring_rptr_offset; | |
888 | dev_priv->buffers_offset = init->buffers_offset; | |
889 | dev_priv->gart_textures_offset = init->gart_textures_offset; | |
b5e89ed5 | 890 | |
da509d7a | 891 | dev_priv->sarea = drm_getsarea(dev); |
b5e89ed5 | 892 | if (!dev_priv->sarea) { |
1da177e4 | 893 | DRM_ERROR("could not find sarea!\n"); |
1da177e4 | 894 | radeon_do_cleanup_cp(dev); |
20caafa6 | 895 | return -EINVAL; |
1da177e4 LT |
896 | } |
897 | ||
1da177e4 | 898 | dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); |
b5e89ed5 | 899 | if (!dev_priv->cp_ring) { |
1da177e4 | 900 | DRM_ERROR("could not find cp ring region!\n"); |
1da177e4 | 901 | radeon_do_cleanup_cp(dev); |
20caafa6 | 902 | return -EINVAL; |
1da177e4 LT |
903 | } |
904 | dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); | |
b5e89ed5 | 905 | if (!dev_priv->ring_rptr) { |
1da177e4 | 906 | DRM_ERROR("could not find ring read pointer!\n"); |
1da177e4 | 907 | radeon_do_cleanup_cp(dev); |
20caafa6 | 908 | return -EINVAL; |
1da177e4 | 909 | } |
d1f2b55a | 910 | dev->agp_buffer_token = init->buffers_offset; |
1da177e4 | 911 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); |
b5e89ed5 | 912 | if (!dev->agp_buffer_map) { |
1da177e4 | 913 | DRM_ERROR("could not find dma buffer region!\n"); |
1da177e4 | 914 | radeon_do_cleanup_cp(dev); |
20caafa6 | 915 | return -EINVAL; |
1da177e4 LT |
916 | } |
917 | ||
b5e89ed5 DA |
918 | if (init->gart_textures_offset) { |
919 | dev_priv->gart_textures = | |
920 | drm_core_findmap(dev, init->gart_textures_offset); | |
921 | if (!dev_priv->gart_textures) { | |
1da177e4 | 922 | DRM_ERROR("could not find GART texture region!\n"); |
1da177e4 | 923 | radeon_do_cleanup_cp(dev); |
20caafa6 | 924 | return -EINVAL; |
1da177e4 LT |
925 | } |
926 | } | |
927 | ||
928 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
929 | (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
930 | init->sarea_priv_offset); | |
1da177e4 LT |
931 | |
932 | #if __OS_HAS_AGP | |
54a56ac5 | 933 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
934 | drm_core_ioremap(dev_priv->cp_ring, dev); |
935 | drm_core_ioremap(dev_priv->ring_rptr, dev); | |
936 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
937 | if (!dev_priv->cp_ring->handle || | |
938 | !dev_priv->ring_rptr->handle || | |
939 | !dev->agp_buffer_map->handle) { | |
1da177e4 | 940 | DRM_ERROR("could not find ioremap agp regions!\n"); |
1da177e4 | 941 | radeon_do_cleanup_cp(dev); |
20caafa6 | 942 | return -EINVAL; |
1da177e4 LT |
943 | } |
944 | } else | |
945 | #endif | |
946 | { | |
b5e89ed5 | 947 | dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; |
1da177e4 | 948 | dev_priv->ring_rptr->handle = |
b5e89ed5 DA |
949 | (void *)dev_priv->ring_rptr->offset; |
950 | dev->agp_buffer_map->handle = | |
951 | (void *)dev->agp_buffer_map->offset; | |
952 | ||
953 | DRM_DEBUG("dev_priv->cp_ring->handle %p\n", | |
954 | dev_priv->cp_ring->handle); | |
955 | DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", | |
956 | dev_priv->ring_rptr->handle); | |
957 | DRM_DEBUG("dev->agp_buffer_map->handle %p\n", | |
958 | dev->agp_buffer_map->handle); | |
1da177e4 LT |
959 | } |
960 | ||
3d5e2c13 | 961 | dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; |
bc5f4523 | 962 | dev_priv->fb_size = |
3d5e2c13 | 963 | ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) |
d5ea702f | 964 | - dev_priv->fb_location; |
1da177e4 | 965 | |
b5e89ed5 DA |
966 | dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | |
967 | ((dev_priv->front_offset | |
968 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 969 | |
b5e89ed5 DA |
970 | dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | |
971 | ((dev_priv->back_offset | |
972 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 973 | |
b5e89ed5 DA |
974 | dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | |
975 | ((dev_priv->depth_offset | |
976 | + dev_priv->fb_location) >> 10)); | |
1da177e4 LT |
977 | |
978 | dev_priv->gart_size = init->gart_size; | |
d5ea702f DA |
979 | |
980 | /* New let's set the memory map ... */ | |
981 | if (dev_priv->new_memmap) { | |
982 | u32 base = 0; | |
983 | ||
984 | DRM_INFO("Setting GART location based on new memory map\n"); | |
985 | ||
986 | /* If using AGP, try to locate the AGP aperture at the same | |
987 | * location in the card and on the bus, though we have to | |
988 | * align it down. | |
989 | */ | |
990 | #if __OS_HAS_AGP | |
54a56ac5 | 991 | if (dev_priv->flags & RADEON_IS_AGP) { |
d5ea702f DA |
992 | base = dev->agp->base; |
993 | /* Check if valid */ | |
80b2c386 MD |
994 | if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && |
995 | base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { | |
d5ea702f DA |
996 | DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", |
997 | dev->agp->base); | |
998 | base = 0; | |
999 | } | |
1000 | } | |
1001 | #endif | |
1002 | /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ | |
1003 | if (base == 0) { | |
1004 | base = dev_priv->fb_location + dev_priv->fb_size; | |
80b2c386 MD |
1005 | if (base < dev_priv->fb_location || |
1006 | ((base + dev_priv->gart_size) & 0xfffffffful) < base) | |
d5ea702f DA |
1007 | base = dev_priv->fb_location |
1008 | - dev_priv->gart_size; | |
bc5f4523 | 1009 | } |
d5ea702f DA |
1010 | dev_priv->gart_vm_start = base & 0xffc00000u; |
1011 | if (dev_priv->gart_vm_start != base) | |
1012 | DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", | |
1013 | base, dev_priv->gart_vm_start); | |
1014 | } else { | |
1015 | DRM_INFO("Setting GART location based on old memory map\n"); | |
1016 | dev_priv->gart_vm_start = dev_priv->fb_location + | |
1017 | RADEON_READ(RADEON_CONFIG_APER_SIZE); | |
1018 | } | |
1da177e4 LT |
1019 | |
1020 | #if __OS_HAS_AGP | |
54a56ac5 | 1021 | if (dev_priv->flags & RADEON_IS_AGP) |
1da177e4 | 1022 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset |
b5e89ed5 DA |
1023 | - dev->agp->base |
1024 | + dev_priv->gart_vm_start); | |
1da177e4 LT |
1025 | else |
1026 | #endif | |
1027 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
b0917bd9 IK |
1028 | - (unsigned long)dev->sg->virtual |
1029 | + dev_priv->gart_vm_start); | |
1da177e4 | 1030 | |
b5e89ed5 DA |
1031 | DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); |
1032 | DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); | |
1033 | DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", | |
1034 | dev_priv->gart_buffers_offset); | |
1da177e4 | 1035 | |
b5e89ed5 DA |
1036 | dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; |
1037 | dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle | |
1da177e4 LT |
1038 | + init->ring_size / sizeof(u32)); |
1039 | dev_priv->ring.size = init->ring_size; | |
b5e89ed5 | 1040 | dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); |
1da177e4 | 1041 | |
576cc458 RS |
1042 | dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; |
1043 | dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); | |
1044 | ||
1045 | dev_priv->ring.fetch_size = /* init->fetch_size */ 32; | |
1046 | dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); | |
b5e89ed5 | 1047 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; |
1da177e4 LT |
1048 | |
1049 | dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; | |
1050 | ||
1051 | #if __OS_HAS_AGP | |
54a56ac5 | 1052 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1053 | /* Turn off PCI GART */ |
b5e89ed5 | 1054 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1055 | } else |
1056 | #endif | |
1057 | { | |
b05c2385 | 1058 | dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); |
ea98a92f | 1059 | /* if we have an offset set from userspace */ |
f2b04cd2 | 1060 | if (dev_priv->pcigart_offset_set) { |
b5e89ed5 DA |
1061 | dev_priv->gart_info.bus_addr = |
1062 | dev_priv->pcigart_offset + dev_priv->fb_location; | |
f26c473c | 1063 | dev_priv->gart_info.mapping.offset = |
7fc86860 | 1064 | dev_priv->pcigart_offset + dev_priv->fb_aper_offset; |
f26c473c | 1065 | dev_priv->gart_info.mapping.size = |
f2b04cd2 | 1066 | dev_priv->gart_info.table_size; |
f26c473c DA |
1067 | |
1068 | drm_core_ioremap(&dev_priv->gart_info.mapping, dev); | |
b5e89ed5 | 1069 | dev_priv->gart_info.addr = |
f26c473c | 1070 | dev_priv->gart_info.mapping.handle; |
b5e89ed5 | 1071 | |
f2b04cd2 DA |
1072 | if (dev_priv->flags & RADEON_IS_PCIE) |
1073 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; | |
1074 | else | |
1075 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1076 | dev_priv->gart_info.gart_table_location = |
1077 | DRM_ATI_GART_FB; | |
1078 | ||
f26c473c | 1079 | DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", |
b5e89ed5 DA |
1080 | dev_priv->gart_info.addr, |
1081 | dev_priv->pcigart_offset); | |
1082 | } else { | |
f2b04cd2 DA |
1083 | if (dev_priv->flags & RADEON_IS_IGPGART) |
1084 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; | |
1085 | else | |
1086 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1087 | dev_priv->gart_info.gart_table_location = |
1088 | DRM_ATI_GART_MAIN; | |
f26c473c DA |
1089 | dev_priv->gart_info.addr = NULL; |
1090 | dev_priv->gart_info.bus_addr = 0; | |
54a56ac5 | 1091 | if (dev_priv->flags & RADEON_IS_PCIE) { |
b5e89ed5 DA |
1092 | DRM_ERROR |
1093 | ("Cannot use PCI Express without GART in FB memory\n"); | |
ea98a92f | 1094 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1095 | return -EINVAL; |
ea98a92f DA |
1096 | } |
1097 | } | |
1098 | ||
1099 | if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { | |
b5e89ed5 | 1100 | DRM_ERROR("failed to init PCI GART!\n"); |
1da177e4 | 1101 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1102 | return -ENOMEM; |
1da177e4 LT |
1103 | } |
1104 | ||
1105 | /* Turn on PCI GART */ | |
b5e89ed5 | 1106 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1107 | } |
1108 | ||
b5e89ed5 DA |
1109 | radeon_cp_load_microcode(dev_priv); |
1110 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 LT |
1111 | |
1112 | dev_priv->last_buf = 0; | |
1113 | ||
b5e89ed5 | 1114 | radeon_do_engine_reset(dev); |
d5ea702f | 1115 | radeon_test_writeback(dev_priv); |
1da177e4 LT |
1116 | |
1117 | return 0; | |
1118 | } | |
1119 | ||
84b1fd10 | 1120 | static int radeon_do_cleanup_cp(struct drm_device * dev) |
1da177e4 LT |
1121 | { |
1122 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1123 | DRM_DEBUG("\n"); |
1da177e4 LT |
1124 | |
1125 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
1126 | * may not have been called from userspace and after dev_private | |
1127 | * is freed, it's too late. | |
1128 | */ | |
b5e89ed5 DA |
1129 | if (dev->irq_enabled) |
1130 | drm_irq_uninstall(dev); | |
1da177e4 LT |
1131 | |
1132 | #if __OS_HAS_AGP | |
54a56ac5 | 1133 | if (dev_priv->flags & RADEON_IS_AGP) { |
d985c108 | 1134 | if (dev_priv->cp_ring != NULL) { |
b5e89ed5 | 1135 | drm_core_ioremapfree(dev_priv->cp_ring, dev); |
d985c108 DA |
1136 | dev_priv->cp_ring = NULL; |
1137 | } | |
1138 | if (dev_priv->ring_rptr != NULL) { | |
b5e89ed5 | 1139 | drm_core_ioremapfree(dev_priv->ring_rptr, dev); |
d985c108 DA |
1140 | dev_priv->ring_rptr = NULL; |
1141 | } | |
b5e89ed5 DA |
1142 | if (dev->agp_buffer_map != NULL) { |
1143 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
1da177e4 LT |
1144 | dev->agp_buffer_map = NULL; |
1145 | } | |
1146 | } else | |
1147 | #endif | |
1148 | { | |
d985c108 DA |
1149 | |
1150 | if (dev_priv->gart_info.bus_addr) { | |
1151 | /* Turn off PCI GART */ | |
1152 | radeon_set_pcigart(dev_priv, 0); | |
ea98a92f DA |
1153 | if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) |
1154 | DRM_ERROR("failed to cleanup PCI GART!\n"); | |
d985c108 | 1155 | } |
b5e89ed5 | 1156 | |
d985c108 DA |
1157 | if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) |
1158 | { | |
f26c473c | 1159 | drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); |
f2b04cd2 | 1160 | dev_priv->gart_info.addr = 0; |
ea98a92f | 1161 | } |
1da177e4 | 1162 | } |
1da177e4 LT |
1163 | /* only clear to the start of flags */ |
1164 | memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); | |
1165 | ||
1166 | return 0; | |
1167 | } | |
1168 | ||
b5e89ed5 DA |
1169 | /* This code will reinit the Radeon CP hardware after a resume from disc. |
1170 | * AFAIK, it would be very difficult to pickle the state at suspend time, so | |
1da177e4 LT |
1171 | * here we make sure that all Radeon hardware initialisation is re-done without |
1172 | * affecting running applications. | |
1173 | * | |
1174 | * Charl P. Botha <http://cpbotha.net> | |
1175 | */ | |
84b1fd10 | 1176 | static int radeon_do_resume_cp(struct drm_device * dev) |
1da177e4 LT |
1177 | { |
1178 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1179 | ||
b5e89ed5 DA |
1180 | if (!dev_priv) { |
1181 | DRM_ERROR("Called with no initialization\n"); | |
20caafa6 | 1182 | return -EINVAL; |
1da177e4 LT |
1183 | } |
1184 | ||
1185 | DRM_DEBUG("Starting radeon_do_resume_cp()\n"); | |
1186 | ||
1187 | #if __OS_HAS_AGP | |
54a56ac5 | 1188 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1189 | /* Turn off PCI GART */ |
b5e89ed5 | 1190 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1191 | } else |
1192 | #endif | |
1193 | { | |
1194 | /* Turn on PCI GART */ | |
b5e89ed5 | 1195 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1196 | } |
1197 | ||
b5e89ed5 DA |
1198 | radeon_cp_load_microcode(dev_priv); |
1199 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 | 1200 | |
b5e89ed5 | 1201 | radeon_do_engine_reset(dev); |
1da177e4 LT |
1202 | |
1203 | DRM_DEBUG("radeon_do_resume_cp() complete\n"); | |
1204 | ||
1205 | return 0; | |
1206 | } | |
1207 | ||
c153f45f | 1208 | int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1209 | { |
c153f45f | 1210 | drm_radeon_init_t *init = data; |
1da177e4 | 1211 | |
6c340eac | 1212 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1213 | |
c153f45f | 1214 | if (init->func == RADEON_INIT_R300_CP) |
3d5e2c13 | 1215 | r300_init_reg_flags(dev); |
414ed537 | 1216 | |
c153f45f | 1217 | switch (init->func) { |
1da177e4 LT |
1218 | case RADEON_INIT_CP: |
1219 | case RADEON_INIT_R200_CP: | |
1220 | case RADEON_INIT_R300_CP: | |
c153f45f | 1221 | return radeon_do_init_cp(dev, init); |
1da177e4 | 1222 | case RADEON_CLEANUP_CP: |
b5e89ed5 | 1223 | return radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1224 | } |
1225 | ||
20caafa6 | 1226 | return -EINVAL; |
1da177e4 LT |
1227 | } |
1228 | ||
c153f45f | 1229 | int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1230 | { |
1da177e4 | 1231 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1232 | DRM_DEBUG("\n"); |
1da177e4 | 1233 | |
6c340eac | 1234 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1235 | |
b5e89ed5 | 1236 | if (dev_priv->cp_running) { |
3e684eae | 1237 | DRM_DEBUG("while CP running\n"); |
1da177e4 LT |
1238 | return 0; |
1239 | } | |
b5e89ed5 | 1240 | if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { |
3e684eae MN |
1241 | DRM_DEBUG("called with bogus CP mode (%d)\n", |
1242 | dev_priv->cp_mode); | |
1da177e4 LT |
1243 | return 0; |
1244 | } | |
1245 | ||
b5e89ed5 | 1246 | radeon_do_cp_start(dev_priv); |
1da177e4 LT |
1247 | |
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | /* Stop the CP. The engine must have been idled before calling this | |
1252 | * routine. | |
1253 | */ | |
c153f45f | 1254 | int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1255 | { |
1da177e4 | 1256 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 1257 | drm_radeon_cp_stop_t *stop = data; |
1da177e4 | 1258 | int ret; |
b5e89ed5 | 1259 | DRM_DEBUG("\n"); |
1da177e4 | 1260 | |
6c340eac | 1261 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1262 | |
1da177e4 LT |
1263 | if (!dev_priv->cp_running) |
1264 | return 0; | |
1265 | ||
1266 | /* Flush any pending CP commands. This ensures any outstanding | |
1267 | * commands are exectuted by the engine before we turn it off. | |
1268 | */ | |
c153f45f | 1269 | if (stop->flush) { |
b5e89ed5 | 1270 | radeon_do_cp_flush(dev_priv); |
1da177e4 LT |
1271 | } |
1272 | ||
1273 | /* If we fail to make the engine go idle, we return an error | |
1274 | * code so that the DRM ioctl wrapper can try again. | |
1275 | */ | |
c153f45f | 1276 | if (stop->idle) { |
b5e89ed5 DA |
1277 | ret = radeon_do_cp_idle(dev_priv); |
1278 | if (ret) | |
1279 | return ret; | |
1da177e4 LT |
1280 | } |
1281 | ||
1282 | /* Finally, we can turn off the CP. If the engine isn't idle, | |
1283 | * we will get some dropped triangles as they won't be fully | |
1284 | * rendered before the CP is shut down. | |
1285 | */ | |
b5e89ed5 | 1286 | radeon_do_cp_stop(dev_priv); |
1da177e4 LT |
1287 | |
1288 | /* Reset the engine */ | |
b5e89ed5 | 1289 | radeon_do_engine_reset(dev); |
1da177e4 LT |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
84b1fd10 | 1294 | void radeon_do_release(struct drm_device * dev) |
1da177e4 LT |
1295 | { |
1296 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1297 | int i, ret; | |
1298 | ||
1299 | if (dev_priv) { | |
1300 | if (dev_priv->cp_running) { | |
1301 | /* Stop the cp */ | |
b5e89ed5 | 1302 | while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { |
1da177e4 LT |
1303 | DRM_DEBUG("radeon_do_cp_idle %d\n", ret); |
1304 | #ifdef __linux__ | |
1305 | schedule(); | |
1306 | #else | |
1307 | tsleep(&ret, PZERO, "rdnrel", 1); | |
1308 | #endif | |
1309 | } | |
b5e89ed5 DA |
1310 | radeon_do_cp_stop(dev_priv); |
1311 | radeon_do_engine_reset(dev); | |
1da177e4 LT |
1312 | } |
1313 | ||
1314 | /* Disable *all* interrupts */ | |
1315 | if (dev_priv->mmio) /* remove this after permanent addmaps */ | |
b5e89ed5 | 1316 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
1da177e4 | 1317 | |
b5e89ed5 | 1318 | if (dev_priv->mmio) { /* remove all surfaces */ |
1da177e4 | 1319 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
b5e89ed5 DA |
1320 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); |
1321 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + | |
1322 | 16 * i, 0); | |
1323 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + | |
1324 | 16 * i, 0); | |
1da177e4 LT |
1325 | } |
1326 | } | |
1327 | ||
1328 | /* Free memory heap structures */ | |
b5e89ed5 DA |
1329 | radeon_mem_takedown(&(dev_priv->gart_heap)); |
1330 | radeon_mem_takedown(&(dev_priv->fb_heap)); | |
1da177e4 LT |
1331 | |
1332 | /* deallocate kernel resources */ | |
b5e89ed5 | 1333 | radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1334 | } |
1335 | } | |
1336 | ||
1337 | /* Just reset the CP ring. Called as part of an X Server engine reset. | |
1338 | */ | |
c153f45f | 1339 | int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1340 | { |
1da177e4 | 1341 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1342 | DRM_DEBUG("\n"); |
1da177e4 | 1343 | |
6c340eac | 1344 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1345 | |
b5e89ed5 | 1346 | if (!dev_priv) { |
3e684eae | 1347 | DRM_DEBUG("called before init done\n"); |
20caafa6 | 1348 | return -EINVAL; |
1da177e4 LT |
1349 | } |
1350 | ||
b5e89ed5 | 1351 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
1352 | |
1353 | /* The CP is no longer running after an engine reset */ | |
1354 | dev_priv->cp_running = 0; | |
1355 | ||
1356 | return 0; | |
1357 | } | |
1358 | ||
c153f45f | 1359 | int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1360 | { |
1da177e4 | 1361 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1362 | DRM_DEBUG("\n"); |
1da177e4 | 1363 | |
6c340eac | 1364 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1365 | |
b5e89ed5 | 1366 | return radeon_do_cp_idle(dev_priv); |
1da177e4 LT |
1367 | } |
1368 | ||
1369 | /* Added by Charl P. Botha to call radeon_do_resume_cp(). | |
1370 | */ | |
c153f45f | 1371 | int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1372 | { |
1da177e4 LT |
1373 | |
1374 | return radeon_do_resume_cp(dev); | |
1375 | } | |
1376 | ||
c153f45f | 1377 | int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1378 | { |
b5e89ed5 | 1379 | DRM_DEBUG("\n"); |
1da177e4 | 1380 | |
6c340eac | 1381 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1382 | |
b5e89ed5 | 1383 | return radeon_do_engine_reset(dev); |
1da177e4 LT |
1384 | } |
1385 | ||
1da177e4 LT |
1386 | /* ================================================================ |
1387 | * Fullscreen mode | |
1388 | */ | |
1389 | ||
1390 | /* KW: Deprecated to say the least: | |
1391 | */ | |
c153f45f | 1392 | int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 LT |
1393 | { |
1394 | return 0; | |
1395 | } | |
1396 | ||
1da177e4 LT |
1397 | /* ================================================================ |
1398 | * Freelist management | |
1399 | */ | |
1400 | ||
1401 | /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through | |
1402 | * bufs until freelist code is used. Note this hides a problem with | |
1403 | * the scratch register * (used to keep track of last buffer | |
1404 | * completed) being written to before * the last buffer has actually | |
b5e89ed5 | 1405 | * completed rendering. |
1da177e4 LT |
1406 | * |
1407 | * KW: It's also a good way to find free buffers quickly. | |
1408 | * | |
1409 | * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't | |
1410 | * sleep. However, bugs in older versions of radeon_accel.c mean that | |
1411 | * we essentially have to do this, else old clients will break. | |
b5e89ed5 | 1412 | * |
1da177e4 LT |
1413 | * However, it does leave open a potential deadlock where all the |
1414 | * buffers are held by other clients, which can't release them because | |
b5e89ed5 | 1415 | * they can't get the lock. |
1da177e4 LT |
1416 | */ |
1417 | ||
056219e2 | 1418 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1419 | { |
cdd55a29 | 1420 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1421 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1422 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1423 | struct drm_buf *buf; |
1da177e4 LT |
1424 | int i, t; |
1425 | int start; | |
1426 | ||
b5e89ed5 | 1427 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1428 | dev_priv->last_buf = 0; |
1429 | ||
1430 | start = dev_priv->last_buf; | |
1431 | ||
b5e89ed5 DA |
1432 | for (t = 0; t < dev_priv->usec_timeout; t++) { |
1433 | u32 done_age = GET_SCRATCH(1); | |
1434 | DRM_DEBUG("done_age = %d\n", done_age); | |
1435 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1436 | buf = dma->buflist[i]; |
1437 | buf_priv = buf->dev_private; | |
6c340eac EA |
1438 | if (buf->file_priv == NULL || (buf->pending && |
1439 | buf_priv->age <= | |
1440 | done_age)) { | |
1da177e4 LT |
1441 | dev_priv->stats.requested_bufs++; |
1442 | buf->pending = 0; | |
1443 | return buf; | |
1444 | } | |
1445 | start = 0; | |
1446 | } | |
1447 | ||
1448 | if (t) { | |
b5e89ed5 | 1449 | DRM_UDELAY(1); |
1da177e4 LT |
1450 | dev_priv->stats.freelist_loops++; |
1451 | } | |
1452 | } | |
1453 | ||
b5e89ed5 | 1454 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
1455 | return NULL; |
1456 | } | |
b5e89ed5 | 1457 | |
1da177e4 | 1458 | #if 0 |
056219e2 | 1459 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1460 | { |
cdd55a29 | 1461 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1462 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1463 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1464 | struct drm_buf *buf; |
1da177e4 LT |
1465 | int i, t; |
1466 | int start; | |
1467 | u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); | |
1468 | ||
b5e89ed5 | 1469 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1470 | dev_priv->last_buf = 0; |
1471 | ||
1472 | start = dev_priv->last_buf; | |
1473 | dev_priv->stats.freelist_loops++; | |
b5e89ed5 DA |
1474 | |
1475 | for (t = 0; t < 2; t++) { | |
1476 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1477 | buf = dma->buflist[i]; |
1478 | buf_priv = buf->dev_private; | |
6c340eac EA |
1479 | if (buf->file_priv == 0 || (buf->pending && |
1480 | buf_priv->age <= | |
1481 | done_age)) { | |
1da177e4 LT |
1482 | dev_priv->stats.requested_bufs++; |
1483 | buf->pending = 0; | |
1484 | return buf; | |
1485 | } | |
1486 | } | |
1487 | start = 0; | |
1488 | } | |
1489 | ||
1490 | return NULL; | |
1491 | } | |
1492 | #endif | |
1493 | ||
84b1fd10 | 1494 | void radeon_freelist_reset(struct drm_device * dev) |
1da177e4 | 1495 | { |
cdd55a29 | 1496 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1497 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1498 | int i; | |
1499 | ||
1500 | dev_priv->last_buf = 0; | |
b5e89ed5 | 1501 | for (i = 0; i < dma->buf_count; i++) { |
056219e2 | 1502 | struct drm_buf *buf = dma->buflist[i]; |
1da177e4 LT |
1503 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
1504 | buf_priv->age = 0; | |
1505 | } | |
1506 | } | |
1507 | ||
1da177e4 LT |
1508 | /* ================================================================ |
1509 | * CP command submission | |
1510 | */ | |
1511 | ||
b5e89ed5 | 1512 | int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) |
1da177e4 LT |
1513 | { |
1514 | drm_radeon_ring_buffer_t *ring = &dev_priv->ring; | |
1515 | int i; | |
b5e89ed5 | 1516 | u32 last_head = GET_RING_HEAD(dev_priv); |
1da177e4 | 1517 | |
b5e89ed5 DA |
1518 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
1519 | u32 head = GET_RING_HEAD(dev_priv); | |
1da177e4 LT |
1520 | |
1521 | ring->space = (head - ring->tail) * sizeof(u32); | |
b5e89ed5 | 1522 | if (ring->space <= 0) |
1da177e4 | 1523 | ring->space += ring->size; |
b5e89ed5 | 1524 | if (ring->space > n) |
1da177e4 | 1525 | return 0; |
b5e89ed5 | 1526 | |
1da177e4 LT |
1527 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
1528 | ||
1529 | if (head != last_head) | |
1530 | i = 0; | |
1531 | last_head = head; | |
1532 | ||
b5e89ed5 | 1533 | DRM_UDELAY(1); |
1da177e4 LT |
1534 | } |
1535 | ||
1536 | /* FIXME: This return value is ignored in the BEGIN_RING macro! */ | |
1537 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
1538 | radeon_status(dev_priv); |
1539 | DRM_ERROR("failed!\n"); | |
1da177e4 | 1540 | #endif |
20caafa6 | 1541 | return -EBUSY; |
1da177e4 LT |
1542 | } |
1543 | ||
6c340eac EA |
1544 | static int radeon_cp_get_buffers(struct drm_device *dev, |
1545 | struct drm_file *file_priv, | |
c60ce623 | 1546 | struct drm_dma * d) |
1da177e4 LT |
1547 | { |
1548 | int i; | |
056219e2 | 1549 | struct drm_buf *buf; |
1da177e4 | 1550 | |
b5e89ed5 DA |
1551 | for (i = d->granted_count; i < d->request_count; i++) { |
1552 | buf = radeon_freelist_get(dev); | |
1553 | if (!buf) | |
20caafa6 | 1554 | return -EBUSY; /* NOTE: broken client */ |
1da177e4 | 1555 | |
6c340eac | 1556 | buf->file_priv = file_priv; |
1da177e4 | 1557 | |
b5e89ed5 DA |
1558 | if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, |
1559 | sizeof(buf->idx))) | |
20caafa6 | 1560 | return -EFAULT; |
b5e89ed5 DA |
1561 | if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, |
1562 | sizeof(buf->total))) | |
20caafa6 | 1563 | return -EFAULT; |
1da177e4 LT |
1564 | |
1565 | d->granted_count++; | |
1566 | } | |
1567 | return 0; | |
1568 | } | |
1569 | ||
c153f45f | 1570 | int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1571 | { |
cdd55a29 | 1572 | struct drm_device_dma *dma = dev->dma; |
1da177e4 | 1573 | int ret = 0; |
c153f45f | 1574 | struct drm_dma *d = data; |
1da177e4 | 1575 | |
6c340eac | 1576 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1577 | |
1da177e4 LT |
1578 | /* Please don't send us buffers. |
1579 | */ | |
c153f45f | 1580 | if (d->send_count != 0) { |
b5e89ed5 | 1581 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", |
c153f45f | 1582 | DRM_CURRENTPID, d->send_count); |
20caafa6 | 1583 | return -EINVAL; |
1da177e4 LT |
1584 | } |
1585 | ||
1586 | /* We'll send you buffers. | |
1587 | */ | |
c153f45f | 1588 | if (d->request_count < 0 || d->request_count > dma->buf_count) { |
b5e89ed5 | 1589 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", |
c153f45f | 1590 | DRM_CURRENTPID, d->request_count, dma->buf_count); |
20caafa6 | 1591 | return -EINVAL; |
1da177e4 LT |
1592 | } |
1593 | ||
c153f45f | 1594 | d->granted_count = 0; |
1da177e4 | 1595 | |
c153f45f EA |
1596 | if (d->request_count) { |
1597 | ret = radeon_cp_get_buffers(dev, file_priv, d); | |
1da177e4 LT |
1598 | } |
1599 | ||
1da177e4 LT |
1600 | return ret; |
1601 | } | |
1602 | ||
22eae947 | 1603 | int radeon_driver_load(struct drm_device *dev, unsigned long flags) |
1da177e4 LT |
1604 | { |
1605 | drm_radeon_private_t *dev_priv; | |
1606 | int ret = 0; | |
1607 | ||
1608 | dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); | |
1609 | if (dev_priv == NULL) | |
20caafa6 | 1610 | return -ENOMEM; |
1da177e4 LT |
1611 | |
1612 | memset(dev_priv, 0, sizeof(drm_radeon_private_t)); | |
1613 | dev->dev_private = (void *)dev_priv; | |
1614 | dev_priv->flags = flags; | |
1615 | ||
54a56ac5 | 1616 | switch (flags & RADEON_FAMILY_MASK) { |
1da177e4 LT |
1617 | case CHIP_R100: |
1618 | case CHIP_RV200: | |
1619 | case CHIP_R200: | |
1620 | case CHIP_R300: | |
b15ec368 | 1621 | case CHIP_R350: |
414ed537 | 1622 | case CHIP_R420: |
b15ec368 | 1623 | case CHIP_RV410: |
3d5e2c13 DA |
1624 | case CHIP_RV515: |
1625 | case CHIP_R520: | |
1626 | case CHIP_RV570: | |
1627 | case CHIP_R580: | |
54a56ac5 | 1628 | dev_priv->flags |= RADEON_HAS_HIERZ; |
1da177e4 LT |
1629 | break; |
1630 | default: | |
b5e89ed5 | 1631 | /* all other chips have no hierarchical z buffer */ |
1da177e4 LT |
1632 | break; |
1633 | } | |
414ed537 DA |
1634 | |
1635 | if (drm_device_is_agp(dev)) | |
54a56ac5 | 1636 | dev_priv->flags |= RADEON_IS_AGP; |
b15ec368 | 1637 | else if (drm_device_is_pcie(dev)) |
54a56ac5 | 1638 | dev_priv->flags |= RADEON_IS_PCIE; |
b15ec368 | 1639 | else |
54a56ac5 | 1640 | dev_priv->flags |= RADEON_IS_PCI; |
ea98a92f | 1641 | |
414ed537 | 1642 | DRM_DEBUG("%s card detected\n", |
54a56ac5 | 1643 | ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); |
1da177e4 LT |
1644 | return ret; |
1645 | } | |
1646 | ||
22eae947 DA |
1647 | /* Create mappings for registers and framebuffer so userland doesn't necessarily |
1648 | * have to find them. | |
1649 | */ | |
1650 | int radeon_driver_firstopen(struct drm_device *dev) | |
836cf046 DA |
1651 | { |
1652 | int ret; | |
1653 | drm_local_map_t *map; | |
1654 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1655 | ||
f2b04cd2 DA |
1656 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; |
1657 | ||
836cf046 DA |
1658 | ret = drm_addmap(dev, drm_get_resource_start(dev, 2), |
1659 | drm_get_resource_len(dev, 2), _DRM_REGISTERS, | |
1660 | _DRM_READ_ONLY, &dev_priv->mmio); | |
1661 | if (ret != 0) | |
1662 | return ret; | |
1663 | ||
7fc86860 DA |
1664 | dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); |
1665 | ret = drm_addmap(dev, dev_priv->fb_aper_offset, | |
836cf046 DA |
1666 | drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, |
1667 | _DRM_WRITE_COMBINING, &map); | |
1668 | if (ret != 0) | |
1669 | return ret; | |
1670 | ||
1671 | return 0; | |
1672 | } | |
1673 | ||
22eae947 | 1674 | int radeon_driver_unload(struct drm_device *dev) |
1da177e4 LT |
1675 | { |
1676 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1677 | ||
1678 | DRM_DEBUG("\n"); | |
1da177e4 LT |
1679 | drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); |
1680 | ||
1681 | dev->dev_private = NULL; | |
1682 | return 0; | |
1683 | } |