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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for-linus
[mirror_ubuntu-jammy-kernel.git] / drivers / char / drm / radeon_cp.c
CommitLineData
f26c473c
DA		 1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
1da177e4
LT		 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#include "drmP.h"
32#include "drm.h"
33#include "radeon_drm.h"
34#include "radeon_drv.h"
414ed537 35#include "r300_reg.h"
1da177e4
LT		 36
37#define RADEON_FIFO_DEBUG 0
38
84b1fd10 39static int radeon_do_cleanup_cp(struct drm_device * dev);
1da177e4
LT		 40
41/* CP microcode (from ATI) */
c499aeb0 42static const u32 R200_cp_microcode[][2] = {
b5e89ed5
DA		 43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
1da177e4
LT		 299};
300
c499aeb0 301static const u32 radeon_cp_microcode[][2] = {
b5e89ed5
DA		 302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
1da177e4
LT		 558};
559
c499aeb0 560static const u32 R300_cp_microcode[][2] = {
b5e89ed5
DA		 561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
1da177e4
LT		 817};
818
3d5e2c13
DA		 819static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
820{
821 u32 ret;
822 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
823 ret = RADEON_READ(R520_MC_IND_DATA);
824 RADEON_WRITE(R520_MC_IND_INDEX, 0);
825 return ret;
826}
827
828u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
829{
830
831 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
832 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
833 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
834 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
835 else
836 return RADEON_READ(RADEON_MC_FB_LOCATION);
837}
838
839static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
840{
841 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
842 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
843 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
844 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
845 else
846 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
847}
848
849static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
850{
851 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
852 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
853 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
854 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
855 else
856 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
857}
858
84b1fd10 859static int RADEON_READ_PLL(struct drm_device * dev, int addr)
1da177e4
LT		 860{
861 drm_radeon_private_t *dev_priv = dev->dev_private;
862
863 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
864 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
865}
866
3d5e2c13 867static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
ea98a92f
DA		 868{
869 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
870 return RADEON_READ(RADEON_PCIE_DATA);
871}
872
f2b04cd2
DA		 873static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
874{
875 u32 ret;
876 RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
877 ret = RADEON_READ(RADEON_IGPGART_DATA);
878 RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
879 return ret;
880}
881
1da177e4 882#if RADEON_FIFO_DEBUG
b5e89ed5 883static void radeon_status(drm_radeon_private_t * dev_priv)
1da177e4 884{
b5e89ed5
DA		 885 printk("%s:\n", __FUNCTION__);
886 printk("RBBM_STATUS = 0x%08x\n",
887 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
888 printk("CP_RB_RTPR = 0x%08x\n",
889 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
890 printk("CP_RB_WTPR = 0x%08x\n",
891 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
892 printk("AIC_CNTL = 0x%08x\n",
893 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
894 printk("AIC_STAT = 0x%08x\n",
895 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
896 printk("AIC_PT_BASE = 0x%08x\n",
897 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
898 printk("TLB_ADDR = 0x%08x\n",
899 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
900 printk("TLB_DATA = 0x%08x\n",
901 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
1da177e4
LT		 902}
903#endif
904
1da177e4
LT		 905/* ================================================================
906 * Engine, FIFO control
907 */
908
b5e89ed5 909static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
1da177e4
LT		 910{
911 u32 tmp;
912 int i;
913
914 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
915
b9b603dd
MD		 916 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
917 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
918 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
1da177e4 919
b5e89ed5 920 for (i = 0; i < dev_priv->usec_timeout; i++) {
b9b603dd
MD		 921 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
922 & RADEON_RB3D_DC_BUSY)) {
1da177e4
LT		 923 return 0;
924 }
b5e89ed5 925 DRM_UDELAY(1);
1da177e4
LT		 926 }
927
928#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 929 DRM_ERROR("failed!\n");
930 radeon_status(dev_priv);
1da177e4 931#endif
20caafa6 932 return -EBUSY;
1da177e4
LT		 933}
934
b5e89ed5 935static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
1da177e4
LT		 936{
937 int i;
938
939 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
940
b5e89ed5
DA		 941 for (i = 0; i < dev_priv->usec_timeout; i++) {
942 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
943 & RADEON_RBBM_FIFOCNT_MASK);
944 if (slots >= entries)
945 return 0;
946 DRM_UDELAY(1);
1da177e4
LT		 947 }
948
949#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 950 DRM_ERROR("failed!\n");
951 radeon_status(dev_priv);
1da177e4 952#endif
20caafa6 953 return -EBUSY;
1da177e4
LT		 954}
955
b5e89ed5 956static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 957{
958 int i, ret;
959
960 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
961
b5e89ed5
DA		 962 ret = radeon_do_wait_for_fifo(dev_priv, 64);
963 if (ret)
964 return ret;
1da177e4 965
b5e89ed5
DA		 966 for (i = 0; i < dev_priv->usec_timeout; i++) {
967 if (!(RADEON_READ(RADEON_RBBM_STATUS)
968 & RADEON_RBBM_ACTIVE)) {
969 radeon_do_pixcache_flush(dev_priv);
1da177e4
LT		 970 return 0;
971 }
b5e89ed5 972 DRM_UDELAY(1);
1da177e4
LT		 973 }
974
975#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 976 DRM_ERROR("failed!\n");
977 radeon_status(dev_priv);
1da177e4 978#endif
20caafa6 979 return -EBUSY;
1da177e4
LT		 980}
981
1da177e4
LT		 982/* ================================================================
983 * CP control, initialization
984 */
985
986/* Load the microcode for the CP */
b5e89ed5 987static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1da177e4
LT		 988{
989 int i;
b5e89ed5 990 DRM_DEBUG("\n");
1da177e4 991
b5e89ed5 992 radeon_do_wait_for_idle(dev_priv);
1da177e4 993
b5e89ed5 994 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1da177e4 995
b5e89ed5 996 if (dev_priv->microcode_version == UCODE_R200) {
1da177e4 997 DRM_INFO("Loading R200 Microcode\n");
b5e89ed5
DA		 998 for (i = 0; i < 256; i++) {
999 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1000 R200_cp_microcode[i][1]);
1001 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1002 R200_cp_microcode[i][0]);
1da177e4 1003 }
b5e89ed5 1004 } else if (dev_priv->microcode_version == UCODE_R300) {
1da177e4 1005 DRM_INFO("Loading R300 Microcode\n");
b5e89ed5
DA		 1006 for (i = 0; i < 256; i++) {
1007 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1008 R300_cp_microcode[i][1]);
1009 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1010 R300_cp_microcode[i][0]);
1da177e4
LT		 1011 }
1012 } else {
b5e89ed5
DA		 1013 for (i = 0; i < 256; i++) {
1014 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1015 radeon_cp_microcode[i][1]);
1016 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1017 radeon_cp_microcode[i][0]);
1da177e4
LT		 1018 }
1019 }
1020}
1021
1022/* Flush any pending commands to the CP. This should only be used just
1023 * prior to a wait for idle, as it informs the engine that the command
1024 * stream is ending.
1025 */
b5e89ed5 1026static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1da177e4 1027{
b5e89ed5 1028 DRM_DEBUG("\n");
1da177e4
LT		 1029#if 0
1030 u32 tmp;
1031
b5e89ed5
DA		 1032 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
1033 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1da177e4
LT		 1034#endif
1035}
1036
1037/* Wait for the CP to go idle.
1038 */
b5e89ed5 1039int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1040{
1041 RING_LOCALS;
b5e89ed5 1042 DRM_DEBUG("\n");
1da177e4 1043
b5e89ed5 1044 BEGIN_RING(6);
1da177e4
LT		 1045
1046 RADEON_PURGE_CACHE();
1047 RADEON_PURGE_ZCACHE();
1048 RADEON_WAIT_UNTIL_IDLE();
1049
1050 ADVANCE_RING();
1051 COMMIT_RING();
1052
b5e89ed5 1053 return radeon_do_wait_for_idle(dev_priv);
1da177e4
LT		 1054}
1055
1056/* Start the Command Processor.
1057 */
b5e89ed5 1058static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1059{
1060 RING_LOCALS;
b5e89ed5 1061 DRM_DEBUG("\n");
1da177e4 1062
b5e89ed5 1063 radeon_do_wait_for_idle(dev_priv);
1da177e4 1064
b5e89ed5 1065 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1da177e4
LT		 1066
1067 dev_priv->cp_running = 1;
1068
b5e89ed5 1069 BEGIN_RING(6);
1da177e4
LT		 1070
1071 RADEON_PURGE_CACHE();
1072 RADEON_PURGE_ZCACHE();
1073 RADEON_WAIT_UNTIL_IDLE();
1074
1075 ADVANCE_RING();
1076 COMMIT_RING();
1077}
1078
1079/* Reset the Command Processor. This will not flush any pending
1080 * commands, so you must wait for the CP command stream to complete
1081 * before calling this routine.
1082 */
b5e89ed5 1083static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1084{
1085 u32 cur_read_ptr;
b5e89ed5 1086 DRM_DEBUG("\n");
1da177e4 1087
b5e89ed5
DA		 1088 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1089 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1090 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 1091 dev_priv->ring.tail = cur_read_ptr;
1092}
1093
1094/* Stop the Command Processor. This will not flush any pending
1095 * commands, so you must flush the command stream and wait for the CP
1096 * to go idle before calling this routine.
1097 */
b5e89ed5 1098static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1da177e4 1099{
b5e89ed5 1100 DRM_DEBUG("\n");
1da177e4 1101
b5e89ed5 1102 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1da177e4
LT		 1103
1104 dev_priv->cp_running = 0;
1105}
1106
1107/* Reset the engine. This will stop the CP if it is running.
1108 */
84b1fd10 1109static int radeon_do_engine_reset(struct drm_device * dev)
1da177e4
LT		 1110{
1111 drm_radeon_private_t *dev_priv = dev->dev_private;
1112 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
b5e89ed5 1113 DRM_DEBUG("\n");
1da177e4 1114
b5e89ed5
DA		 1115 radeon_do_pixcache_flush(dev_priv);
1116
3d5e2c13
DA		 1117 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1118 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1119 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1120
1121 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1122 RADEON_FORCEON_MCLKA |
1123 RADEON_FORCEON_MCLKB |
1124 RADEON_FORCEON_YCLKA |
1125 RADEON_FORCEON_YCLKB |
1126 RADEON_FORCEON_MC |
1127 RADEON_FORCEON_AIC));
1128
1129 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1130
1131 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1132 RADEON_SOFT_RESET_CP |
1133 RADEON_SOFT_RESET_HI |
1134 RADEON_SOFT_RESET_SE |
1135 RADEON_SOFT_RESET_RE |
1136 RADEON_SOFT_RESET_PP |
1137 RADEON_SOFT_RESET_E2 |
1138 RADEON_SOFT_RESET_RB));
1139 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1140 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1141 ~(RADEON_SOFT_RESET_CP |
1142 RADEON_SOFT_RESET_HI |
1143 RADEON_SOFT_RESET_SE |
1144 RADEON_SOFT_RESET_RE |
1145 RADEON_SOFT_RESET_PP |
1146 RADEON_SOFT_RESET_E2 |
1147 RADEON_SOFT_RESET_RB)));
1148 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1149
1150 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1151 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1152 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1153 }
1da177e4
LT		 1154
1155 /* Reset the CP ring */
b5e89ed5 1156 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1157
1158 /* The CP is no longer running after an engine reset */
1159 dev_priv->cp_running = 0;
1160
1161 /* Reset any pending vertex, indirect buffers */
b5e89ed5 1162 radeon_freelist_reset(dev);
1da177e4
LT		 1163
1164 return 0;
1165}
1166
84b1fd10 1167static void radeon_cp_init_ring_buffer(struct drm_device * dev,
b5e89ed5 1168 drm_radeon_private_t * dev_priv)
1da177e4
LT		 1169{
1170 u32 ring_start, cur_read_ptr;
1171 u32 tmp;
bc5f4523 1172
d5ea702f
DA		 1173 /* Initialize the memory controller. With new memory map, the fb location
1174 * is not changed, it should have been properly initialized already. Part
1175 * of the problem is that the code below is bogus, assuming the GART is
1176 * always appended to the fb which is not necessarily the case
1177 */
1178 if (!dev_priv->new_memmap)
3d5e2c13 1179 radeon_write_fb_location(dev_priv,
d5ea702f
DA		 1180 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1181 | (dev_priv->fb_location >> 16));
1da177e4
LT		 1182
1183#if __OS_HAS_AGP
54a56ac5 1184 if (dev_priv->flags & RADEON_IS_AGP) {
d5ea702f 1185 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
3d5e2c13 1186 radeon_write_agp_location(dev_priv,
b5e89ed5
DA		 1187 (((dev_priv->gart_vm_start - 1 +
1188 dev_priv->gart_size) & 0xffff0000) |
1189 (dev_priv->gart_vm_start >> 16)));
1da177e4
LT		 1190
1191 ring_start = (dev_priv->cp_ring->offset
1192 - dev->agp->base
1193 + dev_priv->gart_vm_start);
b0917bd9 1194 } else
1da177e4
LT		 1195#endif
1196 ring_start = (dev_priv->cp_ring->offset
b0917bd9 1197 - (unsigned long)dev->sg->virtual
1da177e4
LT		 1198 + dev_priv->gart_vm_start);
1199
b5e89ed5 1200 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1da177e4
LT		 1201
1202 /* Set the write pointer delay */
b5e89ed5 1203 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1da177e4
LT		 1204
1205 /* Initialize the ring buffer's read and write pointers */
b5e89ed5
DA		 1206 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1207 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1208 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 1209 dev_priv->ring.tail = cur_read_ptr;
1210
1211#if __OS_HAS_AGP
54a56ac5 1212 if (dev_priv->flags & RADEON_IS_AGP) {
b5e89ed5
DA		 1213 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1214 dev_priv->ring_rptr->offset
1215 - dev->agp->base + dev_priv->gart_vm_start);
1da177e4
LT		 1216 } else
1217#endif
1218 {
55910517 1219 struct drm_sg_mem *entry = dev->sg;
1da177e4
LT		 1220 unsigned long tmp_ofs, page_ofs;
1221
b0917bd9
IK		 1222 tmp_ofs = dev_priv->ring_rptr->offset -
1223 (unsigned long)dev->sg->virtual;
1da177e4
LT		 1224 page_ofs = tmp_ofs >> PAGE_SHIFT;
1225
b5e89ed5
DA		 1226 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1227 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1228 (unsigned long)entry->busaddr[page_ofs],
1229 entry->handle + tmp_ofs);
1da177e4
LT		 1230 }
1231
d5ea702f
DA		 1232 /* Set ring buffer size */
1233#ifdef __BIG_ENDIAN
1234 RADEON_WRITE(RADEON_CP_RB_CNTL,
576cc458
RS		 1235 RADEON_BUF_SWAP_32BIT |
1236 (dev_priv->ring.fetch_size_l2ow << 18) |
1237 (dev_priv->ring.rptr_update_l2qw << 8) |
1238 dev_priv->ring.size_l2qw);
d5ea702f 1239#else
576cc458
RS		 1240 RADEON_WRITE(RADEON_CP_RB_CNTL,
1241 (dev_priv->ring.fetch_size_l2ow << 18) |
1242 (dev_priv->ring.rptr_update_l2qw << 8) |
1243 dev_priv->ring.size_l2qw);
d5ea702f
DA		 1244#endif
1245
1246 /* Start with assuming that writeback doesn't work */
1247 dev_priv->writeback_works = 0;
1248
1da177e4
LT		 1249 /* Initialize the scratch register pointer. This will cause
1250 * the scratch register values to be written out to memory
1251 * whenever they are updated.
1252 *
1253 * We simply put this behind the ring read pointer, this works
1254 * with PCI GART as well as (whatever kind of) AGP GART
1255 */
b5e89ed5
DA		 1256 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1257 + RADEON_SCRATCH_REG_OFFSET);
1da177e4
LT		 1258
1259 dev_priv->scratch = ((__volatile__ u32 *)
1260 dev_priv->ring_rptr->handle +
1261 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1262
b5e89ed5 1263 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1da177e4 1264
d5ea702f
DA		 1265 /* Turn on bus mastering */
1266 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1267 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1da177e4
LT		 1268
1269 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
b5e89ed5 1270 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1da177e4
LT		 1271
1272 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
b5e89ed5
DA		 1273 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1274 dev_priv->sarea_priv->last_dispatch);
1da177e4
LT		 1275
1276 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
b5e89ed5 1277 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1da177e4 1278
b5e89ed5 1279 radeon_do_wait_for_idle(dev_priv);
1da177e4 1280
1da177e4 1281 /* Sync everything up */
b5e89ed5
DA		 1282 RADEON_WRITE(RADEON_ISYNC_CNTL,
1283 (RADEON_ISYNC_ANY2D_IDLE3D |
1284 RADEON_ISYNC_ANY3D_IDLE2D |
1285 RADEON_ISYNC_WAIT_IDLEGUI |
1286 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
d5ea702f
DA		 1287
1288}
1289
1290static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1291{
1292 u32 tmp;
1293
1294 /* Writeback doesn't seem to work everywhere, test it here and possibly
1295 * enable it if it appears to work
1296 */
1297 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1298 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1299
1300 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1301 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1302 0xdeadbeef)
1303 break;
1304 DRM_UDELAY(1);
1305 }
1306
1307 if (tmp < dev_priv->usec_timeout) {
1308 dev_priv->writeback_works = 1;
1309 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1310 } else {
1311 dev_priv->writeback_works = 0;
1312 DRM_INFO("writeback test failed\n");
1313 }
1314 if (radeon_no_wb == 1) {
1315 dev_priv->writeback_works = 0;
1316 DRM_INFO("writeback forced off\n");
1317 }
ae1b1a48
MD		 1318
1319 if (!dev_priv->writeback_works) {
1320 /* Disable writeback to avoid unnecessary bus master transfer */
1321 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
1322 RADEON_RB_NO_UPDATE);
1323 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1324 }
1da177e4
LT		 1325}
1326
f2b04cd2
DA		 1327/* Enable or disable IGP GART on the chip */
1328static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1329{
1330 u32 temp, tmp;
1331
1332 tmp = RADEON_READ(RADEON_AIC_CNTL);
1333 if (on) {
1334 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1335 dev_priv->gart_vm_start,
1336 (long)dev_priv->gart_info.bus_addr,
1337 dev_priv->gart_size);
1338
1339 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1340 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1341 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1342 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1343 dev_priv->gart_info.bus_addr);
1344
1345 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1346 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1347
1348 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1349 dev_priv->gart_size = 32*1024*1024;
3d5e2c13 1350 radeon_write_agp_location(dev_priv,
f2b04cd2
DA		 1351 (((dev_priv->gart_vm_start - 1 +
1352 dev_priv->gart_size) & 0xffff0000) |
1353 (dev_priv->gart_vm_start >> 16)));
1354
1355 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1356 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1357
1358 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1359 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1360 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1361 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1362 }
1363}
1364
ea98a92f
DA		 1365static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1366{
1367 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1368 if (on) {
1369
1370 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
b5e89ed5
DA		 1371 dev_priv->gart_vm_start,
1372 (long)dev_priv->gart_info.bus_addr,
ea98a92f 1373 dev_priv->gart_size);
b5e89ed5
DA		 1374 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1375 dev_priv->gart_vm_start);
1376 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1377 dev_priv->gart_info.bus_addr);
1378 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1379 dev_priv->gart_vm_start);
1380 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1381 dev_priv->gart_vm_start +
1382 dev_priv->gart_size - 1);
1383
3d5e2c13 1384 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
b5e89ed5
DA		 1385
1386 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1387 RADEON_PCIE_TX_GART_EN);
ea98a92f 1388 } else {
b5e89ed5
DA		 1389 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1390 tmp & ~RADEON_PCIE_TX_GART_EN);
ea98a92f 1391 }
1da177e4
LT		 1392}
1393
1394/* Enable or disable PCI GART on the chip */
b5e89ed5 1395static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1da177e4 1396{
d985c108 1397 u32 tmp;
1da177e4 1398
f2b04cd2
DA		 1399 if (dev_priv->flags & RADEON_IS_IGPGART) {
1400 radeon_set_igpgart(dev_priv, on);
1401 return;
1402 }
1403
54a56ac5 1404 if (dev_priv->flags & RADEON_IS_PCIE) {
ea98a92f
DA		 1405 radeon_set_pciegart(dev_priv, on);
1406 return;
1407 }
1da177e4 1408
bc5f4523 1409 tmp = RADEON_READ(RADEON_AIC_CNTL);
d985c108 1410
b5e89ed5
DA		 1411 if (on) {
1412 RADEON_WRITE(RADEON_AIC_CNTL,
1413 tmp | RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1414
1415 /* set PCI GART page-table base address
1416 */
ea98a92f 1417 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1da177e4
LT		 1418
1419 /* set address range for PCI address translate
1420 */
b5e89ed5
DA		 1421 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1422 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1423 + dev_priv->gart_size - 1);
1da177e4
LT		 1424
1425 /* Turn off AGP aperture -- is this required for PCI GART?
1426 */
3d5e2c13 1427 radeon_write_agp_location(dev_priv, 0xffffffc0);
b5e89ed5 1428 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1da177e4 1429 } else {
b5e89ed5
DA		 1430 RADEON_WRITE(RADEON_AIC_CNTL,
1431 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1432 }
1433}
1434
84b1fd10 1435static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1da177e4 1436{
d985c108
DA		 1437 drm_radeon_private_t *dev_priv = dev->dev_private;
1438
b5e89ed5 1439 DRM_DEBUG("\n");
1da177e4 1440
f3dd5c37 1441 /* if we require new memory map but we don't have it fail */
54a56ac5 1442 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
b15ec368 1443 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
f3dd5c37 1444 radeon_do_cleanup_cp(dev);
20caafa6 1445 return -EINVAL;
f3dd5c37
DA		 1446 }
1447
54a56ac5 1448 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
d985c108 1449 DRM_DEBUG("Forcing AGP card to PCI mode\n");
54a56ac5
DA		 1450 dev_priv->flags &= ~RADEON_IS_AGP;
1451 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
b15ec368
DA		 1452 && !init->is_pci) {
1453 DRM_DEBUG("Restoring AGP flag\n");
54a56ac5 1454 dev_priv->flags |= RADEON_IS_AGP;
d985c108 1455 }
1da177e4 1456
54a56ac5 1457 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
b5e89ed5 1458 DRM_ERROR("PCI GART memory not allocated!\n");
1da177e4 1459 radeon_do_cleanup_cp(dev);
20caafa6 1460 return -EINVAL;
1da177e4
LT		 1461 }
1462
1463 dev_priv->usec_timeout = init->usec_timeout;
b5e89ed5
DA		 1464 if (dev_priv->usec_timeout < 1 ||
1465 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1466 DRM_DEBUG("TIMEOUT problem!\n");
1da177e4 1467 radeon_do_cleanup_cp(dev);
20caafa6 1468 return -EINVAL;
1da177e4
LT		 1469 }
1470
ddbee333
DA		 1471 /* Enable vblank on CRTC1 for older X servers
1472 */
1473 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1474
d985c108 1475 switch(init->func) {
1da177e4 1476 case RADEON_INIT_R200_CP:
b5e89ed5 1477 dev_priv->microcode_version = UCODE_R200;
1da177e4
LT		 1478 break;
1479 case RADEON_INIT_R300_CP:
b5e89ed5 1480 dev_priv->microcode_version = UCODE_R300;
1da177e4
LT		 1481 break;
1482 default:
b5e89ed5 1483 dev_priv->microcode_version = UCODE_R100;
1da177e4 1484 }
b5e89ed5 1485
1da177e4
LT		 1486 dev_priv->do_boxes = 0;
1487 dev_priv->cp_mode = init->cp_mode;
1488
1489 /* We don't support anything other than bus-mastering ring mode,
1490 * but the ring can be in either AGP or PCI space for the ring
1491 * read pointer.
1492 */
b5e89ed5
DA		 1493 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1494 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1495 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1da177e4 1496 radeon_do_cleanup_cp(dev);
20caafa6 1497 return -EINVAL;
1da177e4
LT		 1498 }
1499
b5e89ed5 1500 switch (init->fb_bpp) {
1da177e4
LT		 1501 case 16:
1502 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1503 break;
1504 case 32:
1505 default:
1506 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1507 break;
1508 }
b5e89ed5
DA		 1509 dev_priv->front_offset = init->front_offset;
1510 dev_priv->front_pitch = init->front_pitch;
1511 dev_priv->back_offset = init->back_offset;
1512 dev_priv->back_pitch = init->back_pitch;
1da177e4 1513
b5e89ed5 1514 switch (init->depth_bpp) {
1da177e4
LT		 1515 case 16:
1516 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1517 break;
1518 case 32:
1519 default:
1520 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1521 break;
1522 }
b5e89ed5
DA		 1523 dev_priv->depth_offset = init->depth_offset;
1524 dev_priv->depth_pitch = init->depth_pitch;
1da177e4
LT		 1525
1526 /* Hardware state for depth clears. Remove this if/when we no
1527 * longer clear the depth buffer with a 3D rectangle. Hard-code
1528 * all values to prevent unwanted 3D state from slipping through
1529 * and screwing with the clear operation.
1530 */
1531 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1532 (dev_priv->color_fmt << 10) |
b5e89ed5
DA		 1533 (dev_priv->microcode_version ==
1534 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1da177e4 1535
b5e89ed5
DA		 1536 dev_priv->depth_clear.rb3d_zstencilcntl =
1537 (dev_priv->depth_fmt |
1538 RADEON_Z_TEST_ALWAYS |
1539 RADEON_STENCIL_TEST_ALWAYS |
1540 RADEON_STENCIL_S_FAIL_REPLACE |
1541 RADEON_STENCIL_ZPASS_REPLACE |
1542 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1da177e4
LT		 1543
1544 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1545 RADEON_BFACE_SOLID |
1546 RADEON_FFACE_SOLID |
1547 RADEON_FLAT_SHADE_VTX_LAST |
1548 RADEON_DIFFUSE_SHADE_FLAT |
1549 RADEON_ALPHA_SHADE_FLAT |
1550 RADEON_SPECULAR_SHADE_FLAT |
1551 RADEON_FOG_SHADE_FLAT |
1552 RADEON_VTX_PIX_CENTER_OGL |
1553 RADEON_ROUND_MODE_TRUNC |
1554 RADEON_ROUND_PREC_8TH_PIX);
1555
1da177e4 1556
1da177e4
LT		 1557 dev_priv->ring_offset = init->ring_offset;
1558 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1559 dev_priv->buffers_offset = init->buffers_offset;
1560 dev_priv->gart_textures_offset = init->gart_textures_offset;
b5e89ed5 1561
da509d7a 1562 dev_priv->sarea = drm_getsarea(dev);
b5e89ed5 1563 if (!dev_priv->sarea) {
1da177e4 1564 DRM_ERROR("could not find sarea!\n");
1da177e4 1565 radeon_do_cleanup_cp(dev);
20caafa6 1566 return -EINVAL;
1da177e4
LT		 1567 }
1568
1da177e4 1569 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
b5e89ed5 1570 if (!dev_priv->cp_ring) {
1da177e4 1571 DRM_ERROR("could not find cp ring region!\n");
1da177e4 1572 radeon_do_cleanup_cp(dev);
20caafa6 1573 return -EINVAL;
1da177e4
LT		 1574 }
1575 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
b5e89ed5 1576 if (!dev_priv->ring_rptr) {
1da177e4 1577 DRM_ERROR("could not find ring read pointer!\n");
1da177e4 1578 radeon_do_cleanup_cp(dev);
20caafa6 1579 return -EINVAL;
1da177e4 1580 }
d1f2b55a 1581 dev->agp_buffer_token = init->buffers_offset;
1da177e4 1582 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
b5e89ed5 1583 if (!dev->agp_buffer_map) {
1da177e4 1584 DRM_ERROR("could not find dma buffer region!\n");
1da177e4 1585 radeon_do_cleanup_cp(dev);
20caafa6 1586 return -EINVAL;
1da177e4
LT		 1587 }
1588
b5e89ed5
DA		 1589 if (init->gart_textures_offset) {
1590 dev_priv->gart_textures =
1591 drm_core_findmap(dev, init->gart_textures_offset);
1592 if (!dev_priv->gart_textures) {
1da177e4 1593 DRM_ERROR("could not find GART texture region!\n");
1da177e4 1594 radeon_do_cleanup_cp(dev);
20caafa6 1595 return -EINVAL;
1da177e4
LT		 1596 }
1597 }
1598
1599 dev_priv->sarea_priv =
b5e89ed5
DA		 1600 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1601 init->sarea_priv_offset);
1da177e4
LT		 1602
1603#if __OS_HAS_AGP
54a56ac5 1604 if (dev_priv->flags & RADEON_IS_AGP) {
b5e89ed5
DA		 1605 drm_core_ioremap(dev_priv->cp_ring, dev);
1606 drm_core_ioremap(dev_priv->ring_rptr, dev);
1607 drm_core_ioremap(dev->agp_buffer_map, dev);
1608 if (!dev_priv->cp_ring->handle ||
1609 !dev_priv->ring_rptr->handle ||
1610 !dev->agp_buffer_map->handle) {
1da177e4 1611 DRM_ERROR("could not find ioremap agp regions!\n");
1da177e4 1612 radeon_do_cleanup_cp(dev);
20caafa6 1613 return -EINVAL;
1da177e4
LT		 1614 }
1615 } else
1616#endif
1617 {
b5e89ed5 1618 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1da177e4 1619 dev_priv->ring_rptr->handle =
b5e89ed5
DA		 1620 (void *)dev_priv->ring_rptr->offset;
1621 dev->agp_buffer_map->handle =
1622 (void *)dev->agp_buffer_map->offset;
1623
1624 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1625 dev_priv->cp_ring->handle);
1626 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1627 dev_priv->ring_rptr->handle);
1628 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1629 dev->agp_buffer_map->handle);
1da177e4
LT		 1630 }
1631
3d5e2c13 1632 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
bc5f4523 1633 dev_priv->fb_size =
3d5e2c13 1634 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
d5ea702f 1635 - dev_priv->fb_location;
1da177e4 1636
b5e89ed5
DA		 1637 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1638 ((dev_priv->front_offset
1639 + dev_priv->fb_location) >> 10));
1da177e4 1640
b5e89ed5
DA		 1641 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1642 ((dev_priv->back_offset
1643 + dev_priv->fb_location) >> 10));
1da177e4 1644
b5e89ed5
DA		 1645 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1646 ((dev_priv->depth_offset
1647 + dev_priv->fb_location) >> 10));
1da177e4
LT		 1648
1649 dev_priv->gart_size = init->gart_size;
d5ea702f
DA		 1650
1651 /* New let's set the memory map ... */
1652 if (dev_priv->new_memmap) {
1653 u32 base = 0;
1654
1655 DRM_INFO("Setting GART location based on new memory map\n");
1656
1657 /* If using AGP, try to locate the AGP aperture at the same
1658 * location in the card and on the bus, though we have to
1659 * align it down.
1660 */
1661#if __OS_HAS_AGP
54a56ac5 1662 if (dev_priv->flags & RADEON_IS_AGP) {
d5ea702f
DA		 1663 base = dev->agp->base;
1664 /* Check if valid */
80b2c386
MD		 1665 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1666 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
d5ea702f
DA		 1667 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1668 dev->agp->base);
1669 base = 0;
1670 }
1671 }
1672#endif
1673 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1674 if (base == 0) {
1675 base = dev_priv->fb_location + dev_priv->fb_size;
80b2c386
MD		 1676 if (base < dev_priv->fb_location ||
1677 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
d5ea702f
DA		 1678 base = dev_priv->fb_location
1679 - dev_priv->gart_size;
bc5f4523 1680 }
d5ea702f
DA		 1681 dev_priv->gart_vm_start = base & 0xffc00000u;
1682 if (dev_priv->gart_vm_start != base)
1683 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1684 base, dev_priv->gart_vm_start);
1685 } else {
1686 DRM_INFO("Setting GART location based on old memory map\n");
1687 dev_priv->gart_vm_start = dev_priv->fb_location +
1688 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1689 }
1da177e4
LT		 1690
1691#if __OS_HAS_AGP
54a56ac5 1692 if (dev_priv->flags & RADEON_IS_AGP)
1da177e4 1693 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b5e89ed5
DA		 1694 - dev->agp->base
1695 + dev_priv->gart_vm_start);
1da177e4
LT		 1696 else
1697#endif
1698 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b0917bd9
IK		 1699 - (unsigned long)dev->sg->virtual
1700 + dev_priv->gart_vm_start);
1da177e4 1701
b5e89ed5
DA		 1702 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1703 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1704 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1705 dev_priv->gart_buffers_offset);
1da177e4 1706
b5e89ed5
DA		 1707 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1708 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1da177e4
LT		 1709 + init->ring_size / sizeof(u32));
1710 dev_priv->ring.size = init->ring_size;
b5e89ed5 1711 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1da177e4 1712
576cc458
RS		 1713 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1714 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1715
1716 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1717 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
b5e89ed5 1718 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1da177e4
LT		 1719
1720 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1721
1722#if __OS_HAS_AGP
54a56ac5 1723 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1724 /* Turn off PCI GART */
b5e89ed5 1725 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1726 } else
1727#endif
1728 {
ea98a92f 1729 /* if we have an offset set from userspace */
f2b04cd2 1730 if (dev_priv->pcigart_offset_set) {
b5e89ed5
DA		 1731 dev_priv->gart_info.bus_addr =
1732 dev_priv->pcigart_offset + dev_priv->fb_location;
f26c473c 1733 dev_priv->gart_info.mapping.offset =
7fc86860 1734 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
f26c473c 1735 dev_priv->gart_info.mapping.size =
f2b04cd2 1736 dev_priv->gart_info.table_size;
f26c473c
DA		 1737
1738 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
b5e89ed5 1739 dev_priv->gart_info.addr =
f26c473c 1740 dev_priv->gart_info.mapping.handle;
b5e89ed5 1741
f2b04cd2
DA		 1742 if (dev_priv->flags & RADEON_IS_PCIE)
1743 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1744 else
1745 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1746 dev_priv->gart_info.gart_table_location =
1747 DRM_ATI_GART_FB;
1748
f26c473c 1749 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
b5e89ed5
DA		 1750 dev_priv->gart_info.addr,
1751 dev_priv->pcigart_offset);
1752 } else {
f2b04cd2
DA		 1753 if (dev_priv->flags & RADEON_IS_IGPGART)
1754 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1755 else
1756 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1757 dev_priv->gart_info.gart_table_location =
1758 DRM_ATI_GART_MAIN;
f26c473c
DA		 1759 dev_priv->gart_info.addr = NULL;
1760 dev_priv->gart_info.bus_addr = 0;
54a56ac5 1761 if (dev_priv->flags & RADEON_IS_PCIE) {
b5e89ed5
DA		 1762 DRM_ERROR
1763 ("Cannot use PCI Express without GART in FB memory\n");
ea98a92f 1764 radeon_do_cleanup_cp(dev);
20caafa6 1765 return -EINVAL;
ea98a92f
DA		 1766 }
1767 }
1768
1769 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
b5e89ed5 1770 DRM_ERROR("failed to init PCI GART!\n");
1da177e4 1771 radeon_do_cleanup_cp(dev);
20caafa6 1772 return -ENOMEM;
1da177e4
LT		 1773 }
1774
1775 /* Turn on PCI GART */
b5e89ed5 1776 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1777 }
1778
b5e89ed5
DA		 1779 radeon_cp_load_microcode(dev_priv);
1780 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4
LT		 1781
1782 dev_priv->last_buf = 0;
1783
b5e89ed5 1784 radeon_do_engine_reset(dev);
d5ea702f 1785 radeon_test_writeback(dev_priv);
1da177e4
LT		 1786
1787 return 0;
1788}
1789
84b1fd10 1790static int radeon_do_cleanup_cp(struct drm_device * dev)
1da177e4
LT		 1791{
1792 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1793 DRM_DEBUG("\n");
1da177e4
LT		 1794
1795 /* Make sure interrupts are disabled here because the uninstall ioctl
1796 * may not have been called from userspace and after dev_private
1797 * is freed, it's too late.
1798 */
b5e89ed5
DA		 1799 if (dev->irq_enabled)
1800 drm_irq_uninstall(dev);
1da177e4
LT		 1801
1802#if __OS_HAS_AGP
54a56ac5 1803 if (dev_priv->flags & RADEON_IS_AGP) {
d985c108 1804 if (dev_priv->cp_ring != NULL) {
b5e89ed5 1805 drm_core_ioremapfree(dev_priv->cp_ring, dev);
d985c108
DA		 1806 dev_priv->cp_ring = NULL;
1807 }
1808 if (dev_priv->ring_rptr != NULL) {
b5e89ed5 1809 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
d985c108
DA		 1810 dev_priv->ring_rptr = NULL;
1811 }
b5e89ed5
DA		 1812 if (dev->agp_buffer_map != NULL) {
1813 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1da177e4
LT		 1814 dev->agp_buffer_map = NULL;
1815 }
1816 } else
1817#endif
1818 {
d985c108
DA		 1819
1820 if (dev_priv->gart_info.bus_addr) {
1821 /* Turn off PCI GART */
1822 radeon_set_pcigart(dev_priv, 0);
ea98a92f
DA		 1823 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1824 DRM_ERROR("failed to cleanup PCI GART!\n");
d985c108 1825 }
b5e89ed5 1826
d985c108
DA		 1827 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1828 {
f26c473c 1829 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
f2b04cd2 1830 dev_priv->gart_info.addr = 0;
ea98a92f 1831 }
1da177e4 1832 }
1da177e4
LT		 1833 /* only clear to the start of flags */
1834 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1835
1836 return 0;
1837}
1838
b5e89ed5
DA		 1839/* This code will reinit the Radeon CP hardware after a resume from disc.
1840 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1da177e4
LT		 1841 * here we make sure that all Radeon hardware initialisation is re-done without
1842 * affecting running applications.
1843 *
1844 * Charl P. Botha <http://cpbotha.net>
1845 */
84b1fd10 1846static int radeon_do_resume_cp(struct drm_device * dev)
1da177e4
LT		 1847{
1848 drm_radeon_private_t *dev_priv = dev->dev_private;
1849
b5e89ed5
DA		 1850 if (!dev_priv) {
1851 DRM_ERROR("Called with no initialization\n");
20caafa6 1852 return -EINVAL;
1da177e4
LT		 1853 }
1854
1855 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1856
1857#if __OS_HAS_AGP
54a56ac5 1858 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1859 /* Turn off PCI GART */
b5e89ed5 1860 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1861 } else
1862#endif
1863 {
1864 /* Turn on PCI GART */
b5e89ed5 1865 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1866 }
1867
b5e89ed5
DA		 1868 radeon_cp_load_microcode(dev_priv);
1869 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4 1870
b5e89ed5 1871 radeon_do_engine_reset(dev);
1da177e4
LT		 1872
1873 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1874
1875 return 0;
1876}
1877
c153f45f 1878int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1879{
c153f45f 1880 drm_radeon_init_t *init = data;
1da177e4 1881
6c340eac 1882 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1883
c153f45f 1884 if (init->func == RADEON_INIT_R300_CP)
3d5e2c13 1885 r300_init_reg_flags(dev);
414ed537 1886
c153f45f 1887 switch (init->func) {
1da177e4
LT		 1888 case RADEON_INIT_CP:
1889 case RADEON_INIT_R200_CP:
1890 case RADEON_INIT_R300_CP:
c153f45f 1891 return radeon_do_init_cp(dev, init);
1da177e4 1892 case RADEON_CLEANUP_CP:
b5e89ed5 1893 return radeon_do_cleanup_cp(dev);
1da177e4
LT		 1894 }
1895
20caafa6 1896 return -EINVAL;
1da177e4
LT		 1897}
1898
c153f45f 1899int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1900{
1da177e4 1901 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1902 DRM_DEBUG("\n");
1da177e4 1903
6c340eac 1904 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1905
b5e89ed5 1906 if (dev_priv->cp_running) {
3e684eae 1907 DRM_DEBUG("while CP running\n");
1da177e4
LT		 1908 return 0;
1909 }
b5e89ed5 1910 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
3e684eae
MN		 1911 DRM_DEBUG("called with bogus CP mode (%d)\n",
1912 dev_priv->cp_mode);
1da177e4
LT		 1913 return 0;
1914 }
1915
b5e89ed5 1916 radeon_do_cp_start(dev_priv);
1da177e4
LT		 1917
1918 return 0;
1919}
1920
1921/* Stop the CP. The engine must have been idled before calling this
1922 * routine.
1923 */
c153f45f 1924int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1925{
1da177e4 1926 drm_radeon_private_t *dev_priv = dev->dev_private;
c153f45f 1927 drm_radeon_cp_stop_t *stop = data;
1da177e4 1928 int ret;
b5e89ed5 1929 DRM_DEBUG("\n");
1da177e4 1930
6c340eac 1931 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1932
1da177e4
LT		 1933 if (!dev_priv->cp_running)
1934 return 0;
1935
1936 /* Flush any pending CP commands. This ensures any outstanding
1937 * commands are exectuted by the engine before we turn it off.
1938 */
c153f45f 1939 if (stop->flush) {
b5e89ed5 1940 radeon_do_cp_flush(dev_priv);
1da177e4
LT		 1941 }
1942
1943 /* If we fail to make the engine go idle, we return an error
1944 * code so that the DRM ioctl wrapper can try again.
1945 */
c153f45f 1946 if (stop->idle) {
b5e89ed5
DA		 1947 ret = radeon_do_cp_idle(dev_priv);
1948 if (ret)
1949 return ret;
1da177e4
LT		 1950 }
1951
1952 /* Finally, we can turn off the CP. If the engine isn't idle,
1953 * we will get some dropped triangles as they won't be fully
1954 * rendered before the CP is shut down.
1955 */
b5e89ed5 1956 radeon_do_cp_stop(dev_priv);
1da177e4
LT		 1957
1958 /* Reset the engine */
b5e89ed5 1959 radeon_do_engine_reset(dev);
1da177e4
LT		 1960
1961 return 0;
1962}
1963
84b1fd10 1964void radeon_do_release(struct drm_device * dev)
1da177e4
LT		 1965{
1966 drm_radeon_private_t *dev_priv = dev->dev_private;
1967 int i, ret;
1968
1969 if (dev_priv) {
1970 if (dev_priv->cp_running) {
1971 /* Stop the cp */
b5e89ed5 1972 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1da177e4
LT		 1973 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1974#ifdef __linux__
1975 schedule();
1976#else
1977 tsleep(&ret, PZERO, "rdnrel", 1);
1978#endif
1979 }
b5e89ed5
DA		 1980 radeon_do_cp_stop(dev_priv);
1981 radeon_do_engine_reset(dev);
1da177e4
LT		 1982 }
1983
1984 /* Disable *all* interrupts */
1985 if (dev_priv->mmio) /* remove this after permanent addmaps */
b5e89ed5 1986 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1da177e4 1987
b5e89ed5 1988 if (dev_priv->mmio) { /* remove all surfaces */
1da177e4 1989 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
b5e89ed5
DA		 1990 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1991 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1992 16 * i, 0);
1993 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1994 16 * i, 0);
1da177e4
LT		 1995 }
1996 }
1997
1998 /* Free memory heap structures */
b5e89ed5
DA		 1999 radeon_mem_takedown(&(dev_priv->gart_heap));
2000 radeon_mem_takedown(&(dev_priv->fb_heap));
1da177e4
LT		 2001
2002 /* deallocate kernel resources */
b5e89ed5 2003 radeon_do_cleanup_cp(dev);
1da177e4
LT		 2004 }
2005}
2006
2007/* Just reset the CP ring. Called as part of an X Server engine reset.
2008 */
c153f45f 2009int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2010{
1da177e4 2011 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 2012 DRM_DEBUG("\n");
1da177e4 2013
6c340eac 2014 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2015
b5e89ed5 2016 if (!dev_priv) {
3e684eae 2017 DRM_DEBUG("called before init done\n");
20caafa6 2018 return -EINVAL;
1da177e4
LT		 2019 }
2020
b5e89ed5 2021 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 2022
2023 /* The CP is no longer running after an engine reset */
2024 dev_priv->cp_running = 0;
2025
2026 return 0;
2027}
2028
c153f45f 2029int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2030{
1da177e4 2031 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 2032 DRM_DEBUG("\n");
1da177e4 2033
6c340eac 2034 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2035
b5e89ed5 2036 return radeon_do_cp_idle(dev_priv);
1da177e4
LT		 2037}
2038
2039/* Added by Charl P. Botha to call radeon_do_resume_cp().
2040 */
c153f45f 2041int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2042{
1da177e4
LT		 2043
2044 return radeon_do_resume_cp(dev);
2045}
2046
c153f45f 2047int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2048{
b5e89ed5 2049 DRM_DEBUG("\n");
1da177e4 2050
6c340eac 2051 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2052
b5e89ed5 2053 return radeon_do_engine_reset(dev);
1da177e4
LT		 2054}
2055
1da177e4
LT		 2056/* ================================================================
2057 * Fullscreen mode
2058 */
2059
2060/* KW: Deprecated to say the least:
2061 */
c153f45f 2062int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4
LT		 2063{
2064 return 0;
2065}
2066
1da177e4
LT		 2067/* ================================================================
2068 * Freelist management
2069 */
2070
2071/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
2072 * bufs until freelist code is used. Note this hides a problem with
2073 * the scratch register * (used to keep track of last buffer
2074 * completed) being written to before * the last buffer has actually
b5e89ed5 2075 * completed rendering.
1da177e4
LT		 2076 *
2077 * KW: It's also a good way to find free buffers quickly.
2078 *
2079 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
2080 * sleep. However, bugs in older versions of radeon_accel.c mean that
2081 * we essentially have to do this, else old clients will break.
b5e89ed5 2082 *
1da177e4
LT		 2083 * However, it does leave open a potential deadlock where all the
2084 * buffers are held by other clients, which can't release them because
b5e89ed5 2085 * they can't get the lock.
1da177e4
LT		 2086 */
2087
056219e2 2088struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 2089{
cdd55a29 2090 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 2091 drm_radeon_private_t *dev_priv = dev->dev_private;
2092 drm_radeon_buf_priv_t *buf_priv;
056219e2 2093 struct drm_buf *buf;
1da177e4
LT		 2094 int i, t;
2095 int start;
2096
b5e89ed5 2097 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 2098 dev_priv->last_buf = 0;
2099
2100 start = dev_priv->last_buf;
2101
b5e89ed5
DA		 2102 for (t = 0; t < dev_priv->usec_timeout; t++) {
2103 u32 done_age = GET_SCRATCH(1);
2104 DRM_DEBUG("done_age = %d\n", done_age);
2105 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 2106 buf = dma->buflist[i];
2107 buf_priv = buf->dev_private;
6c340eac
EA		 2108 if (buf->file_priv == NULL || (buf->pending &&
2109 buf_priv->age <=
2110 done_age)) {
1da177e4
LT		 2111 dev_priv->stats.requested_bufs++;
2112 buf->pending = 0;
2113 return buf;
2114 }
2115 start = 0;
2116 }
2117
2118 if (t) {
b5e89ed5 2119 DRM_UDELAY(1);
1da177e4
LT		 2120 dev_priv->stats.freelist_loops++;
2121 }
2122 }
2123
b5e89ed5 2124 DRM_DEBUG("returning NULL!\n");
1da177e4
LT		 2125 return NULL;
2126}
b5e89ed5 2127
1da177e4 2128#if 0
056219e2 2129struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 2130{
cdd55a29 2131 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 2132 drm_radeon_private_t *dev_priv = dev->dev_private;
2133 drm_radeon_buf_priv_t *buf_priv;
056219e2 2134 struct drm_buf *buf;
1da177e4
LT		 2135 int i, t;
2136 int start;
2137 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2138
b5e89ed5 2139 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 2140 dev_priv->last_buf = 0;
2141
2142 start = dev_priv->last_buf;
2143 dev_priv->stats.freelist_loops++;
b5e89ed5
DA		 2144
2145 for (t = 0; t < 2; t++) {
2146 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 2147 buf = dma->buflist[i];
2148 buf_priv = buf->dev_private;
6c340eac
EA		 2149 if (buf->file_priv == 0 || (buf->pending &&
2150 buf_priv->age <=
2151 done_age)) {
1da177e4
LT		 2152 dev_priv->stats.requested_bufs++;
2153 buf->pending = 0;
2154 return buf;
2155 }
2156 }
2157 start = 0;
2158 }
2159
2160 return NULL;
2161}
2162#endif
2163
84b1fd10 2164void radeon_freelist_reset(struct drm_device * dev)
1da177e4 2165{
cdd55a29 2166 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 2167 drm_radeon_private_t *dev_priv = dev->dev_private;
2168 int i;
2169
2170 dev_priv->last_buf = 0;
b5e89ed5 2171 for (i = 0; i < dma->buf_count; i++) {
056219e2 2172 struct drm_buf *buf = dma->buflist[i];
1da177e4
LT		 2173 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2174 buf_priv->age = 0;
2175 }
2176}
2177
1da177e4
LT		 2178/* ================================================================
2179 * CP command submission
2180 */
2181
b5e89ed5 2182int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1da177e4
LT		 2183{
2184 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2185 int i;
b5e89ed5 2186 u32 last_head = GET_RING_HEAD(dev_priv);
1da177e4 2187
b5e89ed5
DA		 2188 for (i = 0; i < dev_priv->usec_timeout; i++) {
2189 u32 head = GET_RING_HEAD(dev_priv);
1da177e4
LT		 2190
2191 ring->space = (head - ring->tail) * sizeof(u32);
b5e89ed5 2192 if (ring->space <= 0)
1da177e4 2193 ring->space += ring->size;
b5e89ed5 2194 if (ring->space > n)
1da177e4 2195 return 0;
b5e89ed5 2196
1da177e4
LT		 2197 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2198
2199 if (head != last_head)
2200 i = 0;
2201 last_head = head;
2202
b5e89ed5 2203 DRM_UDELAY(1);
1da177e4
LT		 2204 }
2205
2206 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2207#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 2208 radeon_status(dev_priv);
2209 DRM_ERROR("failed!\n");
1da177e4 2210#endif
20caafa6 2211 return -EBUSY;
1da177e4
LT		 2212}
2213
6c340eac
EA		 2214static int radeon_cp_get_buffers(struct drm_device *dev,
2215 struct drm_file *file_priv,
c60ce623 2216 struct drm_dma * d)
1da177e4
LT		 2217{
2218 int i;
056219e2 2219 struct drm_buf *buf;
1da177e4 2220
b5e89ed5
DA		 2221 for (i = d->granted_count; i < d->request_count; i++) {
2222 buf = radeon_freelist_get(dev);
2223 if (!buf)
20caafa6 2224 return -EBUSY; /* NOTE: broken client */
1da177e4 2225
6c340eac 2226 buf->file_priv = file_priv;
1da177e4 2227
b5e89ed5
DA		 2228 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2229 sizeof(buf->idx)))
20caafa6 2230 return -EFAULT;
b5e89ed5
DA		 2231 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2232 sizeof(buf->total)))
20caafa6 2233 return -EFAULT;
1da177e4
LT		 2234
2235 d->granted_count++;
2236 }
2237 return 0;
2238}
2239
c153f45f 2240int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2241{
cdd55a29 2242 struct drm_device_dma *dma = dev->dma;
1da177e4 2243 int ret = 0;
c153f45f 2244 struct drm_dma *d = data;
1da177e4 2245
6c340eac 2246 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2247
1da177e4
LT		 2248 /* Please don't send us buffers.
2249 */
c153f45f 2250 if (d->send_count != 0) {
b5e89ed5 2251 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
c153f45f 2252 DRM_CURRENTPID, d->send_count);
20caafa6 2253 return -EINVAL;
1da177e4
LT		 2254 }
2255
2256 /* We'll send you buffers.
2257 */
c153f45f 2258 if (d->request_count < 0 || d->request_count > dma->buf_count) {
b5e89ed5 2259 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
c153f45f 2260 DRM_CURRENTPID, d->request_count, dma->buf_count);
20caafa6 2261 return -EINVAL;
1da177e4
LT		 2262 }
2263
c153f45f 2264 d->granted_count = 0;
1da177e4 2265
c153f45f
EA		 2266 if (d->request_count) {
2267 ret = radeon_cp_get_buffers(dev, file_priv, d);
1da177e4
LT		 2268 }
2269
1da177e4
LT		 2270 return ret;
2271}
2272
22eae947 2273int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1da177e4
LT		 2274{
2275 drm_radeon_private_t *dev_priv;
2276 int ret = 0;
2277
2278 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2279 if (dev_priv == NULL)
20caafa6 2280 return -ENOMEM;
1da177e4
LT		 2281
2282 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2283 dev->dev_private = (void *)dev_priv;
2284 dev_priv->flags = flags;
2285
54a56ac5 2286 switch (flags & RADEON_FAMILY_MASK) {
1da177e4
LT		 2287 case CHIP_R100:
2288 case CHIP_RV200:
2289 case CHIP_R200:
2290 case CHIP_R300:
b15ec368 2291 case CHIP_R350:
414ed537 2292 case CHIP_R420:
b15ec368 2293 case CHIP_RV410:
3d5e2c13
DA		 2294 case CHIP_RV515:
2295 case CHIP_R520:
2296 case CHIP_RV570:
2297 case CHIP_R580:
54a56ac5 2298 dev_priv->flags |= RADEON_HAS_HIERZ;
1da177e4
LT		 2299 break;
2300 default:
b5e89ed5 2301 /* all other chips have no hierarchical z buffer */
1da177e4
LT		 2302 break;
2303 }
414ed537
DA		 2304
2305 if (drm_device_is_agp(dev))
54a56ac5 2306 dev_priv->flags |= RADEON_IS_AGP;
b15ec368 2307 else if (drm_device_is_pcie(dev))
54a56ac5 2308 dev_priv->flags |= RADEON_IS_PCIE;
b15ec368 2309 else
54a56ac5 2310 dev_priv->flags |= RADEON_IS_PCI;
ea98a92f 2311
414ed537 2312 DRM_DEBUG("%s card detected\n",
54a56ac5 2313 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1da177e4
LT		 2314 return ret;
2315}
2316
22eae947
DA		 2317/* Create mappings for registers and framebuffer so userland doesn't necessarily
2318 * have to find them.
2319 */
2320int radeon_driver_firstopen(struct drm_device *dev)
836cf046
DA		 2321{
2322 int ret;
2323 drm_local_map_t *map;
2324 drm_radeon_private_t *dev_priv = dev->dev_private;
2325
f2b04cd2
DA		 2326 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2327
836cf046
DA		 2328 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2329 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2330 _DRM_READ_ONLY, &dev_priv->mmio);
2331 if (ret != 0)
2332 return ret;
2333
7fc86860
DA		 2334 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2335 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
836cf046
DA		 2336 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2337 _DRM_WRITE_COMBINING, &map);
2338 if (ret != 0)
2339 return ret;
2340
2341 return 0;
2342}
2343
22eae947 2344int radeon_driver_unload(struct drm_device *dev)
1da177e4
LT		 2345{
2346 drm_radeon_private_t *dev_priv = dev->dev_private;
2347
2348 DRM_DEBUG("\n");
1da177e4
LT		 2349 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2350
2351 dev->dev_private = NULL;
2352 return 0;
2353}
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