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1da177e4 LT |
1 | /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- |
2 | * | |
3 | * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. | |
b5e89ed5 | 4 | * |
1da177e4 LT |
5 | * The Weather Channel (TM) funded Tungsten Graphics to develop the |
6 | * initial release of the Radeon 8500 driver under the XFree86 license. | |
7 | * This notice must be preserved. | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a | |
10 | * copy of this software and associated documentation files (the "Software"), | |
11 | * to deal in the Software without restriction, including without limitation | |
12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
13 | * and/or sell copies of the Software, and to permit persons to whom the | |
14 | * Software is furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the next | |
17 | * paragraph) shall be included in all copies or substantial portions of the | |
18 | * Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
26 | * DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | * Michel D�zer <michel@daenzer.net> | |
31 | */ | |
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "radeon_drm.h" | |
36 | #include "radeon_drv.h" | |
37 | ||
b5e89ed5 DA |
38 | static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, |
39 | u32 mask) | |
6921e331 DA |
40 | { |
41 | u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask; | |
42 | if (irqs) | |
43 | RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs); | |
44 | return irqs; | |
45 | } | |
46 | ||
1da177e4 LT |
47 | /* Interrupts - Used for device synchronization and flushing in the |
48 | * following circumstances: | |
49 | * | |
50 | * - Exclusive FB access with hw idle: | |
51 | * - Wait for GUI Idle (?) interrupt, then do normal flush. | |
52 | * | |
53 | * - Frame throttling, NV_fence: | |
54 | * - Drop marker irq's into command stream ahead of time. | |
55 | * - Wait on irq's with lock *not held* | |
56 | * - Check each for termination condition | |
57 | * | |
58 | * - Internally in cp_getbuffer, etc: | |
59 | * - as above, but wait with lock held??? | |
60 | * | |
61 | * NOTE: These functions are misleadingly named -- the irq's aren't | |
62 | * tied to dma at all, this is just a hangover from dri prehistory. | |
63 | */ | |
64 | ||
b5e89ed5 | 65 | irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) |
1da177e4 LT |
66 | { |
67 | drm_device_t *dev = (drm_device_t *) arg; | |
b5e89ed5 DA |
68 | drm_radeon_private_t *dev_priv = |
69 | (drm_radeon_private_t *) dev->dev_private; | |
70 | u32 stat; | |
1da177e4 LT |
71 | |
72 | /* Only consider the bits we're interested in - others could be used | |
73 | * outside the DRM | |
74 | */ | |
b5e89ed5 | 75 | stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | |
6921e331 | 76 | RADEON_CRTC_VBLANK_STAT)); |
1da177e4 LT |
77 | if (!stat) |
78 | return IRQ_NONE; | |
79 | ||
80 | /* SW interrupt */ | |
81 | if (stat & RADEON_SW_INT_TEST) { | |
b5e89ed5 | 82 | DRM_WAKEUP(&dev_priv->swi_queue); |
1da177e4 LT |
83 | } |
84 | ||
85 | /* VBLANK interrupt */ | |
86 | if (stat & RADEON_CRTC_VBLANK_STAT) { | |
87 | atomic_inc(&dev->vbl_received); | |
88 | DRM_WAKEUP(&dev->vbl_queue); | |
b5e89ed5 | 89 | drm_vbl_send_signals(dev); |
1da177e4 LT |
90 | } |
91 | ||
1da177e4 LT |
92 | return IRQ_HANDLED; |
93 | } | |
94 | ||
b5e89ed5 | 95 | static int radeon_emit_irq(drm_device_t * dev) |
1da177e4 LT |
96 | { |
97 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
98 | unsigned int ret; | |
99 | RING_LOCALS; | |
100 | ||
101 | atomic_inc(&dev_priv->swi_emitted); | |
102 | ret = atomic_read(&dev_priv->swi_emitted); | |
103 | ||
b5e89ed5 DA |
104 | BEGIN_RING(4); |
105 | OUT_RING_REG(RADEON_LAST_SWI_REG, ret); | |
106 | OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE); | |
107 | ADVANCE_RING(); | |
108 | COMMIT_RING(); | |
1da177e4 LT |
109 | |
110 | return ret; | |
111 | } | |
112 | ||
b5e89ed5 | 113 | static int radeon_wait_irq(drm_device_t * dev, int swi_nr) |
1da177e4 | 114 | { |
b5e89ed5 DA |
115 | drm_radeon_private_t *dev_priv = |
116 | (drm_radeon_private_t *) dev->dev_private; | |
1da177e4 LT |
117 | int ret = 0; |
118 | ||
b5e89ed5 DA |
119 | if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr) |
120 | return 0; | |
1da177e4 LT |
121 | |
122 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
123 | ||
b5e89ed5 DA |
124 | DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ, |
125 | RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr); | |
1da177e4 LT |
126 | |
127 | return ret; | |
128 | } | |
129 | ||
b5e89ed5 | 130 | int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) |
1da177e4 | 131 | { |
b5e89ed5 DA |
132 | drm_radeon_private_t *dev_priv = |
133 | (drm_radeon_private_t *) dev->dev_private; | |
1da177e4 LT |
134 | unsigned int cur_vblank; |
135 | int ret = 0; | |
136 | ||
b5e89ed5 DA |
137 | if (!dev_priv) { |
138 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
1da177e4 LT |
139 | return DRM_ERR(EINVAL); |
140 | } | |
141 | ||
6921e331 | 142 | radeon_acknowledge_irqs(dev_priv, RADEON_CRTC_VBLANK_STAT); |
1da177e4 LT |
143 | |
144 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
145 | ||
146 | /* Assume that the user has missed the current sequence number | |
147 | * by about a day rather than she wants to wait for years | |
b5e89ed5 | 148 | * using vertical blanks... |
1da177e4 | 149 | */ |
b5e89ed5 DA |
150 | DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, |
151 | (((cur_vblank = atomic_read(&dev->vbl_received)) | |
152 | - *sequence) <= (1 << 23))); | |
1da177e4 LT |
153 | |
154 | *sequence = cur_vblank; | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
1da177e4 LT |
159 | /* Needs the lock as it touches the ring. |
160 | */ | |
b5e89ed5 | 161 | int radeon_irq_emit(DRM_IOCTL_ARGS) |
1da177e4 LT |
162 | { |
163 | DRM_DEVICE; | |
164 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
165 | drm_radeon_irq_emit_t emit; | |
166 | int result; | |
167 | ||
b5e89ed5 | 168 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 169 | |
b5e89ed5 DA |
170 | if (!dev_priv) { |
171 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
1da177e4 LT |
172 | return DRM_ERR(EINVAL); |
173 | } | |
174 | ||
b5e89ed5 DA |
175 | DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data, |
176 | sizeof(emit)); | |
1da177e4 | 177 | |
b5e89ed5 | 178 | result = radeon_emit_irq(dev); |
1da177e4 | 179 | |
b5e89ed5 DA |
180 | if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { |
181 | DRM_ERROR("copy_to_user\n"); | |
1da177e4 LT |
182 | return DRM_ERR(EFAULT); |
183 | } | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
1da177e4 LT |
188 | /* Doesn't need the hardware lock. |
189 | */ | |
b5e89ed5 | 190 | int radeon_irq_wait(DRM_IOCTL_ARGS) |
1da177e4 LT |
191 | { |
192 | DRM_DEVICE; | |
193 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
194 | drm_radeon_irq_wait_t irqwait; | |
195 | ||
b5e89ed5 DA |
196 | if (!dev_priv) { |
197 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
1da177e4 LT |
198 | return DRM_ERR(EINVAL); |
199 | } | |
200 | ||
b5e89ed5 DA |
201 | DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data, |
202 | sizeof(irqwait)); | |
1da177e4 | 203 | |
b5e89ed5 | 204 | return radeon_wait_irq(dev, irqwait.irq_seq); |
1da177e4 LT |
205 | } |
206 | ||
1da177e4 LT |
207 | /* drm_dma.h hooks |
208 | */ | |
b5e89ed5 DA |
209 | void radeon_driver_irq_preinstall(drm_device_t * dev) |
210 | { | |
1da177e4 | 211 | drm_radeon_private_t *dev_priv = |
b5e89ed5 | 212 | (drm_radeon_private_t *) dev->dev_private; |
1da177e4 | 213 | |
b5e89ed5 DA |
214 | /* Disable *all* interrupts */ |
215 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); | |
1da177e4 LT |
216 | |
217 | /* Clear bits if they're already high */ | |
6921e331 DA |
218 | radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | |
219 | RADEON_CRTC_VBLANK_STAT)); | |
1da177e4 LT |
220 | } |
221 | ||
b5e89ed5 DA |
222 | void radeon_driver_irq_postinstall(drm_device_t * dev) |
223 | { | |
1da177e4 | 224 | drm_radeon_private_t *dev_priv = |
b5e89ed5 | 225 | (drm_radeon_private_t *) dev->dev_private; |
1da177e4 | 226 | |
b5e89ed5 DA |
227 | atomic_set(&dev_priv->swi_emitted, 0); |
228 | DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); | |
1da177e4 LT |
229 | |
230 | /* Turn on SW and VBL ints */ | |
b5e89ed5 DA |
231 | RADEON_WRITE(RADEON_GEN_INT_CNTL, |
232 | RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE); | |
1da177e4 LT |
233 | } |
234 | ||
b5e89ed5 DA |
235 | void radeon_driver_irq_uninstall(drm_device_t * dev) |
236 | { | |
1da177e4 | 237 | drm_radeon_private_t *dev_priv = |
b5e89ed5 | 238 | (drm_radeon_private_t *) dev->dev_private; |
1da177e4 LT |
239 | if (!dev_priv) |
240 | return; | |
241 | ||
242 | /* Disable *all* interrupts */ | |
b5e89ed5 | 243 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
1da177e4 | 244 | } |