[mirror_ubuntu-artful-kernel.git] / drivers / char / drm / radeon_irq.c

/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
 *
 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
 * 
 * The Weather Channel (TM) funded Tungsten Graphics to develop the
 * initial release of the Radeon 8500 driver under the XFree86 license.
 * This notice must be preserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Whitwell <keith@tungstengraphics.com>
 *    Michel D�zer <michel@daenzer.net>
 */

#include "drmP.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"

/* Interrupts - Used for device synchronization and flushing in the
 * following circumstances:
 *
 * - Exclusive FB access with hw idle:
 *    - Wait for GUI Idle (?) interrupt, then do normal flush.
 *
 * - Frame throttling, NV_fence:
 *    - Drop marker irq's into command stream ahead of time.
 *    - Wait on irq's with lock *not held*
 *    - Check each for termination condition
 *
 * - Internally in cp_getbuffer, etc:
 *    - as above, but wait with lock held???
 *
 * NOTE: These functions are misleadingly named -- the irq's aren't
 * tied to dma at all, this is just a hangover from dri prehistory.
 */

irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS )
{
	drm_device_t *dev = (drm_device_t *) arg;
	drm_radeon_private_t *dev_priv = 
	   (drm_radeon_private_t *)dev->dev_private;
   	u32 stat;

	/* Only consider the bits we're interested in - others could be used
	 * outside the DRM
	 */
	stat = RADEON_READ(RADEON_GEN_INT_STATUS)
	     & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
	if (!stat)
		return IRQ_NONE;

	/* SW interrupt */
	if (stat & RADEON_SW_INT_TEST) {
		DRM_WAKEUP( &dev_priv->swi_queue );
	}

	/* VBLANK interrupt */
	if (stat & RADEON_CRTC_VBLANK_STAT) {
		atomic_inc(&dev->vbl_received);
		DRM_WAKEUP(&dev->vbl_queue);
		drm_vbl_send_signals( dev );
	}

	/* Acknowledge interrupts we handle */
	RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
	return IRQ_HANDLED;
}

static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
{
	u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
		& (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
	if (tmp)
		RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
}

static int radeon_emit_irq(drm_device_t *dev)
{
	drm_radeon_private_t *dev_priv = dev->dev_private;
	unsigned int ret;
	RING_LOCALS;

	atomic_inc(&dev_priv->swi_emitted);
	ret = atomic_read(&dev_priv->swi_emitted);

	BEGIN_RING( 4 );
	OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
	OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
	ADVANCE_RING(); 
 	COMMIT_RING();

	return ret;
}


static int radeon_wait_irq(drm_device_t *dev, int swi_nr)
{
  	drm_radeon_private_t *dev_priv = 
	   (drm_radeon_private_t *)dev->dev_private;
	int ret = 0;

 	if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)  
 		return 0; 

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ, 
		     RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );

	return ret;
}

int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
{
  	drm_radeon_private_t *dev_priv = 
	   (drm_radeon_private_t *)dev->dev_private;
	unsigned int cur_vblank;
	int ret = 0;

	if ( !dev_priv ) {
		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
		return DRM_ERR(EINVAL);
	}

	radeon_acknowledge_irqs( dev_priv );

	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

	/* Assume that the user has missed the current sequence number
	 * by about a day rather than she wants to wait for years
	 * using vertical blanks... 
	 */
	DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, 
		     ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
			 - *sequence ) <= (1<<23) ) );

	*sequence = cur_vblank;

	return ret;
}


/* Needs the lock as it touches the ring.
 */
int radeon_irq_emit( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_irq_emit_t emit;
	int result;

	LOCK_TEST_WITH_RETURN( dev, filp );

	if ( !dev_priv ) {
		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
		return DRM_ERR(EINVAL);
	}

	DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data,
				  sizeof(emit) );

	result = radeon_emit_irq( dev );

	if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
		DRM_ERROR( "copy_to_user\n" );
		return DRM_ERR(EFAULT);
	}

	return 0;
}


/* Doesn't need the hardware lock.
 */
int radeon_irq_wait( DRM_IOCTL_ARGS )
{
	DRM_DEVICE;
	drm_radeon_private_t *dev_priv = dev->dev_private;
	drm_radeon_irq_wait_t irqwait;

	if ( !dev_priv ) {
		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
		return DRM_ERR(EINVAL);
	}

	DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data,
				  sizeof(irqwait) );

	return radeon_wait_irq( dev, irqwait.irq_seq );
}


/* drm_dma.h hooks
*/
void radeon_driver_irq_preinstall( drm_device_t *dev ) {
	drm_radeon_private_t *dev_priv =
		(drm_radeon_private_t *)dev->dev_private;

 	/* Disable *all* interrupts */
      	RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );

	/* Clear bits if they're already high */
	radeon_acknowledge_irqs( dev_priv );
}

void radeon_driver_irq_postinstall( drm_device_t *dev ) {
	drm_radeon_private_t *dev_priv =
		(drm_radeon_private_t *)dev->dev_private;

   	atomic_set(&dev_priv->swi_emitted, 0);
	DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );

	/* Turn on SW and VBL ints */
   	RADEON_WRITE( RADEON_GEN_INT_CNTL,
		      RADEON_CRTC_VBLANK_MASK |	
		      RADEON_SW_INT_ENABLE );
}

void radeon_driver_irq_uninstall( drm_device_t *dev ) {
	drm_radeon_private_t *dev_priv =
		(drm_radeon_private_t *)dev->dev_private;
	if (!dev_priv)
		return;

	/* Disable *all* interrupts */
	RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
}
Commit	Line	Data
1da177e4 LT	1	/* radeon_irq.c -- IRQ handling for radeon -- linux-c --
	2	*
	3	* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
	4	*
	5	* The Weather Channel (TM) funded Tungsten Graphics to develop the
	6	* initial release of the Radeon 8500 driver under the XFree86 license.
	7	* This notice must be preserved.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a
	10	* copy of this software and associated documentation files (the "Software"),
	11	* to deal in the Software without restriction, including without limitation
	12	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	13	* and/or sell copies of the Software, and to permit persons to whom the
	14	* Software is furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the next
	17	* paragraph) shall be included in all copies or substantial portions of the
	18	* Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	21	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	23	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	24	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	25	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	26	* DEALINGS IN THE SOFTWARE.
	27	*
	28	* Authors:
	29	* Keith Whitwell <keith@tungstengraphics.com>
	30	* Michel D�zer <michel@daenzer.net>
	31	*/
	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "radeon_drm.h"
	36	#include "radeon_drv.h"
	37
	38	/* Interrupts - Used for device synchronization and flushing in the
	39	* following circumstances:
	40	*
	41	* - Exclusive FB access with hw idle:
	42	* - Wait for GUI Idle (?) interrupt, then do normal flush.
	43	*
	44	* - Frame throttling, NV_fence:
	45	* - Drop marker irq's into command stream ahead of time.
	46	* - Wait on irq's with lock not held
	47	* - Check each for termination condition
	48	*
	49	* - Internally in cp_getbuffer, etc:
	50	* - as above, but wait with lock held???
	51	*
	52	* NOTE: These functions are misleadingly named -- the irq's aren't
	53	* tied to dma at all, this is just a hangover from dri prehistory.
	54	*/
	55
	56	irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS )
	57	{
	58	drm_device_t dev = (drm_device_t ) arg;
	59	drm_radeon_private_t *dev_priv =
	60	(drm_radeon_private_t *)dev->dev_private;
	61	u32 stat;
	62
	63	/* Only consider the bits we're interested in - others could be used
	64	* outside the DRM
65	*/
66	stat = RADEON_READ(RADEON_GEN_INT_STATUS)
67	& (RADEON_SW_INT_TEST \| RADEON_CRTC_VBLANK_STAT);
68	if (!stat)
69	return IRQ_NONE;
70
71	/* SW interrupt */
72	if (stat & RADEON_SW_INT_TEST) {
73	DRM_WAKEUP( &dev_priv->swi_queue );
74	}
75
76	/* VBLANK interrupt */
77	if (stat & RADEON_CRTC_VBLANK_STAT) {
78	atomic_inc(&dev->vbl_received);
79	DRM_WAKEUP(&dev->vbl_queue);
80	drm_vbl_send_signals( dev );
81	}
82
83	/* Acknowledge interrupts we handle */
84	RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
85	return IRQ_HANDLED;
86	}
87
88	static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
89	{
90	u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
91	& (RADEON_SW_INT_TEST_ACK \| RADEON_CRTC_VBLANK_STAT);
92	if (tmp)
93	RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
94	}
95
96	static int radeon_emit_irq(drm_device_t *dev)
97	{
98	drm_radeon_private_t *dev_priv = dev->dev_private;
99	unsigned int ret;
100	RING_LOCALS;
101
102	atomic_inc(&dev_priv->swi_emitted);
103	ret = atomic_read(&dev_priv->swi_emitted);
104
105	BEGIN_RING( 4 );
106	OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
107	OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
108	ADVANCE_RING();
109	COMMIT_RING();
110
111	return ret;
112	}
113
114
115	static int radeon_wait_irq(drm_device_t *dev, int swi_nr)
116	{
117	drm_radeon_private_t *dev_priv =
118	(drm_radeon_private_t *)dev->dev_private;
119	int ret = 0;
120
121	if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)
122	return 0;
123
124	dev_priv->stats.boxes \|= RADEON_BOX_WAIT_IDLE;
125
1da177e4 LT	126	DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ,
	127	RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );
	128
	129	return ret;
	130	}
	131
	132	int radeon_driver_vblank_wait(drm_device_t dev, unsigned int sequence)
	133	{
	134	drm_radeon_private_t *dev_priv =
	135	(drm_radeon_private_t *)dev->dev_private;
	136	unsigned int cur_vblank;
	137	int ret = 0;
	138
	139	if ( !dev_priv ) {
	140	DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
	141	return DRM_ERR(EINVAL);
	142	}
	143
	144	radeon_acknowledge_irqs( dev_priv );
	145
	146	dev_priv->stats.boxes \|= RADEON_BOX_WAIT_IDLE;
	147
	148	/* Assume that the user has missed the current sequence number
	149	* by about a day rather than she wants to wait for years
	150	* using vertical blanks...
	151	*/
	152	DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
	153	( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
	154	- *sequence ) <= (1<<23) ) );
	155
	156	*sequence = cur_vblank;
	157
	158	return ret;
	159	}
	160
	161
	162	/* Needs the lock as it touches the ring.
	163	*/
	164	int radeon_irq_emit( DRM_IOCTL_ARGS )
	165	{
	166	DRM_DEVICE;
	167	drm_radeon_private_t *dev_priv = dev->dev_private;
	168	drm_radeon_irq_emit_t emit;
	169	int result;
	170
	171	LOCK_TEST_WITH_RETURN( dev, filp );
	172
	173	if ( !dev_priv ) {
	174	DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
	175	return DRM_ERR(EINVAL);
	176	}
	177
	178	DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data,
	179	sizeof(emit) );
	180
	181	result = radeon_emit_irq( dev );
	182
	183	if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
	184	DRM_ERROR( "copy_to_user\n" );
	185	return DRM_ERR(EFAULT);
	186	}
	187
	188	return 0;
	189	}
190
191
192	/* Doesn't need the hardware lock.
193	*/
194	int radeon_irq_wait( DRM_IOCTL_ARGS )
195	{
196	DRM_DEVICE;
197	drm_radeon_private_t *dev_priv = dev->dev_private;
198	drm_radeon_irq_wait_t irqwait;
199
200	if ( !dev_priv ) {
201	DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
202	return DRM_ERR(EINVAL);
203	}
204
205	DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data,
206	sizeof(irqwait) );
207
208	return radeon_wait_irq( dev, irqwait.irq_seq );
209	}
210
211
212	/* drm_dma.h hooks
213	*/
214	void radeon_driver_irq_preinstall( drm_device_t *dev ) {
215	drm_radeon_private_t *dev_priv =
216	(drm_radeon_private_t *)dev->dev_private;
217
218	/* Disable all interrupts */
219	RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
220
221	/* Clear bits if they're already high */
222	radeon_acknowledge_irqs( dev_priv );
223	}
224
225	void radeon_driver_irq_postinstall( drm_device_t *dev ) {
226	drm_radeon_private_t *dev_priv =
227	(drm_radeon_private_t *)dev->dev_private;
228
229	atomic_set(&dev_priv->swi_emitted, 0);
230	DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );
231
232	/* Turn on SW and VBL ints */
233	RADEON_WRITE( RADEON_GEN_INT_CNTL,
234	RADEON_CRTC_VBLANK_MASK \|
235	RADEON_SW_INT_ENABLE );
236	}
237
238	void radeon_driver_irq_uninstall( drm_device_t *dev ) {
239	drm_radeon_private_t *dev_priv =
240	(drm_radeon_private_t *)dev->dev_private;
241	if (!dev_priv)
242	return;
243
244	/* Disable all interrupts */
245	RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
246	}