]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/char/hpet.c
w1-gpio: Simplify & get rid of defines
[mirror_ubuntu-artful-kernel.git] / drivers / char / hpet.c
CommitLineData
1da177e4
LT
1/*
2 * Intel & MS High Precision Event Timer Implementation.
3 *
4 * Copyright (C) 2003 Intel Corporation
5 * Venki Pallipadi
6 * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
7 * Bob Picco <robert.picco@hp.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
1da177e4
LT
14#include <linux/interrupt.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/miscdevice.h>
19#include <linux/major.h>
20#include <linux/ioport.h>
21#include <linux/fcntl.h>
22#include <linux/init.h>
23#include <linux/poll.h>
f23f6e08 24#include <linux/mm.h>
1da177e4
LT
25#include <linux/proc_fs.h>
26#include <linux/spinlock.h>
27#include <linux/sysctl.h>
28#include <linux/wait.h>
29#include <linux/bcd.h>
30#include <linux/seq_file.h>
31#include <linux/bitops.h>
54066a57 32#include <linux/compat.h>
0aa366f3 33#include <linux/clocksource.h>
0ca01763 34#include <linux/uaccess.h>
5a0e3ad6 35#include <linux/slab.h>
0ca01763 36#include <linux/io.h>
1da177e4
LT
37
38#include <asm/current.h>
1da177e4
LT
39#include <asm/irq.h>
40#include <asm/div64.h>
41
42#include <linux/acpi.h>
43#include <acpi/acpi_bus.h>
44#include <linux/hpet.h>
45
46/*
47 * The High Precision Event Timer driver.
48 * This driver is closely modelled after the rtc.c driver.
e45f2c07 49 * http://www.intel.com/hardwaredesign/hpetspec_1.pdf
1da177e4
LT
50 */
51#define HPET_USER_FREQ (64)
52#define HPET_DRIFT (500)
53
757c4724
RD
54#define HPET_RANGE_SIZE 1024 /* from HPET spec */
55
64a76f66
DB
56
57/* WARNING -- don't get confused. These macros are never used
58 * to write the (single) counter, and rarely to read it.
59 * They're badly named; to fix, someday.
60 */
0aa366f3
TL
61#if BITS_PER_LONG == 64
62#define write_counter(V, MC) writeq(V, MC)
63#define read_counter(MC) readq(MC)
64#else
65#define write_counter(V, MC) writel(V, MC)
66#define read_counter(MC) readl(MC)
67#endif
68
54066a57 69static DEFINE_MUTEX(hpet_mutex); /* replaces BKL */
642d30bb 70static u32 hpet_nhpet, hpet_max_freq = HPET_USER_FREQ;
1da177e4 71
3dffec45
ÇO
72/* This clocksource driver currently only works on ia64 */
73#ifdef CONFIG_IA64
0aa366f3
TL
74static void __iomem *hpet_mctr;
75
8e19608e 76static cycle_t read_hpet(struct clocksource *cs)
0aa366f3
TL
77{
78 return (cycle_t)read_counter((void __iomem *)hpet_mctr);
79}
80
81static struct clocksource clocksource_hpet = {
0ca01763
JSR
82 .name = "hpet",
83 .rating = 250,
84 .read = read_hpet,
85 .mask = CLOCKSOURCE_MASK(64),
0ca01763 86 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
0aa366f3
TL
87};
88static struct clocksource *hpet_clocksource;
3dffec45 89#endif
0aa366f3 90
1da177e4
LT
91/* A lock for concurrent access by app and isr hpet activity. */
92static DEFINE_SPINLOCK(hpet_lock);
1da177e4
LT
93
94#define HPET_DEV_NAME (7)
95
96struct hpet_dev {
97 struct hpets *hd_hpets;
98 struct hpet __iomem *hd_hpet;
99 struct hpet_timer __iomem *hd_timer;
100 unsigned long hd_ireqfreq;
101 unsigned long hd_irqdata;
102 wait_queue_head_t hd_waitqueue;
103 struct fasync_struct *hd_async_queue;
1da177e4
LT
104 unsigned int hd_flags;
105 unsigned int hd_irq;
106 unsigned int hd_hdwirq;
107 char hd_name[HPET_DEV_NAME];
108};
109
110struct hpets {
111 struct hpets *hp_next;
112 struct hpet __iomem *hp_hpet;
113 unsigned long hp_hpet_phys;
0aa366f3 114 struct clocksource *hp_clocksource;
ba3f213f 115 unsigned long long hp_tick_freq;
1da177e4
LT
116 unsigned long hp_delta;
117 unsigned int hp_ntimer;
118 unsigned int hp_which;
119 struct hpet_dev hp_dev[1];
120};
121
122static struct hpets *hpets;
123
124#define HPET_OPEN 0x0001
125#define HPET_IE 0x0002 /* interrupt enabled */
126#define HPET_PERIODIC 0x0004
0d290861 127#define HPET_SHARED_IRQ 0x0008
1da177e4 128
1da177e4
LT
129
130#ifndef readq
887c27f3 131static inline unsigned long long readq(void __iomem *addr)
1da177e4
LT
132{
133 return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL);
134}
135#endif
136
137#ifndef writeq
887c27f3 138static inline void writeq(unsigned long long v, void __iomem *addr)
1da177e4
LT
139{
140 writel(v & 0xffffffff, addr);
141 writel(v >> 32, addr + 4);
142}
143#endif
144
7d12e780 145static irqreturn_t hpet_interrupt(int irq, void *data)
1da177e4
LT
146{
147 struct hpet_dev *devp;
148 unsigned long isr;
149
150 devp = data;
0d290861
CL
151 isr = 1 << (devp - devp->hd_hpets->hp_dev);
152
153 if ((devp->hd_flags & HPET_SHARED_IRQ) &&
154 !(isr & readl(&devp->hd_hpet->hpet_isr)))
155 return IRQ_NONE;
1da177e4
LT
156
157 spin_lock(&hpet_lock);
158 devp->hd_irqdata++;
159
160 /*
161 * For non-periodic timers, increment the accumulator.
162 * This has the effect of treating non-periodic like periodic.
163 */
164 if ((devp->hd_flags & (HPET_IE | HPET_PERIODIC)) == HPET_IE) {
273ef950
NC
165 unsigned long m, t, mc, base, k;
166 struct hpet __iomem *hpet = devp->hd_hpet;
167 struct hpets *hpetp = devp->hd_hpets;
1da177e4
LT
168
169 t = devp->hd_ireqfreq;
ae21cf92 170 m = read_counter(&devp->hd_timer->hpet_compare);
273ef950
NC
171 mc = read_counter(&hpet->hpet_mc);
172 /* The time for the next interrupt would logically be t + m,
173 * however, if we are very unlucky and the interrupt is delayed
174 * for longer than t then we will completely miss the next
175 * interrupt if we set t + m and an application will hang.
176 * Therefore we need to make a more complex computation assuming
177 * that there exists a k for which the following is true:
178 * k * t + base < mc + delta
179 * (k + 1) * t + base > mc + delta
180 * where t is the interval in hpet ticks for the given freq,
181 * base is the theoretical start value 0 < base < t,
182 * mc is the main counter value at the time of the interrupt,
183 * delta is the time it takes to write the a value to the
184 * comparator.
185 * k may then be computed as (mc - base + delta) / t .
186 */
187 base = mc % t;
188 k = (mc - base + hpetp->hp_delta) / t;
189 write_counter(t * (k + 1) + base,
190 &devp->hd_timer->hpet_compare);
1da177e4
LT
191 }
192
0d290861
CL
193 if (devp->hd_flags & HPET_SHARED_IRQ)
194 writel(isr, &devp->hd_hpet->hpet_isr);
1da177e4
LT
195 spin_unlock(&hpet_lock);
196
1da177e4
LT
197 wake_up_interruptible(&devp->hd_waitqueue);
198
199 kill_fasync(&devp->hd_async_queue, SIGIO, POLL_IN);
200
201 return IRQ_HANDLED;
202}
203
70ef6d59
KH
204static void hpet_timer_set_irq(struct hpet_dev *devp)
205{
206 unsigned long v;
207 int irq, gsi;
208 struct hpet_timer __iomem *timer;
209
210 spin_lock_irq(&hpet_lock);
211 if (devp->hd_hdwirq) {
212 spin_unlock_irq(&hpet_lock);
213 return;
214 }
215
216 timer = devp->hd_timer;
217
218 /* we prefer level triggered mode */
219 v = readl(&timer->hpet_config);
220 if (!(v & Tn_INT_TYPE_CNF_MASK)) {
221 v |= Tn_INT_TYPE_CNF_MASK;
222 writel(v, &timer->hpet_config);
223 }
224 spin_unlock_irq(&hpet_lock);
225
226 v = (readq(&timer->hpet_config) & Tn_INT_ROUTE_CAP_MASK) >>
227 Tn_INT_ROUTE_CAP_SHIFT;
228
229 /*
230 * In PIC mode, skip IRQ0-4, IRQ6-9, IRQ12-15 which is always used by
231 * legacy device. In IO APIC mode, we skip all the legacy IRQS.
232 */
233 if (acpi_irq_model == ACPI_IRQ_MODEL_PIC)
234 v &= ~0xf3df;
235 else
236 v &= ~0xffff;
237
e5d61511 238 for_each_set_bit(irq, &v, HPET_MAX_IRQ) {
1f45f562 239 if (irq >= nr_irqs) {
70ef6d59
KH
240 irq = HPET_MAX_IRQ;
241 break;
242 }
243
a2f809b0 244 gsi = acpi_register_gsi(NULL, irq, ACPI_LEVEL_SENSITIVE,
70ef6d59
KH
245 ACPI_ACTIVE_LOW);
246 if (gsi > 0)
247 break;
248
249 /* FIXME: Setup interrupt source table */
250 }
251
252 if (irq < HPET_MAX_IRQ) {
253 spin_lock_irq(&hpet_lock);
254 v = readl(&timer->hpet_config);
255 v |= irq << Tn_INT_ROUTE_CNF_SHIFT;
256 writel(v, &timer->hpet_config);
257 devp->hd_hdwirq = gsi;
258 spin_unlock_irq(&hpet_lock);
259 }
260 return;
261}
262
1da177e4
LT
263static int hpet_open(struct inode *inode, struct file *file)
264{
265 struct hpet_dev *devp;
266 struct hpets *hpetp;
267 int i;
268
269 if (file->f_mode & FMODE_WRITE)
270 return -EINVAL;
271
54066a57 272 mutex_lock(&hpet_mutex);
1da177e4
LT
273 spin_lock_irq(&hpet_lock);
274
275 for (devp = NULL, hpetp = hpets; hpetp && !devp; hpetp = hpetp->hp_next)
276 for (i = 0; i < hpetp->hp_ntimer; i++)
64a76f66 277 if (hpetp->hp_dev[i].hd_flags & HPET_OPEN)
1da177e4
LT
278 continue;
279 else {
280 devp = &hpetp->hp_dev[i];
281 break;
282 }
283
284 if (!devp) {
285 spin_unlock_irq(&hpet_lock);
54066a57 286 mutex_unlock(&hpet_mutex);
1da177e4
LT
287 return -EBUSY;
288 }
289
290 file->private_data = devp;
291 devp->hd_irqdata = 0;
292 devp->hd_flags |= HPET_OPEN;
293 spin_unlock_irq(&hpet_lock);
54066a57 294 mutex_unlock(&hpet_mutex);
1da177e4 295
70ef6d59
KH
296 hpet_timer_set_irq(devp);
297
1da177e4
LT
298 return 0;
299}
300
301static ssize_t
302hpet_read(struct file *file, char __user *buf, size_t count, loff_t * ppos)
303{
304 DECLARE_WAITQUEUE(wait, current);
305 unsigned long data;
306 ssize_t retval;
307 struct hpet_dev *devp;
308
309 devp = file->private_data;
310 if (!devp->hd_ireqfreq)
311 return -EIO;
312
313 if (count < sizeof(unsigned long))
314 return -EINVAL;
315
316 add_wait_queue(&devp->hd_waitqueue, &wait);
317
318 for ( ; ; ) {
319 set_current_state(TASK_INTERRUPTIBLE);
320
321 spin_lock_irq(&hpet_lock);
322 data = devp->hd_irqdata;
323 devp->hd_irqdata = 0;
324 spin_unlock_irq(&hpet_lock);
325
326 if (data)
327 break;
328 else if (file->f_flags & O_NONBLOCK) {
329 retval = -EAGAIN;
330 goto out;
331 } else if (signal_pending(current)) {
332 retval = -ERESTARTSYS;
333 goto out;
334 }
335 schedule();
336 }
337
338 retval = put_user(data, (unsigned long __user *)buf);
339 if (!retval)
340 retval = sizeof(unsigned long);
341out:
342 __set_current_state(TASK_RUNNING);
343 remove_wait_queue(&devp->hd_waitqueue, &wait);
344
345 return retval;
346}
347
348static unsigned int hpet_poll(struct file *file, poll_table * wait)
349{
350 unsigned long v;
351 struct hpet_dev *devp;
352
353 devp = file->private_data;
354
355 if (!devp->hd_ireqfreq)
356 return 0;
357
358 poll_wait(file, &devp->hd_waitqueue, wait);
359
360 spin_lock_irq(&hpet_lock);
361 v = devp->hd_irqdata;
362 spin_unlock_irq(&hpet_lock);
363
364 if (v != 0)
365 return POLLIN | POLLRDNORM;
366
367 return 0;
368}
369
370static int hpet_mmap(struct file *file, struct vm_area_struct *vma)
371{
372#ifdef CONFIG_HPET_MMAP
373 struct hpet_dev *devp;
374 unsigned long addr;
375
376 if (((vma->vm_end - vma->vm_start) != PAGE_SIZE) || vma->vm_pgoff)
377 return -EINVAL;
378
379 devp = file->private_data;
380 addr = devp->hd_hpets->hp_hpet_phys;
381
382 if (addr & (PAGE_SIZE - 1))
383 return -ENOSYS;
384
385 vma->vm_flags |= VM_IO;
386 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1da177e4
LT
387
388 if (io_remap_pfn_range(vma, vma->vm_start, addr >> PAGE_SHIFT,
389 PAGE_SIZE, vma->vm_page_prot)) {
3e6716e7 390 printk(KERN_ERR "%s: io_remap_pfn_range failed\n",
bf9d8929 391 __func__);
1da177e4
LT
392 return -EAGAIN;
393 }
394
395 return 0;
396#else
397 return -ENOSYS;
398#endif
399}
400
401static int hpet_fasync(int fd, struct file *file, int on)
402{
403 struct hpet_dev *devp;
404
405 devp = file->private_data;
406
407 if (fasync_helper(fd, file, on, &devp->hd_async_queue) >= 0)
408 return 0;
409 else
410 return -EIO;
411}
412
413static int hpet_release(struct inode *inode, struct file *file)
414{
415 struct hpet_dev *devp;
416 struct hpet_timer __iomem *timer;
417 int irq = 0;
418
419 devp = file->private_data;
420 timer = devp->hd_timer;
421
422 spin_lock_irq(&hpet_lock);
423
424 writeq((readq(&timer->hpet_config) & ~Tn_INT_ENB_CNF_MASK),
425 &timer->hpet_config);
426
427 irq = devp->hd_irq;
428 devp->hd_irq = 0;
429
430 devp->hd_ireqfreq = 0;
431
432 if (devp->hd_flags & HPET_PERIODIC
433 && readq(&timer->hpet_config) & Tn_TYPE_CNF_MASK) {
434 unsigned long v;
435
436 v = readq(&timer->hpet_config);
437 v ^= Tn_TYPE_CNF_MASK;
438 writeq(v, &timer->hpet_config);
439 }
440
441 devp->hd_flags &= ~(HPET_OPEN | HPET_IE | HPET_PERIODIC);
442 spin_unlock_irq(&hpet_lock);
443
444 if (irq)
445 free_irq(irq, devp);
446
1da177e4
LT
447 file->private_data = NULL;
448 return 0;
449}
450
1da177e4
LT
451static int hpet_ioctl_ieon(struct hpet_dev *devp)
452{
453 struct hpet_timer __iomem *timer;
454 struct hpet __iomem *hpet;
455 struct hpets *hpetp;
456 int irq;
457 unsigned long g, v, t, m;
458 unsigned long flags, isr;
459
460 timer = devp->hd_timer;
461 hpet = devp->hd_hpet;
462 hpetp = devp->hd_hpets;
463
9090e6db
CL
464 if (!devp->hd_ireqfreq)
465 return -EIO;
466
1da177e4
LT
467 spin_lock_irq(&hpet_lock);
468
469 if (devp->hd_flags & HPET_IE) {
470 spin_unlock_irq(&hpet_lock);
471 return -EBUSY;
472 }
473
474 devp->hd_flags |= HPET_IE;
0d290861
CL
475
476 if (readl(&timer->hpet_config) & Tn_INT_TYPE_CNF_MASK)
477 devp->hd_flags |= HPET_SHARED_IRQ;
1da177e4
LT
478 spin_unlock_irq(&hpet_lock);
479
1da177e4
LT
480 irq = devp->hd_hdwirq;
481
482 if (irq) {
0d290861 483 unsigned long irq_flags;
1da177e4 484
96e9694d
CL
485 if (devp->hd_flags & HPET_SHARED_IRQ) {
486 /*
487 * To prevent the interrupt handler from seeing an
488 * unwanted interrupt status bit, program the timer
489 * so that it will not fire in the near future ...
490 */
491 writel(readl(&timer->hpet_config) & ~Tn_TYPE_CNF_MASK,
492 &timer->hpet_config);
493 write_counter(read_counter(&hpet->hpet_mc),
494 &timer->hpet_compare);
495 /* ... and clear any left-over status. */
496 isr = 1 << (devp - devp->hd_hpets->hp_dev);
497 writel(isr, &hpet->hpet_isr);
498 }
499
0d290861
CL
500 sprintf(devp->hd_name, "hpet%d", (int)(devp - hpetp->hp_dev));
501 irq_flags = devp->hd_flags & HPET_SHARED_IRQ
0f2ed4c6 502 ? IRQF_SHARED : IRQF_DISABLED;
0d290861
CL
503 if (request_irq(irq, hpet_interrupt, irq_flags,
504 devp->hd_name, (void *)devp)) {
1da177e4
LT
505 printk(KERN_ERR "hpet: IRQ %d is not free\n", irq);
506 irq = 0;
507 }
508 }
509
510 if (irq == 0) {
511 spin_lock_irq(&hpet_lock);
512 devp->hd_flags ^= HPET_IE;
513 spin_unlock_irq(&hpet_lock);
514 return -EIO;
515 }
516
517 devp->hd_irq = irq;
518 t = devp->hd_ireqfreq;
519 v = readq(&timer->hpet_config);
64a76f66
DB
520
521 /* 64-bit comparators are not yet supported through the ioctls,
522 * so force this into 32-bit mode if it supports both modes
523 */
524 g = v | Tn_32MODE_CNF_MASK | Tn_INT_ENB_CNF_MASK;
1da177e4
LT
525
526 if (devp->hd_flags & HPET_PERIODIC) {
1da177e4 527 g |= Tn_TYPE_CNF_MASK;
ae21cf92 528 v |= Tn_TYPE_CNF_MASK | Tn_VAL_SET_CNF_MASK;
1da177e4
LT
529 writeq(v, &timer->hpet_config);
530 local_irq_save(flags);
64a76f66 531
ae21cf92
NC
532 /*
533 * NOTE: First we modify the hidden accumulator
64a76f66
DB
534 * register supported by periodic-capable comparators.
535 * We never want to modify the (single) counter; that
ae21cf92
NC
536 * would affect all the comparators. The value written
537 * is the counter value when the first interrupt is due.
64a76f66 538 */
1da177e4
LT
539 m = read_counter(&hpet->hpet_mc);
540 write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare);
ae21cf92
NC
541 /*
542 * Then we modify the comparator, indicating the period
543 * for subsequent interrupt.
544 */
545 write_counter(t, &timer->hpet_compare);
1da177e4
LT
546 } else {
547 local_irq_save(flags);
548 m = read_counter(&hpet->hpet_mc);
549 write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare);
550 }
551
0d290861 552 if (devp->hd_flags & HPET_SHARED_IRQ) {
3d5640d1 553 isr = 1 << (devp - devp->hd_hpets->hp_dev);
0d290861
CL
554 writel(isr, &hpet->hpet_isr);
555 }
1da177e4
LT
556 writeq(g, &timer->hpet_config);
557 local_irq_restore(flags);
558
559 return 0;
560}
561
ba3f213f
CL
562/* converts Hz to number of timer ticks */
563static inline unsigned long hpet_time_div(struct hpets *hpets,
564 unsigned long dis)
1da177e4 565{
ba3f213f 566 unsigned long long m;
1da177e4 567
ba3f213f 568 m = hpets->hp_tick_freq + (dis >> 1);
1da177e4 569 do_div(m, dis);
1da177e4
LT
570 return (unsigned long)m;
571}
572
573static int
54066a57
AB
574hpet_ioctl_common(struct hpet_dev *devp, int cmd, unsigned long arg,
575 struct hpet_info *info)
1da177e4
LT
576{
577 struct hpet_timer __iomem *timer;
578 struct hpet __iomem *hpet;
579 struct hpets *hpetp;
580 int err;
581 unsigned long v;
582
583 switch (cmd) {
584 case HPET_IE_OFF:
585 case HPET_INFO:
586 case HPET_EPI:
587 case HPET_DPI:
588 case HPET_IRQFREQ:
589 timer = devp->hd_timer;
590 hpet = devp->hd_hpet;
591 hpetp = devp->hd_hpets;
592 break;
593 case HPET_IE_ON:
594 return hpet_ioctl_ieon(devp);
595 default:
596 return -EINVAL;
597 }
598
599 err = 0;
600
601 switch (cmd) {
602 case HPET_IE_OFF:
603 if ((devp->hd_flags & HPET_IE) == 0)
604 break;
605 v = readq(&timer->hpet_config);
606 v &= ~Tn_INT_ENB_CNF_MASK;
607 writeq(v, &timer->hpet_config);
608 if (devp->hd_irq) {
609 free_irq(devp->hd_irq, devp);
610 devp->hd_irq = 0;
611 }
612 devp->hd_flags ^= HPET_IE;
613 break;
614 case HPET_INFO:
615 {
dae512ed 616 memset(info, 0, sizeof(*info));
af95eade 617 if (devp->hd_ireqfreq)
54066a57 618 info->hi_ireqfreq =
af95eade 619 hpet_time_div(hpetp, devp->hd_ireqfreq);
54066a57 620 info->hi_flags =
1da177e4 621 readq(&timer->hpet_config) & Tn_PER_INT_CAP_MASK;
54066a57
AB
622 info->hi_hpet = hpetp->hp_which;
623 info->hi_timer = devp - hpetp->hp_dev;
1da177e4
LT
624 break;
625 }
626 case HPET_EPI:
627 v = readq(&timer->hpet_config);
628 if ((v & Tn_PER_INT_CAP_MASK) == 0) {
629 err = -ENXIO;
630 break;
631 }
632 devp->hd_flags |= HPET_PERIODIC;
633 break;
634 case HPET_DPI:
635 v = readq(&timer->hpet_config);
636 if ((v & Tn_PER_INT_CAP_MASK) == 0) {
637 err = -ENXIO;
638 break;
639 }
640 if (devp->hd_flags & HPET_PERIODIC &&
641 readq(&timer->hpet_config) & Tn_TYPE_CNF_MASK) {
642 v = readq(&timer->hpet_config);
643 v ^= Tn_TYPE_CNF_MASK;
644 writeq(v, &timer->hpet_config);
645 }
646 devp->hd_flags &= ~HPET_PERIODIC;
647 break;
648 case HPET_IRQFREQ:
54066a57 649 if ((arg > hpet_max_freq) &&
1da177e4
LT
650 !capable(CAP_SYS_RESOURCE)) {
651 err = -EACCES;
652 break;
653 }
654
189e2dd1 655 if (!arg) {
1da177e4
LT
656 err = -EINVAL;
657 break;
658 }
659
ba3f213f 660 devp->hd_ireqfreq = hpet_time_div(hpetp, arg);
1da177e4
LT
661 }
662
663 return err;
664}
665
54066a57
AB
666static long
667hpet_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
668{
669 struct hpet_info info;
670 int err;
671
672 mutex_lock(&hpet_mutex);
673 err = hpet_ioctl_common(file->private_data, cmd, arg, &info);
674 mutex_unlock(&hpet_mutex);
675
676 if ((cmd == HPET_INFO) && !err &&
677 (copy_to_user((void __user *)arg, &info, sizeof(info))))
678 err = -EFAULT;
679
680 return err;
681}
682
683#ifdef CONFIG_COMPAT
684struct compat_hpet_info {
685 compat_ulong_t hi_ireqfreq; /* Hz */
686 compat_ulong_t hi_flags; /* information */
687 unsigned short hi_hpet;
688 unsigned short hi_timer;
689};
690
691static long
692hpet_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
693{
694 struct hpet_info info;
695 int err;
696
697 mutex_lock(&hpet_mutex);
698 err = hpet_ioctl_common(file->private_data, cmd, arg, &info);
699 mutex_unlock(&hpet_mutex);
700
701 if ((cmd == HPET_INFO) && !err) {
702 struct compat_hpet_info __user *u = compat_ptr(arg);
703 if (put_user(info.hi_ireqfreq, &u->hi_ireqfreq) ||
704 put_user(info.hi_flags, &u->hi_flags) ||
705 put_user(info.hi_hpet, &u->hi_hpet) ||
706 put_user(info.hi_timer, &u->hi_timer))
707 err = -EFAULT;
708 }
709
710 return err;
711}
712#endif
713
62322d25 714static const struct file_operations hpet_fops = {
1da177e4
LT
715 .owner = THIS_MODULE,
716 .llseek = no_llseek,
717 .read = hpet_read,
718 .poll = hpet_poll,
55929332 719 .unlocked_ioctl = hpet_ioctl,
54066a57
AB
720#ifdef CONFIG_COMPAT
721 .compat_ioctl = hpet_compat_ioctl,
722#endif
1da177e4
LT
723 .open = hpet_open,
724 .release = hpet_release,
725 .fasync = hpet_fasync,
726 .mmap = hpet_mmap,
727};
728
3e6716e7
RD
729static int hpet_is_known(struct hpet_data *hdp)
730{
731 struct hpets *hpetp;
732
733 for (hpetp = hpets; hpetp; hpetp = hpetp->hp_next)
734 if (hpetp->hp_hpet_phys == hdp->hd_phys_address)
735 return 1;
736
737 return 0;
738}
739
1da177e4
LT
740static ctl_table hpet_table[] = {
741 {
1da177e4
LT
742 .procname = "max-user-freq",
743 .data = &hpet_max_freq,
744 .maxlen = sizeof(int),
745 .mode = 0644,
6d456111 746 .proc_handler = proc_dointvec,
1da177e4 747 },
894d2491 748 {}
1da177e4
LT
749};
750
751static ctl_table hpet_root[] = {
752 {
1da177e4
LT
753 .procname = "hpet",
754 .maxlen = 0,
755 .mode = 0555,
756 .child = hpet_table,
757 },
894d2491 758 {}
1da177e4
LT
759};
760
761static ctl_table dev_root[] = {
762 {
1da177e4
LT
763 .procname = "dev",
764 .maxlen = 0,
765 .mode = 0555,
766 .child = hpet_root,
767 },
894d2491 768 {}
1da177e4
LT
769};
770
771static struct ctl_table_header *sysctl_header;
772
1da177e4
LT
773/*
774 * Adjustment for when arming the timer with
775 * initial conditions. That is, main counter
776 * ticks expired before interrupts are enabled.
777 */
778#define TICK_CALIBRATE (1000UL)
779
303d379c 780static unsigned long __hpet_calibrate(struct hpets *hpetp)
1da177e4
LT
781{
782 struct hpet_timer __iomem *timer = NULL;
783 unsigned long t, m, count, i, flags, start;
784 struct hpet_dev *devp;
785 int j;
786 struct hpet __iomem *hpet;
787
788 for (j = 0, devp = hpetp->hp_dev; j < hpetp->hp_ntimer; j++, devp++)
789 if ((devp->hd_flags & HPET_OPEN) == 0) {
790 timer = devp->hd_timer;
791 break;
792 }
793
794 if (!timer)
795 return 0;
796
3d5640d1 797 hpet = hpetp->hp_hpet;
1da177e4
LT
798 t = read_counter(&timer->hpet_compare);
799
800 i = 0;
ba3f213f 801 count = hpet_time_div(hpetp, TICK_CALIBRATE);
1da177e4
LT
802
803 local_irq_save(flags);
804
805 start = read_counter(&hpet->hpet_mc);
806
807 do {
808 m = read_counter(&hpet->hpet_mc);
809 write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare);
810 } while (i++, (m - start) < count);
811
812 local_irq_restore(flags);
813
814 return (m - start) / i;
815}
816
303d379c
YG
817static unsigned long hpet_calibrate(struct hpets *hpetp)
818{
819 unsigned long ret = -1;
820 unsigned long tmp;
821
822 /*
823 * Try to calibrate until return value becomes stable small value.
824 * If SMI interruption occurs in calibration loop, the return value
825 * will be big. This avoids its impact.
826 */
827 for ( ; ; ) {
828 tmp = __hpet_calibrate(hpetp);
829 if (ret <= tmp)
830 break;
831 ret = tmp;
832 }
833
834 return ret;
835}
836
1da177e4
LT
837int hpet_alloc(struct hpet_data *hdp)
838{
5761d64b 839 u64 cap, mcfg;
1da177e4 840 struct hpet_dev *devp;
5761d64b 841 u32 i, ntimer;
1da177e4
LT
842 struct hpets *hpetp;
843 size_t siz;
844 struct hpet __iomem *hpet;
0ca01763 845 static struct hpets *last;
5761d64b 846 unsigned long period;
ba3f213f 847 unsigned long long temp;
f92a789d 848 u32 remainder;
1da177e4
LT
849
850 /*
851 * hpet_alloc can be called by platform dependent code.
3e6716e7
RD
852 * If platform dependent code has allocated the hpet that
853 * ACPI has also reported, then we catch it here.
1da177e4 854 */
3e6716e7
RD
855 if (hpet_is_known(hdp)) {
856 printk(KERN_DEBUG "%s: duplicate HPET ignored\n",
bf9d8929 857 __func__);
3e6716e7
RD
858 return 0;
859 }
1da177e4
LT
860
861 siz = sizeof(struct hpets) + ((hdp->hd_nirqs - 1) *
862 sizeof(struct hpet_dev));
863
3e6716e7 864 hpetp = kzalloc(siz, GFP_KERNEL);
1da177e4
LT
865
866 if (!hpetp)
867 return -ENOMEM;
868
1da177e4
LT
869 hpetp->hp_which = hpet_nhpet++;
870 hpetp->hp_hpet = hdp->hd_address;
871 hpetp->hp_hpet_phys = hdp->hd_phys_address;
872
873 hpetp->hp_ntimer = hdp->hd_nirqs;
e3f37a54 874
5761d64b
TG
875 for (i = 0; i < hdp->hd_nirqs; i++)
876 hpetp->hp_dev[i].hd_hdwirq = hdp->hd_irq[i];
37a47db8 877
5761d64b 878 hpet = hpetp->hp_hpet;
e3f37a54 879
1da177e4
LT
880 cap = readq(&hpet->hpet_cap);
881
882 ntimer = ((cap & HPET_NUM_TIM_CAP_MASK) >> HPET_NUM_TIM_CAP_SHIFT) + 1;
883
884 if (hpetp->hp_ntimer != ntimer) {
885 printk(KERN_WARNING "hpet: number irqs doesn't agree"
886 " with number of timers\n");
887 kfree(hpetp);
888 return -ENODEV;
889 }
890
891 if (last)
892 last->hp_next = hpetp;
893 else
894 hpets = hpetp;
895
896 last = hpetp;
897
ba3f213f
CL
898 period = (cap & HPET_COUNTER_CLK_PERIOD_MASK) >>
899 HPET_COUNTER_CLK_PERIOD_SHIFT; /* fs, 10^-15 */
900 temp = 1000000000000000uLL; /* 10^15 femtoseconds per second */
901 temp += period >> 1; /* round */
902 do_div(temp, period);
903 hpetp->hp_tick_freq = temp; /* ticks per second */
1da177e4 904
3034d11c
AK
905 printk(KERN_INFO "hpet%d: at MMIO 0x%lx, IRQ%s",
906 hpetp->hp_which, hdp->hd_phys_address,
1da177e4
LT
907 hpetp->hp_ntimer > 1 ? "s" : "");
908 for (i = 0; i < hpetp->hp_ntimer; i++)
5da527aa
KS
909 printk(KERN_CONT "%s %d", i > 0 ? "," : "", hdp->hd_irq[i]);
910 printk(KERN_CONT "\n");
1da177e4 911
f92a789d
DB
912 temp = hpetp->hp_tick_freq;
913 remainder = do_div(temp, 1000000);
64a76f66
DB
914 printk(KERN_INFO
915 "hpet%u: %u comparators, %d-bit %u.%06u MHz counter\n",
916 hpetp->hp_which, hpetp->hp_ntimer,
917 cap & HPET_COUNTER_SIZE_MASK ? 64 : 32,
f92a789d 918 (unsigned) temp, remainder);
1da177e4
LT
919
920 mcfg = readq(&hpet->hpet_config);
921 if ((mcfg & HPET_ENABLE_CNF_MASK) == 0) {
922 write_counter(0L, &hpet->hpet_mc);
923 mcfg |= HPET_ENABLE_CNF_MASK;
924 writeq(mcfg, &hpet->hpet_config);
925 }
926
642d30bb 927 for (i = 0, devp = hpetp->hp_dev; i < hpetp->hp_ntimer; i++, devp++) {
1da177e4
LT
928 struct hpet_timer __iomem *timer;
929
930 timer = &hpet->hpet_timers[devp - hpetp->hp_dev];
1da177e4
LT
931
932 devp->hd_hpets = hpetp;
933 devp->hd_hpet = hpet;
934 devp->hd_timer = timer;
935
936 /*
937 * If the timer was reserved by platform code,
938 * then make timer unavailable for opens.
939 */
940 if (hdp->hd_state & (1 << i)) {
941 devp->hd_flags = HPET_OPEN;
942 continue;
943 }
944
945 init_waitqueue_head(&devp->hd_waitqueue);
946 }
947
948 hpetp->hp_delta = hpet_calibrate(hpetp);
0aa366f3 949
3b2b64fd
LT
950/* This clocksource driver currently only works on ia64 */
951#ifdef CONFIG_IA64
0aa366f3
TL
952 if (!hpet_clocksource) {
953 hpet_mctr = (void __iomem *)&hpetp->hp_hpet->hpet_mc;
574c44fa 954 clocksource_hpet.archdata.fsys_mmio = hpet_mctr;
d60c3041 955 clocksource_register_hz(&clocksource_hpet, hpetp->hp_tick_freq);
0aa366f3
TL
956 hpetp->hp_clocksource = &clocksource_hpet;
957 hpet_clocksource = &clocksource_hpet;
958 }
3b2b64fd 959#endif
1da177e4
LT
960
961 return 0;
962}
963
964static acpi_status hpet_resources(struct acpi_resource *res, void *data)
965{
966 struct hpet_data *hdp;
967 acpi_status status;
968 struct acpi_resource_address64 addr;
1da177e4
LT
969
970 hdp = data;
971
972 status = acpi_resource_to_address64(res, &addr);
973
974 if (ACPI_SUCCESS(status)) {
50eca3eb 975 hdp->hd_phys_address = addr.minimum;
9224a867 976 hdp->hd_address = ioremap(addr.minimum, addr.address_length);
1da177e4 977
3e6716e7 978 if (hpet_is_known(hdp)) {
3e6716e7 979 iounmap(hdp->hd_address);
78e1ca49 980 return AE_ALREADY_EXISTS;
3e6716e7 981 }
50eca3eb
BM
982 } else if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
983 struct acpi_resource_fixed_memory32 *fixmem32;
757c4724
RD
984
985 fixmem32 = &res->data.fixed_memory32;
986 if (!fixmem32)
78e1ca49 987 return AE_NO_MEMORY;
757c4724 988
50eca3eb
BM
989 hdp->hd_phys_address = fixmem32->address;
990 hdp->hd_address = ioremap(fixmem32->address,
757c4724
RD
991 HPET_RANGE_SIZE);
992
3e6716e7 993 if (hpet_is_known(hdp)) {
3e6716e7 994 iounmap(hdp->hd_address);
78e1ca49 995 return AE_ALREADY_EXISTS;
3e6716e7 996 }
50eca3eb
BM
997 } else if (res->type == ACPI_RESOURCE_TYPE_EXTENDED_IRQ) {
998 struct acpi_resource_extended_irq *irqp;
be5efffb 999 int i, irq;
1da177e4
LT
1000
1001 irqp = &res->data.extended_irq;
1002
be5efffb 1003 for (i = 0; i < irqp->interrupt_count; i++) {
a2f809b0 1004 irq = acpi_register_gsi(NULL, irqp->interrupts[i],
be5efffb
BH
1005 irqp->triggering, irqp->polarity);
1006 if (irq < 0)
1007 return AE_ERROR;
1008
1009 hdp->hd_irq[hdp->hd_nirqs] = irq;
1010 hdp->hd_nirqs++;
1da177e4
LT
1011 }
1012 }
1013
1014 return AE_OK;
1015}
1016
1017static int hpet_acpi_add(struct acpi_device *device)
1018{
1019 acpi_status result;
1020 struct hpet_data data;
1021
1022 memset(&data, 0, sizeof(data));
1023
1024 result =
1025 acpi_walk_resources(device->handle, METHOD_NAME__CRS,
1026 hpet_resources, &data);
1027
1028 if (ACPI_FAILURE(result))
1029 return -ENODEV;
1030
1031 if (!data.hd_address || !data.hd_nirqs) {
a56d5318
JS
1032 if (data.hd_address)
1033 iounmap(data.hd_address);
bf9d8929 1034 printk("%s: no address or irqs in _CRS\n", __func__);
1da177e4
LT
1035 return -ENODEV;
1036 }
1037
1038 return hpet_alloc(&data);
1039}
1040
1041static int hpet_acpi_remove(struct acpi_device *device, int type)
1042{
0aa366f3 1043 /* XXX need to unregister clocksource, dealloc mem, etc */
1da177e4
LT
1044 return -EINVAL;
1045}
1046
1ba90e3a
TR
1047static const struct acpi_device_id hpet_device_ids[] = {
1048 {"PNP0103", 0},
1049 {"", 0},
1050};
1051MODULE_DEVICE_TABLE(acpi, hpet_device_ids);
1052
1da177e4
LT
1053static struct acpi_driver hpet_acpi_driver = {
1054 .name = "hpet",
1ba90e3a 1055 .ids = hpet_device_ids,
1da177e4
LT
1056 .ops = {
1057 .add = hpet_acpi_add,
1058 .remove = hpet_acpi_remove,
1059 },
1060};
1061
1062static struct miscdevice hpet_misc = { HPET_MINOR, "hpet", &hpet_fops };
1063
1064static int __init hpet_init(void)
1065{
1066 int result;
1067
1068 result = misc_register(&hpet_misc);
1069 if (result < 0)
1070 return -ENODEV;
1071
0b4d4147 1072 sysctl_header = register_sysctl_table(dev_root);
1da177e4
LT
1073
1074 result = acpi_bus_register_driver(&hpet_acpi_driver);
1075 if (result < 0) {
1076 if (sysctl_header)
1077 unregister_sysctl_table(sysctl_header);
1078 misc_deregister(&hpet_misc);
1079 return result;
1080 }
1081
1082 return 0;
1083}
1084
1085static void __exit hpet_exit(void)
1086{
1087 acpi_bus_unregister_driver(&hpet_acpi_driver);
1088
1089 if (sysctl_header)
1090 unregister_sysctl_table(sysctl_header);
1091 misc_deregister(&hpet_misc);
1092
1093 return;
1094}
1095
1096module_init(hpet_init);
1097module_exit(hpet_exit);
1098MODULE_AUTHOR("Bob Picco <Robert.Picco@hp.com>");
1099MODULE_LICENSE("GPL");