[mirror_ubuntu-artful-kernel.git] / drivers / char / hw_random / n2rng.h

/* n2rng.h: Niagara2 RNG defines.
 *
 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
 */

#ifndef _N2RNG_H
#define _N2RNG_H

/* ver1 devices - n2-rng, vf-rng, kt-rng */
#define RNG_v1_CTL_WAIT       0x0000000001fffe00ULL /* Minimum wait time    */
#define RNG_v1_CTL_WAIT_SHIFT 9
#define RNG_v1_CTL_BYPASS     0x0000000000000100ULL /* VCO voltage source   */
#define RNG_v1_CTL_VCO        0x00000000000000c0ULL /* VCO rate control     */
#define RNG_v1_CTL_VCO_SHIFT  6
#define RNG_v1_CTL_ASEL       0x0000000000000030ULL /* Analog MUX select    */
#define RNG_v1_CTL_ASEL_SHIFT 4
#define RNG_v1_CTL_ASEL_NOOUT 2

/* these are the same in v2 as in v1 */
#define RNG_CTL_LFSR       0x0000000000000008ULL /* Use LFSR or plain shift */
#define RNG_CTL_ES3        0x0000000000000004ULL /* Enable entropy source 3 */
#define RNG_CTL_ES2        0x0000000000000002ULL /* Enable entropy source 2 */
#define RNG_CTL_ES1        0x0000000000000001ULL /* Enable entropy source 1 */

/* ver2 devices - m4-rng, m7-rng */
#define RNG_v2_CTL_WAIT       0x0000000007fff800ULL /* Minimum wait time    */
#define RNG_v2_CTL_WAIT_SHIFT 12
#define RNG_v2_CTL_BYPASS     0x0000000000000400ULL /* VCO voltage source   */
#define RNG_v2_CTL_VCO        0x0000000000000300ULL /* VCO rate control     */
#define RNG_v2_CTL_VCO_SHIFT  9
#define RNG_v2_CTL_PERF       0x0000000000000180ULL /* Perf */
#define RNG_v2_CTL_ASEL       0x0000000000000070ULL /* Analog MUX select    */
#define RNG_v2_CTL_ASEL_SHIFT 4
#define RNG_v2_CTL_ASEL_NOOUT 7


#define HV_FAST_RNG_GET_DIAG_CTL	0x130
#define HV_FAST_RNG_CTL_READ		0x131
#define HV_FAST_RNG_CTL_WRITE		0x132
#define HV_FAST_RNG_DATA_READ_DIAG	0x133
#define HV_FAST_RNG_DATA_READ		0x134

#define HV_RNG_STATE_UNCONFIGURED	0
#define HV_RNG_STATE_CONFIGURED		1
#define HV_RNG_STATE_HEALTHCHECK	2
#define HV_RNG_STATE_ERROR		3

#define HV_RNG_NUM_CONTROL		4

#ifndef __ASSEMBLY__
extern unsigned long sun4v_rng_get_diag_ctl(void);
extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra,
					   unsigned long *state,
					   unsigned long *tick_delta);
extern unsigned long sun4v_rng_ctl_read_v2(unsigned long ctl_regs_ra,
					   unsigned long unit,
					   unsigned long *state,
					   unsigned long *tick_delta,
					   unsigned long *watchdog,
					   unsigned long *write_status);
extern unsigned long sun4v_rng_ctl_write_v1(unsigned long ctl_regs_ra,
					    unsigned long state,
					    unsigned long write_timeout,
					    unsigned long *tick_delta);
extern unsigned long sun4v_rng_ctl_write_v2(unsigned long ctl_regs_ra,
					    unsigned long state,
					    unsigned long write_timeout,
					    unsigned long unit);
extern unsigned long sun4v_rng_data_read_diag_v1(unsigned long data_ra,
						 unsigned long len,
						 unsigned long *tick_delta);
extern unsigned long sun4v_rng_data_read_diag_v2(unsigned long data_ra,
						 unsigned long len,
						 unsigned long unit,
						 unsigned long *tick_delta);
extern unsigned long sun4v_rng_data_read(unsigned long data_ra,
					 unsigned long *tick_delta);

enum n2rng_compat_id {
	N2_n2_rng,
	N2_vf_rng,
	N2_kt_rng,
	N2_m4_rng,
	N2_m7_rng,
};

struct n2rng_template {
	enum n2rng_compat_id id;
	int multi_capable;
	int chip_version;
};

struct n2rng_unit {
	u64			control[HV_RNG_NUM_CONTROL];
};

struct n2rng {
	struct platform_device	*op;

	unsigned long		flags;
#define N2RNG_FLAG_MULTI	0x00000001 /* Multi-unit capable RNG */
#define N2RNG_FLAG_CONTROL	0x00000002 /* Operating in control domain */
#define N2RNG_FLAG_READY	0x00000008 /* Ready for hw-rng layer      */
#define N2RNG_FLAG_SHUTDOWN	0x00000010 /* Driver unregistering        */
#define N2RNG_FLAG_BUFFER_VALID	0x00000020 /* u32 buffer holds valid data */

	struct n2rng_template	*data;
	int			num_units;
	struct n2rng_unit	*units;

	struct hwrng		hwrng;
	u32			buffer;

	/* Registered hypervisor group API major and minor version.  */
	unsigned long		hvapi_major;
	unsigned long		hvapi_minor;

	struct delayed_work	work;

	unsigned long		hv_state; /* HV_RNG_STATE_foo */

	unsigned long		health_check_sec;
	unsigned long		accum_cycles;
	unsigned long		wd_timeo;
#define N2RNG_HEALTH_CHECK_SEC_DEFAULT	0
#define N2RNG_ACCUM_CYCLES_DEFAULT	2048
#define N2RNG_WD_TIMEO_DEFAULT		0

	u64			scratch_control[HV_RNG_NUM_CONTROL];

#define RNG_v1_SELFTEST_TICKS	38859
#define RNG_v1_SELFTEST_VAL	((u64)0xB8820C7BD387E32C)
#define RNG_v2_SELFTEST_TICKS	64
#define RNG_v2_SELFTEST_VAL	((u64)0xffffffffffffffff)
#define SELFTEST_POLY		((u64)0x231DCEE91262B8A3)
#define SELFTEST_MATCH_GOAL	6
#define SELFTEST_LOOPS_MAX	40000
#define SELFTEST_BUFFER_WORDS	8

	u64			test_data;
	u64			test_control[HV_RNG_NUM_CONTROL];
	u64			test_buffer[SELFTEST_BUFFER_WORDS];
};

#define N2RNG_BLOCK_LIMIT	60000
#define N2RNG_BUSY_LIMIT	100
#define N2RNG_HCHECK_LIMIT	100

#endif /* !(__ASSEMBLY__) */

#endif /* _N2RNG_H */
Commit	Line	Data
ce087150 DM	1	/* n2rng.h: Niagara2 RNG defines.
	2	*
	3	* Copyright (C) 2008 David S. Miller <davem@davemloft.net>
	4	*/
	5
	6	#ifndef _N2RNG_H
	7	#define _N2RNG_H
	8
07e25d43 SN	9	/* ver1 devices - n2-rng, vf-rng, kt-rng */
	10	#define RNG_v1_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
	11	#define RNG_v1_CTL_WAIT_SHIFT 9
	12	#define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
	13	#define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
	14	#define RNG_v1_CTL_VCO_SHIFT 6
	15	#define RNG_v1_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
	16	#define RNG_v1_CTL_ASEL_SHIFT 4
	17	#define RNG_v1_CTL_ASEL_NOOUT 2
	18
	19	/* these are the same in v2 as in v1 */
ce087150 DM	20	#define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */
	21	#define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */
	22	#define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */
	23	#define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */
	24
07e25d43 SN	25	/* ver2 devices - m4-rng, m7-rng */
	26	#define RNG_v2_CTL_WAIT 0x0000000007fff800ULL /* Minimum wait time */
	27	#define RNG_v2_CTL_WAIT_SHIFT 12
	28	#define RNG_v2_CTL_BYPASS 0x0000000000000400ULL /* VCO voltage source */
	29	#define RNG_v2_CTL_VCO 0x0000000000000300ULL /* VCO rate control */
	30	#define RNG_v2_CTL_VCO_SHIFT 9
	31	#define RNG_v2_CTL_PERF 0x0000000000000180ULL /* Perf */
	32	#define RNG_v2_CTL_ASEL 0x0000000000000070ULL /* Analog MUX select */
	33	#define RNG_v2_CTL_ASEL_SHIFT 4
	34	#define RNG_v2_CTL_ASEL_NOOUT 7
	35
	36
ce087150 DM	37	#define HV_FAST_RNG_GET_DIAG_CTL 0x130
	38	#define HV_FAST_RNG_CTL_READ 0x131
	39	#define HV_FAST_RNG_CTL_WRITE 0x132
	40	#define HV_FAST_RNG_DATA_READ_DIAG 0x133
	41	#define HV_FAST_RNG_DATA_READ 0x134
	42
	43	#define HV_RNG_STATE_UNCONFIGURED 0
	44	#define HV_RNG_STATE_CONFIGURED 1
	45	#define HV_RNG_STATE_HEALTHCHECK 2
	46	#define HV_RNG_STATE_ERROR 3
	47
	48	#define HV_RNG_NUM_CONTROL 4
	49
	50	#ifndef __ASSEMBLY__
	51	extern unsigned long sun4v_rng_get_diag_ctl(void);
	52	extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra,
	53	unsigned long *state,
	54	unsigned long *tick_delta);
	55	extern unsigned long sun4v_rng_ctl_read_v2(unsigned long ctl_regs_ra,
	56	unsigned long unit,
	57	unsigned long *state,
	58	unsigned long *tick_delta,
	59	unsigned long *watchdog,
	60	unsigned long *write_status);
	61	extern unsigned long sun4v_rng_ctl_write_v1(unsigned long ctl_regs_ra,
	62	unsigned long state,
	63	unsigned long write_timeout,
	64	unsigned long *tick_delta);
	65	extern unsigned long sun4v_rng_ctl_write_v2(unsigned long ctl_regs_ra,
	66	unsigned long state,
	67	unsigned long write_timeout,
	68	unsigned long unit);
	69	extern unsigned long sun4v_rng_data_read_diag_v1(unsigned long data_ra,
	70	unsigned long len,
	71	unsigned long *tick_delta);
	72	extern unsigned long sun4v_rng_data_read_diag_v2(unsigned long data_ra,
	73	unsigned long len,
	74	unsigned long unit,
	75	unsigned long *tick_delta);
	76	extern unsigned long sun4v_rng_data_read(unsigned long data_ra,
	77	unsigned long *tick_delta);
	78
becbc494 SN	79	enum n2rng_compat_id {
	80	N2_n2_rng,
	81	N2_vf_rng,
	82	N2_kt_rng,
	83	N2_m4_rng,
	84	N2_m7_rng,
	85	};
	86
	87	struct n2rng_template {
	88	enum n2rng_compat_id id;
	89	int multi_capable;
	90	int chip_version;
	91	};
	92
ce087150 DM	93	struct n2rng_unit {
	94	u64 control[HV_RNG_NUM_CONTROL];
	95	};
	96
	97	struct n2rng {
2dc11581	98	struct platform_device *op;
ce087150 DM	99
ce087150 DM	100	unsigned long flags;
24f14669	101	#define N2RNG_FLAG_MULTI 0x00000001 /* Multi-unit capable RNG */
ce087150 DM	102	#define N2RNG_FLAG_CONTROL 0x00000002 /* Operating in control domain */
	103	#define N2RNG_FLAG_READY 0x00000008 /* Ready for hw-rng layer */
	104	#define N2RNG_FLAG_SHUTDOWN 0x00000010 /* Driver unregistering */
	105	#define N2RNG_FLAG_BUFFER_VALID 0x00000020 /* u32 buffer holds valid data */
	106
becbc494	107	struct n2rng_template *data;
ce087150 DM	108	int num_units;
	109	struct n2rng_unit *units;
	110
	111	struct hwrng hwrng;
	112	u32 buffer;
	113
	114	/* Registered hypervisor group API major and minor version. */
	115	unsigned long hvapi_major;
	116	unsigned long hvapi_minor;
	117
	118	struct delayed_work work;
	119
	120	unsigned long hv_state; /* HV_RNG_STATE_foo */
	121
	122	unsigned long health_check_sec;
	123	unsigned long accum_cycles;
	124	unsigned long wd_timeo;
	125	#define N2RNG_HEALTH_CHECK_SEC_DEFAULT 0
	126	#define N2RNG_ACCUM_CYCLES_DEFAULT 2048
	127	#define N2RNG_WD_TIMEO_DEFAULT 0
	128
	129	u64 scratch_control[HV_RNG_NUM_CONTROL];
	130
07e25d43 SN	131	#define RNG_v1_SELFTEST_TICKS 38859
	132	#define RNG_v1_SELFTEST_VAL ((u64)0xB8820C7BD387E32C)
	133	#define RNG_v2_SELFTEST_TICKS 64
	134	#define RNG_v2_SELFTEST_VAL ((u64)0xffffffffffffffff)
ce087150 DM	135	#define SELFTEST_POLY ((u64)0x231DCEE91262B8A3)
	136	#define SELFTEST_MATCH_GOAL 6
	137	#define SELFTEST_LOOPS_MAX 40000
	138	#define SELFTEST_BUFFER_WORDS 8
	139
	140	u64 test_data;
	141	u64 test_control[HV_RNG_NUM_CONTROL];
	142	u64 test_buffer[SELFTEST_BUFFER_WORDS];
	143	};
	144
	145	#define N2RNG_BLOCK_LIMIT 60000
	146	#define N2RNG_BUSY_LIMIT 100
	147	#define N2RNG_HCHECK_LIMIT 100
	148
	149	#endif /* !(__ASSEMBLY__) */
	150
	151	#endif /* _N2RNG_H */