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[mirror_ubuntu-bionic-kernel.git] / drivers / char / pcmcia / synclink_cs.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/pcmcia/synclink_cs.c
3 *
a7482a2e 4 * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
1da177e4
LT		 5 *
6 * Device driver for Microgate SyncLink PC Card
7 * multiprotocol serial adapter.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * This code is released under the GNU General Public License (GPL)
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
26 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30#if defined(__i386__)
31# define BREAKPOINT() asm(" int $3");
32#else
33# define BREAKPOINT() { }
34#endif
35
36#define MAX_DEVICE_COUNT 4
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/errno.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/timer.h>
43#include <linux/time.h>
44#include <linux/interrupt.h>
1da177e4
LT		 45#include <linux/tty.h>
46#include <linux/tty_flip.h>
47#include <linux/serial.h>
48#include <linux/major.h>
49#include <linux/string.h>
50#include <linux/fcntl.h>
51#include <linux/ptrace.h>
52#include <linux/ioport.h>
53#include <linux/mm.h>
87687144 54#include <linux/seq_file.h>
1da177e4
LT		 55#include <linux/slab.h>
56#include <linux/netdevice.h>
57#include <linux/vmalloc.h>
58#include <linux/init.h>
1da177e4
LT		 59#include <linux/delay.h>
60#include <linux/ioctl.h>
3dd1247f 61#include <linux/synclink.h>
1da177e4 62
1da177e4
LT		 63#include <asm/io.h>
64#include <asm/irq.h>
65#include <asm/dma.h>
66#include <linux/bitops.h>
67#include <asm/types.h>
68#include <linux/termios.h>
69#include <linux/workqueue.h>
70#include <linux/hdlc.h>
71
1da177e4
LT		 72#include <pcmcia/cistpl.h>
73#include <pcmcia/cisreg.h>
74#include <pcmcia/ds.h>
75
af69c7f9
PF		 76#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
77#define SYNCLINK_GENERIC_HDLC 1
78#else
79#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 80#endif
81
82#define GET_USER(error,value,addr) error = get_user(value,addr)
83#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
84#define PUT_USER(error,value,addr) error = put_user(value,addr)
85#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
86
87#include <asm/uaccess.h>
88
1da177e4
LT		 89static MGSL_PARAMS default_params = {
90 MGSL_MODE_HDLC, /* unsigned long mode */
91 0, /* unsigned char loopback; */
92 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
93 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
94 0, /* unsigned long clock_speed; */
95 0xff, /* unsigned char addr_filter; */
96 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
97 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
98 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
99 9600, /* unsigned long data_rate; */
100 8, /* unsigned char data_bits; */
101 1, /* unsigned char stop_bits; */
102 ASYNC_PARITY_NONE /* unsigned char parity; */
103};
104
105typedef struct
106{
107 int count;
108 unsigned char status;
109 char data[1];
110} RXBUF;
111
112/* The queue of BH actions to be performed */
113
114#define BH_RECEIVE 1
115#define BH_TRANSMIT 2
116#define BH_STATUS 4
117
118#define IO_PIN_SHUTDOWN_LIMIT 100
119
120#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
121
122struct _input_signal_events {
d12341f9 123 int ri_up;
1da177e4
LT		 124 int ri_down;
125 int dsr_up;
126 int dsr_down;
127 int dcd_up;
128 int dcd_down;
129 int cts_up;
130 int cts_down;
131};
132
133
134/*
135 * Device instance data structure
136 */
d12341f9 137
1da177e4 138typedef struct _mgslpc_info {
eeb46134 139 struct tty_port port;
1da177e4
LT		 140 void *if_ptr; /* General purpose pointer (used by SPPP) */
141 int magic;
1da177e4 142 int line;
d12341f9 143
1da177e4 144 struct mgsl_icount icount;
d12341f9 145
1da177e4
LT		 146 int timeout;
147 int x_char; /* xon/xoff character */
1da177e4 148 unsigned char read_status_mask;
d12341f9 149 unsigned char ignore_status_mask;
1da177e4
LT		 150
151 unsigned char *tx_buf;
152 int tx_put;
153 int tx_get;
154 int tx_count;
155
156 /* circular list of fixed length rx buffers */
157
158 unsigned char *rx_buf; /* memory allocated for all rx buffers */
159 int rx_buf_total_size; /* size of memory allocated for rx buffers */
160 int rx_put; /* index of next empty rx buffer */
161 int rx_get; /* index of next full rx buffer */
162 int rx_buf_size; /* size in bytes of single rx buffer */
163 int rx_buf_count; /* total number of rx buffers */
164 int rx_frame_count; /* number of full rx buffers */
d12341f9 165
1da177e4
LT		 166 wait_queue_head_t status_event_wait_q;
167 wait_queue_head_t event_wait_q;
168 struct timer_list tx_timer; /* HDLC transmit timeout timer */
169 struct _mgslpc_info *next_device; /* device list link */
170
171 unsigned short imra_value;
172 unsigned short imrb_value;
173 unsigned char pim_value;
174
175 spinlock_t lock;
176 struct work_struct task; /* task structure for scheduling bh */
177
178 u32 max_frame_size;
179
180 u32 pending_bh;
181
0fab6de0
JP		 182 bool bh_running;
183 bool bh_requested;
d12341f9 184
1da177e4
LT		 185 int dcd_chkcount; /* check counts to prevent */
186 int cts_chkcount; /* too many IRQs if a signal */
187 int dsr_chkcount; /* is floating */
188 int ri_chkcount;
189
0fab6de0
JP		 190 bool rx_enabled;
191 bool rx_overflow;
1da177e4 192
0fab6de0
JP		 193 bool tx_enabled;
194 bool tx_active;
195 bool tx_aborting;
1da177e4
LT		 196 u32 idle_mode;
197
198 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
199
200 char device_name[25]; /* device instance name */
201
202 unsigned int io_base; /* base I/O address of adapter */
203 unsigned int irq_level;
d12341f9 204
1da177e4
LT		 205 MGSL_PARAMS params; /* communications parameters */
206
207 unsigned char serial_signals; /* current serial signal states */
208
0fab6de0 209 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 210 char testing_irq;
211 unsigned int init_error; /* startup error (DIAGS) */
212
a6b68a69 213 char *flag_buf;
0fab6de0 214 bool drop_rts_on_tx_done;
1da177e4
LT		 215
216 struct _input_signal_events input_signal_events;
217
218 /* PCMCIA support */
fd238232 219 struct pcmcia_device *p_dev;
1da177e4
LT		 220 int stop;
221
222 /* SPPP/Cisco HDLC device parts */
223 int netcount;
1da177e4
LT		 224 spinlock_t netlock;
225
af69c7f9 226#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 227 struct net_device *netdev;
228#endif
229
230} MGSLPC_INFO;
231
232#define MGSLPC_MAGIC 0x5402
233
234/*
235 * The size of the serial xmit buffer is 1 page, or 4096 bytes
236 */
237#define TXBUFSIZE 4096
238
d12341f9 239
1da177e4
LT		 240#define CHA 0x00 /* channel A offset */
241#define CHB 0x40 /* channel B offset */
242
243/*
244 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
245 */
246#undef PVR
247
248#define RXFIFO 0
249#define TXFIFO 0
250#define STAR 0x20
251#define CMDR 0x20
252#define RSTA 0x21
253#define PRE 0x21
254#define MODE 0x22
255#define TIMR 0x23
256#define XAD1 0x24
257#define XAD2 0x25
258#define RAH1 0x26
259#define RAH2 0x27
260#define DAFO 0x27
261#define RAL1 0x28
262#define RFC 0x28
263#define RHCR 0x29
264#define RAL2 0x29
265#define RBCL 0x2a
266#define XBCL 0x2a
267#define RBCH 0x2b
268#define XBCH 0x2b
269#define CCR0 0x2c
270#define CCR1 0x2d
271#define CCR2 0x2e
272#define CCR3 0x2f
273#define VSTR 0x34
274#define BGR 0x34
275#define RLCR 0x35
276#define AML 0x36
277#define AMH 0x37
278#define GIS 0x38
279#define IVA 0x38
280#define IPC 0x39
281#define ISR 0x3a
282#define IMR 0x3a
283#define PVR 0x3c
284#define PIS 0x3d
285#define PIM 0x3d
286#define PCR 0x3e
287#define CCR4 0x3f
d12341f9 288
1da177e4 289// IMR/ISR
d12341f9 290
1da177e4
LT		 291#define IRQ_BREAK_ON BIT15 // rx break detected
292#define IRQ_DATAOVERRUN BIT14 // receive data overflow
293#define IRQ_ALLSENT BIT13 // all sent
294#define IRQ_UNDERRUN BIT12 // transmit data underrun
295#define IRQ_TIMER BIT11 // timer interrupt
296#define IRQ_CTS BIT10 // CTS status change
297#define IRQ_TXREPEAT BIT9 // tx message repeat
298#define IRQ_TXFIFO BIT8 // transmit pool ready
299#define IRQ_RXEOM BIT7 // receive message end
300#define IRQ_EXITHUNT BIT6 // receive frame start
301#define IRQ_RXTIME BIT6 // rx char timeout
302#define IRQ_DCD BIT2 // carrier detect status change
303#define IRQ_OVERRUN BIT1 // receive frame overflow
304#define IRQ_RXFIFO BIT0 // receive pool full
d12341f9 305
1da177e4 306// STAR
d12341f9 307
1da177e4
LT		 308#define XFW BIT6 // transmit FIFO write enable
309#define CEC BIT2 // command executing
310#define CTS BIT1 // CTS state
d12341f9 311
1da177e4
LT		 312#define PVR_DTR BIT0
313#define PVR_DSR BIT1
314#define PVR_RI BIT2
315#define PVR_AUTOCTS BIT3
316#define PVR_RS232 0x20 /* 0010b */
317#define PVR_V35 0xe0 /* 1110b */
318#define PVR_RS422 0x40 /* 0100b */
d12341f9
JG		 319
320/* Register access functions */
321
1da177e4
LT		 322#define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
323#define read_reg(info, reg) inb((info)->io_base + (reg))
324
d12341f9 325#define read_reg16(info, reg) inw((info)->io_base + (reg))
1da177e4 326#define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
d12341f9 327
1da177e4
LT		 328#define set_reg_bits(info, reg, mask) \
329 write_reg(info, (reg), \
d12341f9 330 (unsigned char) (read_reg(info, (reg)) | (mask)))
1da177e4
LT		 331#define clear_reg_bits(info, reg, mask) \
332 write_reg(info, (reg), \
d12341f9 333 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
1da177e4
LT		 334/*
335 * interrupt enable/disable routines
d12341f9
JG		 336 */
337static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 338{
339 if (channel == CHA) {
340 info->imra_value |= mask;
341 write_reg16(info, CHA + IMR, info->imra_value);
342 } else {
343 info->imrb_value |= mask;
344 write_reg16(info, CHB + IMR, info->imrb_value);
345 }
346}
d12341f9 347static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 348{
349 if (channel == CHA) {
350 info->imra_value &= ~mask;
351 write_reg16(info, CHA + IMR, info->imra_value);
352 } else {
353 info->imrb_value &= ~mask;
354 write_reg16(info, CHB + IMR, info->imrb_value);
355 }
356}
357
358#define port_irq_disable(info, mask) \
359 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
360
361#define port_irq_enable(info, mask) \
362 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
363
364static void rx_start(MGSLPC_INFO *info);
365static void rx_stop(MGSLPC_INFO *info);
366
eeb46134 367static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 368static void tx_stop(MGSLPC_INFO *info);
369static void tx_set_idle(MGSLPC_INFO *info);
370
371static void get_signals(MGSLPC_INFO *info);
372static void set_signals(MGSLPC_INFO *info);
373
374static void reset_device(MGSLPC_INFO *info);
375
376static void hdlc_mode(MGSLPC_INFO *info);
377static void async_mode(MGSLPC_INFO *info);
378
379static void tx_timeout(unsigned long context);
380
eeb46134 381static int carrier_raised(struct tty_port *port);
fcc8ac18 382static void dtr_rts(struct tty_port *port, int onoff);
1da177e4 383
af69c7f9 384#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 385#define dev_to_port(D) (dev_to_hdlc(D)->priv)
386static void hdlcdev_tx_done(MGSLPC_INFO *info);
387static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
388static int hdlcdev_init(MGSLPC_INFO *info);
389static void hdlcdev_exit(MGSLPC_INFO *info);
390#endif
391
392static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
393
0fab6de0
JP		 394static bool register_test(MGSLPC_INFO *info);
395static bool irq_test(MGSLPC_INFO *info);
1da177e4
LT		 396static int adapter_test(MGSLPC_INFO *info);
397
398static int claim_resources(MGSLPC_INFO *info);
399static void release_resources(MGSLPC_INFO *info);
400static void mgslpc_add_device(MGSLPC_INFO *info);
401static void mgslpc_remove_device(MGSLPC_INFO *info);
402
eeb46134 403static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 404static void rx_reset_buffers(MGSLPC_INFO *info);
405static int rx_alloc_buffers(MGSLPC_INFO *info);
406static void rx_free_buffers(MGSLPC_INFO *info);
407
7d12e780 408static irqreturn_t mgslpc_isr(int irq, void *dev_id);
1da177e4
LT		 409
410/*
411 * Bottom half interrupt handlers
412 */
c4028958 413static void bh_handler(struct work_struct *work);
eeb46134 414static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 415static void bh_status(MGSLPC_INFO *info);
416
417/*
418 * ioctl handlers
419 */
60b33c13 420static int tiocmget(struct tty_struct *tty);
20b9d177
AC		 421static int tiocmset(struct tty_struct *tty,
422 unsigned int set, unsigned int clear);
1da177e4
LT		 423static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
424static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
eeb46134 425static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
1da177e4
LT		 426static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
427static int set_txidle(MGSLPC_INFO *info, int idle_mode);
eeb46134 428static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
1da177e4
LT		 429static int tx_abort(MGSLPC_INFO *info);
430static int set_rxenable(MGSLPC_INFO *info, int enable);
431static int wait_events(MGSLPC_INFO *info, int __user *mask);
432
433static MGSLPC_INFO *mgslpc_device_list = NULL;
434static int mgslpc_device_count = 0;
435
436/*
437 * Set this param to non-zero to load eax with the
438 * .text section address and breakpoint on module load.
439 * This is useful for use with gdb and add-symbol-file command.
440 */
90ab5ee9 441static bool break_on_load=0;
1da177e4
LT		 442
443/*
444 * Driver major number, defaults to zero to get auto
445 * assigned major number. May be forced as module parameter.
446 */
447static int ttymajor=0;
448
449static int debug_level = 0;
450static int maxframe[MAX_DEVICE_COUNT] = {0,};
1da177e4
LT		 451
452module_param(break_on_load, bool, 0);
453module_param(ttymajor, int, 0);
454module_param(debug_level, int, 0);
455module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 456
457MODULE_LICENSE("GPL");
458
459static char *driver_name = "SyncLink PC Card driver";
a7482a2e 460static char *driver_version = "$Revision: 4.34 $";
1da177e4
LT		 461
462static struct tty_driver *serial_driver;
463
464/* number of characters left in xmit buffer before we ask for more */
465#define WAKEUP_CHARS 256
466
eeb46134 467static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 468static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
469
470/* PCMCIA prototypes */
471
15b99ac1 472static int mgslpc_config(struct pcmcia_device *link);
1da177e4 473static void mgslpc_release(u_long arg);
cc3b4866 474static void mgslpc_detach(struct pcmcia_device *p_dev);
1da177e4 475
1da177e4
LT		 476/*
477 * 1st function defined in .text section. Calling this function in
478 * init_module() followed by a breakpoint allows a remote debugger
479 * (gdb) to get the .text address for the add-symbol-file command.
480 * This allows remote debugging of dynamically loadable modules.
481 */
482static void* mgslpc_get_text_ptr(void)
483{
484 return mgslpc_get_text_ptr;
485}
486
487/**
488 * line discipline callback wrappers
489 *
490 * The wrappers maintain line discipline references
491 * while calling into the line discipline.
492 *
1da177e4
LT		 493 * ldisc_receive_buf - pass receive data to line discipline
494 */
495
1da177e4
LT		 496static void ldisc_receive_buf(struct tty_struct *tty,
497 const __u8 *data, char *flags, int count)
498{
499 struct tty_ldisc *ld;
500 if (!tty)
501 return;
502 ld = tty_ldisc_ref(tty);
503 if (ld) {
a352def2
AC		 504 if (ld->ops->receive_buf)
505 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 506 tty_ldisc_deref(ld);
507 }
508}
509
eeb46134
AC		 510static const struct tty_port_operations mgslpc_port_ops = {
511 .carrier_raised = carrier_raised,
fcc8ac18 512 .dtr_rts = dtr_rts
eeb46134
AC		 513};
514
15b99ac1 515static int mgslpc_probe(struct pcmcia_device *link)
1da177e4
LT		 516{
517 MGSLPC_INFO *info;
15b99ac1 518 int ret;
fd238232 519
1da177e4
LT		 520 if (debug_level >= DEBUG_LEVEL_INFO)
521 printk("mgslpc_attach\n");
fd238232 522
dd00cc48 523 info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
1da177e4
LT		 524 if (!info) {
525 printk("Error can't allocate device instance data\n");
f8cfa618 526 return -ENOMEM;
1da177e4
LT		 527 }
528
1da177e4 529 info->magic = MGSLPC_MAGIC;
eeb46134
AC		 530 tty_port_init(&info->port);
531 info->port.ops = &mgslpc_port_ops;
c4028958 532 INIT_WORK(&info->task, bh_handler);
1da177e4 533 info->max_frame_size = 4096;
eeb46134
AC		 534 info->port.close_delay = 5*HZ/10;
535 info->port.closing_wait = 30*HZ;
1da177e4
LT		 536 init_waitqueue_head(&info->status_event_wait_q);
537 init_waitqueue_head(&info->event_wait_q);
538 spin_lock_init(&info->lock);
539 spin_lock_init(&info->netlock);
540 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
d12341f9 541 info->idle_mode = HDLC_TXIDLE_FLAGS;
1da177e4
LT		 542 info->imra_value = 0xffff;
543 info->imrb_value = 0xffff;
544 info->pim_value = 0xff;
545
fba395ee 546 info->p_dev = link;
1da177e4 547 link->priv = info;
fd238232 548
fba395ee 549 /* Initialize the struct pcmcia_device structure */
1da177e4 550
15b99ac1 551 ret = mgslpc_config(link);
191c5f10
JS		 552 if (ret) {
553 tty_port_destroy(&info->port);
15b99ac1 554 return ret;
191c5f10 555 }
1da177e4
LT		 556
557 mgslpc_add_device(info);
558
f8cfa618 559 return 0;
1da177e4
LT		 560}
561
562/* Card has been inserted.
563 */
564
00990e7c 565static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
aaa8cfda 566{
90abdc3b 567 return pcmcia_request_io(p_dev);
aaa8cfda
DB		 568}
569
15b99ac1 570static int mgslpc_config(struct pcmcia_device *link)
1da177e4 571{
1da177e4 572 MGSLPC_INFO *info = link->priv;
cbf624f0 573 int ret;
d12341f9 574
1da177e4
LT		 575 if (debug_level >= DEBUG_LEVEL_INFO)
576 printk("mgslpc_config(0x%p)\n", link);
577
00990e7c
DB		 578 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
579
cbf624f0
DB		 580 ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
581 if (ret != 0)
582 goto failed;
1da177e4 583
7feabb64
DB		 584 link->config_index = 8;
585 link->config_regs = PRESENT_OPTION;
d12341f9 586
eb14120f 587 ret = pcmcia_request_irq(link, mgslpc_isr);
cbf624f0
DB		 588 if (ret)
589 goto failed;
1ac71e5a 590 ret = pcmcia_enable_device(link);
cbf624f0
DB		 591 if (ret)
592 goto failed;
1da177e4 593
9a017a91 594 info->io_base = link->resource[0]->start;
eb14120f 595 info->irq_level = link->irq;
15b99ac1 596 return 0;
1da177e4 597
cbf624f0 598failed:
1da177e4 599 mgslpc_release((u_long)link);
15b99ac1 600 return -ENODEV;
1da177e4
LT		 601}
602
603/* Card has been removed.
604 * Unregister device and release PCMCIA configuration.
605 * If device is open, postpone until it is closed.
606 */
607static void mgslpc_release(u_long arg)
608{
e2d40963 609 struct pcmcia_device *link = (struct pcmcia_device *)arg;
1da177e4 610
e2d40963
DB		 611 if (debug_level >= DEBUG_LEVEL_INFO)
612 printk("mgslpc_release(0x%p)\n", link);
1da177e4 613
e2d40963 614 pcmcia_disable_device(link);
1da177e4
LT		 615}
616
fba395ee 617static void mgslpc_detach(struct pcmcia_device *link)
1da177e4 618{
e2d40963
DB		 619 if (debug_level >= DEBUG_LEVEL_INFO)
620 printk("mgslpc_detach(0x%p)\n", link);
cc3b4866 621
e2d40963
DB		 622 ((MGSLPC_INFO *)link->priv)->stop = 1;
623 mgslpc_release((u_long)link);
1da177e4 624
e2d40963 625 mgslpc_remove_device((MGSLPC_INFO *)link->priv);
1da177e4
LT		 626}
627
fba395ee 628static int mgslpc_suspend(struct pcmcia_device *link)
98e4c28b 629{
98e4c28b
DB		 630 MGSLPC_INFO *info = link->priv;
631
98e4c28b 632 info->stop = 1;
98e4c28b
DB		 633
634 return 0;
635}
636
fba395ee 637static int mgslpc_resume(struct pcmcia_device *link)
98e4c28b 638{
98e4c28b
DB		 639 MGSLPC_INFO *info = link->priv;
640
98e4c28b
DB		 641 info->stop = 0;
642
643 return 0;
644}
645
646
0fab6de0 647static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
1da177e4
LT		 648 char *name, const char *routine)
649{
650#ifdef MGSLPC_PARANOIA_CHECK
651 static const char *badmagic =
652 "Warning: bad magic number for mgsl struct (%s) in %s\n";
653 static const char *badinfo =
654 "Warning: null mgslpc_info for (%s) in %s\n";
655
656 if (!info) {
657 printk(badinfo, name, routine);
0fab6de0 658 return true;
1da177e4
LT		 659 }
660 if (info->magic != MGSLPC_MAGIC) {
661 printk(badmagic, name, routine);
0fab6de0 662 return true;
1da177e4
LT		 663 }
664#else
665 if (!info)
0fab6de0 666 return true;
1da177e4 667#endif
0fab6de0 668 return false;
1da177e4
LT		 669}
670
671
672#define CMD_RXFIFO BIT7 // release current rx FIFO
673#define CMD_RXRESET BIT6 // receiver reset
674#define CMD_RXFIFO_READ BIT5
675#define CMD_START_TIMER BIT4
676#define CMD_TXFIFO BIT3 // release current tx FIFO
677#define CMD_TXEOM BIT1 // transmit end message
678#define CMD_TXRESET BIT0 // transmit reset
679
0fab6de0 680static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
1da177e4
LT		 681{
682 int i = 0;
d12341f9 683 /* wait for command completion */
1da177e4
LT		 684 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
685 udelay(1);
686 if (i++ == 1000)
0fab6de0 687 return false;
1da177e4 688 }
0fab6de0 689 return true;
1da177e4
LT		 690}
691
d12341f9 692static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
1da177e4
LT		 693{
694 wait_command_complete(info, channel);
695 write_reg(info, (unsigned char) (channel + CMDR), cmd);
696}
697
698static void tx_pause(struct tty_struct *tty)
699{
700 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
701 unsigned long flags;
d12341f9 702
1da177e4
LT		 703 if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
704 return;
705 if (debug_level >= DEBUG_LEVEL_INFO)
d12341f9
JG		 706 printk("tx_pause(%s)\n",info->device_name);
707
1da177e4
LT		 708 spin_lock_irqsave(&info->lock,flags);
709 if (info->tx_enabled)
710 tx_stop(info);
711 spin_unlock_irqrestore(&info->lock,flags);
712}
713
714static void tx_release(struct tty_struct *tty)
715{
716 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
717 unsigned long flags;
d12341f9 718
1da177e4
LT		 719 if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
720 return;
721 if (debug_level >= DEBUG_LEVEL_INFO)
d12341f9
JG		 722 printk("tx_release(%s)\n",info->device_name);
723
1da177e4
LT		 724 spin_lock_irqsave(&info->lock,flags);
725 if (!info->tx_enabled)
eeb46134 726 tx_start(info, tty);
1da177e4
LT		 727 spin_unlock_irqrestore(&info->lock,flags);
728}
729
730/* Return next bottom half action to perform.
731 * or 0 if nothing to do.
732 */
733static int bh_action(MGSLPC_INFO *info)
734{
735 unsigned long flags;
736 int rc = 0;
d12341f9 737
1da177e4
LT		 738 spin_lock_irqsave(&info->lock,flags);
739
740 if (info->pending_bh & BH_RECEIVE) {
741 info->pending_bh &= ~BH_RECEIVE;
742 rc = BH_RECEIVE;
743 } else if (info->pending_bh & BH_TRANSMIT) {
744 info->pending_bh &= ~BH_TRANSMIT;
745 rc = BH_TRANSMIT;
746 } else if (info->pending_bh & BH_STATUS) {
747 info->pending_bh &= ~BH_STATUS;
748 rc = BH_STATUS;
749 }
750
751 if (!rc) {
752 /* Mark BH routine as complete */
0fab6de0
JP		 753 info->bh_running = false;
754 info->bh_requested = false;
1da177e4 755 }
d12341f9 756
1da177e4 757 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 758
1da177e4
LT		 759 return rc;
760}
761
c4028958 762static void bh_handler(struct work_struct *work)
1da177e4 763{
c4028958 764 MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
eeb46134 765 struct tty_struct *tty;
1da177e4
LT		 766 int action;
767
768 if (!info)
769 return;
d12341f9 770
1da177e4
LT		 771 if (debug_level >= DEBUG_LEVEL_BH)
772 printk( "%s(%d):bh_handler(%s) entry\n",
773 __FILE__,__LINE__,info->device_name);
d12341f9 774
0fab6de0 775 info->bh_running = true;
eeb46134 776 tty = tty_port_tty_get(&info->port);
1da177e4
LT		 777
778 while((action = bh_action(info)) != 0) {
d12341f9 779
1da177e4
LT		 780 /* Process work item */
781 if ( debug_level >= DEBUG_LEVEL_BH )
782 printk( "%s(%d):bh_handler() work item action=%d\n",
783 __FILE__,__LINE__,action);
784
785 switch (action) {
d12341f9 786
1da177e4 787 case BH_RECEIVE:
eeb46134 788 while(rx_get_frame(info, tty));
1da177e4
LT		 789 break;
790 case BH_TRANSMIT:
eeb46134 791 bh_transmit(info, tty);
1da177e4
LT		 792 break;
793 case BH_STATUS:
794 bh_status(info);
795 break;
796 default:
797 /* unknown work item ID */
798 printk("Unknown work item ID=%08X!\n", action);
799 break;
800 }
801 }
802
eeb46134 803 tty_kref_put(tty);
1da177e4
LT		 804 if (debug_level >= DEBUG_LEVEL_BH)
805 printk( "%s(%d):bh_handler(%s) exit\n",
806 __FILE__,__LINE__,info->device_name);
807}
808
eeb46134 809static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4 810{
1da177e4
LT		 811 if (debug_level >= DEBUG_LEVEL_BH)
812 printk("bh_transmit() entry on %s\n", info->device_name);
813
b963a844 814 if (tty)
1da177e4 815 tty_wakeup(tty);
1da177e4
LT		 816}
817
cdaad343 818static void bh_status(MGSLPC_INFO *info)
1da177e4
LT		 819{
820 info->ri_chkcount = 0;
821 info->dsr_chkcount = 0;
822 info->dcd_chkcount = 0;
823 info->cts_chkcount = 0;
824}
825
d12341f9 826/* eom: non-zero = end of frame */
1da177e4
LT		 827static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
828{
829 unsigned char data[2];
830 unsigned char fifo_count, read_count, i;
831 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
832
833 if (debug_level >= DEBUG_LEVEL_ISR)
834 printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
d12341f9 835
1da177e4
LT		 836 if (!info->rx_enabled)
837 return;
838
839 if (info->rx_frame_count >= info->rx_buf_count) {
840 /* no more free buffers */
841 issue_command(info, CHA, CMD_RXRESET);
842 info->pending_bh |= BH_RECEIVE;
0fab6de0 843 info->rx_overflow = true;
1da177e4
LT		 844 info->icount.buf_overrun++;
845 return;
846 }
847
848 if (eom) {
d12341f9 849 /* end of frame, get FIFO count from RBCL register */
1da177e4
LT		 850 if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
851 fifo_count = 32;
852 } else
853 fifo_count = 32;
d12341f9 854
1da177e4
LT		 855 do {
856 if (fifo_count == 1) {
857 read_count = 1;
858 data[0] = read_reg(info, CHA + RXFIFO);
859 } else {
860 read_count = 2;
861 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
862 }
863 fifo_count -= read_count;
864 if (!fifo_count && eom)
865 buf->status = data[--read_count];
866
867 for (i = 0; i < read_count; i++) {
868 if (buf->count >= info->max_frame_size) {
869 /* frame too large, reset receiver and reset current buffer */
870 issue_command(info, CHA, CMD_RXRESET);
871 buf->count = 0;
872 return;
873 }
874 *(buf->data + buf->count) = data[i];
875 buf->count++;
876 }
877 } while (fifo_count);
878
879 if (eom) {
880 info->pending_bh |= BH_RECEIVE;
881 info->rx_frame_count++;
882 info->rx_put++;
883 if (info->rx_put >= info->rx_buf_count)
884 info->rx_put = 0;
885 }
886 issue_command(info, CHA, CMD_RXFIFO);
887}
888
eeb46134 889static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
1da177e4 890{
227434f8 891 struct tty_port *port = &info->port;
33f0f88f 892 unsigned char data, status, flag;
1da177e4 893 int fifo_count;
33f0f88f 894 int work = 0;
1da177e4
LT		 895 struct mgsl_icount *icount = &info->icount;
896
221b7b57
AK		 897 if (!tty) {
898 /* tty is not available anymore */
899 issue_command(info, CHA, CMD_RXRESET);
900 if (debug_level >= DEBUG_LEVEL_ISR)
901 printk("%s(%d):rx_ready_async(tty=NULL)\n",__FILE__,__LINE__);
902 return;
903 }
904
1da177e4 905 if (tcd) {
d12341f9 906 /* early termination, get FIFO count from RBCL register */
1da177e4
LT		 907 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
908
909 /* Zero fifo count could mean 0 or 32 bytes available.
910 * If BIT5 of STAR is set then at least 1 byte is available.
911 */
912 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
913 fifo_count = 32;
914 } else
915 fifo_count = 32;
33f0f88f 916
227434f8 917 tty_buffer_request_room(port, fifo_count);
d12341f9 918 /* Flush received async data to receive data buffer. */
1da177e4
LT		 919 while (fifo_count) {
920 data = read_reg(info, CHA + RXFIFO);
921 status = read_reg(info, CHA + RXFIFO);
922 fifo_count -= 2;
923
1da177e4 924 icount->rx++;
33f0f88f 925 flag = TTY_NORMAL;
1da177e4
LT		 926
927 // if no frameing/crc error then save data
928 // BIT7:parity error
929 // BIT6:framing error
930
931 if (status & (BIT7 + BIT6)) {
d12341f9 932 if (status & BIT7)
1da177e4
LT		 933 icount->parity++;
934 else
935 icount->frame++;
936
937 /* discard char if tty control flags say so */
938 if (status & info->ignore_status_mask)
939 continue;
d12341f9 940
1da177e4
LT		 941 status &= info->read_status_mask;
942
943 if (status & BIT7)
33f0f88f 944 flag = TTY_PARITY;
1da177e4 945 else if (status & BIT6)
33f0f88f 946 flag = TTY_FRAME;
1da177e4 947 }
92a19f9c 948 work += tty_insert_flip_char(port, data, flag);
1da177e4
LT		 949 }
950 issue_command(info, CHA, CMD_RXFIFO);
951
952 if (debug_level >= DEBUG_LEVEL_ISR) {
33f0f88f
AC		 953 printk("%s(%d):rx_ready_async",
954 __FILE__,__LINE__);
1da177e4
LT		 955 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
956 __FILE__,__LINE__,icount->rx,icount->brk,
957 icount->parity,icount->frame,icount->overrun);
958 }
d12341f9 959
33f0f88f 960 if (work)
1da177e4
LT		 961 tty_flip_buffer_push(tty);
962}
963
964
eeb46134 965static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 966{
967 if (!info->tx_active)
968 return;
d12341f9 969
0fab6de0
JP		 970 info->tx_active = false;
971 info->tx_aborting = false;
1da177e4
LT		 972
973 if (info->params.mode == MGSL_MODE_ASYNC)
974 return;
975
976 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9
JG		 977 del_timer(&info->tx_timer);
978
1da177e4
LT		 979 if (info->drop_rts_on_tx_done) {
980 get_signals(info);
981 if (info->serial_signals & SerialSignal_RTS) {
982 info->serial_signals &= ~SerialSignal_RTS;
983 set_signals(info);
984 }
0fab6de0 985 info->drop_rts_on_tx_done = false;
1da177e4
LT		 986 }
987
af69c7f9 988#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 989 if (info->netcount)
990 hdlcdev_tx_done(info);
d12341f9 991 else
1da177e4
LT		 992#endif
993 {
221b7b57 994 if (tty && (tty->stopped || tty->hw_stopped)) {
1da177e4
LT		 995 tx_stop(info);
996 return;
997 }
998 info->pending_bh |= BH_TRANSMIT;
999 }
1000}
1001
eeb46134 1002static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1003{
1004 unsigned char fifo_count = 32;
1005 int c;
1006
1007 if (debug_level >= DEBUG_LEVEL_ISR)
1008 printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
1009
1010 if (info->params.mode == MGSL_MODE_HDLC) {
1011 if (!info->tx_active)
1012 return;
1013 } else {
221b7b57 1014 if (tty && (tty->stopped || tty->hw_stopped)) {
1da177e4
LT		 1015 tx_stop(info);
1016 return;
1017 }
1018 if (!info->tx_count)
0fab6de0 1019 info->tx_active = false;
1da177e4
LT		 1020 }
1021
1022 if (!info->tx_count)
1023 return;
1024
1025 while (info->tx_count && fifo_count) {
1026 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
d12341f9 1027
1da177e4
LT		 1028 if (c == 1) {
1029 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
1030 } else {
1031 write_reg16(info, CHA + TXFIFO,
1032 *((unsigned short*)(info->tx_buf + info->tx_get)));
1033 }
1034 info->tx_count -= c;
1035 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
1036 fifo_count -= c;
1037 }
1038
1039 if (info->params.mode == MGSL_MODE_ASYNC) {
1040 if (info->tx_count < WAKEUP_CHARS)
1041 info->pending_bh |= BH_TRANSMIT;
1042 issue_command(info, CHA, CMD_TXFIFO);
1043 } else {
1044 if (info->tx_count)
1045 issue_command(info, CHA, CMD_TXFIFO);
1046 else
1047 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
1048 }
1049}
1050
eeb46134 1051static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1052{
1053 get_signals(info);
1054 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1055 irq_disable(info, CHB, IRQ_CTS);
1056 info->icount.cts++;
1057 if (info->serial_signals & SerialSignal_CTS)
1058 info->input_signal_events.cts_up++;
1059 else
1060 info->input_signal_events.cts_down++;
1061 wake_up_interruptible(&info->status_event_wait_q);
1062 wake_up_interruptible(&info->event_wait_q);
1063
3498d13b 1064 if (tty && tty_port_cts_enabled(&info->port)) {
eeb46134 1065 if (tty->hw_stopped) {
1da177e4
LT		 1066 if (info->serial_signals & SerialSignal_CTS) {
1067 if (debug_level >= DEBUG_LEVEL_ISR)
1068 printk("CTS tx start...");
221b7b57 1069 tty->hw_stopped = 0;
eeb46134 1070 tx_start(info, tty);
1da177e4
LT		 1071 info->pending_bh |= BH_TRANSMIT;
1072 return;
1073 }
1074 } else {
1075 if (!(info->serial_signals & SerialSignal_CTS)) {
1076 if (debug_level >= DEBUG_LEVEL_ISR)
1077 printk("CTS tx stop...");
221b7b57 1078 tty->hw_stopped = 1;
1da177e4
LT		 1079 tx_stop(info);
1080 }
1081 }
1082 }
1083 info->pending_bh |= BH_STATUS;
1084}
1085
eeb46134 1086static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1087{
1088 get_signals(info);
1089 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1090 irq_disable(info, CHB, IRQ_DCD);
1091 info->icount.dcd++;
1092 if (info->serial_signals & SerialSignal_DCD) {
1093 info->input_signal_events.dcd_up++;
1094 }
1095 else
1096 info->input_signal_events.dcd_down++;
af69c7f9 1097#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1098 if (info->netcount) {
1099 if (info->serial_signals & SerialSignal_DCD)
1100 netif_carrier_on(info->netdev);
1101 else
1102 netif_carrier_off(info->netdev);
1103 }
1da177e4
LT		 1104#endif
1105 wake_up_interruptible(&info->status_event_wait_q);
1106 wake_up_interruptible(&info->event_wait_q);
1107
eeb46134 1108 if (info->port.flags & ASYNC_CHECK_CD) {
1da177e4
LT		 1109 if (debug_level >= DEBUG_LEVEL_ISR)
1110 printk("%s CD now %s...", info->device_name,
1111 (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
1112 if (info->serial_signals & SerialSignal_DCD)
eeb46134 1113 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1114 else {
1115 if (debug_level >= DEBUG_LEVEL_ISR)
1116 printk("doing serial hangup...");
eeb46134
AC		 1117 if (tty)
1118 tty_hangup(tty);
1da177e4
LT		 1119 }
1120 }
1121 info->pending_bh |= BH_STATUS;
1122}
1123
1124static void dsr_change(MGSLPC_INFO *info)
1125{
1126 get_signals(info);
1127 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1128 port_irq_disable(info, PVR_DSR);
1129 info->icount.dsr++;
1130 if (info->serial_signals & SerialSignal_DSR)
1131 info->input_signal_events.dsr_up++;
1132 else
1133 info->input_signal_events.dsr_down++;
1134 wake_up_interruptible(&info->status_event_wait_q);
1135 wake_up_interruptible(&info->event_wait_q);
1136 info->pending_bh |= BH_STATUS;
1137}
1138
1139static void ri_change(MGSLPC_INFO *info)
1140{
1141 get_signals(info);
1142 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1143 port_irq_disable(info, PVR_RI);
1144 info->icount.rng++;
1145 if (info->serial_signals & SerialSignal_RI)
1146 info->input_signal_events.ri_up++;
1147 else
1148 info->input_signal_events.ri_down++;
1149 wake_up_interruptible(&info->status_event_wait_q);
1150 wake_up_interruptible(&info->event_wait_q);
1151 info->pending_bh |= BH_STATUS;
1152}
1153
1154/* Interrupt service routine entry point.
d12341f9 1155 *
1da177e4 1156 * Arguments:
d12341f9 1157 *
1da177e4
LT		 1158 * irq interrupt number that caused interrupt
1159 * dev_id device ID supplied during interrupt registration
1da177e4 1160 */
a6f97b29 1161static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
1da177e4 1162{
a6f97b29 1163 MGSLPC_INFO *info = dev_id;
eeb46134 1164 struct tty_struct *tty;
1da177e4
LT		 1165 unsigned short isr;
1166 unsigned char gis, pis;
1167 int count=0;
1168
d12341f9 1169 if (debug_level >= DEBUG_LEVEL_ISR)
a6f97b29 1170 printk("mgslpc_isr(%d) entry.\n", info->irq_level);
d12341f9 1171
e2d40963 1172 if (!(info->p_dev->_locked))
1da177e4
LT		 1173 return IRQ_HANDLED;
1174
eeb46134
AC		 1175 tty = tty_port_tty_get(&info->port);
1176
1da177e4
LT		 1177 spin_lock(&info->lock);
1178
1179 while ((gis = read_reg(info, CHA + GIS))) {
d12341f9 1180 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4
LT		 1181 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
1182
1183 if ((gis & 0x70) || count > 1000) {
1184 printk("synclink_cs:hardware failed or ejected\n");
1185 break;
1186 }
1187 count++;
1188
1189 if (gis & (BIT1 + BIT0)) {
1190 isr = read_reg16(info, CHB + ISR);
1191 if (isr & IRQ_DCD)
eeb46134 1192 dcd_change(info, tty);
1da177e4 1193 if (isr & IRQ_CTS)
eeb46134 1194 cts_change(info, tty);
1da177e4
LT		 1195 }
1196 if (gis & (BIT3 + BIT2))
1197 {
1198 isr = read_reg16(info, CHA + ISR);
1199 if (isr & IRQ_TIMER) {
0fab6de0 1200 info->irq_occurred = true;
1da177e4
LT		 1201 irq_disable(info, CHA, IRQ_TIMER);
1202 }
1203
d12341f9 1204 /* receive IRQs */
1da177e4
LT		 1205 if (isr & IRQ_EXITHUNT) {
1206 info->icount.exithunt++;
1207 wake_up_interruptible(&info->event_wait_q);
1208 }
1209 if (isr & IRQ_BREAK_ON) {
1210 info->icount.brk++;
eeb46134
AC		 1211 if (info->port.flags & ASYNC_SAK)
1212 do_SAK(tty);
1da177e4
LT		 1213 }
1214 if (isr & IRQ_RXTIME) {
1215 issue_command(info, CHA, CMD_RXFIFO_READ);
1216 }
1217 if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
1218 if (info->params.mode == MGSL_MODE_HDLC)
d12341f9 1219 rx_ready_hdlc(info, isr & IRQ_RXEOM);
1da177e4 1220 else
eeb46134 1221 rx_ready_async(info, isr & IRQ_RXEOM, tty);
1da177e4
LT		 1222 }
1223
d12341f9 1224 /* transmit IRQs */
1da177e4
LT		 1225 if (isr & IRQ_UNDERRUN) {
1226 if (info->tx_aborting)
1227 info->icount.txabort++;
1228 else
1229 info->icount.txunder++;
eeb46134 1230 tx_done(info, tty);
1da177e4
LT		 1231 }
1232 else if (isr & IRQ_ALLSENT) {
1233 info->icount.txok++;
eeb46134 1234 tx_done(info, tty);
1da177e4
LT		 1235 }
1236 else if (isr & IRQ_TXFIFO)
eeb46134 1237 tx_ready(info, tty);
1da177e4
LT		 1238 }
1239 if (gis & BIT7) {
1240 pis = read_reg(info, CHA + PIS);
1241 if (pis & BIT1)
1242 dsr_change(info);
1243 if (pis & BIT2)
1244 ri_change(info);
1245 }
1246 }
d12341f9
JG		 1247
1248 /* Request bottom half processing if there's something
1da177e4
LT		 1249 * for it to do and the bh is not already running
1250 */
1251
1252 if (info->pending_bh && !info->bh_running && !info->bh_requested) {
d12341f9 1253 if ( debug_level >= DEBUG_LEVEL_ISR )
1da177e4
LT		 1254 printk("%s(%d):%s queueing bh task.\n",
1255 __FILE__,__LINE__,info->device_name);
1256 schedule_work(&info->task);
0fab6de0 1257 info->bh_requested = true;
1da177e4
LT		 1258 }
1259
1260 spin_unlock(&info->lock);
eeb46134 1261 tty_kref_put(tty);
d12341f9
JG		 1262
1263 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4 1264 printk("%s(%d):mgslpc_isr(%d)exit.\n",
a6f97b29 1265 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 1266
1267 return IRQ_HANDLED;
1268}
1269
1270/* Initialize and start device.
1271 */
eeb46134 1272static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1273{
1274 int retval = 0;
d12341f9 1275
1da177e4
LT		 1276 if (debug_level >= DEBUG_LEVEL_INFO)
1277 printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
d12341f9 1278
eeb46134 1279 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4 1280 return 0;
d12341f9 1281
1da177e4
LT		 1282 if (!info->tx_buf) {
1283 /* allocate a page of memory for a transmit buffer */
1284 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1285 if (!info->tx_buf) {
1286 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1287 __FILE__,__LINE__,info->device_name);
1288 return -ENOMEM;
1289 }
1290 }
1291
1292 info->pending_bh = 0;
d12341f9 1293
a7482a2e
PF		 1294 memset(&info->icount, 0, sizeof(info->icount));
1295
40565f19 1296 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
1da177e4
LT		 1297
1298 /* Allocate and claim adapter resources */
1299 retval = claim_resources(info);
d12341f9 1300
25985edc 1301 /* perform existence check and diagnostics */
1da177e4
LT		 1302 if ( !retval )
1303 retval = adapter_test(info);
d12341f9 1304
1da177e4 1305 if ( retval ) {
eeb46134
AC		 1306 if (capable(CAP_SYS_ADMIN) && tty)
1307 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4
LT		 1308 release_resources(info);
1309 return retval;
1310 }
1311
1312 /* program hardware for current parameters */
eeb46134 1313 mgslpc_change_params(info, tty);
d12341f9 1314
eeb46134
AC		 1315 if (tty)
1316 clear_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1317
eeb46134 1318 info->port.flags |= ASYNC_INITIALIZED;
d12341f9 1319
1da177e4
LT		 1320 return 0;
1321}
1322
1323/* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
1324 */
eeb46134 1325static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1326{
1327 unsigned long flags;
d12341f9 1328
eeb46134 1329 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 1330 return;
1331
1332 if (debug_level >= DEBUG_LEVEL_INFO)
1333 printk("%s(%d):mgslpc_shutdown(%s)\n",
1334 __FILE__,__LINE__, info->device_name );
1335
1336 /* clear status wait queue because status changes */
1337 /* can't happen after shutting down the hardware */
1338 wake_up_interruptible(&info->status_event_wait_q);
1339 wake_up_interruptible(&info->event_wait_q);
1340
40565f19 1341 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1342
1343 if (info->tx_buf) {
1344 free_page((unsigned long) info->tx_buf);
1345 info->tx_buf = NULL;
1346 }
1347
1348 spin_lock_irqsave(&info->lock,flags);
1349
1350 rx_stop(info);
1351 tx_stop(info);
1352
1353 /* TODO:disable interrupts instead of reset to preserve signal states */
1354 reset_device(info);
d12341f9 1355
373f5aed 1356 if (!tty || tty->termios.c_cflag & HUPCL) {
1da177e4
LT		 1357 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1358 set_signals(info);
1359 }
d12341f9 1360
1da177e4
LT		 1361 spin_unlock_irqrestore(&info->lock,flags);
1362
d12341f9
JG		 1363 release_resources(info);
1364
eeb46134
AC		 1365 if (tty)
1366 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1367
eeb46134 1368 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 1369}
1370
eeb46134 1371static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1372{
1373 unsigned long flags;
1374
1375 spin_lock_irqsave(&info->lock,flags);
d12341f9 1376
1da177e4
LT		 1377 rx_stop(info);
1378 tx_stop(info);
1379 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1380
1da177e4
LT		 1381 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1382 hdlc_mode(info);
1383 else
1384 async_mode(info);
d12341f9 1385
1da177e4 1386 set_signals(info);
d12341f9 1387
1da177e4
LT		 1388 info->dcd_chkcount = 0;
1389 info->cts_chkcount = 0;
1390 info->ri_chkcount = 0;
1391 info->dsr_chkcount = 0;
1392
1393 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
1394 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
1395 get_signals(info);
d12341f9 1396
373f5aed 1397 if (info->netcount || (tty && (tty->termios.c_cflag & CREAD)))
1da177e4 1398 rx_start(info);
d12341f9 1399
1da177e4
LT		 1400 spin_unlock_irqrestore(&info->lock,flags);
1401}
1402
1403/* Reconfigure adapter based on new parameters
1404 */
eeb46134 1405static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1406{
1407 unsigned cflag;
1408 int bits_per_char;
1409
373f5aed 1410 if (!tty)
1da177e4 1411 return;
d12341f9 1412
1da177e4
LT		 1413 if (debug_level >= DEBUG_LEVEL_INFO)
1414 printk("%s(%d):mgslpc_change_params(%s)\n",
1415 __FILE__,__LINE__, info->device_name );
d12341f9 1416
373f5aed 1417 cflag = tty->termios.c_cflag;
1da177e4
LT		 1418
1419 /* if B0 rate (hangup) specified then negate DTR and RTS */
1420 /* otherwise assert DTR and RTS */
1421 if (cflag & CBAUD)
1422 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1423 else
1424 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
d12341f9 1425
1da177e4 1426 /* byte size and parity */
d12341f9 1427
1da177e4
LT		 1428 switch (cflag & CSIZE) {
1429 case CS5: info->params.data_bits = 5; break;
1430 case CS6: info->params.data_bits = 6; break;
1431 case CS7: info->params.data_bits = 7; break;
1432 case CS8: info->params.data_bits = 8; break;
1433 default: info->params.data_bits = 7; break;
1434 }
d12341f9 1435
1da177e4
LT		 1436 if (cflag & CSTOPB)
1437 info->params.stop_bits = 2;
1438 else
1439 info->params.stop_bits = 1;
1440
1441 info->params.parity = ASYNC_PARITY_NONE;
1442 if (cflag & PARENB) {
1443 if (cflag & PARODD)
1444 info->params.parity = ASYNC_PARITY_ODD;
1445 else
1446 info->params.parity = ASYNC_PARITY_EVEN;
1447#ifdef CMSPAR
1448 if (cflag & CMSPAR)
1449 info->params.parity = ASYNC_PARITY_SPACE;
1450#endif
1451 }
1452
1453 /* calculate number of jiffies to transmit a full
1454 * FIFO (32 bytes) at specified data rate
1455 */
d12341f9 1456 bits_per_char = info->params.data_bits +
1da177e4
LT		 1457 info->params.stop_bits + 1;
1458
1459 /* if port data rate is set to 460800 or less then
1460 * allow tty settings to override, otherwise keep the
1461 * current data rate.
1462 */
1463 if (info->params.data_rate <= 460800) {
eeb46134 1464 info->params.data_rate = tty_get_baud_rate(tty);
1da177e4 1465 }
d12341f9 1466
1da177e4 1467 if ( info->params.data_rate ) {
d12341f9 1468 info->timeout = (32*HZ*bits_per_char) /
1da177e4
LT		 1469 info->params.data_rate;
1470 }
1471 info->timeout += HZ/50; /* Add .02 seconds of slop */
1472
1473 if (cflag & CRTSCTS)
eeb46134 1474 info->port.flags |= ASYNC_CTS_FLOW;
1da177e4 1475 else
eeb46134 1476 info->port.flags &= ~ASYNC_CTS_FLOW;
d12341f9 1477
1da177e4 1478 if (cflag & CLOCAL)
eeb46134 1479 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 1480 else
eeb46134 1481 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 1482
1483 /* process tty input control flags */
d12341f9 1484
1da177e4 1485 info->read_status_mask = 0;
eeb46134 1486 if (I_INPCK(tty))
1da177e4 1487 info->read_status_mask |= BIT7 | BIT6;
eeb46134 1488 if (I_IGNPAR(tty))
1da177e4
LT		 1489 info->ignore_status_mask |= BIT7 | BIT6;
1490
eeb46134 1491 mgslpc_program_hw(info, tty);
1da177e4
LT		 1492}
1493
1494/* Add a character to the transmit buffer
1495 */
d7e752e2 1496static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4
LT		 1497{
1498 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1499 unsigned long flags;
1500
1501 if (debug_level >= DEBUG_LEVEL_INFO) {
1502 printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
1503 __FILE__,__LINE__,ch,info->device_name);
1504 }
1505
1506 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
d7e752e2 1507 return 0;
1da177e4 1508
326f28e9 1509 if (!info->tx_buf)
d7e752e2 1510 return 0;
1da177e4
LT		 1511
1512 spin_lock_irqsave(&info->lock,flags);
d12341f9 1513
1da177e4
LT		 1514 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
1515 if (info->tx_count < TXBUFSIZE - 1) {
1516 info->tx_buf[info->tx_put++] = ch;
1517 info->tx_put &= TXBUFSIZE-1;
1518 info->tx_count++;
1519 }
1520 }
d12341f9 1521
1da177e4 1522 spin_unlock_irqrestore(&info->lock,flags);
d7e752e2 1523 return 1;
1da177e4
LT		 1524}
1525
1526/* Enable transmitter so remaining characters in the
1527 * transmit buffer are sent.
1528 */
1529static void mgslpc_flush_chars(struct tty_struct *tty)
1530{
1531 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1532 unsigned long flags;
d12341f9 1533
1da177e4
LT		 1534 if (debug_level >= DEBUG_LEVEL_INFO)
1535 printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
1536 __FILE__,__LINE__,info->device_name,info->tx_count);
d12341f9 1537
1da177e4
LT		 1538 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
1539 return;
1540
1541 if (info->tx_count <= 0 || tty->stopped ||
1542 tty->hw_stopped || !info->tx_buf)
1543 return;
1544
1545 if (debug_level >= DEBUG_LEVEL_INFO)
1546 printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
1547 __FILE__,__LINE__,info->device_name);
1548
1549 spin_lock_irqsave(&info->lock,flags);
1550 if (!info->tx_active)
eeb46134 1551 tx_start(info, tty);
1da177e4
LT		 1552 spin_unlock_irqrestore(&info->lock,flags);
1553}
1554
1555/* Send a block of data
d12341f9 1556 *
1da177e4 1557 * Arguments:
d12341f9 1558 *
1da177e4
LT		 1559 * tty pointer to tty information structure
1560 * buf pointer to buffer containing send data
1561 * count size of send data in bytes
d12341f9 1562 *
1da177e4
LT		 1563 * Returns: number of characters written
1564 */
1565static int mgslpc_write(struct tty_struct * tty,
1566 const unsigned char *buf, int count)
1567{
1568 int c, ret = 0;
1569 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1570 unsigned long flags;
d12341f9 1571
1da177e4
LT		 1572 if (debug_level >= DEBUG_LEVEL_INFO)
1573 printk( "%s(%d):mgslpc_write(%s) count=%d\n",
1574 __FILE__,__LINE__,info->device_name,count);
d12341f9 1575
1da177e4 1576 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
326f28e9 1577 !info->tx_buf)
1da177e4
LT		 1578 goto cleanup;
1579
1580 if (info->params.mode == MGSL_MODE_HDLC) {
1581 if (count > TXBUFSIZE) {
1582 ret = -EIO;
1583 goto cleanup;
1584 }
1585 if (info->tx_active)
1586 goto cleanup;
1587 else if (info->tx_count)
1588 goto start;
1589 }
1590
1591 for (;;) {
1592 c = min(count,
1593 min(TXBUFSIZE - info->tx_count - 1,
1594 TXBUFSIZE - info->tx_put));
1595 if (c <= 0)
1596 break;
d12341f9 1597
1da177e4
LT		 1598 memcpy(info->tx_buf + info->tx_put, buf, c);
1599
1600 spin_lock_irqsave(&info->lock,flags);
1601 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
1602 info->tx_count += c;
1603 spin_unlock_irqrestore(&info->lock,flags);
1604
1605 buf += c;
1606 count -= c;
1607 ret += c;
1608 }
1609start:
1610 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1611 spin_lock_irqsave(&info->lock,flags);
1612 if (!info->tx_active)
eeb46134 1613 tx_start(info, tty);
1da177e4
LT		 1614 spin_unlock_irqrestore(&info->lock,flags);
1615 }
d12341f9 1616cleanup:
1da177e4
LT		 1617 if (debug_level >= DEBUG_LEVEL_INFO)
1618 printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
1619 __FILE__,__LINE__,info->device_name,ret);
1620 return ret;
1621}
1622
1623/* Return the count of free bytes in transmit buffer
1624 */
1625static int mgslpc_write_room(struct tty_struct *tty)
1626{
1627 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1628 int ret;
d12341f9 1629
1da177e4
LT		 1630 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
1631 return 0;
1632
1633 if (info->params.mode == MGSL_MODE_HDLC) {
1634 /* HDLC (frame oriented) mode */
1635 if (info->tx_active)
1636 return 0;
1637 else
1638 return HDLC_MAX_FRAME_SIZE;
1639 } else {
1640 ret = TXBUFSIZE - info->tx_count - 1;
1641 if (ret < 0)
1642 ret = 0;
1643 }
d12341f9 1644
1da177e4
LT		 1645 if (debug_level >= DEBUG_LEVEL_INFO)
1646 printk("%s(%d):mgslpc_write_room(%s)=%d\n",
1647 __FILE__,__LINE__, info->device_name, ret);
1648 return ret;
1649}
1650
1651/* Return the count of bytes in transmit buffer
1652 */
1653static int mgslpc_chars_in_buffer(struct tty_struct *tty)
1654{
1655 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1656 int rc;
d12341f9 1657
1da177e4
LT		 1658 if (debug_level >= DEBUG_LEVEL_INFO)
1659 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
1660 __FILE__,__LINE__, info->device_name );
d12341f9 1661
1da177e4
LT		 1662 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
1663 return 0;
d12341f9 1664
1da177e4
LT		 1665 if (info->params.mode == MGSL_MODE_HDLC)
1666 rc = info->tx_active ? info->max_frame_size : 0;
1667 else
1668 rc = info->tx_count;
1669
1670 if (debug_level >= DEBUG_LEVEL_INFO)
1671 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
1672 __FILE__,__LINE__, info->device_name, rc);
d12341f9 1673
1da177e4
LT		 1674 return rc;
1675}
1676
1677/* Discard all data in the send buffer
1678 */
1679static void mgslpc_flush_buffer(struct tty_struct *tty)
1680{
1681 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1682 unsigned long flags;
d12341f9 1683
1da177e4
LT		 1684 if (debug_level >= DEBUG_LEVEL_INFO)
1685 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
1686 __FILE__,__LINE__, info->device_name );
d12341f9 1687
1da177e4
LT		 1688 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
1689 return;
d12341f9
JG		 1690
1691 spin_lock_irqsave(&info->lock,flags);
1da177e4 1692 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1693 del_timer(&info->tx_timer);
1da177e4
LT		 1694 spin_unlock_irqrestore(&info->lock,flags);
1695
1696 wake_up_interruptible(&tty->write_wait);
1697 tty_wakeup(tty);
1698}
1699
1700/* Send a high-priority XON/XOFF character
1701 */
1702static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
1703{
1704 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1705 unsigned long flags;
1706
1707 if (debug_level >= DEBUG_LEVEL_INFO)
1708 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
1709 __FILE__,__LINE__, info->device_name, ch );
d12341f9 1710
1da177e4
LT		 1711 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
1712 return;
1713
1714 info->x_char = ch;
1715 if (ch) {
1716 spin_lock_irqsave(&info->lock,flags);
1717 if (!info->tx_enabled)
eeb46134 1718 tx_start(info, tty);
1da177e4
LT		 1719 spin_unlock_irqrestore(&info->lock,flags);
1720 }
1721}
1722
1723/* Signal remote device to throttle send data (our receive data)
1724 */
1725static void mgslpc_throttle(struct tty_struct * tty)
1726{
1727 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1728 unsigned long flags;
d12341f9 1729
1da177e4
LT		 1730 if (debug_level >= DEBUG_LEVEL_INFO)
1731 printk("%s(%d):mgslpc_throttle(%s) entry\n",
1732 __FILE__,__LINE__, info->device_name );
1733
1734 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
1735 return;
d12341f9 1736
1da177e4
LT		 1737 if (I_IXOFF(tty))
1738 mgslpc_send_xchar(tty, STOP_CHAR(tty));
d12341f9 1739
373f5aed 1740 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 1741 spin_lock_irqsave(&info->lock,flags);
1742 info->serial_signals &= ~SerialSignal_RTS;
1743 set_signals(info);
1744 spin_unlock_irqrestore(&info->lock,flags);
1745 }
1746}
1747
1748/* Signal remote device to stop throttling send data (our receive data)
1749 */
1750static void mgslpc_unthrottle(struct tty_struct * tty)
1751{
1752 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1753 unsigned long flags;
d12341f9 1754
1da177e4
LT		 1755 if (debug_level >= DEBUG_LEVEL_INFO)
1756 printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
1757 __FILE__,__LINE__, info->device_name );
1758
1759 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
1760 return;
d12341f9 1761
1da177e4
LT		 1762 if (I_IXOFF(tty)) {
1763 if (info->x_char)
1764 info->x_char = 0;
1765 else
1766 mgslpc_send_xchar(tty, START_CHAR(tty));
1767 }
d12341f9 1768
373f5aed 1769 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 1770 spin_lock_irqsave(&info->lock,flags);
1771 info->serial_signals |= SerialSignal_RTS;
1772 set_signals(info);
1773 spin_unlock_irqrestore(&info->lock,flags);
1774 }
1775}
1776
1777/* get the current serial statistics
1778 */
1779static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
1780{
1781 int err;
1782 if (debug_level >= DEBUG_LEVEL_INFO)
1783 printk("get_params(%s)\n", info->device_name);
a7482a2e
PF		 1784 if (!user_icount) {
1785 memset(&info->icount, 0, sizeof(info->icount));
1786 } else {
1787 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
1788 if (err)
1789 return -EFAULT;
1790 }
1da177e4
LT		 1791 return 0;
1792}
1793
1794/* get the current serial parameters
1795 */
1796static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
1797{
1798 int err;
1799 if (debug_level >= DEBUG_LEVEL_INFO)
1800 printk("get_params(%s)\n", info->device_name);
1801 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
1802 if (err)
1803 return -EFAULT;
1804 return 0;
1805}
1806
1807/* set the serial parameters
d12341f9 1808 *
1da177e4 1809 * Arguments:
d12341f9 1810 *
1da177e4
LT		 1811 * info pointer to device instance data
1812 * new_params user buffer containing new serial params
1813 *
1814 * Returns: 0 if success, otherwise error code
1815 */
eeb46134 1816static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
1da177e4
LT		 1817{
1818 unsigned long flags;
1819 MGSL_PARAMS tmp_params;
1820 int err;
d12341f9 1821
1da177e4
LT		 1822 if (debug_level >= DEBUG_LEVEL_INFO)
1823 printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
1824 info->device_name );
1825 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
1826 if (err) {
1827 if ( debug_level >= DEBUG_LEVEL_INFO )
1828 printk( "%s(%d):set_params(%s) user buffer copy failed\n",
1829 __FILE__,__LINE__,info->device_name);
1830 return -EFAULT;
1831 }
d12341f9 1832
1da177e4
LT		 1833 spin_lock_irqsave(&info->lock,flags);
1834 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
1835 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 1836
eeb46134 1837 mgslpc_change_params(info, tty);
d12341f9 1838
1da177e4
LT		 1839 return 0;
1840}
1841
1842static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
1843{
1844 int err;
1845 if (debug_level >= DEBUG_LEVEL_INFO)
1846 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
1847 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
1848 if (err)
1849 return -EFAULT;
1850 return 0;
1851}
1852
1853static int set_txidle(MGSLPC_INFO * info, int idle_mode)
1854{
1855 unsigned long flags;
1856 if (debug_level >= DEBUG_LEVEL_INFO)
1857 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
1858 spin_lock_irqsave(&info->lock,flags);
1859 info->idle_mode = idle_mode;
1860 tx_set_idle(info);
1861 spin_unlock_irqrestore(&info->lock,flags);
1862 return 0;
1863}
1864
1865static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
1866{
1867 int err;
1868 if (debug_level >= DEBUG_LEVEL_INFO)
1869 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
1870 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
1871 if (err)
1872 return -EFAULT;
1873 return 0;
1874}
1875
1876static int set_interface(MGSLPC_INFO * info, int if_mode)
1877{
1878 unsigned long flags;
1879 unsigned char val;
1880 if (debug_level >= DEBUG_LEVEL_INFO)
1881 printk("set_interface(%s,%d)\n", info->device_name, if_mode);
1882 spin_lock_irqsave(&info->lock,flags);
1883 info->if_mode = if_mode;
1884
1885 val = read_reg(info, PVR) & 0x0f;
1886 switch (info->if_mode)
1887 {
1888 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
1889 case MGSL_INTERFACE_V35: val |= PVR_V35; break;
1890 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
1891 }
1892 write_reg(info, PVR, val);
1893
1894 spin_unlock_irqrestore(&info->lock,flags);
1895 return 0;
1896}
1897
eeb46134 1898static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
1da177e4
LT		 1899{
1900 unsigned long flags;
d12341f9 1901
1da177e4
LT		 1902 if (debug_level >= DEBUG_LEVEL_INFO)
1903 printk("set_txenable(%s,%d)\n", info->device_name, enable);
d12341f9 1904
1da177e4
LT		 1905 spin_lock_irqsave(&info->lock,flags);
1906 if (enable) {
1907 if (!info->tx_enabled)
eeb46134 1908 tx_start(info, tty);
1da177e4
LT		 1909 } else {
1910 if (info->tx_enabled)
1911 tx_stop(info);
1912 }
1913 spin_unlock_irqrestore(&info->lock,flags);
1914 return 0;
1915}
1916
1917static int tx_abort(MGSLPC_INFO * info)
1918{
1919 unsigned long flags;
d12341f9 1920
1da177e4
LT		 1921 if (debug_level >= DEBUG_LEVEL_INFO)
1922 printk("tx_abort(%s)\n", info->device_name);
d12341f9 1923
1da177e4
LT		 1924 spin_lock_irqsave(&info->lock,flags);
1925 if (info->tx_active && info->tx_count &&
1926 info->params.mode == MGSL_MODE_HDLC) {
1927 /* clear data count so FIFO is not filled on next IRQ.
1928 * This results in underrun and abort transmission.
1929 */
1930 info->tx_count = info->tx_put = info->tx_get = 0;
0fab6de0 1931 info->tx_aborting = true;
1da177e4
LT		 1932 }
1933 spin_unlock_irqrestore(&info->lock,flags);
1934 return 0;
1935}
1936
1937static int set_rxenable(MGSLPC_INFO * info, int enable)
1938{
1939 unsigned long flags;
d12341f9 1940
1da177e4
LT		 1941 if (debug_level >= DEBUG_LEVEL_INFO)
1942 printk("set_rxenable(%s,%d)\n", info->device_name, enable);
d12341f9 1943
1da177e4
LT		 1944 spin_lock_irqsave(&info->lock,flags);
1945 if (enable) {
1946 if (!info->rx_enabled)
1947 rx_start(info);
1948 } else {
1949 if (info->rx_enabled)
1950 rx_stop(info);
1951 }
1952 spin_unlock_irqrestore(&info->lock,flags);
1953 return 0;
1954}
1955
1956/* wait for specified event to occur
d12341f9 1957 *
1da177e4
LT		 1958 * Arguments: info pointer to device instance data
1959 * mask pointer to bitmask of events to wait for
1960 * Return Value: 0 if successful and bit mask updated with
1961 * of events triggerred,
1962 * otherwise error code
1963 */
1964static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
1965{
1966 unsigned long flags;
1967 int s;
1968 int rc=0;
1969 struct mgsl_icount cprev, cnow;
1970 int events;
1971 int mask;
1972 struct _input_signal_events oldsigs, newsigs;
1973 DECLARE_WAITQUEUE(wait, current);
1974
1975 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
1976 if (rc)
1977 return -EFAULT;
d12341f9 1978
1da177e4
LT		 1979 if (debug_level >= DEBUG_LEVEL_INFO)
1980 printk("wait_events(%s,%d)\n", info->device_name, mask);
1981
1982 spin_lock_irqsave(&info->lock,flags);
1983
1984 /* return immediately if state matches requested events */
1985 get_signals(info);
1986 s = info->serial_signals;
1987 events = mask &
1988 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
1989 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
1990 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
1991 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
1992 if (events) {
1993 spin_unlock_irqrestore(&info->lock,flags);
1994 goto exit;
1995 }
1996
1997 /* save current irq counts */
1998 cprev = info->icount;
1999 oldsigs = info->input_signal_events;
d12341f9 2000
1da177e4
LT		 2001 if ((info->params.mode == MGSL_MODE_HDLC) &&
2002 (mask & MgslEvent_ExitHuntMode))
2003 irq_enable(info, CHA, IRQ_EXITHUNT);
d12341f9 2004
1da177e4
LT		 2005 set_current_state(TASK_INTERRUPTIBLE);
2006 add_wait_queue(&info->event_wait_q, &wait);
d12341f9 2007
1da177e4 2008 spin_unlock_irqrestore(&info->lock,flags);
d12341f9
JG		 2009
2010
1da177e4
LT		 2011 for(;;) {
2012 schedule();
2013 if (signal_pending(current)) {
2014 rc = -ERESTARTSYS;
2015 break;
2016 }
d12341f9 2017
1da177e4
LT		 2018 /* get current irq counts */
2019 spin_lock_irqsave(&info->lock,flags);
2020 cnow = info->icount;
2021 newsigs = info->input_signal_events;
2022 set_current_state(TASK_INTERRUPTIBLE);
2023 spin_unlock_irqrestore(&info->lock,flags);
2024
2025 /* if no change, wait aborted for some reason */
2026 if (newsigs.dsr_up == oldsigs.dsr_up &&
2027 newsigs.dsr_down == oldsigs.dsr_down &&
2028 newsigs.dcd_up == oldsigs.dcd_up &&
2029 newsigs.dcd_down == oldsigs.dcd_down &&
2030 newsigs.cts_up == oldsigs.cts_up &&
2031 newsigs.cts_down == oldsigs.cts_down &&
2032 newsigs.ri_up == oldsigs.ri_up &&
2033 newsigs.ri_down == oldsigs.ri_down &&
2034 cnow.exithunt == cprev.exithunt &&
2035 cnow.rxidle == cprev.rxidle) {
2036 rc = -EIO;
2037 break;
2038 }
2039
2040 events = mask &
2041 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2042 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2043 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2044 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2045 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2046 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2047 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2048 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2049 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2050 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2051 if (events)
2052 break;
d12341f9 2053
1da177e4
LT		 2054 cprev = cnow;
2055 oldsigs = newsigs;
2056 }
d12341f9 2057
1da177e4
LT		 2058 remove_wait_queue(&info->event_wait_q, &wait);
2059 set_current_state(TASK_RUNNING);
2060
2061 if (mask & MgslEvent_ExitHuntMode) {
2062 spin_lock_irqsave(&info->lock,flags);
2063 if (!waitqueue_active(&info->event_wait_q))
2064 irq_disable(info, CHA, IRQ_EXITHUNT);
2065 spin_unlock_irqrestore(&info->lock,flags);
2066 }
2067exit:
2068 if (rc == 0)
2069 PUT_USER(rc, events, mask_ptr);
2070 return rc;
2071}
2072
2073static int modem_input_wait(MGSLPC_INFO *info,int arg)
2074{
2075 unsigned long flags;
2076 int rc;
2077 struct mgsl_icount cprev, cnow;
2078 DECLARE_WAITQUEUE(wait, current);
2079
2080 /* save current irq counts */
2081 spin_lock_irqsave(&info->lock,flags);
2082 cprev = info->icount;
2083 add_wait_queue(&info->status_event_wait_q, &wait);
2084 set_current_state(TASK_INTERRUPTIBLE);
2085 spin_unlock_irqrestore(&info->lock,flags);
2086
2087 for(;;) {
2088 schedule();
2089 if (signal_pending(current)) {
2090 rc = -ERESTARTSYS;
2091 break;
2092 }
2093
2094 /* get new irq counts */
2095 spin_lock_irqsave(&info->lock,flags);
2096 cnow = info->icount;
2097 set_current_state(TASK_INTERRUPTIBLE);
2098 spin_unlock_irqrestore(&info->lock,flags);
2099
2100 /* if no change, wait aborted for some reason */
2101 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2102 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2103 rc = -EIO;
2104 break;
2105 }
2106
2107 /* check for change in caller specified modem input */
2108 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2109 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2110 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2111 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2112 rc = 0;
2113 break;
2114 }
2115
2116 cprev = cnow;
2117 }
2118 remove_wait_queue(&info->status_event_wait_q, &wait);
2119 set_current_state(TASK_RUNNING);
2120 return rc;
2121}
2122
2123/* return the state of the serial control and status signals
2124 */
60b33c13 2125static int tiocmget(struct tty_struct *tty)
1da177e4
LT		 2126{
2127 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2128 unsigned int result;
2129 unsigned long flags;
2130
2131 spin_lock_irqsave(&info->lock,flags);
2132 get_signals(info);
2133 spin_unlock_irqrestore(&info->lock,flags);
2134
2135 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2136 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2137 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2138 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2139 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2140 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2141
2142 if (debug_level >= DEBUG_LEVEL_INFO)
2143 printk("%s(%d):%s tiocmget() value=%08X\n",
2144 __FILE__,__LINE__, info->device_name, result );
2145 return result;
2146}
2147
2148/* set modem control signals (DTR/RTS)
2149 */
20b9d177 2150static int tiocmset(struct tty_struct *tty,
1da177e4
LT		 2151 unsigned int set, unsigned int clear)
2152{
2153 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2154 unsigned long flags;
2155
2156 if (debug_level >= DEBUG_LEVEL_INFO)
2157 printk("%s(%d):%s tiocmset(%x,%x)\n",
2158 __FILE__,__LINE__,info->device_name, set, clear);
2159
2160 if (set & TIOCM_RTS)
2161 info->serial_signals |= SerialSignal_RTS;
2162 if (set & TIOCM_DTR)
2163 info->serial_signals |= SerialSignal_DTR;
2164 if (clear & TIOCM_RTS)
2165 info->serial_signals &= ~SerialSignal_RTS;
2166 if (clear & TIOCM_DTR)
2167 info->serial_signals &= ~SerialSignal_DTR;
2168
2169 spin_lock_irqsave(&info->lock,flags);
2170 set_signals(info);
2171 spin_unlock_irqrestore(&info->lock,flags);
2172
2173 return 0;
2174}
2175
2176/* Set or clear transmit break condition
2177 *
2178 * Arguments: tty pointer to tty instance data
2179 * break_state -1=set break condition, 0=clear
2180 */
9e98966c 2181static int mgslpc_break(struct tty_struct *tty, int break_state)
1da177e4
LT		 2182{
2183 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2184 unsigned long flags;
d12341f9 2185
1da177e4
LT		 2186 if (debug_level >= DEBUG_LEVEL_INFO)
2187 printk("%s(%d):mgslpc_break(%s,%d)\n",
2188 __FILE__,__LINE__, info->device_name, break_state);
d12341f9 2189
1da177e4 2190 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
9e98966c 2191 return -EINVAL;
1da177e4
LT		 2192
2193 spin_lock_irqsave(&info->lock,flags);
2194 if (break_state == -1)
2195 set_reg_bits(info, CHA+DAFO, BIT6);
d12341f9 2196 else
1da177e4
LT		 2197 clear_reg_bits(info, CHA+DAFO, BIT6);
2198 spin_unlock_irqrestore(&info->lock,flags);
9e98966c 2199 return 0;
1da177e4
LT		 2200}
2201
0587102c
AC		 2202static int mgslpc_get_icount(struct tty_struct *tty,
2203 struct serial_icounter_struct *icount)
2204{
2205 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2206 struct mgsl_icount cnow; /* kernel counter temps */
2207 unsigned long flags;
2208
2209 spin_lock_irqsave(&info->lock,flags);
2210 cnow = info->icount;
2211 spin_unlock_irqrestore(&info->lock,flags);
2212
2213 icount->cts = cnow.cts;
2214 icount->dsr = cnow.dsr;
2215 icount->rng = cnow.rng;
2216 icount->dcd = cnow.dcd;
2217 icount->rx = cnow.rx;
2218 icount->tx = cnow.tx;
2219 icount->frame = cnow.frame;
2220 icount->overrun = cnow.overrun;
2221 icount->parity = cnow.parity;
2222 icount->brk = cnow.brk;
2223 icount->buf_overrun = cnow.buf_overrun;
2224
2225 return 0;
2226}
2227
1da177e4 2228/* Service an IOCTL request
d12341f9 2229 *
1da177e4 2230 * Arguments:
d12341f9 2231 *
1da177e4 2232 * tty pointer to tty instance data
1da177e4
LT		 2233 * cmd IOCTL command code
2234 * arg command argument/context
d12341f9 2235 *
1da177e4
LT		 2236 * Return Value: 0 if success, otherwise error code
2237 */
751b3840 2238static int mgslpc_ioctl(struct tty_struct *tty,
1da177e4
LT		 2239 unsigned int cmd, unsigned long arg)
2240{
2241 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2242 void __user *argp = (void __user *)arg;
d12341f9 2243
1da177e4
LT		 2244 if (debug_level >= DEBUG_LEVEL_INFO)
2245 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2246 info->device_name, cmd );
d12341f9 2247
1da177e4
LT		 2248 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
2249 return -ENODEV;
2250
2251 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 2252 (cmd != TIOCMIWAIT)) {
1da177e4
LT		 2253 if (tty->flags & (1 << TTY_IO_ERROR))
2254 return -EIO;
2255 }
2256
1da177e4
LT		 2257 switch (cmd) {
2258 case MGSL_IOCGPARAMS:
2259 return get_params(info, argp);
2260 case MGSL_IOCSPARAMS:
eeb46134 2261 return set_params(info, argp, tty);
1da177e4
LT		 2262 case MGSL_IOCGTXIDLE:
2263 return get_txidle(info, argp);
2264 case MGSL_IOCSTXIDLE:
2265 return set_txidle(info, (int)arg);
2266 case MGSL_IOCGIF:
2267 return get_interface(info, argp);
2268 case MGSL_IOCSIF:
2269 return set_interface(info,(int)arg);
2270 case MGSL_IOCTXENABLE:
eeb46134 2271 return set_txenable(info,(int)arg, tty);
1da177e4
LT		 2272 case MGSL_IOCRXENABLE:
2273 return set_rxenable(info,(int)arg);
2274 case MGSL_IOCTXABORT:
2275 return tx_abort(info);
2276 case MGSL_IOCGSTATS:
2277 return get_stats(info, argp);
2278 case MGSL_IOCWAITEVENT:
2279 return wait_events(info, argp);
2280 case TIOCMIWAIT:
2281 return modem_input_wait(info,(int)arg);
1da177e4
LT		 2282 default:
2283 return -ENOIOCTLCMD;
2284 }
2285 return 0;
2286}
2287
2288/* Set new termios settings
d12341f9 2289 *
1da177e4 2290 * Arguments:
d12341f9 2291 *
1da177e4
LT		 2292 * tty pointer to tty structure
2293 * termios pointer to buffer to hold returned old termios
2294 */
606d099c 2295static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 2296{
2297 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2298 unsigned long flags;
d12341f9 2299
1da177e4
LT		 2300 if (debug_level >= DEBUG_LEVEL_INFO)
2301 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
2302 tty->driver->name );
d12341f9 2303
1da177e4 2304 /* just return if nothing has changed */
373f5aed
AC		 2305 if ((tty->termios.c_cflag == old_termios->c_cflag)
2306 && (RELEVANT_IFLAG(tty->termios.c_iflag)
1da177e4
LT		 2307 == RELEVANT_IFLAG(old_termios->c_iflag)))
2308 return;
2309
eeb46134 2310 mgslpc_change_params(info, tty);
1da177e4
LT		 2311
2312 /* Handle transition to B0 status */
2313 if (old_termios->c_cflag & CBAUD &&
373f5aed 2314 !(tty->termios.c_cflag & CBAUD)) {
1da177e4
LT		 2315 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2316 spin_lock_irqsave(&info->lock,flags);
2317 set_signals(info);
2318 spin_unlock_irqrestore(&info->lock,flags);
2319 }
d12341f9 2320
1da177e4
LT		 2321 /* Handle transition away from B0 status */
2322 if (!(old_termios->c_cflag & CBAUD) &&
373f5aed 2323 tty->termios.c_cflag & CBAUD) {
1da177e4 2324 info->serial_signals |= SerialSignal_DTR;
373f5aed 2325 if (!(tty->termios.c_cflag & CRTSCTS) ||
1da177e4
LT		 2326 !test_bit(TTY_THROTTLED, &tty->flags)) {
2327 info->serial_signals |= SerialSignal_RTS;
2328 }
2329 spin_lock_irqsave(&info->lock,flags);
2330 set_signals(info);
2331 spin_unlock_irqrestore(&info->lock,flags);
2332 }
d12341f9 2333
1da177e4
LT		 2334 /* Handle turning off CRTSCTS */
2335 if (old_termios->c_cflag & CRTSCTS &&
373f5aed 2336 !(tty->termios.c_cflag & CRTSCTS)) {
1da177e4
LT		 2337 tty->hw_stopped = 0;
2338 tx_release(tty);
2339 }
2340}
2341
2342static void mgslpc_close(struct tty_struct *tty, struct file * filp)
2343{
2344 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2345 struct tty_port *port = &info->port;
1da177e4
LT		 2346
2347 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
2348 return;
d12341f9 2349
1da177e4
LT		 2350 if (debug_level >= DEBUG_LEVEL_INFO)
2351 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
eeb46134 2352 __FILE__,__LINE__, info->device_name, port->count);
1da177e4 2353
eeb46134 2354 WARN_ON(!port->count);
d12341f9 2355
eeb46134 2356 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 2357 goto cleanup;
d12341f9 2358
eeb46134 2359 if (port->flags & ASYNC_INITIALIZED)
1da177e4
LT		 2360 mgslpc_wait_until_sent(tty, info->timeout);
2361
978e595f 2362 mgslpc_flush_buffer(tty);
1da177e4 2363
978e595f 2364 tty_ldisc_flush(tty);
eeb46134
AC		 2365 shutdown(info, tty);
2366
2367 tty_port_close_end(port, tty);
2368 tty_port_tty_set(port, NULL);
d12341f9 2369cleanup:
1da177e4
LT		 2370 if (debug_level >= DEBUG_LEVEL_INFO)
2371 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
eeb46134 2372 tty->driver->name, port->count);
1da177e4
LT		 2373}
2374
2375/* Wait until the transmitter is empty.
2376 */
2377static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
2378{
2379 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2380 unsigned long orig_jiffies, char_time;
2381
2382 if (!info )
2383 return;
2384
2385 if (debug_level >= DEBUG_LEVEL_INFO)
2386 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
2387 __FILE__,__LINE__, info->device_name );
d12341f9 2388
1da177e4
LT		 2389 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
2390 return;
2391
eeb46134 2392 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4 2393 goto exit;
d12341f9 2394
1da177e4 2395 orig_jiffies = jiffies;
d12341f9 2396
1da177e4
LT		 2397 /* Set check interval to 1/5 of estimated time to
2398 * send a character, and make it at least 1. The check
2399 * interval should also be less than the timeout.
2400 * Note: use tight timings here to satisfy the NIST-PCTS.
d12341f9
JG		 2401 */
2402
1da177e4
LT		 2403 if ( info->params.data_rate ) {
2404 char_time = info->timeout/(32 * 5);
2405 if (!char_time)
2406 char_time++;
2407 } else
2408 char_time = 1;
d12341f9 2409
1da177e4
LT		 2410 if (timeout)
2411 char_time = min_t(unsigned long, char_time, timeout);
d12341f9 2412
1da177e4
LT		 2413 if (info->params.mode == MGSL_MODE_HDLC) {
2414 while (info->tx_active) {
2415 msleep_interruptible(jiffies_to_msecs(char_time));
2416 if (signal_pending(current))
2417 break;
2418 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2419 break;
2420 }
2421 } else {
2422 while ((info->tx_count || info->tx_active) &&
2423 info->tx_enabled) {
2424 msleep_interruptible(jiffies_to_msecs(char_time));
2425 if (signal_pending(current))
2426 break;
2427 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2428 break;
2429 }
2430 }
d12341f9 2431
1da177e4
LT		 2432exit:
2433 if (debug_level >= DEBUG_LEVEL_INFO)
2434 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
2435 __FILE__,__LINE__, info->device_name );
2436}
2437
2438/* Called by tty_hangup() when a hangup is signaled.
2439 * This is the same as closing all open files for the port.
2440 */
2441static void mgslpc_hangup(struct tty_struct *tty)
2442{
2443 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
d12341f9 2444
1da177e4
LT		 2445 if (debug_level >= DEBUG_LEVEL_INFO)
2446 printk("%s(%d):mgslpc_hangup(%s)\n",
2447 __FILE__,__LINE__, info->device_name );
d12341f9 2448
1da177e4
LT		 2449 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
2450 return;
2451
2452 mgslpc_flush_buffer(tty);
eeb46134
AC		 2453 shutdown(info, tty);
2454 tty_port_hangup(&info->port);
1da177e4
LT		 2455}
2456
eeb46134 2457static int carrier_raised(struct tty_port *port)
1da177e4 2458{
eeb46134
AC		 2459 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2460 unsigned long flags;
d12341f9 2461
eeb46134
AC		 2462 spin_lock_irqsave(&info->lock,flags);
2463 get_signals(info);
2464 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 2465
eeb46134
AC		 2466 if (info->serial_signals & SerialSignal_DCD)
2467 return 1;
2468 return 0;
2469}
d12341f9 2470
fcc8ac18 2471static void dtr_rts(struct tty_port *port, int onoff)
eeb46134
AC		 2472{
2473 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2474 unsigned long flags;
d12341f9 2475
eeb46134 2476 spin_lock_irqsave(&info->lock,flags);
fcc8ac18
AC		 2477 if (onoff)
2478 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2479 else
2480 info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
eeb46134
AC		 2481 set_signals(info);
2482 spin_unlock_irqrestore(&info->lock,flags);
1da177e4
LT		 2483}
2484
eeb46134 2485
1da177e4
LT		 2486static int mgslpc_open(struct tty_struct *tty, struct file * filp)
2487{
2488 MGSLPC_INFO *info;
eeb46134 2489 struct tty_port *port;
1da177e4
LT		 2490 int retval, line;
2491 unsigned long flags;
2492
d12341f9 2493 /* verify range of specified line number */
1da177e4 2494 line = tty->index;
410235fd 2495 if (line >= mgslpc_device_count) {
1da177e4
LT		 2496 printk("%s(%d):mgslpc_open with invalid line #%d.\n",
2497 __FILE__,__LINE__,line);
2498 return -ENODEV;
2499 }
2500
2501 /* find the info structure for the specified line */
2502 info = mgslpc_device_list;
2503 while(info && info->line != line)
2504 info = info->next_device;
2505 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
2506 return -ENODEV;
d12341f9 2507
eeb46134 2508 port = &info->port;
1da177e4 2509 tty->driver_data = info;
eeb46134 2510 tty_port_tty_set(port, tty);
d12341f9 2511
1da177e4
LT		 2512 if (debug_level >= DEBUG_LEVEL_INFO)
2513 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
eeb46134 2514 __FILE__,__LINE__,tty->driver->name, port->count);
1da177e4
LT		 2515
2516 /* If port is closing, signal caller to try again */
eeb46134
AC		 2517 if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
2518 if (port->flags & ASYNC_CLOSING)
2519 interruptible_sleep_on(&port->close_wait);
2520 retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 2521 -EAGAIN : -ERESTARTSYS);
2522 goto cleanup;
2523 }
d12341f9 2524
eeb46134 2525 tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 2526
2527 spin_lock_irqsave(&info->netlock, flags);
2528 if (info->netcount) {
2529 retval = -EBUSY;
2530 spin_unlock_irqrestore(&info->netlock, flags);
2531 goto cleanup;
2532 }
eeb46134
AC		 2533 spin_lock(&port->lock);
2534 port->count++;
2535 spin_unlock(&port->lock);
1da177e4
LT		 2536 spin_unlock_irqrestore(&info->netlock, flags);
2537
eeb46134 2538 if (port->count == 1) {
1da177e4 2539 /* 1st open on this device, init hardware */
eeb46134 2540 retval = startup(info, tty);
1da177e4
LT		 2541 if (retval < 0)
2542 goto cleanup;
2543 }
2544
eeb46134 2545 retval = tty_port_block_til_ready(&info->port, tty, filp);
1da177e4
LT		 2546 if (retval) {
2547 if (debug_level >= DEBUG_LEVEL_INFO)
2548 printk("%s(%d):block_til_ready(%s) returned %d\n",
2549 __FILE__,__LINE__, info->device_name, retval);
2550 goto cleanup;
2551 }
2552
2553 if (debug_level >= DEBUG_LEVEL_INFO)
2554 printk("%s(%d):mgslpc_open(%s) success\n",
2555 __FILE__,__LINE__, info->device_name);
2556 retval = 0;
d12341f9
JG		 2557
2558cleanup:
1da177e4
LT		 2559 return retval;
2560}
2561
2562/*
2563 * /proc fs routines....
2564 */
2565
87687144 2566static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
1da177e4
LT		 2567{
2568 char stat_buf[30];
1da177e4
LT		 2569 unsigned long flags;
2570
87687144 2571 seq_printf(m, "%s:io:%04X irq:%d",
1da177e4
LT		 2572 info->device_name, info->io_base, info->irq_level);
2573
2574 /* output current serial signal states */
2575 spin_lock_irqsave(&info->lock,flags);
2576 get_signals(info);
2577 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 2578
1da177e4
LT		 2579 stat_buf[0] = 0;
2580 stat_buf[1] = 0;
2581 if (info->serial_signals & SerialSignal_RTS)
2582 strcat(stat_buf, "|RTS");
2583 if (info->serial_signals & SerialSignal_CTS)
2584 strcat(stat_buf, "|CTS");
2585 if (info->serial_signals & SerialSignal_DTR)
2586 strcat(stat_buf, "|DTR");
2587 if (info->serial_signals & SerialSignal_DSR)
2588 strcat(stat_buf, "|DSR");
2589 if (info->serial_signals & SerialSignal_DCD)
2590 strcat(stat_buf, "|CD");
2591 if (info->serial_signals & SerialSignal_RI)
2592 strcat(stat_buf, "|RI");
2593
2594 if (info->params.mode == MGSL_MODE_HDLC) {
87687144 2595 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 2596 info->icount.txok, info->icount.rxok);
2597 if (info->icount.txunder)
87687144 2598 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 2599 if (info->icount.txabort)
87687144 2600 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 2601 if (info->icount.rxshort)
87687144 2602 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 2603 if (info->icount.rxlong)
87687144 2604 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 2605 if (info->icount.rxover)
87687144 2606 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 2607 if (info->icount.rxcrc)
87687144 2608 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 2609 } else {
87687144 2610 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 2611 info->icount.tx, info->icount.rx);
2612 if (info->icount.frame)
87687144 2613 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 2614 if (info->icount.parity)
87687144 2615 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 2616 if (info->icount.brk)
87687144 2617 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 2618 if (info->icount.overrun)
87687144 2619 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4 2620 }
d12341f9 2621
1da177e4 2622 /* Append serial signal status to end */
87687144 2623 seq_printf(m, " %s\n", stat_buf+1);
d12341f9 2624
87687144 2625 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 2626 info->tx_active,info->bh_requested,info->bh_running,
2627 info->pending_bh);
1da177e4
LT		 2628}
2629
2630/* Called to print information about devices
2631 */
87687144 2632static int mgslpc_proc_show(struct seq_file *m, void *v)
1da177e4 2633{
1da177e4 2634 MGSLPC_INFO *info;
d12341f9 2635
87687144 2636 seq_printf(m, "synclink driver:%s\n", driver_version);
d12341f9 2637
1da177e4
LT		 2638 info = mgslpc_device_list;
2639 while( info ) {
87687144 2640 line_info(m, info);
1da177e4
LT		 2641 info = info->next_device;
2642 }
87687144
AD		 2643 return 0;
2644}
1da177e4 2645
87687144
AD		 2646static int mgslpc_proc_open(struct inode *inode, struct file *file)
2647{
2648 return single_open(file, mgslpc_proc_show, NULL);
1da177e4
LT		 2649}
2650
87687144
AD		 2651static const struct file_operations mgslpc_proc_fops = {
2652 .owner = THIS_MODULE,
2653 .open = mgslpc_proc_open,
2654 .read = seq_read,
2655 .llseek = seq_lseek,
2656 .release = single_release,
2657};
2658
cdaad343 2659static int rx_alloc_buffers(MGSLPC_INFO *info)
1da177e4
LT		 2660{
2661 /* each buffer has header and data */
2662 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
2663
2664 /* calculate total allocation size for 8 buffers */
2665 info->rx_buf_total_size = info->rx_buf_size * 8;
2666
2667 /* limit total allocated memory */
2668 if (info->rx_buf_total_size > 0x10000)
2669 info->rx_buf_total_size = 0x10000;
2670
2671 /* calculate number of buffers */
2672 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
2673
2674 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
2675 if (info->rx_buf == NULL)
2676 return -ENOMEM;
2677
a6b68a69
PF		 2678 /* unused flag buffer to satisfy receive_buf calling interface */
2679 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
2680 if (!info->flag_buf) {
2681 kfree(info->rx_buf);
2682 info->rx_buf = NULL;
2683 return -ENOMEM;
2684 }
2685
1da177e4
LT		 2686 rx_reset_buffers(info);
2687 return 0;
2688}
2689
cdaad343 2690static void rx_free_buffers(MGSLPC_INFO *info)
1da177e4 2691{
735d5661 2692 kfree(info->rx_buf);
1da177e4 2693 info->rx_buf = NULL;
a6b68a69
PF		 2694 kfree(info->flag_buf);
2695 info->flag_buf = NULL;
1da177e4
LT		 2696}
2697
cdaad343 2698static int claim_resources(MGSLPC_INFO *info)
1da177e4
LT		 2699{
2700 if (rx_alloc_buffers(info) < 0 ) {
25985edc 2701 printk( "Can't allocate rx buffer %s\n", info->device_name);
1da177e4
LT		 2702 release_resources(info);
2703 return -ENODEV;
d12341f9 2704 }
1da177e4
LT		 2705 return 0;
2706}
2707
cdaad343 2708static void release_resources(MGSLPC_INFO *info)
1da177e4
LT		 2709{
2710 if (debug_level >= DEBUG_LEVEL_INFO)
2711 printk("release_resources(%s)\n", info->device_name);
2712 rx_free_buffers(info);
2713}
2714
2715/* Add the specified device instance data structure to the
2716 * global linked list of devices and increment the device count.
d12341f9 2717 *
1da177e4
LT		 2718 * Arguments: info pointer to device instance data
2719 */
cdaad343 2720static void mgslpc_add_device(MGSLPC_INFO *info)
1da177e4
LT		 2721{
2722 info->next_device = NULL;
2723 info->line = mgslpc_device_count;
2724 sprintf(info->device_name,"ttySLP%d",info->line);
d12341f9 2725
1da177e4
LT		 2726 if (info->line < MAX_DEVICE_COUNT) {
2727 if (maxframe[info->line])
2728 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 2729 }
2730
2731 mgslpc_device_count++;
d12341f9 2732
1da177e4
LT		 2733 if (!mgslpc_device_list)
2734 mgslpc_device_list = info;
d12341f9 2735 else {
1da177e4
LT		 2736 MGSLPC_INFO *current_dev = mgslpc_device_list;
2737 while( current_dev->next_device )
2738 current_dev = current_dev->next_device;
2739 current_dev->next_device = info;
2740 }
d12341f9 2741
1da177e4
LT		 2742 if (info->max_frame_size < 4096)
2743 info->max_frame_size = 4096;
2744 else if (info->max_frame_size > 65535)
2745 info->max_frame_size = 65535;
d12341f9 2746
1da177e4
LT		 2747 printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
2748 info->device_name, info->io_base, info->irq_level);
2749
af69c7f9 2750#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2751 hdlcdev_init(info);
2752#endif
16a1065f 2753 tty_port_register_device(&info->port, serial_driver, info->line,
a33ba827 2754 &info->p_dev->dev);
1da177e4
LT		 2755}
2756
cdaad343 2757static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
1da177e4
LT		 2758{
2759 MGSLPC_INFO *info = mgslpc_device_list;
2760 MGSLPC_INFO *last = NULL;
2761
2762 while(info) {
2763 if (info == remove_info) {
2764 if (last)
2765 last->next_device = info->next_device;
2766 else
2767 mgslpc_device_list = info->next_device;
16a1065f 2768 tty_unregister_device(serial_driver, info->line);
af69c7f9 2769#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2770 hdlcdev_exit(info);
2771#endif
2772 release_resources(info);
191c5f10 2773 tty_port_destroy(&info->port);
1da177e4
LT		 2774 kfree(info);
2775 mgslpc_device_count--;
2776 return;
2777 }
2778 last = info;
2779 info = info->next_device;
2780 }
2781}
2782
25f8f54f 2783static const struct pcmcia_device_id mgslpc_ids[] = {
4af48c8c
DB		 2784 PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
2785 PCMCIA_DEVICE_NULL
2786};
2787MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
2788
1da177e4
LT		 2789static struct pcmcia_driver mgslpc_driver = {
2790 .owner = THIS_MODULE,
2e9b981a 2791 .name = "synclink_cs",
15b99ac1 2792 .probe = mgslpc_probe,
cc3b4866 2793 .remove = mgslpc_detach,
4af48c8c 2794 .id_table = mgslpc_ids,
98e4c28b
DB		 2795 .suspend = mgslpc_suspend,
2796 .resume = mgslpc_resume,
1da177e4
LT		 2797};
2798
b68e31d0 2799static const struct tty_operations mgslpc_ops = {
1da177e4
LT		 2800 .open = mgslpc_open,
2801 .close = mgslpc_close,
2802 .write = mgslpc_write,
2803 .put_char = mgslpc_put_char,
2804 .flush_chars = mgslpc_flush_chars,
2805 .write_room = mgslpc_write_room,
2806 .chars_in_buffer = mgslpc_chars_in_buffer,
2807 .flush_buffer = mgslpc_flush_buffer,
2808 .ioctl = mgslpc_ioctl,
2809 .throttle = mgslpc_throttle,
2810 .unthrottle = mgslpc_unthrottle,
2811 .send_xchar = mgslpc_send_xchar,
2812 .break_ctl = mgslpc_break,
2813 .wait_until_sent = mgslpc_wait_until_sent,
1da177e4
LT		 2814 .set_termios = mgslpc_set_termios,
2815 .stop = tx_pause,
2816 .start = tx_release,
2817 .hangup = mgslpc_hangup,
2818 .tiocmget = tiocmget,
2819 .tiocmset = tiocmset,
dc98d965 2820 .get_icount = mgslpc_get_icount,
87687144 2821 .proc_fops = &mgslpc_proc_fops,
1da177e4
LT		 2822};
2823
1da177e4 2824static int __init synclink_cs_init(void)
1da177e4
LT		 2825{
2826 int rc;
2827
cc93441e
JS		 2828 if (break_on_load) {
2829 mgslpc_get_text_ptr();
2830 BREAKPOINT();
1da177e4
LT		 2831 }
2832
cc93441e
JS		 2833 serial_driver = tty_alloc_driver(MAX_DEVICE_COUNT,
2834 TTY_DRIVER_REAL_RAW |
2835 TTY_DRIVER_DYNAMIC_DEV);
c3a6344a
DC		 2836 if (IS_ERR(serial_driver)) {
2837 rc = PTR_ERR(serial_driver);
cc93441e
JS		 2838 goto err;
2839 }
1da177e4 2840
cc93441e
JS		 2841 /* Initialize the tty_driver structure */
2842 serial_driver->driver_name = "synclink_cs";
2843 serial_driver->name = "ttySLP";
2844 serial_driver->major = ttymajor;
2845 serial_driver->minor_start = 64;
2846 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2847 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2848 serial_driver->init_termios = tty_std_termios;
2849 serial_driver->init_termios.c_cflag =
2850 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2851 tty_set_operations(serial_driver, &mgslpc_ops);
1da177e4 2852
cc93441e
JS		 2853 rc = tty_register_driver(serial_driver);
2854 if (rc < 0) {
2855 printk(KERN_ERR "%s(%d):Couldn't register serial driver\n",
2856 __FILE__, __LINE__);
2857 goto err_put_tty;
2858 }
1da177e4 2859
16a1065f
JS		 2860 rc = pcmcia_register_driver(&mgslpc_driver);
2861 if (rc < 0)
2862 goto err_unreg_tty;
d12341f9 2863
cc93441e
JS		 2864 printk(KERN_INFO "%s %s, tty major#%d\n", driver_name, driver_version,
2865 serial_driver->major);
d12341f9 2866
737586fe 2867 return 0;
16a1065f
JS		 2868err_unreg_tty:
2869 tty_unregister_driver(serial_driver);
737586fe
JS		 2870err_put_tty:
2871 put_tty_driver(serial_driver);
16a1065f 2872err:
737586fe 2873 return rc;
1da177e4
LT		 2874}
2875
d12341f9 2876static void __exit synclink_cs_exit(void)
1da177e4 2877{
16a1065f 2878 pcmcia_unregister_driver(&mgslpc_driver);
737586fe
JS		 2879 tty_unregister_driver(serial_driver);
2880 put_tty_driver(serial_driver);
1da177e4
LT		 2881}
2882
2883module_init(synclink_cs_init);
2884module_exit(synclink_cs_exit);
2885
2886static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
2887{
2888 unsigned int M, N;
2889 unsigned char val;
2890
d12341f9
JG		 2891 /* note:standard BRG mode is broken in V3.2 chip
2892 * so enhanced mode is always used
1da177e4
LT		 2893 */
2894
2895 if (rate) {
2896 N = 3686400 / rate;
2897 if (!N)
2898 N = 1;
2899 N >>= 1;
2900 for (M = 1; N > 64 && M < 16; M++)
2901 N >>= 1;
2902 N--;
2903
2904 /* BGR[5..0] = N
2905 * BGR[9..6] = M
2906 * BGR[7..0] contained in BGR register
2907 * BGR[9..8] contained in CCR2[7..6]
2908 * divisor = (N+1)*2^M
2909 *
2910 * Note: M *must* not be zero (causes asymetric duty cycle)
d12341f9 2911 */
1da177e4
LT		 2912 write_reg(info, (unsigned char) (channel + BGR),
2913 (unsigned char) ((M << 6) + N));
2914 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
2915 val |= ((M << 4) & 0xc0);
2916 write_reg(info, (unsigned char) (channel + CCR2), val);
2917 }
2918}
2919
2920/* Enabled the AUX clock output at the specified frequency.
2921 */
2922static void enable_auxclk(MGSLPC_INFO *info)
2923{
2924 unsigned char val;
d12341f9 2925
1da177e4
LT		 2926 /* MODE
2927 *
2928 * 07..06 MDS[1..0] 10 = transparent HDLC mode
2929 * 05 ADM Address Mode, 0 = no addr recognition
2930 * 04 TMD Timer Mode, 0 = external
2931 * 03 RAC Receiver Active, 0 = inactive
2932 * 02 RTS 0=RTS active during xmit, 1=RTS always active
2933 * 01 TRS Timer Resolution, 1=512
2934 * 00 TLP Test Loop, 0 = no loop
2935 *
2936 * 1000 0010
d12341f9 2937 */
1da177e4 2938 val = 0x82;
d12341f9
JG		 2939
2940 /* channel B RTS is used to enable AUXCLK driver on SP505 */
1da177e4
LT		 2941 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2942 val |= BIT2;
2943 write_reg(info, CHB + MODE, val);
d12341f9 2944
1da177e4
LT		 2945 /* CCR0
2946 *
2947 * 07 PU Power Up, 1=active, 0=power down
2948 * 06 MCE Master Clock Enable, 1=enabled
2949 * 05 Reserved, 0
2950 * 04..02 SC[2..0] Encoding
2951 * 01..00 SM[1..0] Serial Mode, 00=HDLC
2952 *
2953 * 11000000
d12341f9 2954 */
1da177e4 2955 write_reg(info, CHB + CCR0, 0xc0);
d12341f9 2956
1da177e4
LT		 2957 /* CCR1
2958 *
2959 * 07 SFLG Shared Flag, 0 = disable shared flags
2960 * 06 GALP Go Active On Loop, 0 = not used
2961 * 05 GLP Go On Loop, 0 = not used
2962 * 04 ODS Output Driver Select, 1=TxD is push-pull output
2963 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
2964 * 02..00 CM[2..0] Clock Mode
2965 *
2966 * 0001 0111
d12341f9 2967 */
1da177e4 2968 write_reg(info, CHB + CCR1, 0x17);
d12341f9 2969
1da177e4
LT		 2970 /* CCR2 (Channel B)
2971 *
2972 * 07..06 BGR[9..8] Baud rate bits 9..8
2973 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
2974 * 04 SSEL Clock source select, 1=submode b
2975 * 03 TOE 0=TxCLK is input, 1=TxCLK is output
2976 * 02 RWX Read/Write Exchange 0=disabled
2977 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
2978 * 00 DIV, data inversion 0=disabled, 1=enabled
2979 *
2980 * 0011 1000
d12341f9 2981 */
1da177e4
LT		 2982 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2983 write_reg(info, CHB + CCR2, 0x38);
2984 else
2985 write_reg(info, CHB + CCR2, 0x30);
d12341f9 2986
1da177e4
LT		 2987 /* CCR4
2988 *
2989 * 07 MCK4 Master Clock Divide by 4, 1=enabled
2990 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
2991 * 05 TST1 Test Pin, 0=normal operation
2992 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
2993 * 03..02 Reserved, must be 0
2994 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
2995 *
2996 * 0101 0000
d12341f9 2997 */
1da177e4 2998 write_reg(info, CHB + CCR4, 0x50);
d12341f9 2999
1da177e4
LT		 3000 /* if auxclk not enabled, set internal BRG so
3001 * CTS transitions can be detected (requires TxC)
d12341f9 3002 */
1da177e4
LT		 3003 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
3004 mgslpc_set_rate(info, CHB, info->params.clock_speed);
3005 else
3006 mgslpc_set_rate(info, CHB, 921600);
3007}
3008
d12341f9 3009static void loopback_enable(MGSLPC_INFO *info)
1da177e4
LT		 3010{
3011 unsigned char val;
d12341f9
JG		 3012
3013 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
1da177e4
LT		 3014 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
3015 write_reg(info, CHA + CCR1, val);
d12341f9
JG		 3016
3017 /* CCR2:04 SSEL Clock source select, 1=submode b */
1da177e4
LT		 3018 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
3019 write_reg(info, CHA + CCR2, val);
d12341f9
JG		 3020
3021 /* set LinkSpeed if available, otherwise default to 2Mbps */
1da177e4
LT		 3022 if (info->params.clock_speed)
3023 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3024 else
3025 mgslpc_set_rate(info, CHA, 1843200);
d12341f9
JG		 3026
3027 /* MODE:00 TLP Test Loop, 1=loopback enabled */
1da177e4
LT		 3028 val = read_reg(info, CHA + MODE) | BIT0;
3029 write_reg(info, CHA + MODE, val);
3030}
3031
cdaad343 3032static void hdlc_mode(MGSLPC_INFO *info)
1da177e4
LT		 3033{
3034 unsigned char val;
3035 unsigned char clkmode, clksubmode;
3036
d12341f9 3037 /* disable all interrupts */
1da177e4
LT		 3038 irq_disable(info, CHA, 0xffff);
3039 irq_disable(info, CHB, 0xffff);
3040 port_irq_disable(info, 0xff);
d12341f9
JG		 3041
3042 /* assume clock mode 0a, rcv=RxC xmt=TxC */
1da177e4
LT		 3043 clkmode = clksubmode = 0;
3044 if (info->params.flags & HDLC_FLAG_RXC_DPLL
3045 && info->params.flags & HDLC_FLAG_TXC_DPLL) {
d12341f9 3046 /* clock mode 7a, rcv = DPLL, xmt = DPLL */
1da177e4
LT		 3047 clkmode = 7;
3048 } else if (info->params.flags & HDLC_FLAG_RXC_BRG
3049 && info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3050 /* clock mode 7b, rcv = BRG, xmt = BRG */
1da177e4
LT		 3051 clkmode = 7;
3052 clksubmode = 1;
3053 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
3054 if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3055 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
1da177e4
LT		 3056 clkmode = 6;
3057 clksubmode = 1;
3058 } else {
d12341f9 3059 /* clock mode 6a, rcv = DPLL, xmt = TxC */
1da177e4
LT		 3060 clkmode = 6;
3061 }
3062 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3063 /* clock mode 0b, rcv = RxC, xmt = BRG */
1da177e4
LT		 3064 clksubmode = 1;
3065 }
d12341f9 3066
1da177e4
LT		 3067 /* MODE
3068 *
3069 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3070 * 05 ADM Address Mode, 0 = no addr recognition
3071 * 04 TMD Timer Mode, 0 = external
3072 * 03 RAC Receiver Active, 0 = inactive
3073 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3074 * 01 TRS Timer Resolution, 1=512
3075 * 00 TLP Test Loop, 0 = no loop
3076 *
3077 * 1000 0010
d12341f9 3078 */
1da177e4
LT		 3079 val = 0x82;
3080 if (info->params.loopback)
3081 val |= BIT0;
d12341f9
JG		 3082
3083 /* preserve RTS state */
1da177e4
LT		 3084 if (info->serial_signals & SerialSignal_RTS)
3085 val |= BIT2;
3086 write_reg(info, CHA + MODE, val);
d12341f9 3087
1da177e4
LT		 3088 /* CCR0
3089 *
3090 * 07 PU Power Up, 1=active, 0=power down
3091 * 06 MCE Master Clock Enable, 1=enabled
3092 * 05 Reserved, 0
3093 * 04..02 SC[2..0] Encoding
3094 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3095 *
3096 * 11000000
d12341f9 3097 */
1da177e4
LT		 3098 val = 0xc0;
3099 switch (info->params.encoding)
3100 {
3101 case HDLC_ENCODING_NRZI:
3102 val |= BIT3;
3103 break;
3104 case HDLC_ENCODING_BIPHASE_SPACE:
3105 val |= BIT4;
3106 break; // FM0
3107 case HDLC_ENCODING_BIPHASE_MARK:
3108 val |= BIT4 + BIT2;
3109 break; // FM1
3110 case HDLC_ENCODING_BIPHASE_LEVEL:
3111 val |= BIT4 + BIT3;
3112 break; // Manchester
3113 }
3114 write_reg(info, CHA + CCR0, val);
d12341f9 3115
1da177e4
LT		 3116 /* CCR1
3117 *
3118 * 07 SFLG Shared Flag, 0 = disable shared flags
3119 * 06 GALP Go Active On Loop, 0 = not used
3120 * 05 GLP Go On Loop, 0 = not used
3121 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3122 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3123 * 02..00 CM[2..0] Clock Mode
3124 *
3125 * 0001 0000
d12341f9 3126 */
1da177e4
LT		 3127 val = 0x10 + clkmode;
3128 write_reg(info, CHA + CCR1, val);
d12341f9 3129
1da177e4
LT		 3130 /* CCR2
3131 *
3132 * 07..06 BGR[9..8] Baud rate bits 9..8
3133 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3134 * 04 SSEL Clock source select, 1=submode b
3135 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3136 * 02 RWX Read/Write Exchange 0=disabled
3137 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3138 * 00 DIV, data inversion 0=disabled, 1=enabled
3139 *
3140 * 0000 0000
d12341f9 3141 */
1da177e4
LT		 3142 val = 0x00;
3143 if (clkmode == 2 || clkmode == 3 || clkmode == 6
3144 || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
3145 val |= BIT5;
3146 if (clksubmode)
3147 val |= BIT4;
3148 if (info->params.crc_type == HDLC_CRC_32_CCITT)
3149 val |= BIT1;
3150 if (info->params.encoding == HDLC_ENCODING_NRZB)
3151 val |= BIT0;
3152 write_reg(info, CHA + CCR2, val);
d12341f9 3153
1da177e4
LT		 3154 /* CCR3
3155 *
3156 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
3157 * 05 EPT Enable preamble transmission, 1=enabled
3158 * 04 RADD Receive address pushed to FIFO, 0=disabled
3159 * 03 CRL CRC Reset Level, 0=FFFF
3160 * 02 RCRC Rx CRC 0=On 1=Off
3161 * 01 TCRC Tx CRC 0=On 1=Off
3162 * 00 PSD DPLL Phase Shift Disable
3163 *
3164 * 0000 0000
d12341f9 3165 */
1da177e4
LT		 3166 val = 0x00;
3167 if (info->params.crc_type == HDLC_CRC_NONE)
3168 val |= BIT2 + BIT1;
3169 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3170 val |= BIT5;
3171 switch (info->params.preamble_length)
3172 {
3173 case HDLC_PREAMBLE_LENGTH_16BITS:
3174 val |= BIT6;
3175 break;
3176 case HDLC_PREAMBLE_LENGTH_32BITS:
3177 val |= BIT6;
3178 break;
3179 case HDLC_PREAMBLE_LENGTH_64BITS:
3180 val |= BIT7 + BIT6;
3181 break;
3182 }
3183 write_reg(info, CHA + CCR3, val);
d12341f9
JG		 3184
3185 /* PRE - Preamble pattern */
1da177e4
LT		 3186 val = 0;
3187 switch (info->params.preamble)
3188 {
3189 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3190 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
3191 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
3192 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3193 }
3194 write_reg(info, CHA + PRE, val);
d12341f9 3195
1da177e4
LT		 3196 /* CCR4
3197 *
3198 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3199 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3200 * 05 TST1 Test Pin, 0=normal operation
3201 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3202 * 03..02 Reserved, must be 0
3203 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3204 *
3205 * 0101 0000
d12341f9 3206 */
1da177e4
LT		 3207 val = 0x50;
3208 write_reg(info, CHA + CCR4, val);
3209 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3210 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
3211 else
3212 mgslpc_set_rate(info, CHA, info->params.clock_speed);
d12341f9 3213
1da177e4
LT		 3214 /* RLCR Receive length check register
3215 *
3216 * 7 1=enable receive length check
3217 * 6..0 Max frame length = (RL + 1) * 32
d12341f9 3218 */
1da177e4 3219 write_reg(info, CHA + RLCR, 0);
d12341f9 3220
1da177e4
LT		 3221 /* XBCH Transmit Byte Count High
3222 *
3223 * 07 DMA mode, 0 = interrupt driven
3224 * 06 NRM, 0=ABM (ignored)
3225 * 05 CAS Carrier Auto Start
3226 * 04 XC Transmit Continuously (ignored)
3227 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3228 *
3229 * 0000 0000
d12341f9 3230 */
1da177e4
LT		 3231 val = 0x00;
3232 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3233 val |= BIT5;
3234 write_reg(info, CHA + XBCH, val);
3235 enable_auxclk(info);
3236 if (info->params.loopback || info->testing_irq)
3237 loopback_enable(info);
3238 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3239 {
3240 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3241 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3242 set_reg_bits(info, CHA + PVR, BIT3);
3243 } else
3244 clear_reg_bits(info, CHA + PVR, BIT3);
3245
3246 irq_enable(info, CHA,
3247 IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
3248 IRQ_UNDERRUN + IRQ_TXFIFO);
3249 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3250 wait_command_complete(info, CHA);
3251 read_reg16(info, CHA + ISR); /* clear pending IRQs */
d12341f9 3252
1da177e4
LT		 3253 /* Master clock mode enabled above to allow reset commands
3254 * to complete even if no data clocks are present.
3255 *
3256 * Disable master clock mode for normal communications because
3257 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
3258 * IRQ when in master clock mode.
3259 *
3260 * Leave master clock mode enabled for IRQ test because the
3261 * timer IRQ used by the test can only happen in master clock mode.
d12341f9 3262 */
1da177e4
LT		 3263 if (!info->testing_irq)
3264 clear_reg_bits(info, CHA + CCR0, BIT6);
3265
3266 tx_set_idle(info);
3267
3268 tx_stop(info);
3269 rx_stop(info);
3270}
3271
cdaad343 3272static void rx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3273{
3274 if (debug_level >= DEBUG_LEVEL_ISR)
3275 printk("%s(%d):rx_stop(%s)\n",
3276 __FILE__,__LINE__, info->device_name );
d12341f9
JG		 3277
3278 /* MODE:03 RAC Receiver Active, 0=inactive */
1da177e4
LT		 3279 clear_reg_bits(info, CHA + MODE, BIT3);
3280
0fab6de0
JP		 3281 info->rx_enabled = false;
3282 info->rx_overflow = false;
1da177e4
LT		 3283}
3284
cdaad343 3285static void rx_start(MGSLPC_INFO *info)
1da177e4
LT		 3286{
3287 if (debug_level >= DEBUG_LEVEL_ISR)
3288 printk("%s(%d):rx_start(%s)\n",
3289 __FILE__,__LINE__, info->device_name );
3290
3291 rx_reset_buffers(info);
0fab6de0
JP		 3292 info->rx_enabled = false;
3293 info->rx_overflow = false;
1da177e4 3294
d12341f9 3295 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3296 set_reg_bits(info, CHA + MODE, BIT3);
3297
0fab6de0 3298 info->rx_enabled = true;
1da177e4
LT		 3299}
3300
eeb46134 3301static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3302{
3303 if (debug_level >= DEBUG_LEVEL_ISR)
3304 printk("%s(%d):tx_start(%s)\n",
3305 __FILE__,__LINE__, info->device_name );
d12341f9 3306
1da177e4
LT		 3307 if (info->tx_count) {
3308 /* If auto RTS enabled and RTS is inactive, then assert */
3309 /* RTS and set a flag indicating that the driver should */
3310 /* negate RTS when the transmission completes. */
0fab6de0 3311 info->drop_rts_on_tx_done = false;
1da177e4
LT		 3312
3313 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3314 get_signals(info);
3315 if (!(info->serial_signals & SerialSignal_RTS)) {
3316 info->serial_signals |= SerialSignal_RTS;
3317 set_signals(info);
0fab6de0 3318 info->drop_rts_on_tx_done = true;
1da177e4
LT		 3319 }
3320 }
3321
3322 if (info->params.mode == MGSL_MODE_ASYNC) {
3323 if (!info->tx_active) {
0fab6de0 3324 info->tx_active = true;
eeb46134 3325 tx_ready(info, tty);
1da177e4
LT		 3326 }
3327 } else {
0fab6de0 3328 info->tx_active = true;
eeb46134 3329 tx_ready(info, tty);
40565f19
JS		 3330 mod_timer(&info->tx_timer, jiffies +
3331 msecs_to_jiffies(5000));
1da177e4
LT		 3332 }
3333 }
3334
3335 if (!info->tx_enabled)
0fab6de0 3336 info->tx_enabled = true;
1da177e4
LT		 3337}
3338
cdaad343 3339static void tx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3340{
3341 if (debug_level >= DEBUG_LEVEL_ISR)
3342 printk("%s(%d):tx_stop(%s)\n",
3343 __FILE__,__LINE__, info->device_name );
d12341f9
JG		 3344
3345 del_timer(&info->tx_timer);
1da177e4 3346
0fab6de0
JP		 3347 info->tx_enabled = false;
3348 info->tx_active = false;
1da177e4
LT		 3349}
3350
3351/* Reset the adapter to a known state and prepare it for further use.
3352 */
cdaad343 3353static void reset_device(MGSLPC_INFO *info)
1da177e4 3354{
d12341f9 3355 /* power up both channels (set BIT7) */
1da177e4
LT		 3356 write_reg(info, CHA + CCR0, 0x80);
3357 write_reg(info, CHB + CCR0, 0x80);
3358 write_reg(info, CHA + MODE, 0);
3359 write_reg(info, CHB + MODE, 0);
d12341f9
JG		 3360
3361 /* disable all interrupts */
1da177e4
LT		 3362 irq_disable(info, CHA, 0xffff);
3363 irq_disable(info, CHB, 0xffff);
3364 port_irq_disable(info, 0xff);
d12341f9 3365
1da177e4
LT		 3366 /* PCR Port Configuration Register
3367 *
3368 * 07..04 DEC[3..0] Serial I/F select outputs
3369 * 03 output, 1=AUTO CTS control enabled
3370 * 02 RI Ring Indicator input 0=active
3371 * 01 DSR input 0=active
3372 * 00 DTR output 0=active
3373 *
3374 * 0000 0110
d12341f9 3375 */
1da177e4 3376 write_reg(info, PCR, 0x06);
d12341f9 3377
1da177e4
LT		 3378 /* PVR Port Value Register
3379 *
3380 * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
3381 * 03 AUTO CTS output 1=enabled
3382 * 02 RI Ring Indicator input
3383 * 01 DSR input
3384 * 00 DTR output (1=inactive)
3385 *
3386 * 0000 0001
3387 */
3388// write_reg(info, PVR, PVR_DTR);
d12341f9 3389
1da177e4
LT		 3390 /* IPC Interrupt Port Configuration
3391 *
3392 * 07 VIS 1=Masked interrupts visible
3393 * 06..05 Reserved, 0
3394 * 04..03 SLA Slave address, 00 ignored
3395 * 02 CASM Cascading Mode, 1=daisy chain
3396 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
3397 *
3398 * 0000 0101
d12341f9 3399 */
1da177e4
LT		 3400 write_reg(info, IPC, 0x05);
3401}
3402
cdaad343 3403static void async_mode(MGSLPC_INFO *info)
1da177e4
LT		 3404{
3405 unsigned char val;
3406
d12341f9 3407 /* disable all interrupts */
1da177e4
LT		 3408 irq_disable(info, CHA, 0xffff);
3409 irq_disable(info, CHB, 0xffff);
3410 port_irq_disable(info, 0xff);
d12341f9 3411
1da177e4
LT		 3412 /* MODE
3413 *
3414 * 07 Reserved, 0
3415 * 06 FRTS RTS State, 0=active
3416 * 05 FCTS Flow Control on CTS
3417 * 04 FLON Flow Control Enable
3418 * 03 RAC Receiver Active, 0 = inactive
3419 * 02 RTS 0=Auto RTS, 1=manual RTS
3420 * 01 TRS Timer Resolution, 1=512
3421 * 00 TLP Test Loop, 0 = no loop
3422 *
3423 * 0000 0110
d12341f9 3424 */
1da177e4
LT		 3425 val = 0x06;
3426 if (info->params.loopback)
3427 val |= BIT0;
d12341f9
JG		 3428
3429 /* preserve RTS state */
1da177e4
LT		 3430 if (!(info->serial_signals & SerialSignal_RTS))
3431 val |= BIT6;
3432 write_reg(info, CHA + MODE, val);
d12341f9 3433
1da177e4
LT		 3434 /* CCR0
3435 *
3436 * 07 PU Power Up, 1=active, 0=power down
3437 * 06 MCE Master Clock Enable, 1=enabled
3438 * 05 Reserved, 0
3439 * 04..02 SC[2..0] Encoding, 000=NRZ
3440 * 01..00 SM[1..0] Serial Mode, 11=Async
3441 *
3442 * 1000 0011
d12341f9 3443 */
1da177e4 3444 write_reg(info, CHA + CCR0, 0x83);
d12341f9 3445
1da177e4
LT		 3446 /* CCR1
3447 *
3448 * 07..05 Reserved, 0
3449 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3450 * 03 BCR Bit Clock Rate, 1=16x
3451 * 02..00 CM[2..0] Clock Mode, 111=BRG
3452 *
3453 * 0001 1111
d12341f9 3454 */
1da177e4 3455 write_reg(info, CHA + CCR1, 0x1f);
d12341f9 3456
1da177e4
LT		 3457 /* CCR2 (channel A)
3458 *
3459 * 07..06 BGR[9..8] Baud rate bits 9..8
3460 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3461 * 04 SSEL Clock source select, 1=submode b
3462 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3463 * 02 RWX Read/Write Exchange 0=disabled
3464 * 01 Reserved, 0
3465 * 00 DIV, data inversion 0=disabled, 1=enabled
3466 *
3467 * 0001 0000
d12341f9 3468 */
1da177e4 3469 write_reg(info, CHA + CCR2, 0x10);
d12341f9 3470
1da177e4
LT		 3471 /* CCR3
3472 *
3473 * 07..01 Reserved, 0
3474 * 00 PSD DPLL Phase Shift Disable
3475 *
3476 * 0000 0000
d12341f9 3477 */
1da177e4 3478 write_reg(info, CHA + CCR3, 0);
d12341f9 3479
1da177e4
LT		 3480 /* CCR4
3481 *
3482 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3483 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3484 * 05 TST1 Test Pin, 0=normal operation
3485 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3486 * 03..00 Reserved, must be 0
3487 *
3488 * 0101 0000
d12341f9 3489 */
1da177e4
LT		 3490 write_reg(info, CHA + CCR4, 0x50);
3491 mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
d12341f9 3492
1da177e4
LT		 3493 /* DAFO Data Format
3494 *
3495 * 07 Reserved, 0
3496 * 06 XBRK transmit break, 0=normal operation
3497 * 05 Stop bits (0=1, 1=2)
3498 * 04..03 PAR[1..0] Parity (01=odd, 10=even)
3499 * 02 PAREN Parity Enable
3500 * 01..00 CHL[1..0] Character Length (00=8, 01=7)
3501 *
d12341f9 3502 */
1da177e4
LT		 3503 val = 0x00;
3504 if (info->params.data_bits != 8)
3505 val |= BIT0; /* 7 bits */
3506 if (info->params.stop_bits != 1)
3507 val |= BIT5;
3508 if (info->params.parity != ASYNC_PARITY_NONE)
3509 {
3510 val |= BIT2; /* Parity enable */
3511 if (info->params.parity == ASYNC_PARITY_ODD)
3512 val |= BIT3;
3513 else
3514 val |= BIT4;
3515 }
3516 write_reg(info, CHA + DAFO, val);
d12341f9 3517
1da177e4
LT		 3518 /* RFC Rx FIFO Control
3519 *
3520 * 07 Reserved, 0
3521 * 06 DPS, 1=parity bit not stored in data byte
3522 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
3523 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
3524 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
3525 * 01 Reserved, 0
3526 * 00 TCDE Terminate Char Detect Enable, 0=disabled
3527 *
3528 * 0101 1100
d12341f9 3529 */
1da177e4 3530 write_reg(info, CHA + RFC, 0x5c);
d12341f9 3531
1da177e4
LT		 3532 /* RLCR Receive length check register
3533 *
3534 * Max frame length = (RL + 1) * 32
d12341f9 3535 */
1da177e4 3536 write_reg(info, CHA + RLCR, 0);
d12341f9 3537
1da177e4
LT		 3538 /* XBCH Transmit Byte Count High
3539 *
3540 * 07 DMA mode, 0 = interrupt driven
3541 * 06 NRM, 0=ABM (ignored)
3542 * 05 CAS Carrier Auto Start
3543 * 04 XC Transmit Continuously (ignored)
3544 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3545 *
3546 * 0000 0000
d12341f9 3547 */
1da177e4
LT		 3548 val = 0x00;
3549 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3550 val |= BIT5;
3551 write_reg(info, CHA + XBCH, val);
3552 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3553 irq_enable(info, CHA, IRQ_CTS);
d12341f9
JG		 3554
3555 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3556 set_reg_bits(info, CHA + MODE, BIT3);
3557 enable_auxclk(info);
3558 if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
3559 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3560 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3561 set_reg_bits(info, CHA + PVR, BIT3);
3562 } else
3563 clear_reg_bits(info, CHA + PVR, BIT3);
3564 irq_enable(info, CHA,
3565 IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
3566 IRQ_ALLSENT + IRQ_TXFIFO);
3567 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3568 wait_command_complete(info, CHA);
3569 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3570}
3571
3572/* Set the HDLC idle mode for the transmitter.
3573 */
cdaad343 3574static void tx_set_idle(MGSLPC_INFO *info)
1da177e4 3575{
d12341f9 3576 /* Note: ESCC2 only supports flags and one idle modes */
1da177e4
LT		 3577 if (info->idle_mode == HDLC_TXIDLE_FLAGS)
3578 set_reg_bits(info, CHA + CCR1, BIT3);
3579 else
3580 clear_reg_bits(info, CHA + CCR1, BIT3);
3581}
3582
3583/* get state of the V24 status (input) signals.
3584 */
cdaad343 3585static void get_signals(MGSLPC_INFO *info)
1da177e4
LT		 3586{
3587 unsigned char status = 0;
d12341f9
JG		 3588
3589 /* preserve DTR and RTS */
1da177e4
LT		 3590 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
3591
3592 if (read_reg(info, CHB + VSTR) & BIT7)
3593 info->serial_signals |= SerialSignal_DCD;
3594 if (read_reg(info, CHB + STAR) & BIT1)
3595 info->serial_signals |= SerialSignal_CTS;
3596
3597 status = read_reg(info, CHA + PVR);
3598 if (!(status & PVR_RI))
3599 info->serial_signals |= SerialSignal_RI;
3600 if (!(status & PVR_DSR))
3601 info->serial_signals |= SerialSignal_DSR;
3602}
3603
3604/* Set the state of DTR and RTS based on contents of
3605 * serial_signals member of device extension.
3606 */
cdaad343 3607static void set_signals(MGSLPC_INFO *info)
1da177e4
LT		 3608{
3609 unsigned char val;
3610
3611 val = read_reg(info, CHA + MODE);
3612 if (info->params.mode == MGSL_MODE_ASYNC) {
3613 if (info->serial_signals & SerialSignal_RTS)
3614 val &= ~BIT6;
3615 else
3616 val |= BIT6;
3617 } else {
3618 if (info->serial_signals & SerialSignal_RTS)
3619 val |= BIT2;
3620 else
3621 val &= ~BIT2;
3622 }
3623 write_reg(info, CHA + MODE, val);
3624
3625 if (info->serial_signals & SerialSignal_DTR)
3626 clear_reg_bits(info, CHA + PVR, PVR_DTR);
3627 else
3628 set_reg_bits(info, CHA + PVR, PVR_DTR);
3629}
3630
cdaad343 3631static void rx_reset_buffers(MGSLPC_INFO *info)
1da177e4
LT		 3632{
3633 RXBUF *buf;
3634 int i;
3635
3636 info->rx_put = 0;
3637 info->rx_get = 0;
3638 info->rx_frame_count = 0;
3639 for (i=0 ; i < info->rx_buf_count ; i++) {
3640 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
3641 buf->status = buf->count = 0;
3642 }
3643}
3644
3645/* Attempt to return a received HDLC frame
3646 * Only frames received without errors are returned.
3647 *
0fab6de0 3648 * Returns true if frame returned, otherwise false
1da177e4 3649 */
eeb46134 3650static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3651{
3652 unsigned short status;
3653 RXBUF *buf;
3654 unsigned int framesize = 0;
3655 unsigned long flags;
0fab6de0 3656 bool return_frame = false;
d12341f9 3657
1da177e4 3658 if (info->rx_frame_count == 0)
0fab6de0 3659 return false;
1da177e4
LT		 3660
3661 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
3662
3663 status = buf->status;
3664
3665 /* 07 VFR 1=valid frame
3666 * 06 RDO 1=data overrun
3667 * 05 CRC 1=OK, 0=error
3668 * 04 RAB 1=frame aborted
3669 */
3670 if ((status & 0xf0) != 0xA0) {
3671 if (!(status & BIT7) || (status & BIT4))
3672 info->icount.rxabort++;
3673 else if (status & BIT6)
3674 info->icount.rxover++;
3675 else if (!(status & BIT5)) {
3676 info->icount.rxcrc++;
3677 if (info->params.crc_type & HDLC_CRC_RETURN_EX)
0fab6de0 3678 return_frame = true;
1da177e4
LT		 3679 }
3680 framesize = 0;
af69c7f9 3681#if SYNCLINK_GENERIC_HDLC
1da177e4 3682 {
198191c4
KH		 3683 info->netdev->stats.rx_errors++;
3684 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 3685 }
3686#endif
3687 } else
0fab6de0 3688 return_frame = true;
1da177e4
LT		 3689
3690 if (return_frame)
3691 framesize = buf->count;
3692
3693 if (debug_level >= DEBUG_LEVEL_BH)
3694 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
3695 __FILE__,__LINE__,info->device_name,status,framesize);
d12341f9 3696
1da177e4 3697 if (debug_level >= DEBUG_LEVEL_DATA)
d12341f9
JG		 3698 trace_block(info, buf->data, framesize, 0);
3699
1da177e4
LT		 3700 if (framesize) {
3701 if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
3702 framesize+1 > info->max_frame_size) ||
3703 framesize > info->max_frame_size)
3704 info->icount.rxlong++;
3705 else {
3706 if (status & BIT5)
3707 info->icount.rxok++;
3708
3709 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
3710 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
3711 ++framesize;
3712 }
3713
af69c7f9 3714#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3715 if (info->netcount)
3716 hdlcdev_rx(info, buf->data, framesize);
3717 else
3718#endif
3719 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
3720 }
3721 }
3722
3723 spin_lock_irqsave(&info->lock,flags);
3724 buf->status = buf->count = 0;
3725 info->rx_frame_count--;
3726 info->rx_get++;
3727 if (info->rx_get >= info->rx_buf_count)
3728 info->rx_get = 0;
3729 spin_unlock_irqrestore(&info->lock,flags);
3730
0fab6de0 3731 return true;
1da177e4
LT		 3732}
3733
0fab6de0 3734static bool register_test(MGSLPC_INFO *info)
1da177e4 3735{
d12341f9 3736 static unsigned char patterns[] =
1da177e4 3737 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
fe971071 3738 static unsigned int count = ARRAY_SIZE(patterns);
1da177e4 3739 unsigned int i;
0fab6de0 3740 bool rc = true;
1da177e4
LT		 3741 unsigned long flags;
3742
3743 spin_lock_irqsave(&info->lock,flags);
3744 reset_device(info);
3745
3746 for (i = 0; i < count; i++) {
3747 write_reg(info, XAD1, patterns[i]);
3748 write_reg(info, XAD2, patterns[(i + 1) % count]);
fe971071 3749 if ((read_reg(info, XAD1) != patterns[i]) ||
1da177e4 3750 (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
0fab6de0 3751 rc = false;
1da177e4
LT		 3752 break;
3753 }
3754 }
3755
3756 spin_unlock_irqrestore(&info->lock,flags);
3757 return rc;
3758}
3759
0fab6de0 3760static bool irq_test(MGSLPC_INFO *info)
1da177e4
LT		 3761{
3762 unsigned long end_time;
3763 unsigned long flags;
3764
3765 spin_lock_irqsave(&info->lock,flags);
3766 reset_device(info);
3767
0fab6de0 3768 info->testing_irq = true;
1da177e4
LT		 3769 hdlc_mode(info);
3770
0fab6de0 3771 info->irq_occurred = false;
1da177e4
LT		 3772
3773 /* init hdlc mode */
3774
3775 irq_enable(info, CHA, IRQ_TIMER);
3776 write_reg(info, CHA + TIMR, 0); /* 512 cycles */
3777 issue_command(info, CHA, CMD_START_TIMER);
3778
3779 spin_unlock_irqrestore(&info->lock,flags);
3780
3781 end_time=100;
3782 while(end_time-- && !info->irq_occurred) {
3783 msleep_interruptible(10);
3784 }
d12341f9 3785
0fab6de0 3786 info->testing_irq = false;
1da177e4
LT		 3787
3788 spin_lock_irqsave(&info->lock,flags);
3789 reset_device(info);
3790 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 3791
0fab6de0 3792 return info->irq_occurred;
1da177e4
LT		 3793}
3794
cdaad343 3795static int adapter_test(MGSLPC_INFO *info)
1da177e4
LT		 3796{
3797 if (!register_test(info)) {
3798 info->init_error = DiagStatus_AddressFailure;
3799 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
3800 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
3801 return -ENODEV;
3802 }
3803
3804 if (!irq_test(info)) {
3805 info->init_error = DiagStatus_IrqFailure;
3806 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
3807 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
3808 return -ENODEV;
3809 }
3810
3811 if (debug_level >= DEBUG_LEVEL_INFO)
3812 printk("%s(%d):device %s passed diagnostics\n",
3813 __FILE__,__LINE__,info->device_name);
3814 return 0;
3815}
3816
cdaad343 3817static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
1da177e4
LT		 3818{
3819 int i;
3820 int linecount;
3821 if (xmit)
3822 printk("%s tx data:\n",info->device_name);
3823 else
3824 printk("%s rx data:\n",info->device_name);
d12341f9 3825
1da177e4
LT		 3826 while(count) {
3827 if (count > 16)
3828 linecount = 16;
3829 else
3830 linecount = count;
d12341f9 3831
1da177e4
LT		 3832 for(i=0;i<linecount;i++)
3833 printk("%02X ",(unsigned char)data[i]);
3834 for(;i<17;i++)
3835 printk(" ");
3836 for(i=0;i<linecount;i++) {
3837 if (data[i]>=040 && data[i]<=0176)
3838 printk("%c",data[i]);
3839 else
3840 printk(".");
3841 }
3842 printk("\n");
d12341f9 3843
1da177e4
LT		 3844 data += linecount;
3845 count -= linecount;
3846 }
3847}
3848
3849/* HDLC frame time out
3850 * update stats and do tx completion processing
3851 */
cdaad343 3852static void tx_timeout(unsigned long context)
1da177e4
LT		 3853{
3854 MGSLPC_INFO *info = (MGSLPC_INFO*)context;
3855 unsigned long flags;
d12341f9 3856
1da177e4
LT		 3857 if ( debug_level >= DEBUG_LEVEL_INFO )
3858 printk( "%s(%d):tx_timeout(%s)\n",
3859 __FILE__,__LINE__,info->device_name);
3860 if(info->tx_active &&
3861 info->params.mode == MGSL_MODE_HDLC) {
3862 info->icount.txtimeout++;
3863 }
3864 spin_lock_irqsave(&info->lock,flags);
0fab6de0 3865 info->tx_active = false;
1da177e4
LT		 3866 info->tx_count = info->tx_put = info->tx_get = 0;
3867
3868 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 3869
af69c7f9 3870#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3871 if (info->netcount)
3872 hdlcdev_tx_done(info);
3873 else
3874#endif
eeb46134
AC		 3875 {
3876 struct tty_struct *tty = tty_port_tty_get(&info->port);
3877 bh_transmit(info, tty);
3878 tty_kref_put(tty);
3879 }
1da177e4
LT		 3880}
3881
af69c7f9 3882#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3883
3884/**
3885 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
3886 * set encoding and frame check sequence (FCS) options
3887 *
3888 * dev pointer to network device structure
3889 * encoding serial encoding setting
3890 * parity FCS setting
3891 *
3892 * returns 0 if success, otherwise error code
3893 */
3894static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
3895 unsigned short parity)
3896{
3897 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3898 struct tty_struct *tty;
1da177e4
LT		 3899 unsigned char new_encoding;
3900 unsigned short new_crctype;
3901
3902 /* return error if TTY interface open */
eeb46134 3903 if (info->port.count)
1da177e4
LT		 3904 return -EBUSY;
3905
3906 switch (encoding)
3907 {
3908 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
3909 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
3910 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
3911 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
3912 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
3913 default: return -EINVAL;
3914 }
3915
3916 switch (parity)
3917 {
3918 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
3919 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
3920 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
3921 default: return -EINVAL;
3922 }
3923
3924 info->params.encoding = new_encoding;
53b3531b 3925 info->params.crc_type = new_crctype;
1da177e4
LT		 3926
3927 /* if network interface up, reprogram hardware */
eeb46134
AC		 3928 if (info->netcount) {
3929 tty = tty_port_tty_get(&info->port);
3930 mgslpc_program_hw(info, tty);
3931 tty_kref_put(tty);
3932 }
1da177e4
LT		 3933
3934 return 0;
3935}
3936
3937/**
3938 * called by generic HDLC layer to send frame
3939 *
3940 * skb socket buffer containing HDLC frame
3941 * dev pointer to network device structure
1da177e4 3942 */
4c5d502d
SH		 3943static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
3944 struct net_device *dev)
1da177e4
LT		 3945{
3946 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 3947 unsigned long flags;
3948
3949 if (debug_level >= DEBUG_LEVEL_INFO)
3950 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
3951
3952 /* stop sending until this frame completes */
3953 netif_stop_queue(dev);
3954
3955 /* copy data to device buffers */
d626f62b 3956 skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
1da177e4
LT		 3957 info->tx_get = 0;
3958 info->tx_put = info->tx_count = skb->len;
3959
3960 /* update network statistics */
198191c4
KH		 3961 dev->stats.tx_packets++;
3962 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 3963
3964 /* done with socket buffer, so free it */
3965 dev_kfree_skb(skb);
3966
3967 /* save start time for transmit timeout detection */
3968 dev->trans_start = jiffies;
3969
3970 /* start hardware transmitter if necessary */
3971 spin_lock_irqsave(&info->lock,flags);
eeb46134
AC		 3972 if (!info->tx_active) {
3973 struct tty_struct *tty = tty_port_tty_get(&info->port);
3974 tx_start(info, tty);
3975 tty_kref_put(tty);
3976 }
1da177e4
LT		 3977 spin_unlock_irqrestore(&info->lock,flags);
3978
4c5d502d 3979 return NETDEV_TX_OK;
1da177e4
LT		 3980}
3981
3982/**
3983 * called by network layer when interface enabled
3984 * claim resources and initialize hardware
3985 *
3986 * dev pointer to network device structure
3987 *
3988 * returns 0 if success, otherwise error code
3989 */
3990static int hdlcdev_open(struct net_device *dev)
3991{
3992 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3993 struct tty_struct *tty;
1da177e4
LT		 3994 int rc;
3995 unsigned long flags;
3996
3997 if (debug_level >= DEBUG_LEVEL_INFO)
3998 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
3999
4000 /* generic HDLC layer open processing */
4001 if ((rc = hdlc_open(dev)))
4002 return rc;
4003
4004 /* arbitrate between network and tty opens */
4005 spin_lock_irqsave(&info->netlock, flags);
eeb46134 4006 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 4007 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
4008 spin_unlock_irqrestore(&info->netlock, flags);
4009 return -EBUSY;
4010 }
4011 info->netcount=1;
4012 spin_unlock_irqrestore(&info->netlock, flags);
4013
eeb46134 4014 tty = tty_port_tty_get(&info->port);
1da177e4 4015 /* claim resources and init adapter */
eeb46134
AC		 4016 if ((rc = startup(info, tty)) != 0) {
4017 tty_kref_put(tty);
1da177e4
LT		 4018 spin_lock_irqsave(&info->netlock, flags);
4019 info->netcount=0;
4020 spin_unlock_irqrestore(&info->netlock, flags);
4021 return rc;
4022 }
1da177e4
LT		 4023 /* assert DTR and RTS, apply hardware settings */
4024 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
eeb46134
AC		 4025 mgslpc_program_hw(info, tty);
4026 tty_kref_put(tty);
1da177e4
LT		 4027
4028 /* enable network layer transmit */
4029 dev->trans_start = jiffies;
4030 netif_start_queue(dev);
4031
4032 /* inform generic HDLC layer of current DCD status */
4033 spin_lock_irqsave(&info->lock, flags);
4034 get_signals(info);
4035 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 4036 if (info->serial_signals & SerialSignal_DCD)
4037 netif_carrier_on(dev);
4038 else
4039 netif_carrier_off(dev);
1da177e4
LT		 4040 return 0;
4041}
4042
4043/**
4044 * called by network layer when interface is disabled
4045 * shutdown hardware and release resources
4046 *
4047 * dev pointer to network device structure
4048 *
4049 * returns 0 if success, otherwise error code
4050 */
4051static int hdlcdev_close(struct net_device *dev)
4052{
4053 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 4054 struct tty_struct *tty = tty_port_tty_get(&info->port);
1da177e4
LT		 4055 unsigned long flags;
4056
4057 if (debug_level >= DEBUG_LEVEL_INFO)
4058 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
4059
4060 netif_stop_queue(dev);
4061
4062 /* shutdown adapter and release resources */
eeb46134
AC		 4063 shutdown(info, tty);
4064 tty_kref_put(tty);
1da177e4
LT		 4065 hdlc_close(dev);
4066
4067 spin_lock_irqsave(&info->netlock, flags);
4068 info->netcount=0;
4069 spin_unlock_irqrestore(&info->netlock, flags);
4070
4071 return 0;
4072}
4073
4074/**
4075 * called by network layer to process IOCTL call to network device
4076 *
4077 * dev pointer to network device structure
4078 * ifr pointer to network interface request structure
4079 * cmd IOCTL command code
4080 *
4081 * returns 0 if success, otherwise error code
4082 */
4083static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4084{
4085 const size_t size = sizeof(sync_serial_settings);
4086 sync_serial_settings new_line;
4087 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
4088 MGSLPC_INFO *info = dev_to_port(dev);
4089 unsigned int flags;
4090
4091 if (debug_level >= DEBUG_LEVEL_INFO)
4092 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
4093
4094 /* return error if TTY interface open */
eeb46134 4095 if (info->port.count)
1da177e4
LT		 4096 return -EBUSY;
4097
4098 if (cmd != SIOCWANDEV)
4099 return hdlc_ioctl(dev, ifr, cmd);
4100
5b917a14
VK		 4101 memset(&new_line, 0, size);
4102
1da177e4
LT		 4103 switch(ifr->ifr_settings.type) {
4104 case IF_GET_IFACE: /* return current sync_serial_settings */
4105
4106 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
4107 if (ifr->ifr_settings.size < size) {
4108 ifr->ifr_settings.size = size; /* data size wanted */
4109 return -ENOBUFS;
4110 }
4111
4112 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4113 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4114 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4115 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4116
4117 switch (flags){
4118 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4119 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4120 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4121 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4122 default: new_line.clock_type = CLOCK_DEFAULT;
4123 }
4124
4125 new_line.clock_rate = info->params.clock_speed;
4126 new_line.loopback = info->params.loopback ? 1:0;
4127
4128 if (copy_to_user(line, &new_line, size))
4129 return -EFAULT;
4130 return 0;
4131
4132 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
4133
4134 if(!capable(CAP_NET_ADMIN))
4135 return -EPERM;
4136 if (copy_from_user(&new_line, line, size))
4137 return -EFAULT;
4138
4139 switch (new_line.clock_type)
4140 {
4141 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
4142 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
4143 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
4144 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
4145 case CLOCK_DEFAULT: flags = info->params.flags &
4146 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4147 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4148 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4149 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
4150 default: return -EINVAL;
4151 }
4152
4153 if (new_line.loopback != 0 && new_line.loopback != 1)
4154 return -EINVAL;
4155
4156 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4157 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4158 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4159 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4160 info->params.flags |= flags;
4161
4162 info->params.loopback = new_line.loopback;
4163
4164 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
4165 info->params.clock_speed = new_line.clock_rate;
4166 else
4167 info->params.clock_speed = 0;
4168
4169 /* if network interface up, reprogram hardware */
eeb46134
AC		 4170 if (info->netcount) {
4171 struct tty_struct *tty = tty_port_tty_get(&info->port);
4172 mgslpc_program_hw(info, tty);
4173 tty_kref_put(tty);
4174 }
1da177e4
LT		 4175 return 0;
4176
4177 default:
4178 return hdlc_ioctl(dev, ifr, cmd);
4179 }
4180}
4181
4182/**
4183 * called by network layer when transmit timeout is detected
4184 *
4185 * dev pointer to network device structure
4186 */
4187static void hdlcdev_tx_timeout(struct net_device *dev)
4188{
4189 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 4190 unsigned long flags;
4191
4192 if (debug_level >= DEBUG_LEVEL_INFO)
4193 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
4194
198191c4
KH		 4195 dev->stats.tx_errors++;
4196 dev->stats.tx_aborted_errors++;
1da177e4
LT		 4197
4198 spin_lock_irqsave(&info->lock,flags);
4199 tx_stop(info);
4200 spin_unlock_irqrestore(&info->lock,flags);
4201
4202 netif_wake_queue(dev);
4203}
4204
4205/**
4206 * called by device driver when transmit completes
4207 * reenable network layer transmit if stopped
4208 *
4209 * info pointer to device instance information
4210 */
4211static void hdlcdev_tx_done(MGSLPC_INFO *info)
4212{
4213 if (netif_queue_stopped(info->netdev))
4214 netif_wake_queue(info->netdev);
4215}
4216
4217/**
4218 * called by device driver when frame received
4219 * pass frame to network layer
4220 *
4221 * info pointer to device instance information
4222 * buf pointer to buffer contianing frame data
4223 * size count of data bytes in buf
4224 */
4225static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
4226{
4227 struct sk_buff *skb = dev_alloc_skb(size);
4228 struct net_device *dev = info->netdev;
1da177e4
LT		 4229
4230 if (debug_level >= DEBUG_LEVEL_INFO)
4231 printk("hdlcdev_rx(%s)\n",dev->name);
4232
4233 if (skb == NULL) {
4234 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
198191c4 4235 dev->stats.rx_dropped++;
1da177e4
LT		 4236 return;
4237 }
4238
198191c4 4239 memcpy(skb_put(skb, size), buf, size);
1da177e4 4240
198191c4 4241 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 4242
198191c4
KH		 4243 dev->stats.rx_packets++;
4244 dev->stats.rx_bytes += size;
1da177e4
LT		 4245
4246 netif_rx(skb);
1da177e4
LT		 4247}
4248
991990a1
KH		 4249static const struct net_device_ops hdlcdev_ops = {
4250 .ndo_open = hdlcdev_open,
4251 .ndo_stop = hdlcdev_close,
4252 .ndo_change_mtu = hdlc_change_mtu,
4253 .ndo_start_xmit = hdlc_start_xmit,
4254 .ndo_do_ioctl = hdlcdev_ioctl,
4255 .ndo_tx_timeout = hdlcdev_tx_timeout,
4256};
4257
1da177e4
LT		 4258/**
4259 * called by device driver when adding device instance
4260 * do generic HDLC initialization
4261 *
4262 * info pointer to device instance information
4263 *
4264 * returns 0 if success, otherwise error code
4265 */
4266static int hdlcdev_init(MGSLPC_INFO *info)
4267{
4268 int rc;
4269 struct net_device *dev;
4270 hdlc_device *hdlc;
4271
4272 /* allocate and initialize network and HDLC layer objects */
4273
4274 if (!(dev = alloc_hdlcdev(info))) {
4275 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
4276 return -ENOMEM;
4277 }
4278
4279 /* for network layer reporting purposes only */
4280 dev->base_addr = info->io_base;
4281 dev->irq = info->irq_level;
4282
4283 /* network layer callbacks and settings */
991990a1
KH		 4284 dev->netdev_ops = &hdlcdev_ops;
4285 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 4286 dev->tx_queue_len = 50;
4287
4288 /* generic HDLC layer callbacks and settings */
4289 hdlc = dev_to_hdlc(dev);
4290 hdlc->attach = hdlcdev_attach;
4291 hdlc->xmit = hdlcdev_xmit;
4292
4293 /* register objects with HDLC layer */
4294 if ((rc = register_hdlc_device(dev))) {
4295 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
4296 free_netdev(dev);
4297 return rc;
4298 }
4299
4300 info->netdev = dev;
4301 return 0;
4302}
4303
4304/**
4305 * called by device driver when removing device instance
4306 * do generic HDLC cleanup
4307 *
4308 * info pointer to device instance information
4309 */
4310static void hdlcdev_exit(MGSLPC_INFO *info)
4311{
4312 unregister_hdlc_device(info->netdev);
4313 free_netdev(info->netdev);
4314 info->netdev = NULL;
4315}
4316
4317#endif /* CONFIG_HDLC */
4318
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