]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * rocket_int.h --- internal header file for rocket.c | |
3 | * | |
4 | * Written by Theodore Ts'o, Copyright 1997. | |
5 | * Copyright 1997 Comtrol Corporation. | |
6 | * | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Definition of the types in rcktpt_type | |
11 | */ | |
12 | #define ROCKET_TYPE_NORMAL 0 | |
13 | #define ROCKET_TYPE_MODEM 1 | |
14 | #define ROCKET_TYPE_MODEMII 2 | |
15 | #define ROCKET_TYPE_MODEMIII 3 | |
16 | #define ROCKET_TYPE_PC104 4 | |
17 | ||
18 | #include <asm/io.h> | |
19 | #include <asm/byteorder.h> | |
20 | ||
21 | typedef unsigned char Byte_t; | |
22 | typedef unsigned int ByteIO_t; | |
23 | ||
24 | typedef unsigned int Word_t; | |
25 | typedef unsigned int WordIO_t; | |
26 | ||
27 | typedef unsigned long DWord_t; | |
28 | typedef unsigned int DWordIO_t; | |
29 | ||
30 | /* | |
31 | * Note! Normally the Linux I/O macros already take care of | |
32 | * byte-swapping the I/O instructions. However, all accesses using | |
33 | * sOutDW aren't really 32-bit accesses, but should be handled in byte | |
34 | * order. Hence the use of the cpu_to_le32() macro to byte-swap | |
35 | * things to no-op the byte swapping done by the big-endian outl() | |
36 | * instruction. | |
37 | */ | |
38 | ||
39 | #ifdef ROCKET_DEBUG_IO | |
40 | static inline void sOutB(unsigned short port, unsigned char value) | |
41 | { | |
42 | #ifdef ROCKET_DEBUG_IO | |
43 | printk("sOutB(%x, %x)...", port, value); | |
44 | #endif | |
45 | outb_p(value, port); | |
46 | } | |
47 | ||
48 | static inline void sOutW(unsigned short port, unsigned short value) | |
49 | { | |
50 | #ifdef ROCKET_DEBUG_IO | |
51 | printk("sOutW(%x, %x)...", port, value); | |
52 | #endif | |
53 | outw_p(value, port); | |
54 | } | |
55 | ||
56 | static inline void sOutDW(unsigned short port, unsigned long value) | |
57 | { | |
58 | #ifdef ROCKET_DEBUG_IO | |
59 | printk("sOutDW(%x, %lx)...", port, value); | |
60 | #endif | |
61 | outl_p(cpu_to_le32(value), port); | |
62 | } | |
63 | ||
64 | static inline unsigned char sInB(unsigned short port) | |
65 | { | |
66 | return inb_p(port); | |
67 | } | |
68 | ||
69 | static inline unsigned short sInW(unsigned short port) | |
70 | { | |
71 | return inw_p(port); | |
72 | } | |
73 | ||
74 | #else /* !ROCKET_DEBUG_IO */ | |
75 | #define sOutB(a, b) outb_p(b, a) | |
76 | #define sOutW(a, b) outw_p(b, a) | |
77 | #define sOutDW(port, value) outl_p(cpu_to_le32(value), port) | |
78 | #define sInB(a) (inb_p(a)) | |
79 | #define sInW(a) (inw_p(a)) | |
80 | #endif /* ROCKET_DEBUG_IO */ | |
81 | ||
82 | /* This is used to move arrays of bytes so byte swapping isn't appropriate. */ | |
83 | #define sOutStrW(port, addr, count) if (count) outsw(port, addr, count) | |
84 | #define sInStrW(port, addr, count) if (count) insw(port, addr, count) | |
85 | ||
86 | #define CTL_SIZE 8 | |
87 | #define AIOP_CTL_SIZE 4 | |
88 | #define CHAN_AIOP_SIZE 8 | |
89 | #define MAX_PORTS_PER_AIOP 8 | |
90 | #define MAX_AIOPS_PER_BOARD 4 | |
91 | #define MAX_PORTS_PER_BOARD 32 | |
92 | ||
93 | /* Bus type ID */ | |
94 | #define isISA 0 | |
95 | #define isPCI 1 | |
96 | #define isMC 2 | |
97 | ||
98 | /* Controller ID numbers */ | |
99 | #define CTLID_NULL -1 /* no controller exists */ | |
100 | #define CTLID_0001 0x0001 /* controller release 1 */ | |
101 | ||
102 | /* AIOP ID numbers, identifies AIOP type implementing channel */ | |
103 | #define AIOPID_NULL -1 /* no AIOP or channel exists */ | |
104 | #define AIOPID_0001 0x0001 /* AIOP release 1 */ | |
105 | ||
106 | #define NULLDEV -1 /* identifies non-existant device */ | |
107 | #define NULLCTL -1 /* identifies non-existant controller */ | |
108 | #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ | |
109 | #define NULLAIOP -1 /* identifies non-existant AIOP */ | |
110 | #define NULLCHAN -1 /* identifies non-existant channel */ | |
111 | ||
112 | /************************************************************************ | |
113 | Global Register Offsets - Direct Access - Fixed values | |
114 | ************************************************************************/ | |
115 | ||
116 | #define _CMD_REG 0x38 /* Command Register 8 Write */ | |
117 | #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ | |
118 | #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ | |
119 | #define _UNUSED 0x3B /* Unused 8 */ | |
120 | #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ | |
121 | #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ | |
122 | ||
123 | /************************************************************************ | |
124 | Channel Register Offsets for 1st channel in AIOP - Direct Access | |
125 | ************************************************************************/ | |
126 | #define _TD0 0x00 /* Transmit Data 16 Write */ | |
127 | #define _RD0 0x00 /* Receive Data 16 Read */ | |
128 | #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ | |
129 | #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ | |
130 | #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ | |
131 | ||
132 | /************************************************************************ | |
133 | Tx Control Register Offsets - Indexed - External - Fixed | |
134 | ************************************************************************/ | |
135 | #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ | |
136 | #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ | |
137 | #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ | |
138 | #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ | |
139 | #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ | |
140 | #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ | |
141 | ||
142 | /************************************************************************ | |
143 | Memory Controller Register Offsets - Indexed - External - Fixed | |
144 | ************************************************************************/ | |
145 | #define _RX_FIFO 0x000 /* Rx FIFO */ | |
146 | #define _TX_FIFO 0x800 /* Tx FIFO */ | |
147 | #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ | |
148 | #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ | |
149 | #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ | |
150 | #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ | |
151 | #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ | |
152 | #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ | |
153 | ||
154 | #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ | |
155 | #define TXFIFO_SIZE 255 /* size of Tx FIFO */ | |
156 | #define RXFIFO_SIZE 1023 /* size of Rx FIFO */ | |
157 | ||
158 | /************************************************************************ | |
159 | Tx Priority Buffer - Indexed - External - Fixed | |
160 | ************************************************************************/ | |
161 | #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ | |
162 | #define TXP_SIZE 0x20 /* 32 bytes */ | |
163 | ||
164 | /************************************************************************ | |
165 | Channel Register Offsets - Indexed - Internal - Fixed | |
166 | ************************************************************************/ | |
167 | ||
168 | #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ | |
169 | #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ | |
170 | #define _BAUD 0xFF4 /* Baud Rate 16 Write */ | |
171 | #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ | |
172 | ||
173 | #define STMBREAK 0x08 /* BREAK */ | |
174 | #define STMFRAME 0x04 /* framing error */ | |
175 | #define STMRCVROVR 0x02 /* receiver over run error */ | |
176 | #define STMPARITY 0x01 /* parity error */ | |
177 | #define STMERROR (STMBREAK | STMFRAME | STMPARITY) | |
178 | #define STMBREAKH 0x800 /* BREAK */ | |
179 | #define STMFRAMEH 0x400 /* framing error */ | |
180 | #define STMRCVROVRH 0x200 /* receiver over run error */ | |
181 | #define STMPARITYH 0x100 /* parity error */ | |
182 | #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) | |
183 | ||
184 | #define CTS_ACT 0x20 /* CTS input asserted */ | |
185 | #define DSR_ACT 0x10 /* DSR input asserted */ | |
186 | #define CD_ACT 0x08 /* CD input asserted */ | |
187 | #define TXFIFOMT 0x04 /* Tx FIFO is empty */ | |
188 | #define TXSHRMT 0x02 /* Tx shift register is empty */ | |
189 | #define RDA 0x01 /* Rx data available */ | |
190 | #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ | |
191 | ||
192 | #define STATMODE 0x8000 /* status mode enable bit */ | |
193 | #define RXFOVERFL 0x2000 /* receive FIFO overflow */ | |
194 | #define RX2MATCH 0x1000 /* receive compare byte 2 match */ | |
195 | #define RX1MATCH 0x0800 /* receive compare byte 1 match */ | |
196 | #define RXBREAK 0x0400 /* received BREAK */ | |
197 | #define RXFRAME 0x0200 /* received framing error */ | |
198 | #define RXPARITY 0x0100 /* received parity error */ | |
199 | #define STATERROR (RXBREAK | RXFRAME | RXPARITY) | |
200 | ||
201 | #define CTSFC_EN 0x80 /* CTS flow control enable bit */ | |
202 | #define RTSTOG_EN 0x40 /* RTS toggle enable bit */ | |
203 | #define TXINT_EN 0x10 /* transmit interrupt enable */ | |
204 | #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ | |
205 | #define PARITY_EN 0x04 /* enable parity (0 = no parity) */ | |
206 | #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ | |
207 | #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ | |
208 | ||
209 | #define SETBREAK 0x10 /* send break condition (must clear) */ | |
210 | #define LOCALLOOP 0x08 /* local loopback set for test */ | |
211 | #define SET_DTR 0x04 /* assert DTR */ | |
212 | #define SET_RTS 0x02 /* assert RTS */ | |
213 | #define TX_ENABLE 0x01 /* enable transmitter */ | |
214 | ||
215 | #define RTSFC_EN 0x40 /* RTS flow control enable */ | |
216 | #define RXPROC_EN 0x20 /* receive processor enable */ | |
217 | #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ | |
218 | #define TRIG_1 0x08 /* trigger level 1 char */ | |
219 | #define TRIG_1_2 0x10 /* trigger level 1/2 */ | |
220 | #define TRIG_7_8 0x18 /* trigger level 7/8 */ | |
221 | #define TRIG_MASK 0x18 /* trigger level mask */ | |
222 | #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ | |
223 | #define RXINT_EN 0x02 /* Rx interrupt enable */ | |
224 | #define MCINT_EN 0x01 /* modem change interrupt enable */ | |
225 | ||
226 | #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ | |
227 | #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ | |
228 | #define SRC_INT 0x08 /* special receive condition interrupt */ | |
229 | #define DELTA_CD 0x04 /* CD change interrupt */ | |
230 | #define DELTA_CTS 0x02 /* CTS change interrupt */ | |
231 | #define DELTA_DSR 0x01 /* DSR change interrupt */ | |
232 | ||
233 | #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ | |
234 | #define IGN2_EN 0x08 /* ignore byte 2 enable */ | |
235 | #define IGN1_EN 0x04 /* ignore byte 1 enable */ | |
236 | #define COMP2_EN 0x02 /* compare byte 2 enable */ | |
237 | #define COMP1_EN 0x01 /* compare byte 1 enable */ | |
238 | ||
239 | #define RESET_ALL 0x80 /* reset AIOP (all channels) */ | |
240 | #define TXOVERIDE 0x40 /* Transmit software off override */ | |
241 | #define RESETUART 0x20 /* reset channel's UART */ | |
242 | #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ | |
243 | #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ | |
244 | ||
245 | #define INTSTAT0 0x01 /* AIOP 0 interrupt status */ | |
246 | #define INTSTAT1 0x02 /* AIOP 1 interrupt status */ | |
247 | #define INTSTAT2 0x04 /* AIOP 2 interrupt status */ | |
248 | #define INTSTAT3 0x08 /* AIOP 3 interrupt status */ | |
249 | ||
250 | #define INTR_EN 0x08 /* allow interrupts to host */ | |
251 | #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ | |
252 | ||
253 | /************************************************************************** | |
254 | MUDBAC remapped for PCI | |
255 | **************************************************************************/ | |
256 | ||
257 | #define _CFG_INT_PCI 0x40 | |
258 | #define _PCI_INT_FUNC 0x3A | |
259 | ||
260 | #define PCI_STROB 0x2000 /* bit 13 of int aiop register */ | |
261 | #define INTR_EN_PCI 0x0010 /* allow interrupts to host */ | |
262 | ||
263 | /* | |
264 | * Definitions for Universal PCI board registers | |
265 | */ | |
266 | #define _PCI_9030_INT_CTRL 0x4c /* Offsets from BAR1 */ | |
267 | #define _PCI_9030_GPIO_CTRL 0x54 | |
268 | #define PCI_INT_CTRL_AIOP 0x0001 | |
269 | #define PCI_GPIO_CTRL_8PORT 0x4000 | |
270 | #define _PCI_9030_RING_IND 0xc0 /* Offsets from BAR1 */ | |
271 | ||
272 | #define CHAN3_EN 0x08 /* enable AIOP 3 */ | |
273 | #define CHAN2_EN 0x04 /* enable AIOP 2 */ | |
274 | #define CHAN1_EN 0x02 /* enable AIOP 1 */ | |
275 | #define CHAN0_EN 0x01 /* enable AIOP 0 */ | |
276 | #define FREQ_DIS 0x00 | |
277 | #define FREQ_274HZ 0x60 | |
278 | #define FREQ_137HZ 0x50 | |
279 | #define FREQ_69HZ 0x40 | |
280 | #define FREQ_34HZ 0x30 | |
281 | #define FREQ_17HZ 0x20 | |
282 | #define FREQ_9HZ 0x10 | |
283 | #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ | |
284 | ||
285 | #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ | |
286 | ||
287 | #define RDATASIZE 72 | |
288 | #define RREGDATASIZE 52 | |
289 | ||
290 | /* | |
291 | * AIOP interrupt bits for ISA/PCI boards and UPCI boards. | |
292 | */ | |
293 | #define AIOP_INTR_BIT_0 0x0001 | |
294 | #define AIOP_INTR_BIT_1 0x0002 | |
295 | #define AIOP_INTR_BIT_2 0x0004 | |
296 | #define AIOP_INTR_BIT_3 0x0008 | |
297 | ||
298 | #define AIOP_INTR_BITS ( \ | |
299 | AIOP_INTR_BIT_0 \ | |
300 | | AIOP_INTR_BIT_1 \ | |
301 | | AIOP_INTR_BIT_2 \ | |
302 | | AIOP_INTR_BIT_3) | |
303 | ||
304 | #define UPCI_AIOP_INTR_BIT_0 0x0004 | |
305 | #define UPCI_AIOP_INTR_BIT_1 0x0020 | |
306 | #define UPCI_AIOP_INTR_BIT_2 0x0100 | |
307 | #define UPCI_AIOP_INTR_BIT_3 0x0800 | |
308 | ||
309 | #define UPCI_AIOP_INTR_BITS ( \ | |
310 | UPCI_AIOP_INTR_BIT_0 \ | |
311 | | UPCI_AIOP_INTR_BIT_1 \ | |
312 | | UPCI_AIOP_INTR_BIT_2 \ | |
313 | | UPCI_AIOP_INTR_BIT_3) | |
314 | ||
315 | /* Controller level information structure */ | |
316 | typedef struct { | |
317 | int CtlID; | |
318 | int CtlNum; | |
319 | int BusType; | |
320 | int boardType; | |
321 | int isUPCI; | |
322 | WordIO_t PCIIO; | |
323 | WordIO_t PCIIO2; | |
324 | ByteIO_t MBaseIO; | |
325 | ByteIO_t MReg1IO; | |
326 | ByteIO_t MReg2IO; | |
327 | ByteIO_t MReg3IO; | |
328 | Byte_t MReg2; | |
329 | Byte_t MReg3; | |
330 | int NumAiop; | |
331 | int AltChanRingIndicator; | |
332 | ByteIO_t UPCIRingInd; | |
333 | WordIO_t AiopIO[AIOP_CTL_SIZE]; | |
334 | ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE]; | |
335 | int AiopID[AIOP_CTL_SIZE]; | |
336 | int AiopNumChan[AIOP_CTL_SIZE]; | |
337 | Word_t *AiopIntrBits; | |
338 | } CONTROLLER_T; | |
339 | ||
340 | typedef CONTROLLER_T CONTROLLER_t; | |
341 | ||
342 | /* Channel level information structure */ | |
343 | typedef struct { | |
344 | CONTROLLER_T *CtlP; | |
345 | int AiopNum; | |
346 | int ChanID; | |
347 | int ChanNum; | |
348 | int rtsToggle; | |
349 | ||
350 | ByteIO_t Cmd; | |
351 | ByteIO_t IntChan; | |
352 | ByteIO_t IntMask; | |
353 | DWordIO_t IndexAddr; | |
354 | WordIO_t IndexData; | |
355 | ||
356 | WordIO_t TxRxData; | |
357 | WordIO_t ChanStat; | |
358 | WordIO_t TxRxCount; | |
359 | ByteIO_t IntID; | |
360 | ||
361 | Word_t TxFIFO; | |
362 | Word_t TxFIFOPtrs; | |
363 | Word_t RxFIFO; | |
364 | Word_t RxFIFOPtrs; | |
365 | Word_t TxPrioCnt; | |
366 | Word_t TxPrioPtr; | |
367 | Word_t TxPrioBuf; | |
368 | ||
369 | Byte_t R[RREGDATASIZE]; | |
370 | ||
371 | Byte_t BaudDiv[4]; | |
372 | Byte_t TxControl[4]; | |
373 | Byte_t RxControl[4]; | |
374 | Byte_t TxEnables[4]; | |
375 | Byte_t TxCompare[4]; | |
376 | Byte_t TxReplace1[4]; | |
377 | Byte_t TxReplace2[4]; | |
378 | } CHANNEL_T; | |
379 | ||
380 | typedef CHANNEL_T CHANNEL_t; | |
381 | typedef CHANNEL_T *CHANPTR_T; | |
382 | ||
383 | #define InterfaceModeRS232 0x00 | |
384 | #define InterfaceModeRS422 0x08 | |
385 | #define InterfaceModeRS485 0x10 | |
386 | #define InterfaceModeRS232T 0x18 | |
387 | ||
388 | /*************************************************************************** | |
389 | Function: sClrBreak | |
390 | Purpose: Stop sending a transmit BREAK signal | |
391 | Call: sClrBreak(ChP) | |
392 | CHANNEL_T *ChP; Ptr to channel structure | |
393 | */ | |
394 | #define sClrBreak(ChP) \ | |
395 | do { \ | |
396 | (ChP)->TxControl[3] &= ~SETBREAK; \ | |
397 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
398 | } while (0) | |
399 | ||
400 | /*************************************************************************** | |
401 | Function: sClrDTR | |
402 | Purpose: Clr the DTR output | |
403 | Call: sClrDTR(ChP) | |
404 | CHANNEL_T *ChP; Ptr to channel structure | |
405 | */ | |
406 | #define sClrDTR(ChP) \ | |
407 | do { \ | |
408 | (ChP)->TxControl[3] &= ~SET_DTR; \ | |
409 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
410 | } while (0) | |
411 | ||
412 | /*************************************************************************** | |
413 | Function: sClrRTS | |
414 | Purpose: Clr the RTS output | |
415 | Call: sClrRTS(ChP) | |
416 | CHANNEL_T *ChP; Ptr to channel structure | |
417 | */ | |
418 | #define sClrRTS(ChP) \ | |
419 | do { \ | |
420 | if ((ChP)->rtsToggle) break; \ | |
421 | (ChP)->TxControl[3] &= ~SET_RTS; \ | |
422 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
423 | } while (0) | |
424 | ||
425 | /*************************************************************************** | |
426 | Function: sClrTxXOFF | |
427 | Purpose: Clear any existing transmit software flow control off condition | |
428 | Call: sClrTxXOFF(ChP) | |
429 | CHANNEL_T *ChP; Ptr to channel structure | |
430 | */ | |
431 | #define sClrTxXOFF(ChP) \ | |
432 | do { \ | |
433 | sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ | |
434 | sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \ | |
435 | } while (0) | |
436 | ||
437 | /*************************************************************************** | |
438 | Function: sCtlNumToCtlPtr | |
439 | Purpose: Convert a controller number to controller structure pointer | |
440 | Call: sCtlNumToCtlPtr(CtlNum) | |
441 | int CtlNum; Controller number | |
442 | Return: CONTROLLER_T *: Ptr to controller structure | |
443 | */ | |
444 | #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM] | |
445 | ||
446 | /*************************************************************************** | |
447 | Function: sControllerEOI | |
448 | Purpose: Strobe the MUDBAC's End Of Interrupt bit. | |
449 | Call: sControllerEOI(CtlP) | |
450 | CONTROLLER_T *CtlP; Ptr to controller structure | |
451 | */ | |
452 | #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB) | |
453 | ||
454 | /*************************************************************************** | |
455 | Function: sPCIControllerEOI | |
456 | Purpose: Strobe the PCI End Of Interrupt bit. | |
457 | For the UPCI boards, toggle the AIOP interrupt enable bit | |
458 | (this was taken from the Windows driver). | |
459 | Call: sPCIControllerEOI(CtlP) | |
460 | CONTROLLER_T *CtlP; Ptr to controller structure | |
461 | */ | |
462 | #define sPCIControllerEOI(CTLP) \ | |
463 | do { \ | |
464 | if ((CTLP)->isUPCI) { \ | |
465 | Word_t w = sInW((CTLP)->PCIIO); \ | |
466 | sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \ | |
467 | sOutW((CTLP)->PCIIO, w); \ | |
468 | } \ | |
469 | else { \ | |
470 | sOutW((CTLP)->PCIIO, PCI_STROB); \ | |
471 | } \ | |
472 | } while (0) | |
473 | ||
474 | /*************************************************************************** | |
475 | Function: sDisAiop | |
476 | Purpose: Disable I/O access to an AIOP | |
477 | Call: sDisAiop(CltP) | |
478 | CONTROLLER_T *CtlP; Ptr to controller structure | |
479 | int AiopNum; Number of AIOP on controller | |
480 | */ | |
481 | #define sDisAiop(CTLP,AIOPNUM) \ | |
482 | do { \ | |
483 | (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \ | |
484 | sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ | |
485 | } while (0) | |
486 | ||
487 | /*************************************************************************** | |
488 | Function: sDisCTSFlowCtl | |
489 | Purpose: Disable output flow control using CTS | |
490 | Call: sDisCTSFlowCtl(ChP) | |
491 | CHANNEL_T *ChP; Ptr to channel structure | |
492 | */ | |
493 | #define sDisCTSFlowCtl(ChP) \ | |
494 | do { \ | |
495 | (ChP)->TxControl[2] &= ~CTSFC_EN; \ | |
496 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
497 | } while (0) | |
498 | ||
499 | /*************************************************************************** | |
500 | Function: sDisIXANY | |
501 | Purpose: Disable IXANY Software Flow Control | |
502 | Call: sDisIXANY(ChP) | |
503 | CHANNEL_T *ChP; Ptr to channel structure | |
504 | */ | |
505 | #define sDisIXANY(ChP) \ | |
506 | do { \ | |
507 | (ChP)->R[0x0e] = 0x86; \ | |
508 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ | |
509 | } while (0) | |
510 | ||
511 | /*************************************************************************** | |
512 | Function: DisParity | |
513 | Purpose: Disable parity | |
514 | Call: sDisParity(ChP) | |
515 | CHANNEL_T *ChP; Ptr to channel structure | |
516 | Comments: Function sSetParity() can be used in place of functions sEnParity(), | |
517 | sDisParity(), sSetOddParity(), and sSetEvenParity(). | |
518 | */ | |
519 | #define sDisParity(ChP) \ | |
520 | do { \ | |
521 | (ChP)->TxControl[2] &= ~PARITY_EN; \ | |
522 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
523 | } while (0) | |
524 | ||
525 | /*************************************************************************** | |
526 | Function: sDisRTSToggle | |
527 | Purpose: Disable RTS toggle | |
528 | Call: sDisRTSToggle(ChP) | |
529 | CHANNEL_T *ChP; Ptr to channel structure | |
530 | */ | |
531 | #define sDisRTSToggle(ChP) \ | |
532 | do { \ | |
533 | (ChP)->TxControl[2] &= ~RTSTOG_EN; \ | |
534 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
535 | (ChP)->rtsToggle = 0; \ | |
536 | } while (0) | |
537 | ||
538 | /*************************************************************************** | |
539 | Function: sDisRxFIFO | |
540 | Purpose: Disable Rx FIFO | |
541 | Call: sDisRxFIFO(ChP) | |
542 | CHANNEL_T *ChP; Ptr to channel structure | |
543 | */ | |
544 | #define sDisRxFIFO(ChP) \ | |
545 | do { \ | |
546 | (ChP)->R[0x32] = 0x0a; \ | |
547 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ | |
548 | } while (0) | |
549 | ||
550 | /*************************************************************************** | |
551 | Function: sDisRxStatusMode | |
552 | Purpose: Disable the Rx status mode | |
553 | Call: sDisRxStatusMode(ChP) | |
554 | CHANNEL_T *ChP; Ptr to channel structure | |
555 | Comments: This takes the channel out of the receive status mode. All | |
556 | subsequent reads of receive data using sReadRxWord() will return | |
557 | two data bytes. | |
558 | */ | |
559 | #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0) | |
560 | ||
561 | /*************************************************************************** | |
562 | Function: sDisTransmit | |
563 | Purpose: Disable transmit | |
564 | Call: sDisTransmit(ChP) | |
565 | CHANNEL_T *ChP; Ptr to channel structure | |
566 | This disables movement of Tx data from the Tx FIFO into the 1 byte | |
567 | Tx buffer. Therefore there could be up to a 2 byte latency | |
568 | between the time sDisTransmit() is called and the transmit buffer | |
569 | and transmit shift register going completely empty. | |
570 | */ | |
571 | #define sDisTransmit(ChP) \ | |
572 | do { \ | |
573 | (ChP)->TxControl[3] &= ~TX_ENABLE; \ | |
574 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
575 | } while (0) | |
576 | ||
577 | /*************************************************************************** | |
578 | Function: sDisTxSoftFlowCtl | |
579 | Purpose: Disable Tx Software Flow Control | |
580 | Call: sDisTxSoftFlowCtl(ChP) | |
581 | CHANNEL_T *ChP; Ptr to channel structure | |
582 | */ | |
583 | #define sDisTxSoftFlowCtl(ChP) \ | |
584 | do { \ | |
585 | (ChP)->R[0x06] = 0x8a; \ | |
586 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ | |
587 | } while (0) | |
588 | ||
589 | /*************************************************************************** | |
590 | Function: sEnAiop | |
591 | Purpose: Enable I/O access to an AIOP | |
592 | Call: sEnAiop(CltP) | |
593 | CONTROLLER_T *CtlP; Ptr to controller structure | |
594 | int AiopNum; Number of AIOP on controller | |
595 | */ | |
596 | #define sEnAiop(CTLP,AIOPNUM) \ | |
597 | do { \ | |
598 | (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \ | |
599 | sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ | |
600 | } while (0) | |
601 | ||
602 | /*************************************************************************** | |
603 | Function: sEnCTSFlowCtl | |
604 | Purpose: Enable output flow control using CTS | |
605 | Call: sEnCTSFlowCtl(ChP) | |
606 | CHANNEL_T *ChP; Ptr to channel structure | |
607 | */ | |
608 | #define sEnCTSFlowCtl(ChP) \ | |
609 | do { \ | |
610 | (ChP)->TxControl[2] |= CTSFC_EN; \ | |
611 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
612 | } while (0) | |
613 | ||
614 | /*************************************************************************** | |
615 | Function: sEnIXANY | |
616 | Purpose: Enable IXANY Software Flow Control | |
617 | Call: sEnIXANY(ChP) | |
618 | CHANNEL_T *ChP; Ptr to channel structure | |
619 | */ | |
620 | #define sEnIXANY(ChP) \ | |
621 | do { \ | |
622 | (ChP)->R[0x0e] = 0x21; \ | |
623 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ | |
624 | } while (0) | |
625 | ||
626 | /*************************************************************************** | |
627 | Function: EnParity | |
628 | Purpose: Enable parity | |
629 | Call: sEnParity(ChP) | |
630 | CHANNEL_T *ChP; Ptr to channel structure | |
631 | Comments: Function sSetParity() can be used in place of functions sEnParity(), | |
632 | sDisParity(), sSetOddParity(), and sSetEvenParity(). | |
633 | ||
634 | Warnings: Before enabling parity odd or even parity should be chosen using | |
635 | functions sSetOddParity() or sSetEvenParity(). | |
636 | */ | |
637 | #define sEnParity(ChP) \ | |
638 | do { \ | |
639 | (ChP)->TxControl[2] |= PARITY_EN; \ | |
640 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
641 | } while (0) | |
642 | ||
643 | /*************************************************************************** | |
644 | Function: sEnRTSToggle | |
645 | Purpose: Enable RTS toggle | |
646 | Call: sEnRTSToggle(ChP) | |
647 | CHANNEL_T *ChP; Ptr to channel structure | |
648 | Comments: This function will disable RTS flow control and clear the RTS | |
649 | line to allow operation of RTS toggle. | |
650 | */ | |
651 | #define sEnRTSToggle(ChP) \ | |
652 | do { \ | |
653 | (ChP)->RxControl[2] &= ~RTSFC_EN; \ | |
654 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ | |
655 | (ChP)->TxControl[2] |= RTSTOG_EN; \ | |
656 | (ChP)->TxControl[3] &= ~SET_RTS; \ | |
657 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
658 | (ChP)->rtsToggle = 1; \ | |
659 | } while (0) | |
660 | ||
661 | /*************************************************************************** | |
662 | Function: sEnRxFIFO | |
663 | Purpose: Enable Rx FIFO | |
664 | Call: sEnRxFIFO(ChP) | |
665 | CHANNEL_T *ChP; Ptr to channel structure | |
666 | */ | |
667 | #define sEnRxFIFO(ChP) \ | |
668 | do { \ | |
669 | (ChP)->R[0x32] = 0x08; \ | |
670 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ | |
671 | } while (0) | |
672 | ||
673 | /*************************************************************************** | |
674 | Function: sEnRxProcessor | |
675 | Purpose: Enable the receive processor | |
676 | Call: sEnRxProcessor(ChP) | |
677 | CHANNEL_T *ChP; Ptr to channel structure | |
678 | Comments: This function is used to start the receive processor. When | |
679 | the channel is in the reset state the receive processor is not | |
680 | running. This is done to prevent the receive processor from | |
681 | executing invalid microcode instructions prior to the | |
682 | downloading of the microcode. | |
683 | ||
684 | Warnings: This function must be called after valid microcode has been | |
685 | downloaded to the AIOP, and it must not be called before the | |
686 | microcode has been downloaded. | |
687 | */ | |
688 | #define sEnRxProcessor(ChP) \ | |
689 | do { \ | |
690 | (ChP)->RxControl[2] |= RXPROC_EN; \ | |
691 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ | |
692 | } while (0) | |
693 | ||
694 | /*************************************************************************** | |
695 | Function: sEnRxStatusMode | |
696 | Purpose: Enable the Rx status mode | |
697 | Call: sEnRxStatusMode(ChP) | |
698 | CHANNEL_T *ChP; Ptr to channel structure | |
699 | Comments: This places the channel in the receive status mode. All subsequent | |
700 | reads of receive data using sReadRxWord() will return a data byte | |
701 | in the low word and a status byte in the high word. | |
702 | ||
703 | */ | |
704 | #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE) | |
705 | ||
706 | /*************************************************************************** | |
707 | Function: sEnTransmit | |
708 | Purpose: Enable transmit | |
709 | Call: sEnTransmit(ChP) | |
710 | CHANNEL_T *ChP; Ptr to channel structure | |
711 | */ | |
712 | #define sEnTransmit(ChP) \ | |
713 | do { \ | |
714 | (ChP)->TxControl[3] |= TX_ENABLE; \ | |
715 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
716 | } while (0) | |
717 | ||
718 | /*************************************************************************** | |
719 | Function: sEnTxSoftFlowCtl | |
720 | Purpose: Enable Tx Software Flow Control | |
721 | Call: sEnTxSoftFlowCtl(ChP) | |
722 | CHANNEL_T *ChP; Ptr to channel structure | |
723 | */ | |
724 | #define sEnTxSoftFlowCtl(ChP) \ | |
725 | do { \ | |
726 | (ChP)->R[0x06] = 0xc5; \ | |
727 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ | |
728 | } while (0) | |
729 | ||
730 | /*************************************************************************** | |
731 | Function: sGetAiopIntStatus | |
732 | Purpose: Get the AIOP interrupt status | |
733 | Call: sGetAiopIntStatus(CtlP,AiopNum) | |
734 | CONTROLLER_T *CtlP; Ptr to controller structure | |
735 | int AiopNum; AIOP number | |
736 | Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 | |
737 | represent channels 0 through 7 respectively. If a | |
738 | bit is set that channel is interrupting. | |
739 | */ | |
740 | #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM]) | |
741 | ||
742 | /*************************************************************************** | |
743 | Function: sGetAiopNumChan | |
744 | Purpose: Get the number of channels supported by an AIOP | |
745 | Call: sGetAiopNumChan(CtlP,AiopNum) | |
746 | CONTROLLER_T *CtlP; Ptr to controller structure | |
747 | int AiopNum; AIOP number | |
748 | Return: int: The number of channels supported by the AIOP | |
749 | */ | |
750 | #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM] | |
751 | ||
752 | /*************************************************************************** | |
753 | Function: sGetChanIntID | |
754 | Purpose: Get a channel's interrupt identification byte | |
755 | Call: sGetChanIntID(ChP) | |
756 | CHANNEL_T *ChP; Ptr to channel structure | |
757 | Return: Byte_t: The channel interrupt ID. Can be any | |
758 | combination of the following flags: | |
759 | RXF_TRIG: Rx FIFO trigger level interrupt | |
760 | TXFIFO_MT: Tx FIFO empty interrupt | |
761 | SRC_INT: Special receive condition interrupt | |
762 | DELTA_CD: CD change interrupt | |
763 | DELTA_CTS: CTS change interrupt | |
764 | DELTA_DSR: DSR change interrupt | |
765 | */ | |
766 | #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) | |
767 | ||
768 | /*************************************************************************** | |
769 | Function: sGetChanNum | |
770 | Purpose: Get the number of a channel within an AIOP | |
771 | Call: sGetChanNum(ChP) | |
772 | CHANNEL_T *ChP; Ptr to channel structure | |
773 | Return: int: Channel number within AIOP, or NULLCHAN if channel does | |
774 | not exist. | |
775 | */ | |
776 | #define sGetChanNum(ChP) (ChP)->ChanNum | |
777 | ||
778 | /*************************************************************************** | |
779 | Function: sGetChanStatus | |
780 | Purpose: Get the channel status | |
781 | Call: sGetChanStatus(ChP) | |
782 | CHANNEL_T *ChP; Ptr to channel structure | |
783 | Return: Word_t: The channel status. Can be any combination of | |
784 | the following flags: | |
785 | LOW BYTE FLAGS | |
786 | CTS_ACT: CTS input asserted | |
787 | DSR_ACT: DSR input asserted | |
788 | CD_ACT: CD input asserted | |
789 | TXFIFOMT: Tx FIFO is empty | |
790 | TXSHRMT: Tx shift register is empty | |
791 | RDA: Rx data available | |
792 | ||
793 | HIGH BYTE FLAGS | |
794 | STATMODE: status mode enable bit | |
795 | RXFOVERFL: receive FIFO overflow | |
796 | RX2MATCH: receive compare byte 2 match | |
797 | RX1MATCH: receive compare byte 1 match | |
798 | RXBREAK: received BREAK | |
799 | RXFRAME: received framing error | |
800 | RXPARITY: received parity error | |
801 | Warnings: This function will clear the high byte flags in the Channel | |
802 | Status Register. | |
803 | */ | |
804 | #define sGetChanStatus(ChP) sInW((ChP)->ChanStat) | |
805 | ||
806 | /*************************************************************************** | |
807 | Function: sGetChanStatusLo | |
808 | Purpose: Get the low byte only of the channel status | |
809 | Call: sGetChanStatusLo(ChP) | |
810 | CHANNEL_T *ChP; Ptr to channel structure | |
811 | Return: Byte_t: The channel status low byte. Can be any combination | |
812 | of the following flags: | |
813 | CTS_ACT: CTS input asserted | |
814 | DSR_ACT: DSR input asserted | |
815 | CD_ACT: CD input asserted | |
816 | TXFIFOMT: Tx FIFO is empty | |
817 | TXSHRMT: Tx shift register is empty | |
818 | RDA: Rx data available | |
819 | */ | |
820 | #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat) | |
821 | ||
822 | /********************************************************************** | |
823 | * Get RI status of channel | |
824 | * Defined as a function in rocket.c -aes | |
825 | */ | |
826 | #if 0 | |
827 | #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \ | |
828 | (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \ | |
829 | (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \ | |
830 | (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \ | |
831 | 0)) | |
832 | #endif | |
833 | ||
834 | /*************************************************************************** | |
835 | Function: sGetControllerIntStatus | |
836 | Purpose: Get the controller interrupt status | |
837 | Call: sGetControllerIntStatus(CtlP) | |
838 | CONTROLLER_T *CtlP; Ptr to controller structure | |
839 | Return: Byte_t: The controller interrupt status in the lower 4 | |
840 | bits. Bits 0 through 3 represent AIOP's 0 | |
841 | through 3 respectively. If a bit is set that | |
842 | AIOP is interrupting. Bits 4 through 7 will | |
843 | always be cleared. | |
844 | */ | |
845 | #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f) | |
846 | ||
847 | /*************************************************************************** | |
848 | Function: sPCIGetControllerIntStatus | |
849 | Purpose: Get the controller interrupt status | |
850 | Call: sPCIGetControllerIntStatus(CtlP) | |
851 | CONTROLLER_T *CtlP; Ptr to controller structure | |
852 | Return: unsigned char: The controller interrupt status in the lower 4 | |
853 | bits and bit 4. Bits 0 through 3 represent AIOP's 0 | |
854 | through 3 respectively. Bit 4 is set if the int | |
855 | was generated from periodic. If a bit is set the | |
856 | AIOP is interrupting. | |
857 | */ | |
858 | #define sPCIGetControllerIntStatus(CTLP) \ | |
859 | ((CTLP)->isUPCI ? \ | |
860 | (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \ | |
861 | ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS)) | |
862 | ||
863 | /*************************************************************************** | |
864 | ||
865 | Function: sGetRxCnt | |
866 | Purpose: Get the number of data bytes in the Rx FIFO | |
867 | Call: sGetRxCnt(ChP) | |
868 | CHANNEL_T *ChP; Ptr to channel structure | |
869 | Return: int: The number of data bytes in the Rx FIFO. | |
870 | Comments: Byte read of count register is required to obtain Rx count. | |
871 | ||
872 | */ | |
873 | #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount) | |
874 | ||
875 | /*************************************************************************** | |
876 | Function: sGetTxCnt | |
877 | Purpose: Get the number of data bytes in the Tx FIFO | |
878 | Call: sGetTxCnt(ChP) | |
879 | CHANNEL_T *ChP; Ptr to channel structure | |
880 | Return: Byte_t: The number of data bytes in the Tx FIFO. | |
881 | Comments: Byte read of count register is required to obtain Tx count. | |
882 | ||
883 | */ | |
884 | #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount) | |
885 | ||
886 | /***************************************************************************** | |
887 | Function: sGetTxRxDataIO | |
888 | Purpose: Get the I/O address of a channel's TxRx Data register | |
889 | Call: sGetTxRxDataIO(ChP) | |
890 | CHANNEL_T *ChP; Ptr to channel structure | |
891 | Return: WordIO_t: I/O address of a channel's TxRx Data register | |
892 | */ | |
893 | #define sGetTxRxDataIO(ChP) (ChP)->TxRxData | |
894 | ||
895 | /*************************************************************************** | |
896 | Function: sInitChanDefaults | |
897 | Purpose: Initialize a channel structure to it's default state. | |
898 | Call: sInitChanDefaults(ChP) | |
899 | CHANNEL_T *ChP; Ptr to the channel structure | |
900 | Comments: This function must be called once for every channel structure | |
901 | that exists before any other SSCI calls can be made. | |
902 | ||
903 | */ | |
904 | #define sInitChanDefaults(ChP) \ | |
905 | do { \ | |
906 | (ChP)->CtlP = NULLCTLPTR; \ | |
907 | (ChP)->AiopNum = NULLAIOP; \ | |
908 | (ChP)->ChanID = AIOPID_NULL; \ | |
909 | (ChP)->ChanNum = NULLCHAN; \ | |
910 | } while (0) | |
911 | ||
912 | /*************************************************************************** | |
913 | Function: sResetAiopByNum | |
914 | Purpose: Reset the AIOP by number | |
915 | Call: sResetAiopByNum(CTLP,AIOPNUM) | |
916 | CONTROLLER_T CTLP; Ptr to controller structure | |
917 | AIOPNUM; AIOP index | |
918 | */ | |
919 | #define sResetAiopByNum(CTLP,AIOPNUM) \ | |
920 | do { \ | |
921 | sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \ | |
922 | sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \ | |
923 | } while (0) | |
924 | ||
925 | /*************************************************************************** | |
926 | Function: sSendBreak | |
927 | Purpose: Send a transmit BREAK signal | |
928 | Call: sSendBreak(ChP) | |
929 | CHANNEL_T *ChP; Ptr to channel structure | |
930 | */ | |
931 | #define sSendBreak(ChP) \ | |
932 | do { \ | |
933 | (ChP)->TxControl[3] |= SETBREAK; \ | |
934 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
935 | } while (0) | |
936 | ||
937 | /*************************************************************************** | |
938 | Function: sSetBaud | |
939 | Purpose: Set baud rate | |
940 | Call: sSetBaud(ChP,Divisor) | |
941 | CHANNEL_T *ChP; Ptr to channel structure | |
942 | Word_t Divisor; 16 bit baud rate divisor for channel | |
943 | */ | |
944 | #define sSetBaud(ChP,DIVISOR) \ | |
945 | do { \ | |
946 | (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ | |
947 | (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ | |
948 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \ | |
949 | } while (0) | |
950 | ||
951 | /*************************************************************************** | |
952 | Function: sSetData7 | |
953 | Purpose: Set data bits to 7 | |
954 | Call: sSetData7(ChP) | |
955 | CHANNEL_T *ChP; Ptr to channel structure | |
956 | */ | |
957 | #define sSetData7(ChP) \ | |
958 | do { \ | |
959 | (ChP)->TxControl[2] &= ~DATA8BIT; \ | |
960 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
961 | } while (0) | |
962 | ||
963 | /*************************************************************************** | |
964 | Function: sSetData8 | |
965 | Purpose: Set data bits to 8 | |
966 | Call: sSetData8(ChP) | |
967 | CHANNEL_T *ChP; Ptr to channel structure | |
968 | */ | |
969 | #define sSetData8(ChP) \ | |
970 | do { \ | |
971 | (ChP)->TxControl[2] |= DATA8BIT; \ | |
972 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
973 | } while (0) | |
974 | ||
975 | /*************************************************************************** | |
976 | Function: sSetDTR | |
977 | Purpose: Set the DTR output | |
978 | Call: sSetDTR(ChP) | |
979 | CHANNEL_T *ChP; Ptr to channel structure | |
980 | */ | |
981 | #define sSetDTR(ChP) \ | |
982 | do { \ | |
983 | (ChP)->TxControl[3] |= SET_DTR; \ | |
984 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
985 | } while (0) | |
986 | ||
987 | /*************************************************************************** | |
988 | Function: sSetEvenParity | |
989 | Purpose: Set even parity | |
990 | Call: sSetEvenParity(ChP) | |
991 | CHANNEL_T *ChP; Ptr to channel structure | |
992 | Comments: Function sSetParity() can be used in place of functions sEnParity(), | |
993 | sDisParity(), sSetOddParity(), and sSetEvenParity(). | |
994 | ||
995 | Warnings: This function has no effect unless parity is enabled with function | |
996 | sEnParity(). | |
997 | */ | |
998 | #define sSetEvenParity(ChP) \ | |
999 | do { \ | |
1000 | (ChP)->TxControl[2] |= EVEN_PAR; \ | |
1001 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
1002 | } while (0) | |
1003 | ||
1004 | /*************************************************************************** | |
1005 | Function: sSetOddParity | |
1006 | Purpose: Set odd parity | |
1007 | Call: sSetOddParity(ChP) | |
1008 | CHANNEL_T *ChP; Ptr to channel structure | |
1009 | Comments: Function sSetParity() can be used in place of functions sEnParity(), | |
1010 | sDisParity(), sSetOddParity(), and sSetEvenParity(). | |
1011 | ||
1012 | Warnings: This function has no effect unless parity is enabled with function | |
1013 | sEnParity(). | |
1014 | */ | |
1015 | #define sSetOddParity(ChP) \ | |
1016 | do { \ | |
1017 | (ChP)->TxControl[2] &= ~EVEN_PAR; \ | |
1018 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
1019 | } while (0) | |
1020 | ||
1021 | /*************************************************************************** | |
1022 | Function: sSetRTS | |
1023 | Purpose: Set the RTS output | |
1024 | Call: sSetRTS(ChP) | |
1025 | CHANNEL_T *ChP; Ptr to channel structure | |
1026 | */ | |
1027 | #define sSetRTS(ChP) \ | |
1028 | do { \ | |
1029 | if ((ChP)->rtsToggle) break; \ | |
1030 | (ChP)->TxControl[3] |= SET_RTS; \ | |
1031 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
1032 | } while (0) | |
1033 | ||
1034 | /*************************************************************************** | |
1035 | Function: sSetRxTrigger | |
1036 | Purpose: Set the Rx FIFO trigger level | |
1037 | Call: sSetRxProcessor(ChP,Level) | |
1038 | CHANNEL_T *ChP; Ptr to channel structure | |
1039 | Byte_t Level; Number of characters in Rx FIFO at which the | |
1040 | interrupt will be generated. Can be any of the following flags: | |
1041 | ||
1042 | TRIG_NO: no trigger | |
1043 | TRIG_1: 1 character in FIFO | |
1044 | TRIG_1_2: FIFO 1/2 full | |
1045 | TRIG_7_8: FIFO 7/8 full | |
1046 | Comments: An interrupt will be generated when the trigger level is reached | |
1047 | only if function sEnInterrupt() has been called with flag | |
1048 | RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification | |
1049 | register will be set whenever the trigger level is reached | |
1050 | regardless of the setting of RXINT_EN. | |
1051 | ||
1052 | */ | |
1053 | #define sSetRxTrigger(ChP,LEVEL) \ | |
1054 | do { \ | |
1055 | (ChP)->RxControl[2] &= ~TRIG_MASK; \ | |
1056 | (ChP)->RxControl[2] |= LEVEL; \ | |
1057 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ | |
1058 | } while (0) | |
1059 | ||
1060 | /*************************************************************************** | |
1061 | Function: sSetStop1 | |
1062 | Purpose: Set stop bits to 1 | |
1063 | Call: sSetStop1(ChP) | |
1064 | CHANNEL_T *ChP; Ptr to channel structure | |
1065 | */ | |
1066 | #define sSetStop1(ChP) \ | |
1067 | do { \ | |
1068 | (ChP)->TxControl[2] &= ~STOP2; \ | |
1069 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
1070 | } while (0) | |
1071 | ||
1072 | /*************************************************************************** | |
1073 | Function: sSetStop2 | |
1074 | Purpose: Set stop bits to 2 | |
1075 | Call: sSetStop2(ChP) | |
1076 | CHANNEL_T *ChP; Ptr to channel structure | |
1077 | */ | |
1078 | #define sSetStop2(ChP) \ | |
1079 | do { \ | |
1080 | (ChP)->TxControl[2] |= STOP2; \ | |
1081 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | |
1082 | } while (0) | |
1083 | ||
1084 | /*************************************************************************** | |
1085 | Function: sSetTxXOFFChar | |
1086 | Purpose: Set the Tx XOFF flow control character | |
1087 | Call: sSetTxXOFFChar(ChP,Ch) | |
1088 | CHANNEL_T *ChP; Ptr to channel structure | |
1089 | Byte_t Ch; The value to set the Tx XOFF character to | |
1090 | */ | |
1091 | #define sSetTxXOFFChar(ChP,CH) \ | |
1092 | do { \ | |
1093 | (ChP)->R[0x07] = (CH); \ | |
1094 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ | |
1095 | } while (0) | |
1096 | ||
1097 | /*************************************************************************** | |
1098 | Function: sSetTxXONChar | |
1099 | Purpose: Set the Tx XON flow control character | |
1100 | Call: sSetTxXONChar(ChP,Ch) | |
1101 | CHANNEL_T *ChP; Ptr to channel structure | |
1102 | Byte_t Ch; The value to set the Tx XON character to | |
1103 | */ | |
1104 | #define sSetTxXONChar(ChP,CH) \ | |
1105 | do { \ | |
1106 | (ChP)->R[0x0b] = (CH); \ | |
1107 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \ | |
1108 | } while (0) | |
1109 | ||
1110 | /*************************************************************************** | |
1111 | Function: sStartRxProcessor | |
1112 | Purpose: Start a channel's receive processor | |
1113 | Call: sStartRxProcessor(ChP) | |
1114 | CHANNEL_T *ChP; Ptr to channel structure | |
1115 | Comments: This function is used to start a Rx processor after it was | |
1116 | stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It | |
1117 | will restart both the Rx processor and software input flow control. | |
1118 | ||
1119 | */ | |
1120 | #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0]) | |
1121 | ||
1122 | /*************************************************************************** | |
1123 | Function: sWriteTxByte | |
1124 | Purpose: Write a transmit data byte to a channel. | |
1125 | ByteIO_t io: Channel transmit register I/O address. This can | |
1126 | be obtained with sGetTxRxDataIO(). | |
1127 | Byte_t Data; The transmit data byte. | |
1128 | Warnings: This function writes the data byte without checking to see if | |
1129 | sMaxTxSize is exceeded in the Tx FIFO. | |
1130 | */ | |
1131 | #define sWriteTxByte(IO,DATA) sOutB(IO,DATA) | |
1132 | ||
1133 | int sInitController(CONTROLLER_T * CtlP, | |
1134 | int CtlNum, | |
1135 | ByteIO_t MudbacIO, | |
1136 | ByteIO_t * AiopIOList, | |
1137 | int AiopIOListSize, | |
1138 | int IRQNum, Byte_t Frequency, int PeriodicOnly); | |
1139 | ||
1140 | int sPCIInitController(CONTROLLER_T * CtlP, | |
1141 | int CtlNum, | |
1142 | ByteIO_t * AiopIOList, | |
1143 | int AiopIOListSize, | |
1144 | WordIO_t ConfigIO, | |
1145 | int IRQNum, | |
1146 | Byte_t Frequency, | |
1147 | int PeriodicOnly, | |
1148 | int altChanRingIndicator, int UPCIRingInd); | |
1149 | ||
1150 | int sReadAiopID(ByteIO_t io); | |
1151 | int sReadAiopNumChan(WordIO_t io); | |
1152 | int sInitChan(CONTROLLER_T * CtlP, | |
1153 | CHANNEL_T * ChP, int AiopNum, int ChanNum); | |
1154 | Byte_t sGetRxErrStatus(CHANNEL_T * ChP); | |
1155 | void sStopRxProcessor(CHANNEL_T * ChP); | |
1156 | void sStopSWInFlowCtl(CHANNEL_T * ChP); | |
1157 | void sFlushRxFIFO(CHANNEL_T * ChP); | |
1158 | void sFlushTxFIFO(CHANNEL_T * ChP); | |
1159 | int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data); | |
1160 | void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags); | |
1161 | void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags); | |
1162 | void sModemReset(CONTROLLER_T * CtlP, int chan, int on); | |
1163 | void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on); | |
1164 | void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode); | |
1165 | ||
1166 | extern Byte_t R[RDATASIZE]; | |
1167 | extern CONTROLLER_T sController[CTL_SIZE]; | |
1168 | extern Byte_t sIRQMap[16]; | |
1169 | extern Byte_t sBitMapClrTbl[8]; | |
1170 | extern Byte_t sBitMapSetTbl[8]; | |
1171 | extern int sClockPrescale; | |
1172 | ||
1173 | /* | |
1174 | * Begin Linux specific definitions for the Rocketport driver | |
1175 | * | |
1176 | * This code is Copyright Theodore Ts'o, 1995-1997 | |
1177 | */ | |
1178 | ||
1179 | struct r_port { | |
1180 | int magic; | |
1181 | int line; | |
1182 | int flags; | |
1183 | int count; | |
1184 | int blocked_open; | |
1185 | struct tty_struct *tty; | |
1186 | unsigned int board:3; | |
1187 | unsigned int aiop:2; | |
1188 | unsigned int chan:3; | |
1189 | CONTROLLER_t *ctlp; | |
1190 | CHANNEL_t channel; | |
1191 | int closing_wait; | |
1192 | int close_delay; | |
1193 | int intmask; | |
1194 | int xmit_fifo_room; /* room in xmit fifo */ | |
1195 | unsigned char *xmit_buf; | |
1196 | int xmit_head; | |
1197 | int xmit_tail; | |
1198 | int xmit_cnt; | |
1199 | int session; | |
1200 | int pgrp; | |
1201 | int cd_status; | |
1202 | int ignore_status_mask; | |
1203 | int read_status_mask; | |
1204 | int cps; | |
1205 | ||
1206 | #ifdef DECLARE_WAITQUEUE | |
1207 | wait_queue_head_t open_wait; | |
1208 | wait_queue_head_t close_wait; | |
1209 | #else | |
1210 | struct wait_queue *open_wait; | |
1211 | struct wait_queue *close_wait; | |
1212 | #endif | |
1213 | spinlock_t slock; | |
1214 | struct semaphore write_sem; | |
1215 | }; | |
1216 | ||
1217 | #define RPORT_MAGIC 0x525001 | |
1218 | ||
1219 | #define NUM_BOARDS 8 | |
1220 | #define MAX_RP_PORTS (32*NUM_BOARDS) | |
1221 | ||
1222 | /* | |
1223 | * The size of the xmit buffer is 1 page, or 4096 bytes | |
1224 | */ | |
1225 | #define XMIT_BUF_SIZE 4096 | |
1226 | ||
1227 | /* number of characters left in xmit buffer before we ask for more */ | |
1228 | #define WAKEUP_CHARS 256 | |
1229 | ||
1230 | /* Internal flags used only by the rocketport driver */ | |
1231 | #define ROCKET_INITIALIZED 0x80000000 /* Port is active */ | |
1232 | #define ROCKET_CLOSING 0x40000000 /* Serial port is closing */ | |
1233 | #define ROCKET_NORMAL_ACTIVE 0x20000000 /* Normal port is active */ | |
1234 | ||
1235 | /* tty subtypes */ | |
1236 | #define SERIAL_TYPE_NORMAL 1 | |
1237 | ||
1238 | /* | |
1239 | * Assigned major numbers for the Comtrol Rocketport | |
1240 | */ | |
1241 | #define TTY_ROCKET_MAJOR 46 | |
1242 | #define CUA_ROCKET_MAJOR 47 | |
1243 | ||
1244 | #ifdef PCI_VENDOR_ID_RP | |
1245 | #undef PCI_VENDOR_ID_RP | |
1246 | #undef PCI_DEVICE_ID_RP8OCTA | |
1247 | #undef PCI_DEVICE_ID_RP8INTF | |
1248 | #undef PCI_DEVICE_ID_RP16INTF | |
1249 | #undef PCI_DEVICE_ID_RP32INTF | |
1250 | #undef PCI_DEVICE_ID_URP8OCTA | |
1251 | #undef PCI_DEVICE_ID_URP8INTF | |
1252 | #undef PCI_DEVICE_ID_URP16INTF | |
1253 | #undef PCI_DEVICE_ID_CRP16INTF | |
1254 | #undef PCI_DEVICE_ID_URP32INTF | |
1255 | #endif | |
1256 | ||
1257 | /* Comtrol PCI Vendor ID */ | |
1258 | #define PCI_VENDOR_ID_RP 0x11fe | |
1259 | ||
1260 | /* Comtrol Device ID's */ | |
1261 | #define PCI_DEVICE_ID_RP32INTF 0x0001 /* Rocketport 32 port w/external I/F */ | |
1262 | #define PCI_DEVICE_ID_RP8INTF 0x0002 /* Rocketport 8 port w/external I/F */ | |
1263 | #define PCI_DEVICE_ID_RP16INTF 0x0003 /* Rocketport 16 port w/external I/F */ | |
1264 | #define PCI_DEVICE_ID_RP4QUAD 0x0004 /* Rocketport 4 port w/quad cable */ | |
1265 | #define PCI_DEVICE_ID_RP8OCTA 0x0005 /* Rocketport 8 port w/octa cable */ | |
1266 | #define PCI_DEVICE_ID_RP8J 0x0006 /* Rocketport 8 port w/RJ11 connectors */ | |
1267 | #define PCI_DEVICE_ID_RP4J 0x0007 /* Rocketport 4 port w/RJ11 connectors */ | |
1268 | #define PCI_DEVICE_ID_RP8SNI 0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */ | |
1269 | #define PCI_DEVICE_ID_RP16SNI 0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */ | |
1270 | #define PCI_DEVICE_ID_RPP4 0x000A /* Rocketport Plus 4 port */ | |
1271 | #define PCI_DEVICE_ID_RPP8 0x000B /* Rocketport Plus 8 port */ | |
1272 | #define PCI_DEVICE_ID_RP6M 0x000C /* RocketModem 6 port */ | |
1273 | #define PCI_DEVICE_ID_RP4M 0x000D /* RocketModem 4 port */ | |
1274 | #define PCI_DEVICE_ID_RP2_232 0x000E /* Rocketport Plus 2 port RS232 */ | |
1275 | #define PCI_DEVICE_ID_RP2_422 0x000F /* Rocketport Plus 2 port RS422 */ | |
1276 | ||
1277 | /* Universal PCI boards */ | |
1278 | #define PCI_DEVICE_ID_URP32INTF 0x0801 /* Rocketport UPCI 32 port w/external I/F */ | |
1279 | #define PCI_DEVICE_ID_URP8INTF 0x0802 /* Rocketport UPCI 8 port w/external I/F */ | |
1280 | #define PCI_DEVICE_ID_URP16INTF 0x0803 /* Rocketport UPCI 16 port w/external I/F */ | |
1281 | #define PCI_DEVICE_ID_URP8OCTA 0x0805 /* Rocketport UPCI 8 port w/octa cable */ | |
1282 | #define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C /* Rocketmodem III 8 port */ | |
1283 | #define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D /* Rocketmodem III 4 port */ | |
1284 | ||
1285 | /* Compact PCI device */ | |
1286 | #define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */ | |
1287 | ||
1288 | #define TTY_GET_LINE(t) t->index | |
1289 | #define TTY_DRIVER_MINOR_START(t) t->driver->minor_start | |
1290 | #define TTY_DRIVER_SUBTYPE(t) t->driver->subtype | |
1291 | #define TTY_DRIVER_NAME(t) t->driver->name | |
1292 | #define TTY_DRIVER_NAME_BASE(t) t->driver->name_base | |
1293 | #define TTY_DRIVER_FLUSH_BUFFER_EXISTS(t) t->driver->flush_buffer | |
1294 | #define TTY_DRIVER_FLUSH_BUFFER(t) t->driver->flush_buffer(t) | |
1295 | ||
1296 |