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705b6c7b | 1 | /* |
0c8365ec | 2 | * $Id: synclink_gt.c,v 4.22 2006/01/09 20:16:06 paulkf Exp $ |
705b6c7b PF |
3 | * |
4 | * Device driver for Microgate SyncLink GT serial adapters. | |
5 | * | |
6 | * written by Paul Fulghum for Microgate Corporation | |
7 | * paulkf@microgate.com | |
8 | * | |
9 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
10 | * | |
11 | * This code is released under the GNU General Public License (GPL) | |
12 | * | |
13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
15 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
16 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
17 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
18 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
19 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
21 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
22 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
23 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
24 | */ | |
25 | ||
26 | /* | |
27 | * DEBUG OUTPUT DEFINITIONS | |
28 | * | |
29 | * uncomment lines below to enable specific types of debug output | |
30 | * | |
31 | * DBGINFO information - most verbose output | |
32 | * DBGERR serious errors | |
33 | * DBGBH bottom half service routine debugging | |
34 | * DBGISR interrupt service routine debugging | |
35 | * DBGDATA output receive and transmit data | |
36 | * DBGTBUF output transmit DMA buffers and registers | |
37 | * DBGRBUF output receive DMA buffers and registers | |
38 | */ | |
39 | ||
40 | #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt | |
41 | #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt | |
42 | #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt | |
43 | #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt | |
44 | #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) | |
45 | //#define DBGTBUF(info) dump_tbufs(info) | |
46 | //#define DBGRBUF(info) dump_rbufs(info) | |
47 | ||
48 | ||
49 | #include <linux/config.h> | |
50 | #include <linux/module.h> | |
51 | #include <linux/version.h> | |
52 | #include <linux/errno.h> | |
53 | #include <linux/signal.h> | |
54 | #include <linux/sched.h> | |
55 | #include <linux/timer.h> | |
56 | #include <linux/interrupt.h> | |
57 | #include <linux/pci.h> | |
58 | #include <linux/tty.h> | |
59 | #include <linux/tty_flip.h> | |
60 | #include <linux/serial.h> | |
61 | #include <linux/major.h> | |
62 | #include <linux/string.h> | |
63 | #include <linux/fcntl.h> | |
64 | #include <linux/ptrace.h> | |
65 | #include <linux/ioport.h> | |
66 | #include <linux/mm.h> | |
67 | #include <linux/slab.h> | |
68 | #include <linux/netdevice.h> | |
69 | #include <linux/vmalloc.h> | |
70 | #include <linux/init.h> | |
71 | #include <linux/delay.h> | |
72 | #include <linux/ioctl.h> | |
73 | #include <linux/termios.h> | |
74 | #include <linux/bitops.h> | |
75 | #include <linux/workqueue.h> | |
76 | #include <linux/hdlc.h> | |
77 | ||
705b6c7b PF |
78 | #include <asm/system.h> |
79 | #include <asm/io.h> | |
80 | #include <asm/irq.h> | |
81 | #include <asm/dma.h> | |
82 | #include <asm/types.h> | |
83 | #include <asm/uaccess.h> | |
84 | ||
85 | #include "linux/synclink.h" | |
86 | ||
87 | #ifdef CONFIG_HDLC_MODULE | |
88 | #define CONFIG_HDLC 1 | |
89 | #endif | |
90 | ||
91 | /* | |
92 | * module identification | |
93 | */ | |
94 | static char *driver_name = "SyncLink GT"; | |
0c8365ec | 95 | static char *driver_version = "$Revision: 4.22 $"; |
705b6c7b PF |
96 | static char *tty_driver_name = "synclink_gt"; |
97 | static char *tty_dev_prefix = "ttySLG"; | |
98 | MODULE_LICENSE("GPL"); | |
99 | #define MGSL_MAGIC 0x5401 | |
100 | #define MAX_DEVICES 12 | |
101 | ||
102 | static struct pci_device_id pci_table[] = { | |
103 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
104 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
105 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
106 | {0,}, /* terminate list */ | |
107 | }; | |
108 | MODULE_DEVICE_TABLE(pci, pci_table); | |
109 | ||
110 | static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); | |
111 | static void remove_one(struct pci_dev *dev); | |
112 | static struct pci_driver pci_driver = { | |
113 | .name = "synclink_gt", | |
114 | .id_table = pci_table, | |
115 | .probe = init_one, | |
116 | .remove = __devexit_p(remove_one), | |
117 | }; | |
118 | ||
119 | static int pci_registered; | |
120 | ||
121 | /* | |
122 | * module configuration and status | |
123 | */ | |
124 | static struct slgt_info *slgt_device_list; | |
125 | static int slgt_device_count; | |
126 | ||
127 | static int ttymajor; | |
128 | static int debug_level; | |
129 | static int maxframe[MAX_DEVICES]; | |
130 | static int dosyncppp[MAX_DEVICES]; | |
131 | ||
132 | module_param(ttymajor, int, 0); | |
133 | module_param(debug_level, int, 0); | |
134 | module_param_array(maxframe, int, NULL, 0); | |
135 | module_param_array(dosyncppp, int, NULL, 0); | |
136 | ||
137 | MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); | |
138 | MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); | |
139 | MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); | |
140 | MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable"); | |
141 | ||
142 | /* | |
143 | * tty support and callbacks | |
144 | */ | |
145 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) | |
146 | ||
147 | static struct tty_driver *serial_driver; | |
148 | ||
149 | static int open(struct tty_struct *tty, struct file * filp); | |
150 | static void close(struct tty_struct *tty, struct file * filp); | |
151 | static void hangup(struct tty_struct *tty); | |
152 | static void set_termios(struct tty_struct *tty, struct termios *old_termios); | |
153 | ||
154 | static int write(struct tty_struct *tty, const unsigned char *buf, int count); | |
155 | static void put_char(struct tty_struct *tty, unsigned char ch); | |
156 | static void send_xchar(struct tty_struct *tty, char ch); | |
157 | static void wait_until_sent(struct tty_struct *tty, int timeout); | |
158 | static int write_room(struct tty_struct *tty); | |
159 | static void flush_chars(struct tty_struct *tty); | |
160 | static void flush_buffer(struct tty_struct *tty); | |
161 | static void tx_hold(struct tty_struct *tty); | |
162 | static void tx_release(struct tty_struct *tty); | |
163 | ||
164 | static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg); | |
165 | static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data); | |
166 | static int chars_in_buffer(struct tty_struct *tty); | |
167 | static void throttle(struct tty_struct * tty); | |
168 | static void unthrottle(struct tty_struct * tty); | |
169 | static void set_break(struct tty_struct *tty, int break_state); | |
170 | ||
171 | /* | |
172 | * generic HDLC support and callbacks | |
173 | */ | |
174 | #ifdef CONFIG_HDLC | |
175 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) | |
176 | static void hdlcdev_tx_done(struct slgt_info *info); | |
177 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); | |
178 | static int hdlcdev_init(struct slgt_info *info); | |
179 | static void hdlcdev_exit(struct slgt_info *info); | |
180 | #endif | |
181 | ||
182 | ||
183 | /* | |
184 | * device specific structures, macros and functions | |
185 | */ | |
186 | ||
187 | #define SLGT_MAX_PORTS 4 | |
188 | #define SLGT_REG_SIZE 256 | |
189 | ||
190 | /* | |
191 | * DMA buffer descriptor and access macros | |
192 | */ | |
193 | struct slgt_desc | |
194 | { | |
195 | unsigned short count; | |
196 | unsigned short status; | |
197 | unsigned int pbuf; /* physical address of data buffer */ | |
198 | unsigned int next; /* physical address of next descriptor */ | |
199 | ||
200 | /* driver book keeping */ | |
201 | char *buf; /* virtual address of data buffer */ | |
202 | unsigned int pdesc; /* physical address of this descriptor */ | |
203 | dma_addr_t buf_dma_addr; | |
204 | }; | |
205 | ||
206 | #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) | |
207 | #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) | |
208 | #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) | |
209 | #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) | |
210 | #define desc_count(a) (le16_to_cpu((a).count)) | |
211 | #define desc_status(a) (le16_to_cpu((a).status)) | |
212 | #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) | |
213 | #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) | |
214 | #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) | |
215 | #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) | |
216 | #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) | |
217 | ||
218 | struct _input_signal_events { | |
219 | int ri_up; | |
220 | int ri_down; | |
221 | int dsr_up; | |
222 | int dsr_down; | |
223 | int dcd_up; | |
224 | int dcd_down; | |
225 | int cts_up; | |
226 | int cts_down; | |
227 | }; | |
228 | ||
229 | /* | |
230 | * device instance data structure | |
231 | */ | |
232 | struct slgt_info { | |
233 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | |
234 | ||
235 | struct slgt_info *next_device; /* device list link */ | |
236 | ||
237 | int magic; | |
238 | int flags; | |
239 | ||
240 | char device_name[25]; | |
241 | struct pci_dev *pdev; | |
242 | ||
243 | int port_count; /* count of ports on adapter */ | |
244 | int adapter_num; /* adapter instance number */ | |
245 | int port_num; /* port instance number */ | |
246 | ||
247 | /* array of pointers to port contexts on this adapter */ | |
248 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
249 | ||
250 | int count; /* count of opens */ | |
251 | int line; /* tty line instance number */ | |
252 | unsigned short close_delay; | |
253 | unsigned short closing_wait; /* time to wait before closing */ | |
254 | ||
255 | struct mgsl_icount icount; | |
256 | ||
257 | struct tty_struct *tty; | |
258 | int timeout; | |
259 | int x_char; /* xon/xoff character */ | |
260 | int blocked_open; /* # of blocked opens */ | |
261 | unsigned int read_status_mask; | |
262 | unsigned int ignore_status_mask; | |
263 | ||
264 | wait_queue_head_t open_wait; | |
265 | wait_queue_head_t close_wait; | |
266 | ||
267 | wait_queue_head_t status_event_wait_q; | |
268 | wait_queue_head_t event_wait_q; | |
269 | struct timer_list tx_timer; | |
270 | struct timer_list rx_timer; | |
271 | ||
272 | spinlock_t lock; /* spinlock for synchronizing with ISR */ | |
273 | ||
274 | struct work_struct task; | |
275 | u32 pending_bh; | |
276 | int bh_requested; | |
277 | int bh_running; | |
278 | ||
279 | int isr_overflow; | |
280 | int irq_requested; /* nonzero if IRQ requested */ | |
281 | int irq_occurred; /* for diagnostics use */ | |
282 | ||
283 | /* device configuration */ | |
284 | ||
285 | unsigned int bus_type; | |
286 | unsigned int irq_level; | |
287 | unsigned long irq_flags; | |
288 | ||
289 | unsigned char __iomem * reg_addr; /* memory mapped registers address */ | |
290 | u32 phys_reg_addr; | |
705b6c7b PF |
291 | int reg_addr_requested; |
292 | ||
293 | MGSL_PARAMS params; /* communications parameters */ | |
294 | u32 idle_mode; | |
295 | u32 max_frame_size; /* as set by device config */ | |
296 | ||
297 | unsigned int raw_rx_size; | |
298 | unsigned int if_mode; | |
299 | ||
300 | /* device status */ | |
301 | ||
302 | int rx_enabled; | |
303 | int rx_restart; | |
304 | ||
305 | int tx_enabled; | |
306 | int tx_active; | |
307 | ||
308 | unsigned char signals; /* serial signal states */ | |
309 | unsigned int init_error; /* initialization error */ | |
310 | ||
311 | unsigned char *tx_buf; | |
312 | int tx_count; | |
313 | ||
314 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; | |
315 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; | |
316 | BOOLEAN drop_rts_on_tx_done; | |
317 | struct _input_signal_events input_signal_events; | |
318 | ||
319 | int dcd_chkcount; /* check counts to prevent */ | |
320 | int cts_chkcount; /* too many IRQs if a signal */ | |
321 | int dsr_chkcount; /* is floating */ | |
322 | int ri_chkcount; | |
323 | ||
324 | char *bufs; /* virtual address of DMA buffer lists */ | |
325 | dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ | |
326 | ||
327 | unsigned int rbuf_count; | |
328 | struct slgt_desc *rbufs; | |
329 | unsigned int rbuf_current; | |
330 | unsigned int rbuf_index; | |
331 | ||
332 | unsigned int tbuf_count; | |
333 | struct slgt_desc *tbufs; | |
334 | unsigned int tbuf_current; | |
335 | unsigned int tbuf_start; | |
336 | ||
337 | unsigned char *tmp_rbuf; | |
338 | unsigned int tmp_rbuf_count; | |
339 | ||
340 | /* SPPP/Cisco HDLC device parts */ | |
341 | ||
342 | int netcount; | |
343 | int dosyncppp; | |
344 | spinlock_t netlock; | |
345 | #ifdef CONFIG_HDLC | |
346 | struct net_device *netdev; | |
347 | #endif | |
348 | ||
349 | }; | |
350 | ||
351 | static MGSL_PARAMS default_params = { | |
352 | .mode = MGSL_MODE_HDLC, | |
353 | .loopback = 0, | |
354 | .flags = HDLC_FLAG_UNDERRUN_ABORT15, | |
355 | .encoding = HDLC_ENCODING_NRZI_SPACE, | |
356 | .clock_speed = 0, | |
357 | .addr_filter = 0xff, | |
358 | .crc_type = HDLC_CRC_16_CCITT, | |
359 | .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, | |
360 | .preamble = HDLC_PREAMBLE_PATTERN_NONE, | |
361 | .data_rate = 9600, | |
362 | .data_bits = 8, | |
363 | .stop_bits = 1, | |
364 | .parity = ASYNC_PARITY_NONE | |
365 | }; | |
366 | ||
367 | ||
368 | #define BH_RECEIVE 1 | |
369 | #define BH_TRANSMIT 2 | |
370 | #define BH_STATUS 4 | |
371 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
372 | ||
373 | #define DMABUFSIZE 256 | |
374 | #define DESC_LIST_SIZE 4096 | |
375 | ||
376 | #define MASK_PARITY BIT1 | |
377 | #define MASK_FRAMING BIT2 | |
378 | #define MASK_BREAK BIT3 | |
379 | #define MASK_OVERRUN BIT4 | |
380 | ||
381 | #define GSR 0x00 /* global status */ | |
382 | #define TDR 0x80 /* tx data */ | |
383 | #define RDR 0x80 /* rx data */ | |
384 | #define TCR 0x82 /* tx control */ | |
385 | #define TIR 0x84 /* tx idle */ | |
386 | #define TPR 0x85 /* tx preamble */ | |
387 | #define RCR 0x86 /* rx control */ | |
388 | #define VCR 0x88 /* V.24 control */ | |
389 | #define CCR 0x89 /* clock control */ | |
390 | #define BDR 0x8a /* baud divisor */ | |
391 | #define SCR 0x8c /* serial control */ | |
392 | #define SSR 0x8e /* serial status */ | |
393 | #define RDCSR 0x90 /* rx DMA control/status */ | |
394 | #define TDCSR 0x94 /* tx DMA control/status */ | |
395 | #define RDDAR 0x98 /* rx DMA descriptor address */ | |
396 | #define TDDAR 0x9c /* tx DMA descriptor address */ | |
397 | ||
398 | #define RXIDLE BIT14 | |
399 | #define RXBREAK BIT14 | |
400 | #define IRQ_TXDATA BIT13 | |
401 | #define IRQ_TXIDLE BIT12 | |
402 | #define IRQ_TXUNDER BIT11 /* HDLC */ | |
403 | #define IRQ_RXDATA BIT10 | |
404 | #define IRQ_RXIDLE BIT9 /* HDLC */ | |
405 | #define IRQ_RXBREAK BIT9 /* async */ | |
406 | #define IRQ_RXOVER BIT8 | |
407 | #define IRQ_DSR BIT7 | |
408 | #define IRQ_CTS BIT6 | |
409 | #define IRQ_DCD BIT5 | |
410 | #define IRQ_RI BIT4 | |
411 | #define IRQ_ALL 0x3ff0 | |
412 | #define IRQ_MASTER BIT0 | |
413 | ||
414 | #define slgt_irq_on(info, mask) \ | |
415 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) | |
416 | #define slgt_irq_off(info, mask) \ | |
417 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) | |
418 | ||
419 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); | |
420 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); | |
421 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); | |
422 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); | |
423 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); | |
424 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); | |
425 | ||
426 | static void msc_set_vcr(struct slgt_info *info); | |
427 | ||
428 | static int startup(struct slgt_info *info); | |
429 | static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); | |
430 | static void shutdown(struct slgt_info *info); | |
431 | static void program_hw(struct slgt_info *info); | |
432 | static void change_params(struct slgt_info *info); | |
433 | ||
434 | static int register_test(struct slgt_info *info); | |
435 | static int irq_test(struct slgt_info *info); | |
436 | static int loopback_test(struct slgt_info *info); | |
437 | static int adapter_test(struct slgt_info *info); | |
438 | ||
439 | static void reset_adapter(struct slgt_info *info); | |
440 | static void reset_port(struct slgt_info *info); | |
441 | static void async_mode(struct slgt_info *info); | |
442 | static void hdlc_mode(struct slgt_info *info); | |
443 | ||
444 | static void rx_stop(struct slgt_info *info); | |
445 | static void rx_start(struct slgt_info *info); | |
446 | static void reset_rbufs(struct slgt_info *info); | |
447 | static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); | |
448 | static void rdma_reset(struct slgt_info *info); | |
449 | static int rx_get_frame(struct slgt_info *info); | |
450 | static int rx_get_buf(struct slgt_info *info); | |
451 | ||
452 | static void tx_start(struct slgt_info *info); | |
453 | static void tx_stop(struct slgt_info *info); | |
454 | static void tx_set_idle(struct slgt_info *info); | |
455 | static unsigned int free_tbuf_count(struct slgt_info *info); | |
456 | static void reset_tbufs(struct slgt_info *info); | |
457 | static void tdma_reset(struct slgt_info *info); | |
458 | static void tx_load(struct slgt_info *info, const char *buf, unsigned int count); | |
459 | ||
460 | static void get_signals(struct slgt_info *info); | |
461 | static void set_signals(struct slgt_info *info); | |
462 | static void enable_loopback(struct slgt_info *info); | |
463 | static void set_rate(struct slgt_info *info, u32 data_rate); | |
464 | ||
465 | static int bh_action(struct slgt_info *info); | |
466 | static void bh_handler(void* context); | |
467 | static void bh_transmit(struct slgt_info *info); | |
468 | static void isr_serial(struct slgt_info *info); | |
469 | static void isr_rdma(struct slgt_info *info); | |
470 | static void isr_txeom(struct slgt_info *info, unsigned short status); | |
471 | static void isr_tdma(struct slgt_info *info); | |
472 | static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs); | |
473 | ||
474 | static int alloc_dma_bufs(struct slgt_info *info); | |
475 | static void free_dma_bufs(struct slgt_info *info); | |
476 | static int alloc_desc(struct slgt_info *info); | |
477 | static void free_desc(struct slgt_info *info); | |
478 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
479 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
480 | ||
481 | static int alloc_tmp_rbuf(struct slgt_info *info); | |
482 | static void free_tmp_rbuf(struct slgt_info *info); | |
483 | ||
484 | static void tx_timeout(unsigned long context); | |
485 | static void rx_timeout(unsigned long context); | |
486 | ||
487 | /* | |
488 | * ioctl handlers | |
489 | */ | |
490 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); | |
491 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
492 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
493 | static int get_txidle(struct slgt_info *info, int __user *idle_mode); | |
494 | static int set_txidle(struct slgt_info *info, int idle_mode); | |
495 | static int tx_enable(struct slgt_info *info, int enable); | |
496 | static int tx_abort(struct slgt_info *info); | |
497 | static int rx_enable(struct slgt_info *info, int enable); | |
498 | static int modem_input_wait(struct slgt_info *info,int arg); | |
499 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); | |
500 | static int tiocmget(struct tty_struct *tty, struct file *file); | |
501 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
502 | unsigned int set, unsigned int clear); | |
503 | static void set_break(struct tty_struct *tty, int break_state); | |
504 | static int get_interface(struct slgt_info *info, int __user *if_mode); | |
505 | static int set_interface(struct slgt_info *info, int if_mode); | |
506 | ||
507 | /* | |
508 | * driver functions | |
509 | */ | |
510 | static void add_device(struct slgt_info *info); | |
511 | static void device_init(int adapter_num, struct pci_dev *pdev); | |
512 | static int claim_resources(struct slgt_info *info); | |
513 | static void release_resources(struct slgt_info *info); | |
514 | ||
515 | /* | |
516 | * DEBUG OUTPUT CODE | |
517 | */ | |
518 | #ifndef DBGINFO | |
519 | #define DBGINFO(fmt) | |
520 | #endif | |
521 | #ifndef DBGERR | |
522 | #define DBGERR(fmt) | |
523 | #endif | |
524 | #ifndef DBGBH | |
525 | #define DBGBH(fmt) | |
526 | #endif | |
527 | #ifndef DBGISR | |
528 | #define DBGISR(fmt) | |
529 | #endif | |
530 | ||
531 | #ifdef DBGDATA | |
532 | static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) | |
533 | { | |
534 | int i; | |
535 | int linecount; | |
536 | printk("%s %s data:\n",info->device_name, label); | |
537 | while(count) { | |
538 | linecount = (count > 16) ? 16 : count; | |
539 | for(i=0; i < linecount; i++) | |
540 | printk("%02X ",(unsigned char)data[i]); | |
541 | for(;i<17;i++) | |
542 | printk(" "); | |
543 | for(i=0;i<linecount;i++) { | |
544 | if (data[i]>=040 && data[i]<=0176) | |
545 | printk("%c",data[i]); | |
546 | else | |
547 | printk("."); | |
548 | } | |
549 | printk("\n"); | |
550 | data += linecount; | |
551 | count -= linecount; | |
552 | } | |
553 | } | |
554 | #else | |
555 | #define DBGDATA(info, buf, size, label) | |
556 | #endif | |
557 | ||
558 | #ifdef DBGTBUF | |
559 | static void dump_tbufs(struct slgt_info *info) | |
560 | { | |
561 | int i; | |
562 | printk("tbuf_current=%d\n", info->tbuf_current); | |
563 | for (i=0 ; i < info->tbuf_count ; i++) { | |
564 | printk("%d: count=%04X status=%04X\n", | |
565 | i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); | |
566 | } | |
567 | } | |
568 | #else | |
569 | #define DBGTBUF(info) | |
570 | #endif | |
571 | ||
572 | #ifdef DBGRBUF | |
573 | static void dump_rbufs(struct slgt_info *info) | |
574 | { | |
575 | int i; | |
576 | printk("rbuf_current=%d\n", info->rbuf_current); | |
577 | for (i=0 ; i < info->rbuf_count ; i++) { | |
578 | printk("%d: count=%04X status=%04X\n", | |
579 | i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); | |
580 | } | |
581 | } | |
582 | #else | |
583 | #define DBGRBUF(info) | |
584 | #endif | |
585 | ||
586 | static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) | |
587 | { | |
588 | #ifdef SANITY_CHECK | |
589 | if (!info) { | |
590 | printk("null struct slgt_info for (%s) in %s\n", devname, name); | |
591 | return 1; | |
592 | } | |
593 | if (info->magic != MGSL_MAGIC) { | |
594 | printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); | |
595 | return 1; | |
596 | } | |
597 | #else | |
598 | if (!info) | |
599 | return 1; | |
600 | #endif | |
601 | return 0; | |
602 | } | |
603 | ||
604 | /** | |
605 | * line discipline callback wrappers | |
606 | * | |
607 | * The wrappers maintain line discipline references | |
608 | * while calling into the line discipline. | |
609 | * | |
610 | * ldisc_receive_buf - pass receive data to line discipline | |
611 | */ | |
612 | static void ldisc_receive_buf(struct tty_struct *tty, | |
613 | const __u8 *data, char *flags, int count) | |
614 | { | |
615 | struct tty_ldisc *ld; | |
616 | if (!tty) | |
617 | return; | |
618 | ld = tty_ldisc_ref(tty); | |
619 | if (ld) { | |
620 | if (ld->receive_buf) | |
621 | ld->receive_buf(tty, data, flags, count); | |
622 | tty_ldisc_deref(ld); | |
623 | } | |
624 | } | |
625 | ||
626 | /* tty callbacks */ | |
627 | ||
628 | static int open(struct tty_struct *tty, struct file *filp) | |
629 | { | |
630 | struct slgt_info *info; | |
631 | int retval, line; | |
632 | unsigned long flags; | |
633 | ||
634 | line = tty->index; | |
635 | if ((line < 0) || (line >= slgt_device_count)) { | |
636 | DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); | |
637 | return -ENODEV; | |
638 | } | |
639 | ||
640 | info = slgt_device_list; | |
641 | while(info && info->line != line) | |
642 | info = info->next_device; | |
643 | if (sanity_check(info, tty->name, "open")) | |
644 | return -ENODEV; | |
645 | if (info->init_error) { | |
646 | DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); | |
647 | return -ENODEV; | |
648 | } | |
649 | ||
650 | tty->driver_data = info; | |
651 | info->tty = tty; | |
652 | ||
653 | DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count)); | |
654 | ||
655 | /* If port is closing, signal caller to try again */ | |
656 | if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){ | |
657 | if (info->flags & ASYNC_CLOSING) | |
658 | interruptible_sleep_on(&info->close_wait); | |
659 | retval = ((info->flags & ASYNC_HUP_NOTIFY) ? | |
660 | -EAGAIN : -ERESTARTSYS); | |
661 | goto cleanup; | |
662 | } | |
663 | ||
664 | info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; | |
665 | ||
666 | spin_lock_irqsave(&info->netlock, flags); | |
667 | if (info->netcount) { | |
668 | retval = -EBUSY; | |
669 | spin_unlock_irqrestore(&info->netlock, flags); | |
670 | goto cleanup; | |
671 | } | |
672 | info->count++; | |
673 | spin_unlock_irqrestore(&info->netlock, flags); | |
674 | ||
675 | if (info->count == 1) { | |
676 | /* 1st open on this device, init hardware */ | |
677 | retval = startup(info); | |
678 | if (retval < 0) | |
679 | goto cleanup; | |
680 | } | |
681 | ||
682 | retval = block_til_ready(tty, filp, info); | |
683 | if (retval) { | |
684 | DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); | |
685 | goto cleanup; | |
686 | } | |
687 | ||
688 | retval = 0; | |
689 | ||
690 | cleanup: | |
691 | if (retval) { | |
692 | if (tty->count == 1) | |
693 | info->tty = NULL; /* tty layer will release tty struct */ | |
694 | if(info->count) | |
695 | info->count--; | |
696 | } | |
697 | ||
698 | DBGINFO(("%s open rc=%d\n", info->device_name, retval)); | |
699 | return retval; | |
700 | } | |
701 | ||
702 | static void close(struct tty_struct *tty, struct file *filp) | |
703 | { | |
704 | struct slgt_info *info = tty->driver_data; | |
705 | ||
706 | if (sanity_check(info, tty->name, "close")) | |
707 | return; | |
708 | DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count)); | |
709 | ||
710 | if (!info->count) | |
711 | return; | |
712 | ||
713 | if (tty_hung_up_p(filp)) | |
714 | goto cleanup; | |
715 | ||
716 | if ((tty->count == 1) && (info->count != 1)) { | |
717 | /* | |
718 | * tty->count is 1 and the tty structure will be freed. | |
719 | * info->count should be one in this case. | |
720 | * if it's not, correct it so that the port is shutdown. | |
721 | */ | |
722 | DBGERR(("%s close: bad refcount; tty->count=1, " | |
723 | "info->count=%d\n", info->device_name, info->count)); | |
724 | info->count = 1; | |
725 | } | |
726 | ||
727 | info->count--; | |
728 | ||
729 | /* if at least one open remaining, leave hardware active */ | |
730 | if (info->count) | |
731 | goto cleanup; | |
732 | ||
733 | info->flags |= ASYNC_CLOSING; | |
734 | ||
735 | /* set tty->closing to notify line discipline to | |
736 | * only process XON/XOFF characters. Only the N_TTY | |
737 | * discipline appears to use this (ppp does not). | |
738 | */ | |
739 | tty->closing = 1; | |
740 | ||
741 | /* wait for transmit data to clear all layers */ | |
742 | ||
743 | if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) { | |
744 | DBGINFO(("%s call tty_wait_until_sent\n", info->device_name)); | |
745 | tty_wait_until_sent(tty, info->closing_wait); | |
746 | } | |
747 | ||
748 | if (info->flags & ASYNC_INITIALIZED) | |
749 | wait_until_sent(tty, info->timeout); | |
750 | if (tty->driver->flush_buffer) | |
751 | tty->driver->flush_buffer(tty); | |
752 | tty_ldisc_flush(tty); | |
753 | ||
754 | shutdown(info); | |
755 | ||
756 | tty->closing = 0; | |
757 | info->tty = NULL; | |
758 | ||
759 | if (info->blocked_open) { | |
760 | if (info->close_delay) { | |
761 | msleep_interruptible(jiffies_to_msecs(info->close_delay)); | |
762 | } | |
763 | wake_up_interruptible(&info->open_wait); | |
764 | } | |
765 | ||
766 | info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); | |
767 | ||
768 | wake_up_interruptible(&info->close_wait); | |
769 | ||
770 | cleanup: | |
771 | DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count)); | |
772 | } | |
773 | ||
774 | static void hangup(struct tty_struct *tty) | |
775 | { | |
776 | struct slgt_info *info = tty->driver_data; | |
777 | ||
778 | if (sanity_check(info, tty->name, "hangup")) | |
779 | return; | |
780 | DBGINFO(("%s hangup\n", info->device_name)); | |
781 | ||
782 | flush_buffer(tty); | |
783 | shutdown(info); | |
784 | ||
785 | info->count = 0; | |
786 | info->flags &= ~ASYNC_NORMAL_ACTIVE; | |
787 | info->tty = NULL; | |
788 | ||
789 | wake_up_interruptible(&info->open_wait); | |
790 | } | |
791 | ||
792 | static void set_termios(struct tty_struct *tty, struct termios *old_termios) | |
793 | { | |
794 | struct slgt_info *info = tty->driver_data; | |
795 | unsigned long flags; | |
796 | ||
797 | DBGINFO(("%s set_termios\n", tty->driver->name)); | |
798 | ||
799 | /* just return if nothing has changed */ | |
800 | if ((tty->termios->c_cflag == old_termios->c_cflag) | |
801 | && (RELEVANT_IFLAG(tty->termios->c_iflag) | |
802 | == RELEVANT_IFLAG(old_termios->c_iflag))) | |
803 | return; | |
804 | ||
805 | change_params(info); | |
806 | ||
807 | /* Handle transition to B0 status */ | |
808 | if (old_termios->c_cflag & CBAUD && | |
809 | !(tty->termios->c_cflag & CBAUD)) { | |
810 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
811 | spin_lock_irqsave(&info->lock,flags); | |
812 | set_signals(info); | |
813 | spin_unlock_irqrestore(&info->lock,flags); | |
814 | } | |
815 | ||
816 | /* Handle transition away from B0 status */ | |
817 | if (!(old_termios->c_cflag & CBAUD) && | |
818 | tty->termios->c_cflag & CBAUD) { | |
819 | info->signals |= SerialSignal_DTR; | |
820 | if (!(tty->termios->c_cflag & CRTSCTS) || | |
821 | !test_bit(TTY_THROTTLED, &tty->flags)) { | |
822 | info->signals |= SerialSignal_RTS; | |
823 | } | |
824 | spin_lock_irqsave(&info->lock,flags); | |
825 | set_signals(info); | |
826 | spin_unlock_irqrestore(&info->lock,flags); | |
827 | } | |
828 | ||
829 | /* Handle turning off CRTSCTS */ | |
830 | if (old_termios->c_cflag & CRTSCTS && | |
831 | !(tty->termios->c_cflag & CRTSCTS)) { | |
832 | tty->hw_stopped = 0; | |
833 | tx_release(tty); | |
834 | } | |
835 | } | |
836 | ||
837 | static int write(struct tty_struct *tty, | |
838 | const unsigned char *buf, int count) | |
839 | { | |
840 | int ret = 0; | |
841 | struct slgt_info *info = tty->driver_data; | |
842 | unsigned long flags; | |
843 | ||
844 | if (sanity_check(info, tty->name, "write")) | |
845 | goto cleanup; | |
846 | DBGINFO(("%s write count=%d\n", info->device_name, count)); | |
847 | ||
848 | if (!tty || !info->tx_buf) | |
849 | goto cleanup; | |
850 | ||
851 | if (count > info->max_frame_size) { | |
852 | ret = -EIO; | |
853 | goto cleanup; | |
854 | } | |
855 | ||
856 | if (!count) | |
857 | goto cleanup; | |
858 | ||
859 | if (info->params.mode == MGSL_MODE_RAW) { | |
860 | unsigned int bufs_needed = (count/DMABUFSIZE); | |
861 | unsigned int bufs_free = free_tbuf_count(info); | |
862 | if (count % DMABUFSIZE) | |
863 | ++bufs_needed; | |
864 | if (bufs_needed > bufs_free) | |
865 | goto cleanup; | |
866 | } else { | |
867 | if (info->tx_active) | |
868 | goto cleanup; | |
869 | if (info->tx_count) { | |
870 | /* send accumulated data from send_char() calls */ | |
871 | /* as frame and wait before accepting more data. */ | |
872 | tx_load(info, info->tx_buf, info->tx_count); | |
873 | goto start; | |
874 | } | |
875 | } | |
876 | ||
877 | ret = info->tx_count = count; | |
878 | tx_load(info, buf, count); | |
879 | goto start; | |
880 | ||
881 | start: | |
882 | if (info->tx_count && !tty->stopped && !tty->hw_stopped) { | |
883 | spin_lock_irqsave(&info->lock,flags); | |
884 | if (!info->tx_active) | |
885 | tx_start(info); | |
886 | spin_unlock_irqrestore(&info->lock,flags); | |
887 | } | |
888 | ||
889 | cleanup: | |
890 | DBGINFO(("%s write rc=%d\n", info->device_name, ret)); | |
891 | return ret; | |
892 | } | |
893 | ||
894 | static void put_char(struct tty_struct *tty, unsigned char ch) | |
895 | { | |
896 | struct slgt_info *info = tty->driver_data; | |
897 | unsigned long flags; | |
898 | ||
899 | if (sanity_check(info, tty->name, "put_char")) | |
900 | return; | |
901 | DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); | |
902 | if (!tty || !info->tx_buf) | |
903 | return; | |
904 | spin_lock_irqsave(&info->lock,flags); | |
905 | if (!info->tx_active && (info->tx_count < info->max_frame_size)) | |
906 | info->tx_buf[info->tx_count++] = ch; | |
907 | spin_unlock_irqrestore(&info->lock,flags); | |
908 | } | |
909 | ||
910 | static void send_xchar(struct tty_struct *tty, char ch) | |
911 | { | |
912 | struct slgt_info *info = tty->driver_data; | |
913 | unsigned long flags; | |
914 | ||
915 | if (sanity_check(info, tty->name, "send_xchar")) | |
916 | return; | |
917 | DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); | |
918 | info->x_char = ch; | |
919 | if (ch) { | |
920 | spin_lock_irqsave(&info->lock,flags); | |
921 | if (!info->tx_enabled) | |
922 | tx_start(info); | |
923 | spin_unlock_irqrestore(&info->lock,flags); | |
924 | } | |
925 | } | |
926 | ||
927 | static void wait_until_sent(struct tty_struct *tty, int timeout) | |
928 | { | |
929 | struct slgt_info *info = tty->driver_data; | |
930 | unsigned long orig_jiffies, char_time; | |
931 | ||
932 | if (!info ) | |
933 | return; | |
934 | if (sanity_check(info, tty->name, "wait_until_sent")) | |
935 | return; | |
936 | DBGINFO(("%s wait_until_sent entry\n", info->device_name)); | |
937 | if (!(info->flags & ASYNC_INITIALIZED)) | |
938 | goto exit; | |
939 | ||
940 | orig_jiffies = jiffies; | |
941 | ||
942 | /* Set check interval to 1/5 of estimated time to | |
943 | * send a character, and make it at least 1. The check | |
944 | * interval should also be less than the timeout. | |
945 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
946 | */ | |
947 | ||
948 | if (info->params.data_rate) { | |
949 | char_time = info->timeout/(32 * 5); | |
950 | if (!char_time) | |
951 | char_time++; | |
952 | } else | |
953 | char_time = 1; | |
954 | ||
955 | if (timeout) | |
956 | char_time = min_t(unsigned long, char_time, timeout); | |
957 | ||
958 | while (info->tx_active) { | |
959 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
960 | if (signal_pending(current)) | |
961 | break; | |
962 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
963 | break; | |
964 | } | |
965 | ||
966 | exit: | |
967 | DBGINFO(("%s wait_until_sent exit\n", info->device_name)); | |
968 | } | |
969 | ||
970 | static int write_room(struct tty_struct *tty) | |
971 | { | |
972 | struct slgt_info *info = tty->driver_data; | |
973 | int ret; | |
974 | ||
975 | if (sanity_check(info, tty->name, "write_room")) | |
976 | return 0; | |
977 | ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; | |
978 | DBGINFO(("%s write_room=%d\n", info->device_name, ret)); | |
979 | return ret; | |
980 | } | |
981 | ||
982 | static void flush_chars(struct tty_struct *tty) | |
983 | { | |
984 | struct slgt_info *info = tty->driver_data; | |
985 | unsigned long flags; | |
986 | ||
987 | if (sanity_check(info, tty->name, "flush_chars")) | |
988 | return; | |
989 | DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); | |
990 | ||
991 | if (info->tx_count <= 0 || tty->stopped || | |
992 | tty->hw_stopped || !info->tx_buf) | |
993 | return; | |
994 | ||
995 | DBGINFO(("%s flush_chars start transmit\n", info->device_name)); | |
996 | ||
997 | spin_lock_irqsave(&info->lock,flags); | |
998 | if (!info->tx_active && info->tx_count) { | |
999 | tx_load(info, info->tx_buf,info->tx_count); | |
1000 | tx_start(info); | |
1001 | } | |
1002 | spin_unlock_irqrestore(&info->lock,flags); | |
1003 | } | |
1004 | ||
1005 | static void flush_buffer(struct tty_struct *tty) | |
1006 | { | |
1007 | struct slgt_info *info = tty->driver_data; | |
1008 | unsigned long flags; | |
1009 | ||
1010 | if (sanity_check(info, tty->name, "flush_buffer")) | |
1011 | return; | |
1012 | DBGINFO(("%s flush_buffer\n", info->device_name)); | |
1013 | ||
1014 | spin_lock_irqsave(&info->lock,flags); | |
1015 | if (!info->tx_active) | |
1016 | info->tx_count = 0; | |
1017 | spin_unlock_irqrestore(&info->lock,flags); | |
1018 | ||
1019 | wake_up_interruptible(&tty->write_wait); | |
1020 | tty_wakeup(tty); | |
1021 | } | |
1022 | ||
1023 | /* | |
1024 | * throttle (stop) transmitter | |
1025 | */ | |
1026 | static void tx_hold(struct tty_struct *tty) | |
1027 | { | |
1028 | struct slgt_info *info = tty->driver_data; | |
1029 | unsigned long flags; | |
1030 | ||
1031 | if (sanity_check(info, tty->name, "tx_hold")) | |
1032 | return; | |
1033 | DBGINFO(("%s tx_hold\n", info->device_name)); | |
1034 | spin_lock_irqsave(&info->lock,flags); | |
1035 | if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) | |
1036 | tx_stop(info); | |
1037 | spin_unlock_irqrestore(&info->lock,flags); | |
1038 | } | |
1039 | ||
1040 | /* | |
1041 | * release (start) transmitter | |
1042 | */ | |
1043 | static void tx_release(struct tty_struct *tty) | |
1044 | { | |
1045 | struct slgt_info *info = tty->driver_data; | |
1046 | unsigned long flags; | |
1047 | ||
1048 | if (sanity_check(info, tty->name, "tx_release")) | |
1049 | return; | |
1050 | DBGINFO(("%s tx_release\n", info->device_name)); | |
1051 | spin_lock_irqsave(&info->lock,flags); | |
1052 | if (!info->tx_active && info->tx_count) { | |
1053 | tx_load(info, info->tx_buf, info->tx_count); | |
1054 | tx_start(info); | |
1055 | } | |
1056 | spin_unlock_irqrestore(&info->lock,flags); | |
1057 | } | |
1058 | ||
1059 | /* | |
1060 | * Service an IOCTL request | |
1061 | * | |
1062 | * Arguments | |
1063 | * | |
1064 | * tty pointer to tty instance data | |
1065 | * file pointer to associated file object for device | |
1066 | * cmd IOCTL command code | |
1067 | * arg command argument/context | |
1068 | * | |
1069 | * Return 0 if success, otherwise error code | |
1070 | */ | |
1071 | static int ioctl(struct tty_struct *tty, struct file *file, | |
1072 | unsigned int cmd, unsigned long arg) | |
1073 | { | |
1074 | struct slgt_info *info = tty->driver_data; | |
1075 | struct mgsl_icount cnow; /* kernel counter temps */ | |
1076 | struct serial_icounter_struct __user *p_cuser; /* user space */ | |
1077 | unsigned long flags; | |
1078 | void __user *argp = (void __user *)arg; | |
1079 | ||
1080 | if (sanity_check(info, tty->name, "ioctl")) | |
1081 | return -ENODEV; | |
1082 | DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1083 | ||
1084 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
1085 | (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { | |
1086 | if (tty->flags & (1 << TTY_IO_ERROR)) | |
1087 | return -EIO; | |
1088 | } | |
1089 | ||
1090 | switch (cmd) { | |
1091 | case MGSL_IOCGPARAMS: | |
1092 | return get_params(info, argp); | |
1093 | case MGSL_IOCSPARAMS: | |
1094 | return set_params(info, argp); | |
1095 | case MGSL_IOCGTXIDLE: | |
1096 | return get_txidle(info, argp); | |
1097 | case MGSL_IOCSTXIDLE: | |
1098 | return set_txidle(info, (int)arg); | |
1099 | case MGSL_IOCTXENABLE: | |
1100 | return tx_enable(info, (int)arg); | |
1101 | case MGSL_IOCRXENABLE: | |
1102 | return rx_enable(info, (int)arg); | |
1103 | case MGSL_IOCTXABORT: | |
1104 | return tx_abort(info); | |
1105 | case MGSL_IOCGSTATS: | |
1106 | return get_stats(info, argp); | |
1107 | case MGSL_IOCWAITEVENT: | |
1108 | return wait_mgsl_event(info, argp); | |
1109 | case TIOCMIWAIT: | |
1110 | return modem_input_wait(info,(int)arg); | |
1111 | case MGSL_IOCGIF: | |
1112 | return get_interface(info, argp); | |
1113 | case MGSL_IOCSIF: | |
1114 | return set_interface(info,(int)arg); | |
1115 | case TIOCGICOUNT: | |
1116 | spin_lock_irqsave(&info->lock,flags); | |
1117 | cnow = info->icount; | |
1118 | spin_unlock_irqrestore(&info->lock,flags); | |
1119 | p_cuser = argp; | |
1120 | if (put_user(cnow.cts, &p_cuser->cts) || | |
1121 | put_user(cnow.dsr, &p_cuser->dsr) || | |
1122 | put_user(cnow.rng, &p_cuser->rng) || | |
1123 | put_user(cnow.dcd, &p_cuser->dcd) || | |
1124 | put_user(cnow.rx, &p_cuser->rx) || | |
1125 | put_user(cnow.tx, &p_cuser->tx) || | |
1126 | put_user(cnow.frame, &p_cuser->frame) || | |
1127 | put_user(cnow.overrun, &p_cuser->overrun) || | |
1128 | put_user(cnow.parity, &p_cuser->parity) || | |
1129 | put_user(cnow.brk, &p_cuser->brk) || | |
1130 | put_user(cnow.buf_overrun, &p_cuser->buf_overrun)) | |
1131 | return -EFAULT; | |
1132 | return 0; | |
1133 | default: | |
1134 | return -ENOIOCTLCMD; | |
1135 | } | |
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | /* | |
1140 | * proc fs support | |
1141 | */ | |
1142 | static inline int line_info(char *buf, struct slgt_info *info) | |
1143 | { | |
1144 | char stat_buf[30]; | |
1145 | int ret; | |
1146 | unsigned long flags; | |
1147 | ||
1148 | ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", | |
1149 | info->device_name, info->phys_reg_addr, | |
1150 | info->irq_level, info->max_frame_size); | |
1151 | ||
1152 | /* output current serial signal states */ | |
1153 | spin_lock_irqsave(&info->lock,flags); | |
1154 | get_signals(info); | |
1155 | spin_unlock_irqrestore(&info->lock,flags); | |
1156 | ||
1157 | stat_buf[0] = 0; | |
1158 | stat_buf[1] = 0; | |
1159 | if (info->signals & SerialSignal_RTS) | |
1160 | strcat(stat_buf, "|RTS"); | |
1161 | if (info->signals & SerialSignal_CTS) | |
1162 | strcat(stat_buf, "|CTS"); | |
1163 | if (info->signals & SerialSignal_DTR) | |
1164 | strcat(stat_buf, "|DTR"); | |
1165 | if (info->signals & SerialSignal_DSR) | |
1166 | strcat(stat_buf, "|DSR"); | |
1167 | if (info->signals & SerialSignal_DCD) | |
1168 | strcat(stat_buf, "|CD"); | |
1169 | if (info->signals & SerialSignal_RI) | |
1170 | strcat(stat_buf, "|RI"); | |
1171 | ||
1172 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
1173 | ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d", | |
1174 | info->icount.txok, info->icount.rxok); | |
1175 | if (info->icount.txunder) | |
1176 | ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder); | |
1177 | if (info->icount.txabort) | |
1178 | ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort); | |
1179 | if (info->icount.rxshort) | |
1180 | ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort); | |
1181 | if (info->icount.rxlong) | |
1182 | ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong); | |
1183 | if (info->icount.rxover) | |
1184 | ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover); | |
1185 | if (info->icount.rxcrc) | |
1186 | ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc); | |
1187 | } else { | |
1188 | ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d", | |
1189 | info->icount.tx, info->icount.rx); | |
1190 | if (info->icount.frame) | |
1191 | ret += sprintf(buf+ret, " fe:%d", info->icount.frame); | |
1192 | if (info->icount.parity) | |
1193 | ret += sprintf(buf+ret, " pe:%d", info->icount.parity); | |
1194 | if (info->icount.brk) | |
1195 | ret += sprintf(buf+ret, " brk:%d", info->icount.brk); | |
1196 | if (info->icount.overrun) | |
1197 | ret += sprintf(buf+ret, " oe:%d", info->icount.overrun); | |
1198 | } | |
1199 | ||
1200 | /* Append serial signal status to end */ | |
1201 | ret += sprintf(buf+ret, " %s\n", stat_buf+1); | |
1202 | ||
1203 | ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", | |
1204 | info->tx_active,info->bh_requested,info->bh_running, | |
1205 | info->pending_bh); | |
1206 | ||
1207 | return ret; | |
1208 | } | |
1209 | ||
1210 | /* Called to print information about devices | |
1211 | */ | |
1212 | static int read_proc(char *page, char **start, off_t off, int count, | |
1213 | int *eof, void *data) | |
1214 | { | |
1215 | int len = 0, l; | |
1216 | off_t begin = 0; | |
1217 | struct slgt_info *info; | |
1218 | ||
1219 | len += sprintf(page, "synclink_gt driver:%s\n", driver_version); | |
1220 | ||
1221 | info = slgt_device_list; | |
1222 | while( info ) { | |
1223 | l = line_info(page + len, info); | |
1224 | len += l; | |
1225 | if (len+begin > off+count) | |
1226 | goto done; | |
1227 | if (len+begin < off) { | |
1228 | begin += len; | |
1229 | len = 0; | |
1230 | } | |
1231 | info = info->next_device; | |
1232 | } | |
1233 | ||
1234 | *eof = 1; | |
1235 | done: | |
1236 | if (off >= len+begin) | |
1237 | return 0; | |
1238 | *start = page + (off-begin); | |
1239 | return ((count < begin+len-off) ? count : begin+len-off); | |
1240 | } | |
1241 | ||
1242 | /* | |
1243 | * return count of bytes in transmit buffer | |
1244 | */ | |
1245 | static int chars_in_buffer(struct tty_struct *tty) | |
1246 | { | |
1247 | struct slgt_info *info = tty->driver_data; | |
1248 | if (sanity_check(info, tty->name, "chars_in_buffer")) | |
1249 | return 0; | |
1250 | DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count)); | |
1251 | return info->tx_count; | |
1252 | } | |
1253 | ||
1254 | /* | |
1255 | * signal remote device to throttle send data (our receive data) | |
1256 | */ | |
1257 | static void throttle(struct tty_struct * tty) | |
1258 | { | |
1259 | struct slgt_info *info = tty->driver_data; | |
1260 | unsigned long flags; | |
1261 | ||
1262 | if (sanity_check(info, tty->name, "throttle")) | |
1263 | return; | |
1264 | DBGINFO(("%s throttle\n", info->device_name)); | |
1265 | if (I_IXOFF(tty)) | |
1266 | send_xchar(tty, STOP_CHAR(tty)); | |
1267 | if (tty->termios->c_cflag & CRTSCTS) { | |
1268 | spin_lock_irqsave(&info->lock,flags); | |
1269 | info->signals &= ~SerialSignal_RTS; | |
1270 | set_signals(info); | |
1271 | spin_unlock_irqrestore(&info->lock,flags); | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | /* | |
1276 | * signal remote device to stop throttling send data (our receive data) | |
1277 | */ | |
1278 | static void unthrottle(struct tty_struct * tty) | |
1279 | { | |
1280 | struct slgt_info *info = tty->driver_data; | |
1281 | unsigned long flags; | |
1282 | ||
1283 | if (sanity_check(info, tty->name, "unthrottle")) | |
1284 | return; | |
1285 | DBGINFO(("%s unthrottle\n", info->device_name)); | |
1286 | if (I_IXOFF(tty)) { | |
1287 | if (info->x_char) | |
1288 | info->x_char = 0; | |
1289 | else | |
1290 | send_xchar(tty, START_CHAR(tty)); | |
1291 | } | |
1292 | if (tty->termios->c_cflag & CRTSCTS) { | |
1293 | spin_lock_irqsave(&info->lock,flags); | |
1294 | info->signals |= SerialSignal_RTS; | |
1295 | set_signals(info); | |
1296 | spin_unlock_irqrestore(&info->lock,flags); | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | /* | |
1301 | * set or clear transmit break condition | |
1302 | * break_state -1=set break condition, 0=clear | |
1303 | */ | |
1304 | static void set_break(struct tty_struct *tty, int break_state) | |
1305 | { | |
1306 | struct slgt_info *info = tty->driver_data; | |
1307 | unsigned short value; | |
1308 | unsigned long flags; | |
1309 | ||
1310 | if (sanity_check(info, tty->name, "set_break")) | |
1311 | return; | |
1312 | DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); | |
1313 | ||
1314 | spin_lock_irqsave(&info->lock,flags); | |
1315 | value = rd_reg16(info, TCR); | |
1316 | if (break_state == -1) | |
1317 | value |= BIT6; | |
1318 | else | |
1319 | value &= ~BIT6; | |
1320 | wr_reg16(info, TCR, value); | |
1321 | spin_unlock_irqrestore(&info->lock,flags); | |
1322 | } | |
1323 | ||
1324 | #ifdef CONFIG_HDLC | |
1325 | ||
1326 | /** | |
1327 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
1328 | * set encoding and frame check sequence (FCS) options | |
1329 | * | |
1330 | * dev pointer to network device structure | |
1331 | * encoding serial encoding setting | |
1332 | * parity FCS setting | |
1333 | * | |
1334 | * returns 0 if success, otherwise error code | |
1335 | */ | |
1336 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
1337 | unsigned short parity) | |
1338 | { | |
1339 | struct slgt_info *info = dev_to_port(dev); | |
1340 | unsigned char new_encoding; | |
1341 | unsigned short new_crctype; | |
1342 | ||
1343 | /* return error if TTY interface open */ | |
1344 | if (info->count) | |
1345 | return -EBUSY; | |
1346 | ||
1347 | DBGINFO(("%s hdlcdev_attach\n", info->device_name)); | |
1348 | ||
1349 | switch (encoding) | |
1350 | { | |
1351 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
1352 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
1353 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
1354 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
1355 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
1356 | default: return -EINVAL; | |
1357 | } | |
1358 | ||
1359 | switch (parity) | |
1360 | { | |
1361 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
1362 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
1363 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
1364 | default: return -EINVAL; | |
1365 | } | |
1366 | ||
1367 | info->params.encoding = new_encoding; | |
1368 | info->params.crc_type = new_crctype;; | |
1369 | ||
1370 | /* if network interface up, reprogram hardware */ | |
1371 | if (info->netcount) | |
1372 | program_hw(info); | |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | /** | |
1378 | * called by generic HDLC layer to send frame | |
1379 | * | |
1380 | * skb socket buffer containing HDLC frame | |
1381 | * dev pointer to network device structure | |
1382 | * | |
1383 | * returns 0 if success, otherwise error code | |
1384 | */ | |
1385 | static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev) | |
1386 | { | |
1387 | struct slgt_info *info = dev_to_port(dev); | |
1388 | struct net_device_stats *stats = hdlc_stats(dev); | |
1389 | unsigned long flags; | |
1390 | ||
1391 | DBGINFO(("%s hdlc_xmit\n", dev->name)); | |
1392 | ||
1393 | /* stop sending until this frame completes */ | |
1394 | netif_stop_queue(dev); | |
1395 | ||
1396 | /* copy data to device buffers */ | |
1397 | info->tx_count = skb->len; | |
1398 | tx_load(info, skb->data, skb->len); | |
1399 | ||
1400 | /* update network statistics */ | |
1401 | stats->tx_packets++; | |
1402 | stats->tx_bytes += skb->len; | |
1403 | ||
1404 | /* done with socket buffer, so free it */ | |
1405 | dev_kfree_skb(skb); | |
1406 | ||
1407 | /* save start time for transmit timeout detection */ | |
1408 | dev->trans_start = jiffies; | |
1409 | ||
1410 | /* start hardware transmitter if necessary */ | |
1411 | spin_lock_irqsave(&info->lock,flags); | |
1412 | if (!info->tx_active) | |
1413 | tx_start(info); | |
1414 | spin_unlock_irqrestore(&info->lock,flags); | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | /** | |
1420 | * called by network layer when interface enabled | |
1421 | * claim resources and initialize hardware | |
1422 | * | |
1423 | * dev pointer to network device structure | |
1424 | * | |
1425 | * returns 0 if success, otherwise error code | |
1426 | */ | |
1427 | static int hdlcdev_open(struct net_device *dev) | |
1428 | { | |
1429 | struct slgt_info *info = dev_to_port(dev); | |
1430 | int rc; | |
1431 | unsigned long flags; | |
1432 | ||
1433 | DBGINFO(("%s hdlcdev_open\n", dev->name)); | |
1434 | ||
1435 | /* generic HDLC layer open processing */ | |
1436 | if ((rc = hdlc_open(dev))) | |
1437 | return rc; | |
1438 | ||
1439 | /* arbitrate between network and tty opens */ | |
1440 | spin_lock_irqsave(&info->netlock, flags); | |
1441 | if (info->count != 0 || info->netcount != 0) { | |
1442 | DBGINFO(("%s hdlc_open busy\n", dev->name)); | |
1443 | spin_unlock_irqrestore(&info->netlock, flags); | |
1444 | return -EBUSY; | |
1445 | } | |
1446 | info->netcount=1; | |
1447 | spin_unlock_irqrestore(&info->netlock, flags); | |
1448 | ||
1449 | /* claim resources and init adapter */ | |
1450 | if ((rc = startup(info)) != 0) { | |
1451 | spin_lock_irqsave(&info->netlock, flags); | |
1452 | info->netcount=0; | |
1453 | spin_unlock_irqrestore(&info->netlock, flags); | |
1454 | return rc; | |
1455 | } | |
1456 | ||
1457 | /* assert DTR and RTS, apply hardware settings */ | |
1458 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
1459 | program_hw(info); | |
1460 | ||
1461 | /* enable network layer transmit */ | |
1462 | dev->trans_start = jiffies; | |
1463 | netif_start_queue(dev); | |
1464 | ||
1465 | /* inform generic HDLC layer of current DCD status */ | |
1466 | spin_lock_irqsave(&info->lock, flags); | |
1467 | get_signals(info); | |
1468 | spin_unlock_irqrestore(&info->lock, flags); | |
1469 | hdlc_set_carrier(info->signals & SerialSignal_DCD, dev); | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | /** | |
1475 | * called by network layer when interface is disabled | |
1476 | * shutdown hardware and release resources | |
1477 | * | |
1478 | * dev pointer to network device structure | |
1479 | * | |
1480 | * returns 0 if success, otherwise error code | |
1481 | */ | |
1482 | static int hdlcdev_close(struct net_device *dev) | |
1483 | { | |
1484 | struct slgt_info *info = dev_to_port(dev); | |
1485 | unsigned long flags; | |
1486 | ||
1487 | DBGINFO(("%s hdlcdev_close\n", dev->name)); | |
1488 | ||
1489 | netif_stop_queue(dev); | |
1490 | ||
1491 | /* shutdown adapter and release resources */ | |
1492 | shutdown(info); | |
1493 | ||
1494 | hdlc_close(dev); | |
1495 | ||
1496 | spin_lock_irqsave(&info->netlock, flags); | |
1497 | info->netcount=0; | |
1498 | spin_unlock_irqrestore(&info->netlock, flags); | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
1503 | /** | |
1504 | * called by network layer to process IOCTL call to network device | |
1505 | * | |
1506 | * dev pointer to network device structure | |
1507 | * ifr pointer to network interface request structure | |
1508 | * cmd IOCTL command code | |
1509 | * | |
1510 | * returns 0 if success, otherwise error code | |
1511 | */ | |
1512 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1513 | { | |
1514 | const size_t size = sizeof(sync_serial_settings); | |
1515 | sync_serial_settings new_line; | |
1516 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1517 | struct slgt_info *info = dev_to_port(dev); | |
1518 | unsigned int flags; | |
1519 | ||
1520 | DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); | |
1521 | ||
1522 | /* return error if TTY interface open */ | |
1523 | if (info->count) | |
1524 | return -EBUSY; | |
1525 | ||
1526 | if (cmd != SIOCWANDEV) | |
1527 | return hdlc_ioctl(dev, ifr, cmd); | |
1528 | ||
1529 | switch(ifr->ifr_settings.type) { | |
1530 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
1531 | ||
1532 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1533 | if (ifr->ifr_settings.size < size) { | |
1534 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1535 | return -ENOBUFS; | |
1536 | } | |
1537 | ||
1538 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1539 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1540 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1541 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1542 | ||
1543 | switch (flags){ | |
1544 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
1545 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
1546 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
1547 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
1548 | default: new_line.clock_type = CLOCK_DEFAULT; | |
1549 | } | |
1550 | ||
1551 | new_line.clock_rate = info->params.clock_speed; | |
1552 | new_line.loopback = info->params.loopback ? 1:0; | |
1553 | ||
1554 | if (copy_to_user(line, &new_line, size)) | |
1555 | return -EFAULT; | |
1556 | return 0; | |
1557 | ||
1558 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
1559 | ||
1560 | if(!capable(CAP_NET_ADMIN)) | |
1561 | return -EPERM; | |
1562 | if (copy_from_user(&new_line, line, size)) | |
1563 | return -EFAULT; | |
1564 | ||
1565 | switch (new_line.clock_type) | |
1566 | { | |
1567 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
1568 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
1569 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
1570 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
1571 | case CLOCK_DEFAULT: flags = info->params.flags & | |
1572 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1573 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1574 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1575 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
1576 | default: return -EINVAL; | |
1577 | } | |
1578 | ||
1579 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
1580 | return -EINVAL; | |
1581 | ||
1582 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1583 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1584 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1585 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1586 | info->params.flags |= flags; | |
1587 | ||
1588 | info->params.loopback = new_line.loopback; | |
1589 | ||
1590 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
1591 | info->params.clock_speed = new_line.clock_rate; | |
1592 | else | |
1593 | info->params.clock_speed = 0; | |
1594 | ||
1595 | /* if network interface up, reprogram hardware */ | |
1596 | if (info->netcount) | |
1597 | program_hw(info); | |
1598 | return 0; | |
1599 | ||
1600 | default: | |
1601 | return hdlc_ioctl(dev, ifr, cmd); | |
1602 | } | |
1603 | } | |
1604 | ||
1605 | /** | |
1606 | * called by network layer when transmit timeout is detected | |
1607 | * | |
1608 | * dev pointer to network device structure | |
1609 | */ | |
1610 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
1611 | { | |
1612 | struct slgt_info *info = dev_to_port(dev); | |
1613 | struct net_device_stats *stats = hdlc_stats(dev); | |
1614 | unsigned long flags; | |
1615 | ||
1616 | DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); | |
1617 | ||
1618 | stats->tx_errors++; | |
1619 | stats->tx_aborted_errors++; | |
1620 | ||
1621 | spin_lock_irqsave(&info->lock,flags); | |
1622 | tx_stop(info); | |
1623 | spin_unlock_irqrestore(&info->lock,flags); | |
1624 | ||
1625 | netif_wake_queue(dev); | |
1626 | } | |
1627 | ||
1628 | /** | |
1629 | * called by device driver when transmit completes | |
1630 | * reenable network layer transmit if stopped | |
1631 | * | |
1632 | * info pointer to device instance information | |
1633 | */ | |
1634 | static void hdlcdev_tx_done(struct slgt_info *info) | |
1635 | { | |
1636 | if (netif_queue_stopped(info->netdev)) | |
1637 | netif_wake_queue(info->netdev); | |
1638 | } | |
1639 | ||
1640 | /** | |
1641 | * called by device driver when frame received | |
1642 | * pass frame to network layer | |
1643 | * | |
1644 | * info pointer to device instance information | |
1645 | * buf pointer to buffer contianing frame data | |
1646 | * size count of data bytes in buf | |
1647 | */ | |
1648 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) | |
1649 | { | |
1650 | struct sk_buff *skb = dev_alloc_skb(size); | |
1651 | struct net_device *dev = info->netdev; | |
1652 | struct net_device_stats *stats = hdlc_stats(dev); | |
1653 | ||
1654 | DBGINFO(("%s hdlcdev_rx\n", dev->name)); | |
1655 | ||
1656 | if (skb == NULL) { | |
1657 | DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); | |
1658 | stats->rx_dropped++; | |
1659 | return; | |
1660 | } | |
1661 | ||
1662 | memcpy(skb_put(skb, size),buf,size); | |
1663 | ||
1664 | skb->protocol = hdlc_type_trans(skb, info->netdev); | |
1665 | ||
1666 | stats->rx_packets++; | |
1667 | stats->rx_bytes += size; | |
1668 | ||
1669 | netif_rx(skb); | |
1670 | ||
1671 | info->netdev->last_rx = jiffies; | |
1672 | } | |
1673 | ||
1674 | /** | |
1675 | * called by device driver when adding device instance | |
1676 | * do generic HDLC initialization | |
1677 | * | |
1678 | * info pointer to device instance information | |
1679 | * | |
1680 | * returns 0 if success, otherwise error code | |
1681 | */ | |
1682 | static int hdlcdev_init(struct slgt_info *info) | |
1683 | { | |
1684 | int rc; | |
1685 | struct net_device *dev; | |
1686 | hdlc_device *hdlc; | |
1687 | ||
1688 | /* allocate and initialize network and HDLC layer objects */ | |
1689 | ||
1690 | if (!(dev = alloc_hdlcdev(info))) { | |
1691 | printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); | |
1692 | return -ENOMEM; | |
1693 | } | |
1694 | ||
1695 | /* for network layer reporting purposes only */ | |
1696 | dev->mem_start = info->phys_reg_addr; | |
1697 | dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; | |
1698 | dev->irq = info->irq_level; | |
1699 | ||
1700 | /* network layer callbacks and settings */ | |
1701 | dev->do_ioctl = hdlcdev_ioctl; | |
1702 | dev->open = hdlcdev_open; | |
1703 | dev->stop = hdlcdev_close; | |
1704 | dev->tx_timeout = hdlcdev_tx_timeout; | |
1705 | dev->watchdog_timeo = 10*HZ; | |
1706 | dev->tx_queue_len = 50; | |
1707 | ||
1708 | /* generic HDLC layer callbacks and settings */ | |
1709 | hdlc = dev_to_hdlc(dev); | |
1710 | hdlc->attach = hdlcdev_attach; | |
1711 | hdlc->xmit = hdlcdev_xmit; | |
1712 | ||
1713 | /* register objects with HDLC layer */ | |
1714 | if ((rc = register_hdlc_device(dev))) { | |
1715 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); | |
1716 | free_netdev(dev); | |
1717 | return rc; | |
1718 | } | |
1719 | ||
1720 | info->netdev = dev; | |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | /** | |
1725 | * called by device driver when removing device instance | |
1726 | * do generic HDLC cleanup | |
1727 | * | |
1728 | * info pointer to device instance information | |
1729 | */ | |
1730 | static void hdlcdev_exit(struct slgt_info *info) | |
1731 | { | |
1732 | unregister_hdlc_device(info->netdev); | |
1733 | free_netdev(info->netdev); | |
1734 | info->netdev = NULL; | |
1735 | } | |
1736 | ||
1737 | #endif /* ifdef CONFIG_HDLC */ | |
1738 | ||
1739 | /* | |
1740 | * get async data from rx DMA buffers | |
1741 | */ | |
1742 | static void rx_async(struct slgt_info *info) | |
1743 | { | |
1744 | struct tty_struct *tty = info->tty; | |
1745 | struct mgsl_icount *icount = &info->icount; | |
1746 | unsigned int start, end; | |
1747 | unsigned char *p; | |
1748 | unsigned char status; | |
1749 | struct slgt_desc *bufs = info->rbufs; | |
1750 | int i, count; | |
33f0f88f AC |
1751 | int chars = 0; |
1752 | int stat; | |
1753 | unsigned char ch; | |
705b6c7b PF |
1754 | |
1755 | start = end = info->rbuf_current; | |
1756 | ||
1757 | while(desc_complete(bufs[end])) { | |
1758 | count = desc_count(bufs[end]) - info->rbuf_index; | |
1759 | p = bufs[end].buf + info->rbuf_index; | |
1760 | ||
1761 | DBGISR(("%s rx_async count=%d\n", info->device_name, count)); | |
1762 | DBGDATA(info, p, count, "rx"); | |
1763 | ||
1764 | for(i=0 ; i < count; i+=2, p+=2) { | |
33f0f88f AC |
1765 | if (tty && chars) { |
1766 | tty_flip_buffer_push(tty); | |
1767 | chars = 0; | |
705b6c7b | 1768 | } |
33f0f88f | 1769 | ch = *p; |
705b6c7b PF |
1770 | icount->rx++; |
1771 | ||
33f0f88f AC |
1772 | stat = 0; |
1773 | ||
705b6c7b PF |
1774 | if ((status = *(p+1) & (BIT9 + BIT8))) { |
1775 | if (status & BIT9) | |
1776 | icount->parity++; | |
1777 | else if (status & BIT8) | |
1778 | icount->frame++; | |
1779 | /* discard char if tty control flags say so */ | |
1780 | if (status & info->ignore_status_mask) | |
1781 | continue; | |
33f0f88f AC |
1782 | if (status & BIT9) |
1783 | stat = TTY_PARITY; | |
1784 | else if (status & BIT8) | |
1785 | stat = TTY_FRAME; | |
705b6c7b PF |
1786 | } |
1787 | if (tty) { | |
33f0f88f AC |
1788 | tty_insert_flip_char(tty, ch, stat); |
1789 | chars++; | |
705b6c7b PF |
1790 | } |
1791 | } | |
1792 | ||
1793 | if (i < count) { | |
1794 | /* receive buffer not completed */ | |
1795 | info->rbuf_index += i; | |
1796 | info->rx_timer.expires = jiffies + 1; | |
1797 | add_timer(&info->rx_timer); | |
1798 | break; | |
1799 | } | |
1800 | ||
1801 | info->rbuf_index = 0; | |
1802 | free_rbufs(info, end, end); | |
1803 | ||
1804 | if (++end == info->rbuf_count) | |
1805 | end = 0; | |
1806 | ||
1807 | /* if entire list searched then no frame available */ | |
1808 | if (end == start) | |
1809 | break; | |
1810 | } | |
1811 | ||
33f0f88f | 1812 | if (tty && chars) |
705b6c7b PF |
1813 | tty_flip_buffer_push(tty); |
1814 | } | |
1815 | ||
1816 | /* | |
1817 | * return next bottom half action to perform | |
1818 | */ | |
1819 | static int bh_action(struct slgt_info *info) | |
1820 | { | |
1821 | unsigned long flags; | |
1822 | int rc; | |
1823 | ||
1824 | spin_lock_irqsave(&info->lock,flags); | |
1825 | ||
1826 | if (info->pending_bh & BH_RECEIVE) { | |
1827 | info->pending_bh &= ~BH_RECEIVE; | |
1828 | rc = BH_RECEIVE; | |
1829 | } else if (info->pending_bh & BH_TRANSMIT) { | |
1830 | info->pending_bh &= ~BH_TRANSMIT; | |
1831 | rc = BH_TRANSMIT; | |
1832 | } else if (info->pending_bh & BH_STATUS) { | |
1833 | info->pending_bh &= ~BH_STATUS; | |
1834 | rc = BH_STATUS; | |
1835 | } else { | |
1836 | /* Mark BH routine as complete */ | |
1837 | info->bh_running = 0; | |
1838 | info->bh_requested = 0; | |
1839 | rc = 0; | |
1840 | } | |
1841 | ||
1842 | spin_unlock_irqrestore(&info->lock,flags); | |
1843 | ||
1844 | return rc; | |
1845 | } | |
1846 | ||
1847 | /* | |
1848 | * perform bottom half processing | |
1849 | */ | |
1850 | static void bh_handler(void* context) | |
1851 | { | |
1852 | struct slgt_info *info = context; | |
1853 | int action; | |
1854 | ||
1855 | if (!info) | |
1856 | return; | |
1857 | info->bh_running = 1; | |
1858 | ||
1859 | while((action = bh_action(info))) { | |
1860 | switch (action) { | |
1861 | case BH_RECEIVE: | |
1862 | DBGBH(("%s bh receive\n", info->device_name)); | |
1863 | switch(info->params.mode) { | |
1864 | case MGSL_MODE_ASYNC: | |
1865 | rx_async(info); | |
1866 | break; | |
1867 | case MGSL_MODE_HDLC: | |
1868 | while(rx_get_frame(info)); | |
1869 | break; | |
1870 | case MGSL_MODE_RAW: | |
1871 | while(rx_get_buf(info)); | |
1872 | break; | |
1873 | } | |
1874 | /* restart receiver if rx DMA buffers exhausted */ | |
1875 | if (info->rx_restart) | |
1876 | rx_start(info); | |
1877 | break; | |
1878 | case BH_TRANSMIT: | |
1879 | bh_transmit(info); | |
1880 | break; | |
1881 | case BH_STATUS: | |
1882 | DBGBH(("%s bh status\n", info->device_name)); | |
1883 | info->ri_chkcount = 0; | |
1884 | info->dsr_chkcount = 0; | |
1885 | info->dcd_chkcount = 0; | |
1886 | info->cts_chkcount = 0; | |
1887 | break; | |
1888 | default: | |
1889 | DBGBH(("%s unknown action\n", info->device_name)); | |
1890 | break; | |
1891 | } | |
1892 | } | |
1893 | DBGBH(("%s bh_handler exit\n", info->device_name)); | |
1894 | } | |
1895 | ||
1896 | static void bh_transmit(struct slgt_info *info) | |
1897 | { | |
1898 | struct tty_struct *tty = info->tty; | |
1899 | ||
1900 | DBGBH(("%s bh_transmit\n", info->device_name)); | |
1901 | if (tty) { | |
1902 | tty_wakeup(tty); | |
1903 | wake_up_interruptible(&tty->write_wait); | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | static void dsr_change(struct slgt_info *info) | |
1908 | { | |
1909 | get_signals(info); | |
1910 | DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); | |
1911 | if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
1912 | slgt_irq_off(info, IRQ_DSR); | |
1913 | return; | |
1914 | } | |
1915 | info->icount.dsr++; | |
1916 | if (info->signals & SerialSignal_DSR) | |
1917 | info->input_signal_events.dsr_up++; | |
1918 | else | |
1919 | info->input_signal_events.dsr_down++; | |
1920 | wake_up_interruptible(&info->status_event_wait_q); | |
1921 | wake_up_interruptible(&info->event_wait_q); | |
1922 | info->pending_bh |= BH_STATUS; | |
1923 | } | |
1924 | ||
1925 | static void cts_change(struct slgt_info *info) | |
1926 | { | |
1927 | get_signals(info); | |
1928 | DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); | |
1929 | if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
1930 | slgt_irq_off(info, IRQ_CTS); | |
1931 | return; | |
1932 | } | |
1933 | info->icount.cts++; | |
1934 | if (info->signals & SerialSignal_CTS) | |
1935 | info->input_signal_events.cts_up++; | |
1936 | else | |
1937 | info->input_signal_events.cts_down++; | |
1938 | wake_up_interruptible(&info->status_event_wait_q); | |
1939 | wake_up_interruptible(&info->event_wait_q); | |
1940 | info->pending_bh |= BH_STATUS; | |
1941 | ||
1942 | if (info->flags & ASYNC_CTS_FLOW) { | |
1943 | if (info->tty) { | |
1944 | if (info->tty->hw_stopped) { | |
1945 | if (info->signals & SerialSignal_CTS) { | |
1946 | info->tty->hw_stopped = 0; | |
1947 | info->pending_bh |= BH_TRANSMIT; | |
1948 | return; | |
1949 | } | |
1950 | } else { | |
1951 | if (!(info->signals & SerialSignal_CTS)) | |
1952 | info->tty->hw_stopped = 1; | |
1953 | } | |
1954 | } | |
1955 | } | |
1956 | } | |
1957 | ||
1958 | static void dcd_change(struct slgt_info *info) | |
1959 | { | |
1960 | get_signals(info); | |
1961 | DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); | |
1962 | if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
1963 | slgt_irq_off(info, IRQ_DCD); | |
1964 | return; | |
1965 | } | |
1966 | info->icount.dcd++; | |
1967 | if (info->signals & SerialSignal_DCD) { | |
1968 | info->input_signal_events.dcd_up++; | |
1969 | } else { | |
1970 | info->input_signal_events.dcd_down++; | |
1971 | } | |
1972 | #ifdef CONFIG_HDLC | |
1973 | if (info->netcount) | |
1974 | hdlc_set_carrier(info->signals & SerialSignal_DCD, info->netdev); | |
1975 | #endif | |
1976 | wake_up_interruptible(&info->status_event_wait_q); | |
1977 | wake_up_interruptible(&info->event_wait_q); | |
1978 | info->pending_bh |= BH_STATUS; | |
1979 | ||
1980 | if (info->flags & ASYNC_CHECK_CD) { | |
1981 | if (info->signals & SerialSignal_DCD) | |
1982 | wake_up_interruptible(&info->open_wait); | |
1983 | else { | |
1984 | if (info->tty) | |
1985 | tty_hangup(info->tty); | |
1986 | } | |
1987 | } | |
1988 | } | |
1989 | ||
1990 | static void ri_change(struct slgt_info *info) | |
1991 | { | |
1992 | get_signals(info); | |
1993 | DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); | |
1994 | if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
1995 | slgt_irq_off(info, IRQ_RI); | |
1996 | return; | |
1997 | } | |
1998 | info->icount.dcd++; | |
1999 | if (info->signals & SerialSignal_RI) { | |
2000 | info->input_signal_events.ri_up++; | |
2001 | } else { | |
2002 | info->input_signal_events.ri_down++; | |
2003 | } | |
2004 | wake_up_interruptible(&info->status_event_wait_q); | |
2005 | wake_up_interruptible(&info->event_wait_q); | |
2006 | info->pending_bh |= BH_STATUS; | |
2007 | } | |
2008 | ||
2009 | static void isr_serial(struct slgt_info *info) | |
2010 | { | |
2011 | unsigned short status = rd_reg16(info, SSR); | |
2012 | ||
2013 | DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); | |
2014 | ||
2015 | wr_reg16(info, SSR, status); /* clear pending */ | |
2016 | ||
2017 | info->irq_occurred = 1; | |
2018 | ||
2019 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
2020 | if (status & IRQ_TXIDLE) { | |
2021 | if (info->tx_count) | |
2022 | isr_txeom(info, status); | |
2023 | } | |
2024 | if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { | |
2025 | info->icount.brk++; | |
2026 | /* process break detection if tty control allows */ | |
2027 | if (info->tty) { | |
2028 | if (!(status & info->ignore_status_mask)) { | |
2029 | if (info->read_status_mask & MASK_BREAK) { | |
33f0f88f | 2030 | tty_insert_flip_char(info->tty, 0, TTY_BREAK); |
705b6c7b PF |
2031 | if (info->flags & ASYNC_SAK) |
2032 | do_SAK(info->tty); | |
2033 | } | |
2034 | } | |
2035 | } | |
2036 | } | |
2037 | } else { | |
2038 | if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) | |
2039 | isr_txeom(info, status); | |
2040 | ||
2041 | if (status & IRQ_RXIDLE) { | |
2042 | if (status & RXIDLE) | |
2043 | info->icount.rxidle++; | |
2044 | else | |
2045 | info->icount.exithunt++; | |
2046 | wake_up_interruptible(&info->event_wait_q); | |
2047 | } | |
2048 | ||
2049 | if (status & IRQ_RXOVER) | |
2050 | rx_start(info); | |
2051 | } | |
2052 | ||
2053 | if (status & IRQ_DSR) | |
2054 | dsr_change(info); | |
2055 | if (status & IRQ_CTS) | |
2056 | cts_change(info); | |
2057 | if (status & IRQ_DCD) | |
2058 | dcd_change(info); | |
2059 | if (status & IRQ_RI) | |
2060 | ri_change(info); | |
2061 | } | |
2062 | ||
2063 | static void isr_rdma(struct slgt_info *info) | |
2064 | { | |
2065 | unsigned int status = rd_reg32(info, RDCSR); | |
2066 | ||
2067 | DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); | |
2068 | ||
2069 | /* RDCSR (rx DMA control/status) | |
2070 | * | |
2071 | * 31..07 reserved | |
2072 | * 06 save status byte to DMA buffer | |
2073 | * 05 error | |
2074 | * 04 eol (end of list) | |
2075 | * 03 eob (end of buffer) | |
2076 | * 02 IRQ enable | |
2077 | * 01 reset | |
2078 | * 00 enable | |
2079 | */ | |
2080 | wr_reg32(info, RDCSR, status); /* clear pending */ | |
2081 | ||
2082 | if (status & (BIT5 + BIT4)) { | |
2083 | DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); | |
2084 | info->rx_restart = 1; | |
2085 | } | |
2086 | info->pending_bh |= BH_RECEIVE; | |
2087 | } | |
2088 | ||
2089 | static void isr_tdma(struct slgt_info *info) | |
2090 | { | |
2091 | unsigned int status = rd_reg32(info, TDCSR); | |
2092 | ||
2093 | DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); | |
2094 | ||
2095 | /* TDCSR (tx DMA control/status) | |
2096 | * | |
2097 | * 31..06 reserved | |
2098 | * 05 error | |
2099 | * 04 eol (end of list) | |
2100 | * 03 eob (end of buffer) | |
2101 | * 02 IRQ enable | |
2102 | * 01 reset | |
2103 | * 00 enable | |
2104 | */ | |
2105 | wr_reg32(info, TDCSR, status); /* clear pending */ | |
2106 | ||
2107 | if (status & (BIT5 + BIT4 + BIT3)) { | |
2108 | // another transmit buffer has completed | |
2109 | // run bottom half to get more send data from user | |
2110 | info->pending_bh |= BH_TRANSMIT; | |
2111 | } | |
2112 | } | |
2113 | ||
2114 | static void isr_txeom(struct slgt_info *info, unsigned short status) | |
2115 | { | |
2116 | DBGISR(("%s txeom status=%04x\n", info->device_name, status)); | |
2117 | ||
2118 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
2119 | tdma_reset(info); | |
2120 | reset_tbufs(info); | |
2121 | if (status & IRQ_TXUNDER) { | |
2122 | unsigned short val = rd_reg16(info, TCR); | |
2123 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
2124 | wr_reg16(info, TCR, val); /* clear reset bit */ | |
2125 | } | |
2126 | ||
2127 | if (info->tx_active) { | |
2128 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2129 | if (status & IRQ_TXUNDER) | |
2130 | info->icount.txunder++; | |
2131 | else if (status & IRQ_TXIDLE) | |
2132 | info->icount.txok++; | |
2133 | } | |
2134 | ||
2135 | info->tx_active = 0; | |
2136 | info->tx_count = 0; | |
2137 | ||
2138 | del_timer(&info->tx_timer); | |
2139 | ||
2140 | if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { | |
2141 | info->signals &= ~SerialSignal_RTS; | |
2142 | info->drop_rts_on_tx_done = 0; | |
2143 | set_signals(info); | |
2144 | } | |
2145 | ||
2146 | #ifdef CONFIG_HDLC | |
2147 | if (info->netcount) | |
2148 | hdlcdev_tx_done(info); | |
2149 | else | |
2150 | #endif | |
2151 | { | |
2152 | if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) { | |
2153 | tx_stop(info); | |
2154 | return; | |
2155 | } | |
2156 | info->pending_bh |= BH_TRANSMIT; | |
2157 | } | |
2158 | } | |
2159 | } | |
2160 | ||
2161 | /* interrupt service routine | |
2162 | * | |
2163 | * irq interrupt number | |
2164 | * dev_id device ID supplied during interrupt registration | |
2165 | * regs interrupted processor context | |
2166 | */ | |
2167 | static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs) | |
2168 | { | |
2169 | struct slgt_info *info; | |
2170 | unsigned int gsr; | |
2171 | unsigned int i; | |
2172 | ||
2173 | DBGISR(("slgt_interrupt irq=%d entry\n", irq)); | |
2174 | ||
2175 | info = dev_id; | |
2176 | if (!info) | |
2177 | return IRQ_NONE; | |
2178 | ||
2179 | spin_lock(&info->lock); | |
2180 | ||
2181 | while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { | |
2182 | DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); | |
2183 | info->irq_occurred = 1; | |
2184 | for(i=0; i < info->port_count ; i++) { | |
2185 | if (info->port_array[i] == NULL) | |
2186 | continue; | |
2187 | if (gsr & (BIT8 << i)) | |
2188 | isr_serial(info->port_array[i]); | |
2189 | if (gsr & (BIT16 << (i*2))) | |
2190 | isr_rdma(info->port_array[i]); | |
2191 | if (gsr & (BIT17 << (i*2))) | |
2192 | isr_tdma(info->port_array[i]); | |
2193 | } | |
2194 | } | |
2195 | ||
2196 | for(i=0; i < info->port_count ; i++) { | |
2197 | struct slgt_info *port = info->port_array[i]; | |
2198 | ||
2199 | if (port && (port->count || port->netcount) && | |
2200 | port->pending_bh && !port->bh_running && | |
2201 | !port->bh_requested) { | |
2202 | DBGISR(("%s bh queued\n", port->device_name)); | |
2203 | schedule_work(&port->task); | |
2204 | port->bh_requested = 1; | |
2205 | } | |
2206 | } | |
2207 | ||
2208 | spin_unlock(&info->lock); | |
2209 | ||
2210 | DBGISR(("slgt_interrupt irq=%d exit\n", irq)); | |
2211 | return IRQ_HANDLED; | |
2212 | } | |
2213 | ||
2214 | static int startup(struct slgt_info *info) | |
2215 | { | |
2216 | DBGINFO(("%s startup\n", info->device_name)); | |
2217 | ||
2218 | if (info->flags & ASYNC_INITIALIZED) | |
2219 | return 0; | |
2220 | ||
2221 | if (!info->tx_buf) { | |
2222 | info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); | |
2223 | if (!info->tx_buf) { | |
2224 | DBGERR(("%s can't allocate tx buffer\n", info->device_name)); | |
2225 | return -ENOMEM; | |
2226 | } | |
2227 | } | |
2228 | ||
2229 | info->pending_bh = 0; | |
2230 | ||
2231 | memset(&info->icount, 0, sizeof(info->icount)); | |
2232 | ||
2233 | /* program hardware for current parameters */ | |
2234 | change_params(info); | |
2235 | ||
2236 | if (info->tty) | |
2237 | clear_bit(TTY_IO_ERROR, &info->tty->flags); | |
2238 | ||
2239 | info->flags |= ASYNC_INITIALIZED; | |
2240 | ||
2241 | return 0; | |
2242 | } | |
2243 | ||
2244 | /* | |
2245 | * called by close() and hangup() to shutdown hardware | |
2246 | */ | |
2247 | static void shutdown(struct slgt_info *info) | |
2248 | { | |
2249 | unsigned long flags; | |
2250 | ||
2251 | if (!(info->flags & ASYNC_INITIALIZED)) | |
2252 | return; | |
2253 | ||
2254 | DBGINFO(("%s shutdown\n", info->device_name)); | |
2255 | ||
2256 | /* clear status wait queue because status changes */ | |
2257 | /* can't happen after shutting down the hardware */ | |
2258 | wake_up_interruptible(&info->status_event_wait_q); | |
2259 | wake_up_interruptible(&info->event_wait_q); | |
2260 | ||
2261 | del_timer_sync(&info->tx_timer); | |
2262 | del_timer_sync(&info->rx_timer); | |
2263 | ||
2264 | kfree(info->tx_buf); | |
2265 | info->tx_buf = NULL; | |
2266 | ||
2267 | spin_lock_irqsave(&info->lock,flags); | |
2268 | ||
2269 | tx_stop(info); | |
2270 | rx_stop(info); | |
2271 | ||
2272 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
2273 | ||
2274 | if (!info->tty || info->tty->termios->c_cflag & HUPCL) { | |
2275 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
2276 | set_signals(info); | |
2277 | } | |
2278 | ||
2279 | spin_unlock_irqrestore(&info->lock,flags); | |
2280 | ||
2281 | if (info->tty) | |
2282 | set_bit(TTY_IO_ERROR, &info->tty->flags); | |
2283 | ||
2284 | info->flags &= ~ASYNC_INITIALIZED; | |
2285 | } | |
2286 | ||
2287 | static void program_hw(struct slgt_info *info) | |
2288 | { | |
2289 | unsigned long flags; | |
2290 | ||
2291 | spin_lock_irqsave(&info->lock,flags); | |
2292 | ||
2293 | rx_stop(info); | |
2294 | tx_stop(info); | |
2295 | ||
2296 | if (info->params.mode == MGSL_MODE_HDLC || | |
2297 | info->params.mode == MGSL_MODE_RAW || | |
2298 | info->netcount) | |
2299 | hdlc_mode(info); | |
2300 | else | |
2301 | async_mode(info); | |
2302 | ||
2303 | set_signals(info); | |
2304 | ||
2305 | info->dcd_chkcount = 0; | |
2306 | info->cts_chkcount = 0; | |
2307 | info->ri_chkcount = 0; | |
2308 | info->dsr_chkcount = 0; | |
2309 | ||
2310 | slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR); | |
2311 | get_signals(info); | |
2312 | ||
2313 | if (info->netcount || | |
2314 | (info->tty && info->tty->termios->c_cflag & CREAD)) | |
2315 | rx_start(info); | |
2316 | ||
2317 | spin_unlock_irqrestore(&info->lock,flags); | |
2318 | } | |
2319 | ||
2320 | /* | |
2321 | * reconfigure adapter based on new parameters | |
2322 | */ | |
2323 | static void change_params(struct slgt_info *info) | |
2324 | { | |
2325 | unsigned cflag; | |
2326 | int bits_per_char; | |
2327 | ||
2328 | if (!info->tty || !info->tty->termios) | |
2329 | return; | |
2330 | DBGINFO(("%s change_params\n", info->device_name)); | |
2331 | ||
2332 | cflag = info->tty->termios->c_cflag; | |
2333 | ||
2334 | /* if B0 rate (hangup) specified then negate DTR and RTS */ | |
2335 | /* otherwise assert DTR and RTS */ | |
2336 | if (cflag & CBAUD) | |
2337 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
2338 | else | |
2339 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
2340 | ||
2341 | /* byte size and parity */ | |
2342 | ||
2343 | switch (cflag & CSIZE) { | |
2344 | case CS5: info->params.data_bits = 5; break; | |
2345 | case CS6: info->params.data_bits = 6; break; | |
2346 | case CS7: info->params.data_bits = 7; break; | |
2347 | case CS8: info->params.data_bits = 8; break; | |
2348 | default: info->params.data_bits = 7; break; | |
2349 | } | |
2350 | ||
2351 | info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; | |
2352 | ||
2353 | if (cflag & PARENB) | |
2354 | info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; | |
2355 | else | |
2356 | info->params.parity = ASYNC_PARITY_NONE; | |
2357 | ||
2358 | /* calculate number of jiffies to transmit a full | |
2359 | * FIFO (32 bytes) at specified data rate | |
2360 | */ | |
2361 | bits_per_char = info->params.data_bits + | |
2362 | info->params.stop_bits + 1; | |
2363 | ||
2364 | info->params.data_rate = tty_get_baud_rate(info->tty); | |
2365 | ||
2366 | if (info->params.data_rate) { | |
2367 | info->timeout = (32*HZ*bits_per_char) / | |
2368 | info->params.data_rate; | |
2369 | } | |
2370 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
2371 | ||
2372 | if (cflag & CRTSCTS) | |
2373 | info->flags |= ASYNC_CTS_FLOW; | |
2374 | else | |
2375 | info->flags &= ~ASYNC_CTS_FLOW; | |
2376 | ||
2377 | if (cflag & CLOCAL) | |
2378 | info->flags &= ~ASYNC_CHECK_CD; | |
2379 | else | |
2380 | info->flags |= ASYNC_CHECK_CD; | |
2381 | ||
2382 | /* process tty input control flags */ | |
2383 | ||
2384 | info->read_status_mask = IRQ_RXOVER; | |
2385 | if (I_INPCK(info->tty)) | |
2386 | info->read_status_mask |= MASK_PARITY | MASK_FRAMING; | |
2387 | if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) | |
2388 | info->read_status_mask |= MASK_BREAK; | |
2389 | if (I_IGNPAR(info->tty)) | |
2390 | info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; | |
2391 | if (I_IGNBRK(info->tty)) { | |
2392 | info->ignore_status_mask |= MASK_BREAK; | |
2393 | /* If ignoring parity and break indicators, ignore | |
2394 | * overruns too. (For real raw support). | |
2395 | */ | |
2396 | if (I_IGNPAR(info->tty)) | |
2397 | info->ignore_status_mask |= MASK_OVERRUN; | |
2398 | } | |
2399 | ||
2400 | program_hw(info); | |
2401 | } | |
2402 | ||
2403 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) | |
2404 | { | |
2405 | DBGINFO(("%s get_stats\n", info->device_name)); | |
2406 | if (!user_icount) { | |
2407 | memset(&info->icount, 0, sizeof(info->icount)); | |
2408 | } else { | |
2409 | if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) | |
2410 | return -EFAULT; | |
2411 | } | |
2412 | return 0; | |
2413 | } | |
2414 | ||
2415 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) | |
2416 | { | |
2417 | DBGINFO(("%s get_params\n", info->device_name)); | |
2418 | if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) | |
2419 | return -EFAULT; | |
2420 | return 0; | |
2421 | } | |
2422 | ||
2423 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) | |
2424 | { | |
2425 | unsigned long flags; | |
2426 | MGSL_PARAMS tmp_params; | |
2427 | ||
2428 | DBGINFO(("%s set_params\n", info->device_name)); | |
2429 | if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) | |
2430 | return -EFAULT; | |
2431 | ||
2432 | spin_lock_irqsave(&info->lock, flags); | |
2433 | memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); | |
2434 | spin_unlock_irqrestore(&info->lock, flags); | |
2435 | ||
2436 | change_params(info); | |
2437 | ||
2438 | return 0; | |
2439 | } | |
2440 | ||
2441 | static int get_txidle(struct slgt_info *info, int __user *idle_mode) | |
2442 | { | |
2443 | DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); | |
2444 | if (put_user(info->idle_mode, idle_mode)) | |
2445 | return -EFAULT; | |
2446 | return 0; | |
2447 | } | |
2448 | ||
2449 | static int set_txidle(struct slgt_info *info, int idle_mode) | |
2450 | { | |
2451 | unsigned long flags; | |
2452 | DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); | |
2453 | spin_lock_irqsave(&info->lock,flags); | |
2454 | info->idle_mode = idle_mode; | |
2455 | tx_set_idle(info); | |
2456 | spin_unlock_irqrestore(&info->lock,flags); | |
2457 | return 0; | |
2458 | } | |
2459 | ||
2460 | static int tx_enable(struct slgt_info *info, int enable) | |
2461 | { | |
2462 | unsigned long flags; | |
2463 | DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); | |
2464 | spin_lock_irqsave(&info->lock,flags); | |
2465 | if (enable) { | |
2466 | if (!info->tx_enabled) | |
2467 | tx_start(info); | |
2468 | } else { | |
2469 | if (info->tx_enabled) | |
2470 | tx_stop(info); | |
2471 | } | |
2472 | spin_unlock_irqrestore(&info->lock,flags); | |
2473 | return 0; | |
2474 | } | |
2475 | ||
2476 | /* | |
2477 | * abort transmit HDLC frame | |
2478 | */ | |
2479 | static int tx_abort(struct slgt_info *info) | |
2480 | { | |
2481 | unsigned long flags; | |
2482 | DBGINFO(("%s tx_abort\n", info->device_name)); | |
2483 | spin_lock_irqsave(&info->lock,flags); | |
2484 | tdma_reset(info); | |
2485 | spin_unlock_irqrestore(&info->lock,flags); | |
2486 | return 0; | |
2487 | } | |
2488 | ||
2489 | static int rx_enable(struct slgt_info *info, int enable) | |
2490 | { | |
2491 | unsigned long flags; | |
2492 | DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable)); | |
2493 | spin_lock_irqsave(&info->lock,flags); | |
2494 | if (enable) { | |
2495 | if (!info->rx_enabled) | |
2496 | rx_start(info); | |
2497 | } else { | |
2498 | if (info->rx_enabled) | |
2499 | rx_stop(info); | |
2500 | } | |
2501 | spin_unlock_irqrestore(&info->lock,flags); | |
2502 | return 0; | |
2503 | } | |
2504 | ||
2505 | /* | |
2506 | * wait for specified event to occur | |
2507 | */ | |
2508 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) | |
2509 | { | |
2510 | unsigned long flags; | |
2511 | int s; | |
2512 | int rc=0; | |
2513 | struct mgsl_icount cprev, cnow; | |
2514 | int events; | |
2515 | int mask; | |
2516 | struct _input_signal_events oldsigs, newsigs; | |
2517 | DECLARE_WAITQUEUE(wait, current); | |
2518 | ||
2519 | if (get_user(mask, mask_ptr)) | |
2520 | return -EFAULT; | |
2521 | ||
2522 | DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); | |
2523 | ||
2524 | spin_lock_irqsave(&info->lock,flags); | |
2525 | ||
2526 | /* return immediately if state matches requested events */ | |
2527 | get_signals(info); | |
2528 | s = info->signals; | |
2529 | ||
2530 | events = mask & | |
2531 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
2532 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
2533 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
2534 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
2535 | if (events) { | |
2536 | spin_unlock_irqrestore(&info->lock,flags); | |
2537 | goto exit; | |
2538 | } | |
2539 | ||
2540 | /* save current irq counts */ | |
2541 | cprev = info->icount; | |
2542 | oldsigs = info->input_signal_events; | |
2543 | ||
2544 | /* enable hunt and idle irqs if needed */ | |
2545 | if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { | |
2546 | unsigned short val = rd_reg16(info, SCR); | |
2547 | if (!(val & IRQ_RXIDLE)) | |
2548 | wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); | |
2549 | } | |
2550 | ||
2551 | set_current_state(TASK_INTERRUPTIBLE); | |
2552 | add_wait_queue(&info->event_wait_q, &wait); | |
2553 | ||
2554 | spin_unlock_irqrestore(&info->lock,flags); | |
2555 | ||
2556 | for(;;) { | |
2557 | schedule(); | |
2558 | if (signal_pending(current)) { | |
2559 | rc = -ERESTARTSYS; | |
2560 | break; | |
2561 | } | |
2562 | ||
2563 | /* get current irq counts */ | |
2564 | spin_lock_irqsave(&info->lock,flags); | |
2565 | cnow = info->icount; | |
2566 | newsigs = info->input_signal_events; | |
2567 | set_current_state(TASK_INTERRUPTIBLE); | |
2568 | spin_unlock_irqrestore(&info->lock,flags); | |
2569 | ||
2570 | /* if no change, wait aborted for some reason */ | |
2571 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
2572 | newsigs.dsr_down == oldsigs.dsr_down && | |
2573 | newsigs.dcd_up == oldsigs.dcd_up && | |
2574 | newsigs.dcd_down == oldsigs.dcd_down && | |
2575 | newsigs.cts_up == oldsigs.cts_up && | |
2576 | newsigs.cts_down == oldsigs.cts_down && | |
2577 | newsigs.ri_up == oldsigs.ri_up && | |
2578 | newsigs.ri_down == oldsigs.ri_down && | |
2579 | cnow.exithunt == cprev.exithunt && | |
2580 | cnow.rxidle == cprev.rxidle) { | |
2581 | rc = -EIO; | |
2582 | break; | |
2583 | } | |
2584 | ||
2585 | events = mask & | |
2586 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
2587 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
2588 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
2589 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
2590 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
2591 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
2592 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
2593 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
2594 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
2595 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
2596 | if (events) | |
2597 | break; | |
2598 | ||
2599 | cprev = cnow; | |
2600 | oldsigs = newsigs; | |
2601 | } | |
2602 | ||
2603 | remove_wait_queue(&info->event_wait_q, &wait); | |
2604 | set_current_state(TASK_RUNNING); | |
2605 | ||
2606 | ||
2607 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
2608 | spin_lock_irqsave(&info->lock,flags); | |
2609 | if (!waitqueue_active(&info->event_wait_q)) { | |
2610 | /* disable enable exit hunt mode/idle rcvd IRQs */ | |
2611 | wr_reg16(info, SCR, | |
2612 | (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); | |
2613 | } | |
2614 | spin_unlock_irqrestore(&info->lock,flags); | |
2615 | } | |
2616 | exit: | |
2617 | if (rc == 0) | |
2618 | rc = put_user(events, mask_ptr); | |
2619 | return rc; | |
2620 | } | |
2621 | ||
2622 | static int get_interface(struct slgt_info *info, int __user *if_mode) | |
2623 | { | |
2624 | DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); | |
2625 | if (put_user(info->if_mode, if_mode)) | |
2626 | return -EFAULT; | |
2627 | return 0; | |
2628 | } | |
2629 | ||
2630 | static int set_interface(struct slgt_info *info, int if_mode) | |
2631 | { | |
2632 | unsigned long flags; | |
35fbd397 | 2633 | unsigned short val; |
705b6c7b PF |
2634 | |
2635 | DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); | |
2636 | spin_lock_irqsave(&info->lock,flags); | |
2637 | info->if_mode = if_mode; | |
2638 | ||
2639 | msc_set_vcr(info); | |
2640 | ||
2641 | /* TCR (tx control) 07 1=RTS driver control */ | |
2642 | val = rd_reg16(info, TCR); | |
2643 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
2644 | val |= BIT7; | |
2645 | else | |
2646 | val &= ~BIT7; | |
2647 | wr_reg16(info, TCR, val); | |
2648 | ||
2649 | spin_unlock_irqrestore(&info->lock,flags); | |
2650 | return 0; | |
2651 | } | |
2652 | ||
2653 | static int modem_input_wait(struct slgt_info *info,int arg) | |
2654 | { | |
2655 | unsigned long flags; | |
2656 | int rc; | |
2657 | struct mgsl_icount cprev, cnow; | |
2658 | DECLARE_WAITQUEUE(wait, current); | |
2659 | ||
2660 | /* save current irq counts */ | |
2661 | spin_lock_irqsave(&info->lock,flags); | |
2662 | cprev = info->icount; | |
2663 | add_wait_queue(&info->status_event_wait_q, &wait); | |
2664 | set_current_state(TASK_INTERRUPTIBLE); | |
2665 | spin_unlock_irqrestore(&info->lock,flags); | |
2666 | ||
2667 | for(;;) { | |
2668 | schedule(); | |
2669 | if (signal_pending(current)) { | |
2670 | rc = -ERESTARTSYS; | |
2671 | break; | |
2672 | } | |
2673 | ||
2674 | /* get new irq counts */ | |
2675 | spin_lock_irqsave(&info->lock,flags); | |
2676 | cnow = info->icount; | |
2677 | set_current_state(TASK_INTERRUPTIBLE); | |
2678 | spin_unlock_irqrestore(&info->lock,flags); | |
2679 | ||
2680 | /* if no change, wait aborted for some reason */ | |
2681 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
2682 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
2683 | rc = -EIO; | |
2684 | break; | |
2685 | } | |
2686 | ||
2687 | /* check for change in caller specified modem input */ | |
2688 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
2689 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
2690 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
2691 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
2692 | rc = 0; | |
2693 | break; | |
2694 | } | |
2695 | ||
2696 | cprev = cnow; | |
2697 | } | |
2698 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
2699 | set_current_state(TASK_RUNNING); | |
2700 | return rc; | |
2701 | } | |
2702 | ||
2703 | /* | |
2704 | * return state of serial control and status signals | |
2705 | */ | |
2706 | static int tiocmget(struct tty_struct *tty, struct file *file) | |
2707 | { | |
2708 | struct slgt_info *info = tty->driver_data; | |
2709 | unsigned int result; | |
2710 | unsigned long flags; | |
2711 | ||
2712 | spin_lock_irqsave(&info->lock,flags); | |
2713 | get_signals(info); | |
2714 | spin_unlock_irqrestore(&info->lock,flags); | |
2715 | ||
2716 | result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + | |
2717 | ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + | |
2718 | ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + | |
2719 | ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + | |
2720 | ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + | |
2721 | ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); | |
2722 | ||
2723 | DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); | |
2724 | return result; | |
2725 | } | |
2726 | ||
2727 | /* | |
2728 | * set modem control signals (DTR/RTS) | |
2729 | * | |
2730 | * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit | |
2731 | * TIOCMSET = set/clear signal values | |
2732 | * value bit mask for command | |
2733 | */ | |
2734 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
2735 | unsigned int set, unsigned int clear) | |
2736 | { | |
2737 | struct slgt_info *info = tty->driver_data; | |
2738 | unsigned long flags; | |
2739 | ||
2740 | DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); | |
2741 | ||
2742 | if (set & TIOCM_RTS) | |
2743 | info->signals |= SerialSignal_RTS; | |
2744 | if (set & TIOCM_DTR) | |
2745 | info->signals |= SerialSignal_DTR; | |
2746 | if (clear & TIOCM_RTS) | |
2747 | info->signals &= ~SerialSignal_RTS; | |
2748 | if (clear & TIOCM_DTR) | |
2749 | info->signals &= ~SerialSignal_DTR; | |
2750 | ||
2751 | spin_lock_irqsave(&info->lock,flags); | |
2752 | set_signals(info); | |
2753 | spin_unlock_irqrestore(&info->lock,flags); | |
2754 | return 0; | |
2755 | } | |
2756 | ||
2757 | /* | |
2758 | * block current process until the device is ready to open | |
2759 | */ | |
2760 | static int block_til_ready(struct tty_struct *tty, struct file *filp, | |
2761 | struct slgt_info *info) | |
2762 | { | |
2763 | DECLARE_WAITQUEUE(wait, current); | |
2764 | int retval; | |
2765 | int do_clocal = 0, extra_count = 0; | |
2766 | unsigned long flags; | |
2767 | ||
2768 | DBGINFO(("%s block_til_ready\n", tty->driver->name)); | |
2769 | ||
2770 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ | |
2771 | /* nonblock mode is set or port is not enabled */ | |
2772 | info->flags |= ASYNC_NORMAL_ACTIVE; | |
2773 | return 0; | |
2774 | } | |
2775 | ||
2776 | if (tty->termios->c_cflag & CLOCAL) | |
2777 | do_clocal = 1; | |
2778 | ||
2779 | /* Wait for carrier detect and the line to become | |
2780 | * free (i.e., not in use by the callout). While we are in | |
2781 | * this loop, info->count is dropped by one, so that | |
2782 | * close() knows when to free things. We restore it upon | |
2783 | * exit, either normal or abnormal. | |
2784 | */ | |
2785 | ||
2786 | retval = 0; | |
2787 | add_wait_queue(&info->open_wait, &wait); | |
2788 | ||
2789 | spin_lock_irqsave(&info->lock, flags); | |
2790 | if (!tty_hung_up_p(filp)) { | |
2791 | extra_count = 1; | |
2792 | info->count--; | |
2793 | } | |
2794 | spin_unlock_irqrestore(&info->lock, flags); | |
2795 | info->blocked_open++; | |
2796 | ||
2797 | while (1) { | |
2798 | if ((tty->termios->c_cflag & CBAUD)) { | |
2799 | spin_lock_irqsave(&info->lock,flags); | |
2800 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
2801 | set_signals(info); | |
2802 | spin_unlock_irqrestore(&info->lock,flags); | |
2803 | } | |
2804 | ||
2805 | set_current_state(TASK_INTERRUPTIBLE); | |
2806 | ||
2807 | if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){ | |
2808 | retval = (info->flags & ASYNC_HUP_NOTIFY) ? | |
2809 | -EAGAIN : -ERESTARTSYS; | |
2810 | break; | |
2811 | } | |
2812 | ||
2813 | spin_lock_irqsave(&info->lock,flags); | |
2814 | get_signals(info); | |
2815 | spin_unlock_irqrestore(&info->lock,flags); | |
2816 | ||
2817 | if (!(info->flags & ASYNC_CLOSING) && | |
2818 | (do_clocal || (info->signals & SerialSignal_DCD)) ) { | |
2819 | break; | |
2820 | } | |
2821 | ||
2822 | if (signal_pending(current)) { | |
2823 | retval = -ERESTARTSYS; | |
2824 | break; | |
2825 | } | |
2826 | ||
2827 | DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); | |
2828 | schedule(); | |
2829 | } | |
2830 | ||
2831 | set_current_state(TASK_RUNNING); | |
2832 | remove_wait_queue(&info->open_wait, &wait); | |
2833 | ||
2834 | if (extra_count) | |
2835 | info->count++; | |
2836 | info->blocked_open--; | |
2837 | ||
2838 | if (!retval) | |
2839 | info->flags |= ASYNC_NORMAL_ACTIVE; | |
2840 | ||
2841 | DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); | |
2842 | return retval; | |
2843 | } | |
2844 | ||
2845 | static int alloc_tmp_rbuf(struct slgt_info *info) | |
2846 | { | |
2847 | info->tmp_rbuf = kmalloc(info->max_frame_size, GFP_KERNEL); | |
2848 | if (info->tmp_rbuf == NULL) | |
2849 | return -ENOMEM; | |
2850 | return 0; | |
2851 | } | |
2852 | ||
2853 | static void free_tmp_rbuf(struct slgt_info *info) | |
2854 | { | |
2855 | kfree(info->tmp_rbuf); | |
2856 | info->tmp_rbuf = NULL; | |
2857 | } | |
2858 | ||
2859 | /* | |
2860 | * allocate DMA descriptor lists. | |
2861 | */ | |
2862 | static int alloc_desc(struct slgt_info *info) | |
2863 | { | |
2864 | unsigned int i; | |
2865 | unsigned int pbufs; | |
2866 | ||
2867 | /* allocate memory to hold descriptor lists */ | |
2868 | info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr); | |
2869 | if (info->bufs == NULL) | |
2870 | return -ENOMEM; | |
2871 | ||
2872 | memset(info->bufs, 0, DESC_LIST_SIZE); | |
2873 | ||
2874 | info->rbufs = (struct slgt_desc*)info->bufs; | |
2875 | info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; | |
2876 | ||
2877 | pbufs = (unsigned int)info->bufs_dma_addr; | |
2878 | ||
2879 | /* | |
2880 | * Build circular lists of descriptors | |
2881 | */ | |
2882 | ||
2883 | for (i=0; i < info->rbuf_count; i++) { | |
2884 | /* physical address of this descriptor */ | |
2885 | info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); | |
2886 | ||
2887 | /* physical address of next descriptor */ | |
2888 | if (i == info->rbuf_count - 1) | |
2889 | info->rbufs[i].next = cpu_to_le32(pbufs); | |
2890 | else | |
2891 | info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); | |
2892 | set_desc_count(info->rbufs[i], DMABUFSIZE); | |
2893 | } | |
2894 | ||
2895 | for (i=0; i < info->tbuf_count; i++) { | |
2896 | /* physical address of this descriptor */ | |
2897 | info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); | |
2898 | ||
2899 | /* physical address of next descriptor */ | |
2900 | if (i == info->tbuf_count - 1) | |
2901 | info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); | |
2902 | else | |
2903 | info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); | |
2904 | } | |
2905 | ||
2906 | return 0; | |
2907 | } | |
2908 | ||
2909 | static void free_desc(struct slgt_info *info) | |
2910 | { | |
2911 | if (info->bufs != NULL) { | |
2912 | pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr); | |
2913 | info->bufs = NULL; | |
2914 | info->rbufs = NULL; | |
2915 | info->tbufs = NULL; | |
2916 | } | |
2917 | } | |
2918 | ||
2919 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
2920 | { | |
2921 | int i; | |
2922 | for (i=0; i < count; i++) { | |
2923 | if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL) | |
2924 | return -ENOMEM; | |
2925 | bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); | |
2926 | } | |
2927 | return 0; | |
2928 | } | |
2929 | ||
2930 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
2931 | { | |
2932 | int i; | |
2933 | for (i=0; i < count; i++) { | |
2934 | if (bufs[i].buf == NULL) | |
2935 | continue; | |
2936 | pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr); | |
2937 | bufs[i].buf = NULL; | |
2938 | } | |
2939 | } | |
2940 | ||
2941 | static int alloc_dma_bufs(struct slgt_info *info) | |
2942 | { | |
2943 | info->rbuf_count = 32; | |
2944 | info->tbuf_count = 32; | |
2945 | ||
2946 | if (alloc_desc(info) < 0 || | |
2947 | alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || | |
2948 | alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || | |
2949 | alloc_tmp_rbuf(info) < 0) { | |
2950 | DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); | |
2951 | return -ENOMEM; | |
2952 | } | |
2953 | reset_rbufs(info); | |
2954 | return 0; | |
2955 | } | |
2956 | ||
2957 | static void free_dma_bufs(struct slgt_info *info) | |
2958 | { | |
2959 | if (info->bufs) { | |
2960 | free_bufs(info, info->rbufs, info->rbuf_count); | |
2961 | free_bufs(info, info->tbufs, info->tbuf_count); | |
2962 | free_desc(info); | |
2963 | } | |
2964 | free_tmp_rbuf(info); | |
2965 | } | |
2966 | ||
2967 | static int claim_resources(struct slgt_info *info) | |
2968 | { | |
2969 | if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { | |
2970 | DBGERR(("%s reg addr conflict, addr=%08X\n", | |
2971 | info->device_name, info->phys_reg_addr)); | |
2972 | info->init_error = DiagStatus_AddressConflict; | |
2973 | goto errout; | |
2974 | } | |
2975 | else | |
2976 | info->reg_addr_requested = 1; | |
2977 | ||
0c8365ec | 2978 | info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE); |
705b6c7b PF |
2979 | if (!info->reg_addr) { |
2980 | DBGERR(("%s cant map device registers, addr=%08X\n", | |
2981 | info->device_name, info->phys_reg_addr)); | |
2982 | info->init_error = DiagStatus_CantAssignPciResources; | |
2983 | goto errout; | |
2984 | } | |
705b6c7b PF |
2985 | return 0; |
2986 | ||
2987 | errout: | |
2988 | release_resources(info); | |
2989 | return -ENODEV; | |
2990 | } | |
2991 | ||
2992 | static void release_resources(struct slgt_info *info) | |
2993 | { | |
2994 | if (info->irq_requested) { | |
2995 | free_irq(info->irq_level, info); | |
2996 | info->irq_requested = 0; | |
2997 | } | |
2998 | ||
2999 | if (info->reg_addr_requested) { | |
3000 | release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); | |
3001 | info->reg_addr_requested = 0; | |
3002 | } | |
3003 | ||
3004 | if (info->reg_addr) { | |
0c8365ec | 3005 | iounmap(info->reg_addr); |
705b6c7b PF |
3006 | info->reg_addr = NULL; |
3007 | } | |
3008 | } | |
3009 | ||
3010 | /* Add the specified device instance data structure to the | |
3011 | * global linked list of devices and increment the device count. | |
3012 | */ | |
3013 | static void add_device(struct slgt_info *info) | |
3014 | { | |
3015 | char *devstr; | |
3016 | ||
3017 | info->next_device = NULL; | |
3018 | info->line = slgt_device_count; | |
3019 | sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); | |
3020 | ||
3021 | if (info->line < MAX_DEVICES) { | |
3022 | if (maxframe[info->line]) | |
3023 | info->max_frame_size = maxframe[info->line]; | |
3024 | info->dosyncppp = dosyncppp[info->line]; | |
3025 | } | |
3026 | ||
3027 | slgt_device_count++; | |
3028 | ||
3029 | if (!slgt_device_list) | |
3030 | slgt_device_list = info; | |
3031 | else { | |
3032 | struct slgt_info *current_dev = slgt_device_list; | |
3033 | while(current_dev->next_device) | |
3034 | current_dev = current_dev->next_device; | |
3035 | current_dev->next_device = info; | |
3036 | } | |
3037 | ||
3038 | if (info->max_frame_size < 4096) | |
3039 | info->max_frame_size = 4096; | |
3040 | else if (info->max_frame_size > 65535) | |
3041 | info->max_frame_size = 65535; | |
3042 | ||
3043 | switch(info->pdev->device) { | |
3044 | case SYNCLINK_GT_DEVICE_ID: | |
3045 | devstr = "GT"; | |
3046 | break; | |
3047 | case SYNCLINK_GT4_DEVICE_ID: | |
3048 | devstr = "GT4"; | |
3049 | break; | |
3050 | case SYNCLINK_AC_DEVICE_ID: | |
3051 | devstr = "AC"; | |
3052 | info->params.mode = MGSL_MODE_ASYNC; | |
3053 | break; | |
3054 | default: | |
3055 | devstr = "(unknown model)"; | |
3056 | } | |
3057 | printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", | |
3058 | devstr, info->device_name, info->phys_reg_addr, | |
3059 | info->irq_level, info->max_frame_size); | |
3060 | ||
3061 | #ifdef CONFIG_HDLC | |
3062 | hdlcdev_init(info); | |
3063 | #endif | |
3064 | } | |
3065 | ||
3066 | /* | |
3067 | * allocate device instance structure, return NULL on failure | |
3068 | */ | |
3069 | static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) | |
3070 | { | |
3071 | struct slgt_info *info; | |
3072 | ||
3073 | info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL); | |
3074 | ||
3075 | if (!info) { | |
3076 | DBGERR(("%s device alloc failed adapter=%d port=%d\n", | |
3077 | driver_name, adapter_num, port_num)); | |
3078 | } else { | |
3079 | memset(info, 0, sizeof(struct slgt_info)); | |
3080 | info->magic = MGSL_MAGIC; | |
3081 | INIT_WORK(&info->task, bh_handler, info); | |
3082 | info->max_frame_size = 4096; | |
3083 | info->raw_rx_size = DMABUFSIZE; | |
3084 | info->close_delay = 5*HZ/10; | |
3085 | info->closing_wait = 30*HZ; | |
3086 | init_waitqueue_head(&info->open_wait); | |
3087 | init_waitqueue_head(&info->close_wait); | |
3088 | init_waitqueue_head(&info->status_event_wait_q); | |
3089 | init_waitqueue_head(&info->event_wait_q); | |
3090 | spin_lock_init(&info->netlock); | |
3091 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
3092 | info->idle_mode = HDLC_TXIDLE_FLAGS; | |
3093 | info->adapter_num = adapter_num; | |
3094 | info->port_num = port_num; | |
3095 | ||
3096 | init_timer(&info->tx_timer); | |
3097 | info->tx_timer.data = (unsigned long)info; | |
3098 | info->tx_timer.function = tx_timeout; | |
3099 | ||
3100 | init_timer(&info->rx_timer); | |
3101 | info->rx_timer.data = (unsigned long)info; | |
3102 | info->rx_timer.function = rx_timeout; | |
3103 | ||
3104 | /* Copy configuration info to device instance data */ | |
3105 | info->pdev = pdev; | |
3106 | info->irq_level = pdev->irq; | |
3107 | info->phys_reg_addr = pci_resource_start(pdev,0); | |
3108 | ||
705b6c7b PF |
3109 | info->bus_type = MGSL_BUS_TYPE_PCI; |
3110 | info->irq_flags = SA_SHIRQ; | |
3111 | ||
3112 | info->init_error = -1; /* assume error, set to 0 on successful init */ | |
3113 | } | |
3114 | ||
3115 | return info; | |
3116 | } | |
3117 | ||
3118 | static void device_init(int adapter_num, struct pci_dev *pdev) | |
3119 | { | |
3120 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
3121 | int i; | |
3122 | int port_count = 1; | |
3123 | ||
3124 | if (pdev->device == SYNCLINK_GT4_DEVICE_ID) | |
3125 | port_count = 4; | |
3126 | ||
3127 | /* allocate device instances for all ports */ | |
3128 | for (i=0; i < port_count; ++i) { | |
3129 | port_array[i] = alloc_dev(adapter_num, i, pdev); | |
3130 | if (port_array[i] == NULL) { | |
3131 | for (--i; i >= 0; --i) | |
3132 | kfree(port_array[i]); | |
3133 | return; | |
3134 | } | |
3135 | } | |
3136 | ||
3137 | /* give copy of port_array to all ports and add to device list */ | |
3138 | for (i=0; i < port_count; ++i) { | |
3139 | memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); | |
3140 | add_device(port_array[i]); | |
3141 | port_array[i]->port_count = port_count; | |
3142 | spin_lock_init(&port_array[i]->lock); | |
3143 | } | |
3144 | ||
3145 | /* Allocate and claim adapter resources */ | |
3146 | if (!claim_resources(port_array[0])) { | |
3147 | ||
3148 | alloc_dma_bufs(port_array[0]); | |
3149 | ||
3150 | /* copy resource information from first port to others */ | |
3151 | for (i = 1; i < port_count; ++i) { | |
3152 | port_array[i]->lock = port_array[0]->lock; | |
3153 | port_array[i]->irq_level = port_array[0]->irq_level; | |
3154 | port_array[i]->reg_addr = port_array[0]->reg_addr; | |
3155 | alloc_dma_bufs(port_array[i]); | |
3156 | } | |
3157 | ||
3158 | if (request_irq(port_array[0]->irq_level, | |
3159 | slgt_interrupt, | |
3160 | port_array[0]->irq_flags, | |
3161 | port_array[0]->device_name, | |
3162 | port_array[0]) < 0) { | |
3163 | DBGERR(("%s request_irq failed IRQ=%d\n", | |
3164 | port_array[0]->device_name, | |
3165 | port_array[0]->irq_level)); | |
3166 | } else { | |
3167 | port_array[0]->irq_requested = 1; | |
3168 | adapter_test(port_array[0]); | |
3169 | for (i=1 ; i < port_count ; i++) | |
3170 | port_array[i]->init_error = port_array[0]->init_error; | |
3171 | } | |
3172 | } | |
3173 | } | |
3174 | ||
3175 | static int __devinit init_one(struct pci_dev *dev, | |
3176 | const struct pci_device_id *ent) | |
3177 | { | |
3178 | if (pci_enable_device(dev)) { | |
3179 | printk("error enabling pci device %p\n", dev); | |
3180 | return -EIO; | |
3181 | } | |
3182 | pci_set_master(dev); | |
3183 | device_init(slgt_device_count, dev); | |
3184 | return 0; | |
3185 | } | |
3186 | ||
3187 | static void __devexit remove_one(struct pci_dev *dev) | |
3188 | { | |
3189 | } | |
3190 | ||
3191 | static struct tty_operations ops = { | |
3192 | .open = open, | |
3193 | .close = close, | |
3194 | .write = write, | |
3195 | .put_char = put_char, | |
3196 | .flush_chars = flush_chars, | |
3197 | .write_room = write_room, | |
3198 | .chars_in_buffer = chars_in_buffer, | |
3199 | .flush_buffer = flush_buffer, | |
3200 | .ioctl = ioctl, | |
3201 | .throttle = throttle, | |
3202 | .unthrottle = unthrottle, | |
3203 | .send_xchar = send_xchar, | |
3204 | .break_ctl = set_break, | |
3205 | .wait_until_sent = wait_until_sent, | |
3206 | .read_proc = read_proc, | |
3207 | .set_termios = set_termios, | |
3208 | .stop = tx_hold, | |
3209 | .start = tx_release, | |
3210 | .hangup = hangup, | |
3211 | .tiocmget = tiocmget, | |
3212 | .tiocmset = tiocmset, | |
3213 | }; | |
3214 | ||
3215 | static void slgt_cleanup(void) | |
3216 | { | |
3217 | int rc; | |
3218 | struct slgt_info *info; | |
3219 | struct slgt_info *tmp; | |
3220 | ||
3221 | printk("unload %s %s\n", driver_name, driver_version); | |
3222 | ||
3223 | if (serial_driver) { | |
3224 | if ((rc = tty_unregister_driver(serial_driver))) | |
3225 | DBGERR(("tty_unregister_driver error=%d\n", rc)); | |
3226 | put_tty_driver(serial_driver); | |
3227 | } | |
3228 | ||
3229 | /* reset devices */ | |
3230 | info = slgt_device_list; | |
3231 | while(info) { | |
3232 | reset_port(info); | |
3233 | info = info->next_device; | |
3234 | } | |
3235 | ||
3236 | /* release devices */ | |
3237 | info = slgt_device_list; | |
3238 | while(info) { | |
3239 | #ifdef CONFIG_HDLC | |
3240 | hdlcdev_exit(info); | |
3241 | #endif | |
3242 | free_dma_bufs(info); | |
3243 | free_tmp_rbuf(info); | |
3244 | if (info->port_num == 0) | |
3245 | release_resources(info); | |
3246 | tmp = info; | |
3247 | info = info->next_device; | |
3248 | kfree(tmp); | |
3249 | } | |
3250 | ||
3251 | if (pci_registered) | |
3252 | pci_unregister_driver(&pci_driver); | |
3253 | } | |
3254 | ||
3255 | /* | |
3256 | * Driver initialization entry point. | |
3257 | */ | |
3258 | static int __init slgt_init(void) | |
3259 | { | |
3260 | int rc; | |
3261 | ||
3262 | printk("%s %s\n", driver_name, driver_version); | |
3263 | ||
3264 | slgt_device_count = 0; | |
3265 | if ((rc = pci_register_driver(&pci_driver)) < 0) { | |
3266 | printk("%s pci_register_driver error=%d\n", driver_name, rc); | |
3267 | return rc; | |
3268 | } | |
3269 | pci_registered = 1; | |
3270 | ||
3271 | if (!slgt_device_list) { | |
3272 | printk("%s no devices found\n",driver_name); | |
3273 | return -ENODEV; | |
3274 | } | |
3275 | ||
3276 | serial_driver = alloc_tty_driver(MAX_DEVICES); | |
3277 | if (!serial_driver) { | |
3278 | rc = -ENOMEM; | |
3279 | goto error; | |
3280 | } | |
3281 | ||
3282 | /* Initialize the tty_driver structure */ | |
3283 | ||
3284 | serial_driver->owner = THIS_MODULE; | |
3285 | serial_driver->driver_name = tty_driver_name; | |
3286 | serial_driver->name = tty_dev_prefix; | |
3287 | serial_driver->major = ttymajor; | |
3288 | serial_driver->minor_start = 64; | |
3289 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
3290 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
3291 | serial_driver->init_termios = tty_std_termios; | |
3292 | serial_driver->init_termios.c_cflag = | |
3293 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
3294 | serial_driver->flags = TTY_DRIVER_REAL_RAW; | |
3295 | tty_set_operations(serial_driver, &ops); | |
3296 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
3297 | DBGERR(("%s can't register serial driver\n", driver_name)); | |
3298 | put_tty_driver(serial_driver); | |
3299 | serial_driver = NULL; | |
3300 | goto error; | |
3301 | } | |
3302 | ||
3303 | printk("%s %s, tty major#%d\n", | |
3304 | driver_name, driver_version, | |
3305 | serial_driver->major); | |
3306 | ||
3307 | return 0; | |
3308 | ||
3309 | error: | |
3310 | slgt_cleanup(); | |
3311 | return rc; | |
3312 | } | |
3313 | ||
3314 | static void __exit slgt_exit(void) | |
3315 | { | |
3316 | slgt_cleanup(); | |
3317 | } | |
3318 | ||
3319 | module_init(slgt_init); | |
3320 | module_exit(slgt_exit); | |
3321 | ||
3322 | /* | |
3323 | * register access routines | |
3324 | */ | |
3325 | ||
3326 | #define CALC_REGADDR() \ | |
3327 | unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ | |
3328 | if (addr >= 0x80) \ | |
3329 | reg_addr += (info->port_num) * 32; | |
3330 | ||
3331 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) | |
3332 | { | |
3333 | CALC_REGADDR(); | |
3334 | return readb((void __iomem *)reg_addr); | |
3335 | } | |
3336 | ||
3337 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) | |
3338 | { | |
3339 | CALC_REGADDR(); | |
3340 | writeb(value, (void __iomem *)reg_addr); | |
3341 | } | |
3342 | ||
3343 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) | |
3344 | { | |
3345 | CALC_REGADDR(); | |
3346 | return readw((void __iomem *)reg_addr); | |
3347 | } | |
3348 | ||
3349 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) | |
3350 | { | |
3351 | CALC_REGADDR(); | |
3352 | writew(value, (void __iomem *)reg_addr); | |
3353 | } | |
3354 | ||
3355 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) | |
3356 | { | |
3357 | CALC_REGADDR(); | |
3358 | return readl((void __iomem *)reg_addr); | |
3359 | } | |
3360 | ||
3361 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) | |
3362 | { | |
3363 | CALC_REGADDR(); | |
3364 | writel(value, (void __iomem *)reg_addr); | |
3365 | } | |
3366 | ||
3367 | static void rdma_reset(struct slgt_info *info) | |
3368 | { | |
3369 | unsigned int i; | |
3370 | ||
3371 | /* set reset bit */ | |
3372 | wr_reg32(info, RDCSR, BIT1); | |
3373 | ||
3374 | /* wait for enable bit cleared */ | |
3375 | for(i=0 ; i < 1000 ; i++) | |
3376 | if (!(rd_reg32(info, RDCSR) & BIT0)) | |
3377 | break; | |
3378 | } | |
3379 | ||
3380 | static void tdma_reset(struct slgt_info *info) | |
3381 | { | |
3382 | unsigned int i; | |
3383 | ||
3384 | /* set reset bit */ | |
3385 | wr_reg32(info, TDCSR, BIT1); | |
3386 | ||
3387 | /* wait for enable bit cleared */ | |
3388 | for(i=0 ; i < 1000 ; i++) | |
3389 | if (!(rd_reg32(info, TDCSR) & BIT0)) | |
3390 | break; | |
3391 | } | |
3392 | ||
3393 | /* | |
3394 | * enable internal loopback | |
3395 | * TxCLK and RxCLK are generated from BRG | |
3396 | * and TxD is looped back to RxD internally. | |
3397 | */ | |
3398 | static void enable_loopback(struct slgt_info *info) | |
3399 | { | |
3400 | /* SCR (serial control) BIT2=looopback enable */ | |
3401 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); | |
3402 | ||
3403 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3404 | /* CCR (clock control) | |
3405 | * 07..05 tx clock source (010 = BRG) | |
3406 | * 04..02 rx clock source (010 = BRG) | |
3407 | * 01 auxclk enable (0 = disable) | |
3408 | * 00 BRG enable (1 = enable) | |
3409 | * | |
3410 | * 0100 1001 | |
3411 | */ | |
3412 | wr_reg8(info, CCR, 0x49); | |
3413 | ||
3414 | /* set speed if available, otherwise use default */ | |
3415 | if (info->params.clock_speed) | |
3416 | set_rate(info, info->params.clock_speed); | |
3417 | else | |
3418 | set_rate(info, 3686400); | |
3419 | } | |
3420 | } | |
3421 | ||
3422 | /* | |
3423 | * set baud rate generator to specified rate | |
3424 | */ | |
3425 | static void set_rate(struct slgt_info *info, u32 rate) | |
3426 | { | |
3427 | unsigned int div; | |
3428 | static unsigned int osc = 14745600; | |
3429 | ||
3430 | /* div = osc/rate - 1 | |
3431 | * | |
3432 | * Round div up if osc/rate is not integer to | |
3433 | * force to next slowest rate. | |
3434 | */ | |
3435 | ||
3436 | if (rate) { | |
3437 | div = osc/rate; | |
3438 | if (!(osc % rate) && div) | |
3439 | div--; | |
3440 | wr_reg16(info, BDR, (unsigned short)div); | |
3441 | } | |
3442 | } | |
3443 | ||
3444 | static void rx_stop(struct slgt_info *info) | |
3445 | { | |
3446 | unsigned short val; | |
3447 | ||
3448 | /* disable and reset receiver */ | |
3449 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3450 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3451 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3452 | ||
3453 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); | |
3454 | ||
3455 | /* clear pending rx interrupts */ | |
3456 | wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); | |
3457 | ||
3458 | rdma_reset(info); | |
3459 | ||
3460 | info->rx_enabled = 0; | |
3461 | info->rx_restart = 0; | |
3462 | } | |
3463 | ||
3464 | static void rx_start(struct slgt_info *info) | |
3465 | { | |
3466 | unsigned short val; | |
3467 | ||
3468 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); | |
3469 | ||
3470 | /* clear pending rx overrun IRQ */ | |
3471 | wr_reg16(info, SSR, IRQ_RXOVER); | |
3472 | ||
3473 | /* reset and disable receiver */ | |
3474 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3475 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3476 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3477 | ||
3478 | rdma_reset(info); | |
3479 | reset_rbufs(info); | |
3480 | ||
3481 | /* set 1st descriptor address */ | |
3482 | wr_reg32(info, RDDAR, info->rbufs[0].pdesc); | |
3483 | ||
3484 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3485 | /* enable rx DMA and DMA interrupt */ | |
3486 | wr_reg32(info, RDCSR, (BIT2 + BIT0)); | |
3487 | } else { | |
3488 | /* enable saving of rx status, rx DMA and DMA interrupt */ | |
3489 | wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); | |
3490 | } | |
3491 | ||
3492 | slgt_irq_on(info, IRQ_RXOVER); | |
3493 | ||
3494 | /* enable receiver */ | |
3495 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); | |
3496 | ||
3497 | info->rx_restart = 0; | |
3498 | info->rx_enabled = 1; | |
3499 | } | |
3500 | ||
3501 | static void tx_start(struct slgt_info *info) | |
3502 | { | |
3503 | if (!info->tx_enabled) { | |
3504 | wr_reg16(info, TCR, | |
3505 | (unsigned short)(rd_reg16(info, TCR) | BIT1)); | |
3506 | info->tx_enabled = TRUE; | |
3507 | } | |
3508 | ||
3509 | if (info->tx_count) { | |
3510 | info->drop_rts_on_tx_done = 0; | |
3511 | ||
3512 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3513 | if (info->params.flags & HDLC_FLAG_AUTO_RTS) { | |
3514 | get_signals(info); | |
3515 | if (!(info->signals & SerialSignal_RTS)) { | |
3516 | info->signals |= SerialSignal_RTS; | |
3517 | set_signals(info); | |
3518 | info->drop_rts_on_tx_done = 1; | |
3519 | } | |
3520 | } | |
3521 | ||
3522 | slgt_irq_off(info, IRQ_TXDATA); | |
3523 | slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); | |
3524 | /* clear tx idle and underrun status bits */ | |
3525 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
3526 | ||
3527 | if (!(rd_reg32(info, TDCSR) & BIT0)) { | |
3528 | /* tx DMA stopped, restart tx DMA */ | |
3529 | tdma_reset(info); | |
3530 | /* set 1st descriptor address */ | |
3531 | wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); | |
3532 | if (info->params.mode == MGSL_MODE_RAW) | |
3533 | wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */ | |
3534 | else | |
3535 | wr_reg32(info, TDCSR, BIT0); /* DMA enable */ | |
3536 | } | |
3537 | ||
3538 | if (info->params.mode != MGSL_MODE_RAW) { | |
3539 | info->tx_timer.expires = jiffies + msecs_to_jiffies(5000); | |
3540 | add_timer(&info->tx_timer); | |
3541 | } | |
3542 | } else { | |
3543 | tdma_reset(info); | |
3544 | /* set 1st descriptor address */ | |
3545 | wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); | |
3546 | ||
3547 | slgt_irq_off(info, IRQ_TXDATA); | |
3548 | slgt_irq_on(info, IRQ_TXIDLE); | |
3549 | /* clear tx idle status bit */ | |
3550 | wr_reg16(info, SSR, IRQ_TXIDLE); | |
3551 | ||
3552 | /* enable tx DMA */ | |
3553 | wr_reg32(info, TDCSR, BIT0); | |
3554 | } | |
3555 | ||
3556 | info->tx_active = 1; | |
3557 | } | |
3558 | } | |
3559 | ||
3560 | static void tx_stop(struct slgt_info *info) | |
3561 | { | |
3562 | unsigned short val; | |
3563 | ||
3564 | del_timer(&info->tx_timer); | |
3565 | ||
3566 | tdma_reset(info); | |
3567 | ||
3568 | /* reset and disable transmitter */ | |
3569 | val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ | |
3570 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3571 | wr_reg16(info, TCR, val); /* clear reset */ | |
3572 | ||
3573 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
3574 | ||
3575 | /* clear tx idle and underrun status bit */ | |
3576 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
3577 | ||
3578 | reset_tbufs(info); | |
3579 | ||
3580 | info->tx_enabled = 0; | |
3581 | info->tx_active = 0; | |
3582 | } | |
3583 | ||
3584 | static void reset_port(struct slgt_info *info) | |
3585 | { | |
3586 | if (!info->reg_addr) | |
3587 | return; | |
3588 | ||
3589 | tx_stop(info); | |
3590 | rx_stop(info); | |
3591 | ||
3592 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
3593 | set_signals(info); | |
3594 | ||
3595 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
3596 | } | |
3597 | ||
3598 | static void reset_adapter(struct slgt_info *info) | |
3599 | { | |
3600 | int i; | |
3601 | for (i=0; i < info->port_count; ++i) { | |
3602 | if (info->port_array[i]) | |
3603 | reset_port(info->port_array[i]); | |
3604 | } | |
3605 | } | |
3606 | ||
3607 | static void async_mode(struct slgt_info *info) | |
3608 | { | |
3609 | unsigned short val; | |
3610 | ||
3611 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
3612 | tx_stop(info); | |
3613 | rx_stop(info); | |
3614 | ||
3615 | /* TCR (tx control) | |
3616 | * | |
3617 | * 15..13 mode, 010=async | |
3618 | * 12..10 encoding, 000=NRZ | |
3619 | * 09 parity enable | |
3620 | * 08 1=odd parity, 0=even parity | |
3621 | * 07 1=RTS driver control | |
3622 | * 06 1=break enable | |
3623 | * 05..04 character length | |
3624 | * 00=5 bits | |
3625 | * 01=6 bits | |
3626 | * 10=7 bits | |
3627 | * 11=8 bits | |
3628 | * 03 0=1 stop bit, 1=2 stop bits | |
3629 | * 02 reset | |
3630 | * 01 enable | |
3631 | * 00 auto-CTS enable | |
3632 | */ | |
3633 | val = 0x4000; | |
3634 | ||
3635 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
3636 | val |= BIT7; | |
3637 | ||
3638 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
3639 | val |= BIT9; | |
3640 | if (info->params.parity == ASYNC_PARITY_ODD) | |
3641 | val |= BIT8; | |
3642 | } | |
3643 | ||
3644 | switch (info->params.data_bits) | |
3645 | { | |
3646 | case 6: val |= BIT4; break; | |
3647 | case 7: val |= BIT5; break; | |
3648 | case 8: val |= BIT5 + BIT4; break; | |
3649 | } | |
3650 | ||
3651 | if (info->params.stop_bits != 1) | |
3652 | val |= BIT3; | |
3653 | ||
3654 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
3655 | val |= BIT0; | |
3656 | ||
3657 | wr_reg16(info, TCR, val); | |
3658 | ||
3659 | /* RCR (rx control) | |
3660 | * | |
3661 | * 15..13 mode, 010=async | |
3662 | * 12..10 encoding, 000=NRZ | |
3663 | * 09 parity enable | |
3664 | * 08 1=odd parity, 0=even parity | |
3665 | * 07..06 reserved, must be 0 | |
3666 | * 05..04 character length | |
3667 | * 00=5 bits | |
3668 | * 01=6 bits | |
3669 | * 10=7 bits | |
3670 | * 11=8 bits | |
3671 | * 03 reserved, must be zero | |
3672 | * 02 reset | |
3673 | * 01 enable | |
3674 | * 00 auto-DCD enable | |
3675 | */ | |
3676 | val = 0x4000; | |
3677 | ||
3678 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
3679 | val |= BIT9; | |
3680 | if (info->params.parity == ASYNC_PARITY_ODD) | |
3681 | val |= BIT8; | |
3682 | } | |
3683 | ||
3684 | switch (info->params.data_bits) | |
3685 | { | |
3686 | case 6: val |= BIT4; break; | |
3687 | case 7: val |= BIT5; break; | |
3688 | case 8: val |= BIT5 + BIT4; break; | |
3689 | } | |
3690 | ||
3691 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
3692 | val |= BIT0; | |
3693 | ||
3694 | wr_reg16(info, RCR, val); | |
3695 | ||
3696 | /* CCR (clock control) | |
3697 | * | |
3698 | * 07..05 011 = tx clock source is BRG/16 | |
3699 | * 04..02 010 = rx clock source is BRG | |
3700 | * 01 0 = auxclk disabled | |
3701 | * 00 1 = BRG enabled | |
3702 | * | |
3703 | * 0110 1001 | |
3704 | */ | |
3705 | wr_reg8(info, CCR, 0x69); | |
3706 | ||
3707 | msc_set_vcr(info); | |
3708 | ||
3709 | tx_set_idle(info); | |
3710 | ||
3711 | /* SCR (serial control) | |
3712 | * | |
3713 | * 15 1=tx req on FIFO half empty | |
3714 | * 14 1=rx req on FIFO half full | |
3715 | * 13 tx data IRQ enable | |
3716 | * 12 tx idle IRQ enable | |
3717 | * 11 rx break on IRQ enable | |
3718 | * 10 rx data IRQ enable | |
3719 | * 09 rx break off IRQ enable | |
3720 | * 08 overrun IRQ enable | |
3721 | * 07 DSR IRQ enable | |
3722 | * 06 CTS IRQ enable | |
3723 | * 05 DCD IRQ enable | |
3724 | * 04 RI IRQ enable | |
3725 | * 03 reserved, must be zero | |
3726 | * 02 1=txd->rxd internal loopback enable | |
3727 | * 01 reserved, must be zero | |
3728 | * 00 1=master IRQ enable | |
3729 | */ | |
3730 | val = BIT15 + BIT14 + BIT0; | |
3731 | wr_reg16(info, SCR, val); | |
3732 | ||
3733 | slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); | |
3734 | ||
3735 | set_rate(info, info->params.data_rate * 16); | |
3736 | ||
3737 | if (info->params.loopback) | |
3738 | enable_loopback(info); | |
3739 | } | |
3740 | ||
3741 | static void hdlc_mode(struct slgt_info *info) | |
3742 | { | |
3743 | unsigned short val; | |
3744 | ||
3745 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
3746 | tx_stop(info); | |
3747 | rx_stop(info); | |
3748 | ||
3749 | /* TCR (tx control) | |
3750 | * | |
3751 | * 15..13 mode, 000=HDLC 001=raw sync | |
3752 | * 12..10 encoding | |
3753 | * 09 CRC enable | |
3754 | * 08 CRC32 | |
3755 | * 07 1=RTS driver control | |
3756 | * 06 preamble enable | |
3757 | * 05..04 preamble length | |
3758 | * 03 share open/close flag | |
3759 | * 02 reset | |
3760 | * 01 enable | |
3761 | * 00 auto-CTS enable | |
3762 | */ | |
3763 | val = 0; | |
3764 | ||
3765 | if (info->params.mode == MGSL_MODE_RAW) | |
3766 | val |= BIT13; | |
3767 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
3768 | val |= BIT7; | |
3769 | ||
3770 | switch(info->params.encoding) | |
3771 | { | |
3772 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
3773 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
3774 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
3775 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
3776 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
3777 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
3778 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
3779 | } | |
3780 | ||
3781 | switch (info->params.crc_type) | |
3782 | { | |
3783 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
3784 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
3785 | } | |
3786 | ||
3787 | if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) | |
3788 | val |= BIT6; | |
3789 | ||
3790 | switch (info->params.preamble_length) | |
3791 | { | |
3792 | case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; | |
3793 | case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; | |
3794 | case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; | |
3795 | } | |
3796 | ||
3797 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
3798 | val |= BIT0; | |
3799 | ||
3800 | wr_reg16(info, TCR, val); | |
3801 | ||
3802 | /* TPR (transmit preamble) */ | |
3803 | ||
3804 | switch (info->params.preamble) | |
3805 | { | |
3806 | case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; | |
3807 | case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; | |
3808 | case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; | |
3809 | case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; | |
3810 | case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; | |
3811 | default: val = 0x7e; break; | |
3812 | } | |
3813 | wr_reg8(info, TPR, (unsigned char)val); | |
3814 | ||
3815 | /* RCR (rx control) | |
3816 | * | |
3817 | * 15..13 mode, 000=HDLC 001=raw sync | |
3818 | * 12..10 encoding | |
3819 | * 09 CRC enable | |
3820 | * 08 CRC32 | |
3821 | * 07..03 reserved, must be 0 | |
3822 | * 02 reset | |
3823 | * 01 enable | |
3824 | * 00 auto-DCD enable | |
3825 | */ | |
3826 | val = 0; | |
3827 | ||
3828 | if (info->params.mode == MGSL_MODE_RAW) | |
3829 | val |= BIT13; | |
3830 | ||
3831 | switch(info->params.encoding) | |
3832 | { | |
3833 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
3834 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
3835 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
3836 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
3837 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
3838 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
3839 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
3840 | } | |
3841 | ||
3842 | switch (info->params.crc_type) | |
3843 | { | |
3844 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
3845 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
3846 | } | |
3847 | ||
3848 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
3849 | val |= BIT0; | |
3850 | ||
3851 | wr_reg16(info, RCR, val); | |
3852 | ||
3853 | /* CCR (clock control) | |
3854 | * | |
3855 | * 07..05 tx clock source | |
3856 | * 04..02 rx clock source | |
3857 | * 01 auxclk enable | |
3858 | * 00 BRG enable | |
3859 | */ | |
3860 | val = 0; | |
3861 | ||
3862 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
3863 | { | |
3864 | // when RxC source is DPLL, BRG generates 16X DPLL | |
3865 | // reference clock, so take TxC from BRG/16 to get | |
3866 | // transmit clock at actual data rate | |
3867 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
3868 | val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ | |
3869 | else | |
3870 | val |= BIT6; /* 010, txclk = BRG */ | |
3871 | } | |
3872 | else if (info->params.flags & HDLC_FLAG_TXC_DPLL) | |
3873 | val |= BIT7; /* 100, txclk = DPLL Input */ | |
3874 | else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) | |
3875 | val |= BIT5; /* 001, txclk = RXC Input */ | |
3876 | ||
3877 | if (info->params.flags & HDLC_FLAG_RXC_BRG) | |
3878 | val |= BIT3; /* 010, rxclk = BRG */ | |
3879 | else if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
3880 | val |= BIT4; /* 100, rxclk = DPLL */ | |
3881 | else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) | |
3882 | val |= BIT2; /* 001, rxclk = TXC Input */ | |
3883 | ||
3884 | if (info->params.clock_speed) | |
3885 | val |= BIT1 + BIT0; | |
3886 | ||
3887 | wr_reg8(info, CCR, (unsigned char)val); | |
3888 | ||
3889 | if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) | |
3890 | { | |
3891 | // program DPLL mode | |
3892 | switch(info->params.encoding) | |
3893 | { | |
3894 | case HDLC_ENCODING_BIPHASE_MARK: | |
3895 | case HDLC_ENCODING_BIPHASE_SPACE: | |
3896 | val = BIT7; break; | |
3897 | case HDLC_ENCODING_BIPHASE_LEVEL: | |
3898 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: | |
3899 | val = BIT7 + BIT6; break; | |
3900 | default: val = BIT6; // NRZ encodings | |
3901 | } | |
3902 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); | |
3903 | ||
3904 | // DPLL requires a 16X reference clock from BRG | |
3905 | set_rate(info, info->params.clock_speed * 16); | |
3906 | } | |
3907 | else | |
3908 | set_rate(info, info->params.clock_speed); | |
3909 | ||
3910 | tx_set_idle(info); | |
3911 | ||
3912 | msc_set_vcr(info); | |
3913 | ||
3914 | /* SCR (serial control) | |
3915 | * | |
3916 | * 15 1=tx req on FIFO half empty | |
3917 | * 14 1=rx req on FIFO half full | |
3918 | * 13 tx data IRQ enable | |
3919 | * 12 tx idle IRQ enable | |
3920 | * 11 underrun IRQ enable | |
3921 | * 10 rx data IRQ enable | |
3922 | * 09 rx idle IRQ enable | |
3923 | * 08 overrun IRQ enable | |
3924 | * 07 DSR IRQ enable | |
3925 | * 06 CTS IRQ enable | |
3926 | * 05 DCD IRQ enable | |
3927 | * 04 RI IRQ enable | |
3928 | * 03 reserved, must be zero | |
3929 | * 02 1=txd->rxd internal loopback enable | |
3930 | * 01 reserved, must be zero | |
3931 | * 00 1=master IRQ enable | |
3932 | */ | |
3933 | wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); | |
3934 | ||
3935 | if (info->params.loopback) | |
3936 | enable_loopback(info); | |
3937 | } | |
3938 | ||
3939 | /* | |
3940 | * set transmit idle mode | |
3941 | */ | |
3942 | static void tx_set_idle(struct slgt_info *info) | |
3943 | { | |
3944 | unsigned char val = 0xff; | |
3945 | ||
3946 | switch(info->idle_mode) | |
3947 | { | |
3948 | case HDLC_TXIDLE_FLAGS: val = 0x7e; break; | |
3949 | case HDLC_TXIDLE_ALT_ZEROS_ONES: val = 0xaa; break; | |
3950 | case HDLC_TXIDLE_ZEROS: val = 0x00; break; | |
3951 | case HDLC_TXIDLE_ONES: val = 0xff; break; | |
3952 | case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; | |
3953 | case HDLC_TXIDLE_SPACE: val = 0x00; break; | |
3954 | case HDLC_TXIDLE_MARK: val = 0xff; break; | |
3955 | } | |
3956 | ||
3957 | wr_reg8(info, TIR, val); | |
3958 | } | |
3959 | ||
3960 | /* | |
3961 | * get state of V24 status (input) signals | |
3962 | */ | |
3963 | static void get_signals(struct slgt_info *info) | |
3964 | { | |
3965 | unsigned short status = rd_reg16(info, SSR); | |
3966 | ||
3967 | /* clear all serial signals except DTR and RTS */ | |
3968 | info->signals &= SerialSignal_DTR + SerialSignal_RTS; | |
3969 | ||
3970 | if (status & BIT3) | |
3971 | info->signals |= SerialSignal_DSR; | |
3972 | if (status & BIT2) | |
3973 | info->signals |= SerialSignal_CTS; | |
3974 | if (status & BIT1) | |
3975 | info->signals |= SerialSignal_DCD; | |
3976 | if (status & BIT0) | |
3977 | info->signals |= SerialSignal_RI; | |
3978 | } | |
3979 | ||
3980 | /* | |
3981 | * set V.24 Control Register based on current configuration | |
3982 | */ | |
3983 | static void msc_set_vcr(struct slgt_info *info) | |
3984 | { | |
3985 | unsigned char val = 0; | |
3986 | ||
3987 | /* VCR (V.24 control) | |
3988 | * | |
3989 | * 07..04 serial IF select | |
3990 | * 03 DTR | |
3991 | * 02 RTS | |
3992 | * 01 LL | |
3993 | * 00 RL | |
3994 | */ | |
3995 | ||
3996 | switch(info->if_mode & MGSL_INTERFACE_MASK) | |
3997 | { | |
3998 | case MGSL_INTERFACE_RS232: | |
3999 | val |= BIT5; /* 0010 */ | |
4000 | break; | |
4001 | case MGSL_INTERFACE_V35: | |
4002 | val |= BIT7 + BIT6 + BIT5; /* 1110 */ | |
4003 | break; | |
4004 | case MGSL_INTERFACE_RS422: | |
4005 | val |= BIT6; /* 0100 */ | |
4006 | break; | |
4007 | } | |
4008 | ||
4009 | if (info->signals & SerialSignal_DTR) | |
4010 | val |= BIT3; | |
4011 | if (info->signals & SerialSignal_RTS) | |
4012 | val |= BIT2; | |
4013 | if (info->if_mode & MGSL_INTERFACE_LL) | |
4014 | val |= BIT1; | |
4015 | if (info->if_mode & MGSL_INTERFACE_RL) | |
4016 | val |= BIT0; | |
4017 | wr_reg8(info, VCR, val); | |
4018 | } | |
4019 | ||
4020 | /* | |
4021 | * set state of V24 control (output) signals | |
4022 | */ | |
4023 | static void set_signals(struct slgt_info *info) | |
4024 | { | |
4025 | unsigned char val = rd_reg8(info, VCR); | |
4026 | if (info->signals & SerialSignal_DTR) | |
4027 | val |= BIT3; | |
4028 | else | |
4029 | val &= ~BIT3; | |
4030 | if (info->signals & SerialSignal_RTS) | |
4031 | val |= BIT2; | |
4032 | else | |
4033 | val &= ~BIT2; | |
4034 | wr_reg8(info, VCR, val); | |
4035 | } | |
4036 | ||
4037 | /* | |
4038 | * free range of receive DMA buffers (i to last) | |
4039 | */ | |
4040 | static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) | |
4041 | { | |
4042 | int done = 0; | |
4043 | ||
4044 | while(!done) { | |
4045 | /* reset current buffer for reuse */ | |
4046 | info->rbufs[i].status = 0; | |
4047 | if (info->params.mode == MGSL_MODE_RAW) | |
4048 | set_desc_count(info->rbufs[i], info->raw_rx_size); | |
4049 | else | |
4050 | set_desc_count(info->rbufs[i], DMABUFSIZE); | |
4051 | ||
4052 | if (i == last) | |
4053 | done = 1; | |
4054 | if (++i == info->rbuf_count) | |
4055 | i = 0; | |
4056 | } | |
4057 | info->rbuf_current = i; | |
4058 | } | |
4059 | ||
4060 | /* | |
4061 | * mark all receive DMA buffers as free | |
4062 | */ | |
4063 | static void reset_rbufs(struct slgt_info *info) | |
4064 | { | |
4065 | free_rbufs(info, 0, info->rbuf_count - 1); | |
4066 | } | |
4067 | ||
4068 | /* | |
4069 | * pass receive HDLC frame to upper layer | |
4070 | * | |
4071 | * return 1 if frame available, otherwise 0 | |
4072 | */ | |
4073 | static int rx_get_frame(struct slgt_info *info) | |
4074 | { | |
4075 | unsigned int start, end; | |
4076 | unsigned short status; | |
4077 | unsigned int framesize = 0; | |
4078 | int rc = 0; | |
4079 | unsigned long flags; | |
4080 | struct tty_struct *tty = info->tty; | |
4081 | unsigned char addr_field = 0xff; | |
4082 | ||
4083 | check_again: | |
4084 | ||
4085 | framesize = 0; | |
4086 | addr_field = 0xff; | |
4087 | start = end = info->rbuf_current; | |
4088 | ||
4089 | for (;;) { | |
4090 | if (!desc_complete(info->rbufs[end])) | |
4091 | goto cleanup; | |
4092 | ||
4093 | if (framesize == 0 && info->params.addr_filter != 0xff) | |
4094 | addr_field = info->rbufs[end].buf[0]; | |
4095 | ||
4096 | framesize += desc_count(info->rbufs[end]); | |
4097 | ||
4098 | if (desc_eof(info->rbufs[end])) | |
4099 | break; | |
4100 | ||
4101 | if (++end == info->rbuf_count) | |
4102 | end = 0; | |
4103 | ||
4104 | if (end == info->rbuf_current) { | |
4105 | if (info->rx_enabled){ | |
4106 | spin_lock_irqsave(&info->lock,flags); | |
4107 | rx_start(info); | |
4108 | spin_unlock_irqrestore(&info->lock,flags); | |
4109 | } | |
4110 | goto cleanup; | |
4111 | } | |
4112 | } | |
4113 | ||
4114 | /* status | |
4115 | * | |
4116 | * 15 buffer complete | |
4117 | * 14..06 reserved | |
4118 | * 05..04 residue | |
4119 | * 02 eof (end of frame) | |
4120 | * 01 CRC error | |
4121 | * 00 abort | |
4122 | */ | |
4123 | status = desc_status(info->rbufs[end]); | |
4124 | ||
4125 | /* ignore CRC bit if not using CRC (bit is undefined) */ | |
4126 | if (info->params.crc_type == HDLC_CRC_NONE) | |
4127 | status &= ~BIT1; | |
4128 | ||
4129 | if (framesize == 0 || | |
4130 | (addr_field != 0xff && addr_field != info->params.addr_filter)) { | |
4131 | free_rbufs(info, start, end); | |
4132 | goto check_again; | |
4133 | } | |
4134 | ||
4135 | if (framesize < 2 || status & (BIT1+BIT0)) { | |
4136 | if (framesize < 2 || (status & BIT0)) | |
4137 | info->icount.rxshort++; | |
4138 | else | |
4139 | info->icount.rxcrc++; | |
4140 | framesize = 0; | |
4141 | ||
4142 | #ifdef CONFIG_HDLC | |
4143 | { | |
4144 | struct net_device_stats *stats = hdlc_stats(info->netdev); | |
4145 | stats->rx_errors++; | |
4146 | stats->rx_frame_errors++; | |
4147 | } | |
4148 | #endif | |
4149 | } else { | |
4150 | /* adjust frame size for CRC, if any */ | |
4151 | if (info->params.crc_type == HDLC_CRC_16_CCITT) | |
4152 | framesize -= 2; | |
4153 | else if (info->params.crc_type == HDLC_CRC_32_CCITT) | |
4154 | framesize -= 4; | |
4155 | } | |
4156 | ||
4157 | DBGBH(("%s rx frame status=%04X size=%d\n", | |
4158 | info->device_name, status, framesize)); | |
4159 | DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx"); | |
4160 | ||
4161 | if (framesize) { | |
4162 | if (framesize > info->max_frame_size) | |
4163 | info->icount.rxlong++; | |
4164 | else { | |
4165 | /* copy dma buffer(s) to contiguous temp buffer */ | |
4166 | int copy_count = framesize; | |
4167 | int i = start; | |
4168 | unsigned char *p = info->tmp_rbuf; | |
4169 | info->tmp_rbuf_count = framesize; | |
4170 | ||
4171 | info->icount.rxok++; | |
4172 | ||
4173 | while(copy_count) { | |
4174 | int partial_count = min(copy_count, DMABUFSIZE); | |
4175 | memcpy(p, info->rbufs[i].buf, partial_count); | |
4176 | p += partial_count; | |
4177 | copy_count -= partial_count; | |
4178 | if (++i == info->rbuf_count) | |
4179 | i = 0; | |
4180 | } | |
4181 | ||
4182 | #ifdef CONFIG_HDLC | |
4183 | if (info->netcount) | |
4184 | hdlcdev_rx(info,info->tmp_rbuf, framesize); | |
4185 | else | |
4186 | #endif | |
4187 | ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); | |
4188 | } | |
4189 | } | |
4190 | free_rbufs(info, start, end); | |
4191 | rc = 1; | |
4192 | ||
4193 | cleanup: | |
4194 | return rc; | |
4195 | } | |
4196 | ||
4197 | /* | |
4198 | * pass receive buffer (RAW synchronous mode) to tty layer | |
4199 | * return 1 if buffer available, otherwise 0 | |
4200 | */ | |
4201 | static int rx_get_buf(struct slgt_info *info) | |
4202 | { | |
4203 | unsigned int i = info->rbuf_current; | |
4204 | ||
4205 | if (!desc_complete(info->rbufs[i])) | |
4206 | return 0; | |
4207 | DBGDATA(info, info->rbufs[i].buf, desc_count(info->rbufs[i]), "rx"); | |
4208 | DBGINFO(("rx_get_buf size=%d\n", desc_count(info->rbufs[i]))); | |
4209 | ldisc_receive_buf(info->tty, info->rbufs[i].buf, | |
4210 | info->flag_buf, desc_count(info->rbufs[i])); | |
4211 | free_rbufs(info, i, i); | |
4212 | return 1; | |
4213 | } | |
4214 | ||
4215 | static void reset_tbufs(struct slgt_info *info) | |
4216 | { | |
4217 | unsigned int i; | |
4218 | info->tbuf_current = 0; | |
4219 | for (i=0 ; i < info->tbuf_count ; i++) { | |
4220 | info->tbufs[i].status = 0; | |
4221 | info->tbufs[i].count = 0; | |
4222 | } | |
4223 | } | |
4224 | ||
4225 | /* | |
4226 | * return number of free transmit DMA buffers | |
4227 | */ | |
4228 | static unsigned int free_tbuf_count(struct slgt_info *info) | |
4229 | { | |
4230 | unsigned int count = 0; | |
4231 | unsigned int i = info->tbuf_current; | |
4232 | ||
4233 | do | |
4234 | { | |
4235 | if (desc_count(info->tbufs[i])) | |
4236 | break; /* buffer in use */ | |
4237 | ++count; | |
4238 | if (++i == info->tbuf_count) | |
4239 | i=0; | |
4240 | } while (i != info->tbuf_current); | |
4241 | ||
4242 | /* last buffer with zero count may be in use, assume it is */ | |
4243 | if (count) | |
4244 | --count; | |
4245 | ||
4246 | return count; | |
4247 | } | |
4248 | ||
4249 | /* | |
4250 | * load transmit DMA buffer(s) with data | |
4251 | */ | |
4252 | static void tx_load(struct slgt_info *info, const char *buf, unsigned int size) | |
4253 | { | |
4254 | unsigned short count; | |
4255 | unsigned int i; | |
4256 | struct slgt_desc *d; | |
4257 | ||
4258 | if (size == 0) | |
4259 | return; | |
4260 | ||
4261 | DBGDATA(info, buf, size, "tx"); | |
4262 | ||
4263 | info->tbuf_start = i = info->tbuf_current; | |
4264 | ||
4265 | while (size) { | |
4266 | d = &info->tbufs[i]; | |
4267 | if (++i == info->tbuf_count) | |
4268 | i = 0; | |
4269 | ||
4270 | count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); | |
4271 | memcpy(d->buf, buf, count); | |
4272 | ||
4273 | size -= count; | |
4274 | buf += count; | |
4275 | ||
4276 | if (!size && info->params.mode != MGSL_MODE_RAW) | |
4277 | set_desc_eof(*d, 1); /* HDLC: set EOF of last desc */ | |
4278 | else | |
4279 | set_desc_eof(*d, 0); | |
4280 | ||
4281 | set_desc_count(*d, count); | |
4282 | } | |
4283 | ||
4284 | info->tbuf_current = i; | |
4285 | } | |
4286 | ||
4287 | static int register_test(struct slgt_info *info) | |
4288 | { | |
4289 | static unsigned short patterns[] = | |
4290 | {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; | |
4291 | static unsigned int count = sizeof(patterns)/sizeof(patterns[0]); | |
4292 | unsigned int i; | |
4293 | int rc = 0; | |
4294 | ||
4295 | for (i=0 ; i < count ; i++) { | |
4296 | wr_reg16(info, TIR, patterns[i]); | |
4297 | wr_reg16(info, BDR, patterns[(i+1)%count]); | |
4298 | if ((rd_reg16(info, TIR) != patterns[i]) || | |
4299 | (rd_reg16(info, BDR) != patterns[(i+1)%count])) { | |
4300 | rc = -ENODEV; | |
4301 | break; | |
4302 | } | |
4303 | } | |
4304 | ||
4305 | info->init_error = rc ? 0 : DiagStatus_AddressFailure; | |
4306 | return rc; | |
4307 | } | |
4308 | ||
4309 | static int irq_test(struct slgt_info *info) | |
4310 | { | |
4311 | unsigned long timeout; | |
4312 | unsigned long flags; | |
4313 | struct tty_struct *oldtty = info->tty; | |
4314 | u32 speed = info->params.data_rate; | |
4315 | ||
4316 | info->params.data_rate = 921600; | |
4317 | info->tty = NULL; | |
4318 | ||
4319 | spin_lock_irqsave(&info->lock, flags); | |
4320 | async_mode(info); | |
4321 | slgt_irq_on(info, IRQ_TXIDLE); | |
4322 | ||
4323 | /* enable transmitter */ | |
4324 | wr_reg16(info, TCR, | |
4325 | (unsigned short)(rd_reg16(info, TCR) | BIT1)); | |
4326 | ||
4327 | /* write one byte and wait for tx idle */ | |
4328 | wr_reg16(info, TDR, 0); | |
4329 | ||
4330 | /* assume failure */ | |
4331 | info->init_error = DiagStatus_IrqFailure; | |
4332 | info->irq_occurred = FALSE; | |
4333 | ||
4334 | spin_unlock_irqrestore(&info->lock, flags); | |
4335 | ||
4336 | timeout=100; | |
4337 | while(timeout-- && !info->irq_occurred) | |
4338 | msleep_interruptible(10); | |
4339 | ||
4340 | spin_lock_irqsave(&info->lock,flags); | |
4341 | reset_port(info); | |
4342 | spin_unlock_irqrestore(&info->lock,flags); | |
4343 | ||
4344 | info->params.data_rate = speed; | |
4345 | info->tty = oldtty; | |
4346 | ||
4347 | info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; | |
4348 | return info->irq_occurred ? 0 : -ENODEV; | |
4349 | } | |
4350 | ||
4351 | static int loopback_test_rx(struct slgt_info *info) | |
4352 | { | |
4353 | unsigned char *src, *dest; | |
4354 | int count; | |
4355 | ||
4356 | if (desc_complete(info->rbufs[0])) { | |
4357 | count = desc_count(info->rbufs[0]); | |
4358 | src = info->rbufs[0].buf; | |
4359 | dest = info->tmp_rbuf; | |
4360 | ||
4361 | for( ; count ; count-=2, src+=2) { | |
4362 | /* src=data byte (src+1)=status byte */ | |
4363 | if (!(*(src+1) & (BIT9 + BIT8))) { | |
4364 | *dest = *src; | |
4365 | dest++; | |
4366 | info->tmp_rbuf_count++; | |
4367 | } | |
4368 | } | |
4369 | DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); | |
4370 | return 1; | |
4371 | } | |
4372 | return 0; | |
4373 | } | |
4374 | ||
4375 | static int loopback_test(struct slgt_info *info) | |
4376 | { | |
4377 | #define TESTFRAMESIZE 20 | |
4378 | ||
4379 | unsigned long timeout; | |
4380 | u16 count = TESTFRAMESIZE; | |
4381 | unsigned char buf[TESTFRAMESIZE]; | |
4382 | int rc = -ENODEV; | |
4383 | unsigned long flags; | |
4384 | ||
4385 | struct tty_struct *oldtty = info->tty; | |
4386 | MGSL_PARAMS params; | |
4387 | ||
4388 | memcpy(¶ms, &info->params, sizeof(params)); | |
4389 | ||
4390 | info->params.mode = MGSL_MODE_ASYNC; | |
4391 | info->params.data_rate = 921600; | |
4392 | info->params.loopback = 1; | |
4393 | info->tty = NULL; | |
4394 | ||
4395 | /* build and send transmit frame */ | |
4396 | for (count = 0; count < TESTFRAMESIZE; ++count) | |
4397 | buf[count] = (unsigned char)count; | |
4398 | ||
4399 | info->tmp_rbuf_count = 0; | |
4400 | memset(info->tmp_rbuf, 0, TESTFRAMESIZE); | |
4401 | ||
4402 | /* program hardware for HDLC and enabled receiver */ | |
4403 | spin_lock_irqsave(&info->lock,flags); | |
4404 | async_mode(info); | |
4405 | rx_start(info); | |
4406 | info->tx_count = count; | |
4407 | tx_load(info, buf, count); | |
4408 | tx_start(info); | |
4409 | spin_unlock_irqrestore(&info->lock, flags); | |
4410 | ||
4411 | /* wait for receive complete */ | |
4412 | for (timeout = 100; timeout; --timeout) { | |
4413 | msleep_interruptible(10); | |
4414 | if (loopback_test_rx(info)) { | |
4415 | rc = 0; | |
4416 | break; | |
4417 | } | |
4418 | } | |
4419 | ||
4420 | /* verify received frame length and contents */ | |
4421 | if (!rc && (info->tmp_rbuf_count != count || | |
4422 | memcmp(buf, info->tmp_rbuf, count))) { | |
4423 | rc = -ENODEV; | |
4424 | } | |
4425 | ||
4426 | spin_lock_irqsave(&info->lock,flags); | |
4427 | reset_adapter(info); | |
4428 | spin_unlock_irqrestore(&info->lock,flags); | |
4429 | ||
4430 | memcpy(&info->params, ¶ms, sizeof(info->params)); | |
4431 | info->tty = oldtty; | |
4432 | ||
4433 | info->init_error = rc ? DiagStatus_DmaFailure : 0; | |
4434 | return rc; | |
4435 | } | |
4436 | ||
4437 | static int adapter_test(struct slgt_info *info) | |
4438 | { | |
4439 | DBGINFO(("testing %s\n", info->device_name)); | |
4440 | if ((info->init_error = register_test(info)) < 0) { | |
4441 | printk("register test failure %s addr=%08X\n", | |
4442 | info->device_name, info->phys_reg_addr); | |
4443 | } else if ((info->init_error = irq_test(info)) < 0) { | |
4444 | printk("IRQ test failure %s IRQ=%d\n", | |
4445 | info->device_name, info->irq_level); | |
4446 | } else if ((info->init_error = loopback_test(info)) < 0) { | |
4447 | printk("loopback test failure %s\n", info->device_name); | |
4448 | } | |
4449 | return info->init_error; | |
4450 | } | |
4451 | ||
4452 | /* | |
4453 | * transmit timeout handler | |
4454 | */ | |
4455 | static void tx_timeout(unsigned long context) | |
4456 | { | |
4457 | struct slgt_info *info = (struct slgt_info*)context; | |
4458 | unsigned long flags; | |
4459 | ||
4460 | DBGINFO(("%s tx_timeout\n", info->device_name)); | |
4461 | if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { | |
4462 | info->icount.txtimeout++; | |
4463 | } | |
4464 | spin_lock_irqsave(&info->lock,flags); | |
4465 | info->tx_active = 0; | |
4466 | info->tx_count = 0; | |
4467 | spin_unlock_irqrestore(&info->lock,flags); | |
4468 | ||
4469 | #ifdef CONFIG_HDLC | |
4470 | if (info->netcount) | |
4471 | hdlcdev_tx_done(info); | |
4472 | else | |
4473 | #endif | |
4474 | bh_transmit(info); | |
4475 | } | |
4476 | ||
4477 | /* | |
4478 | * receive buffer polling timer | |
4479 | */ | |
4480 | static void rx_timeout(unsigned long context) | |
4481 | { | |
4482 | struct slgt_info *info = (struct slgt_info*)context; | |
4483 | unsigned long flags; | |
4484 | ||
4485 | DBGINFO(("%s rx_timeout\n", info->device_name)); | |
4486 | spin_lock_irqsave(&info->lock, flags); | |
4487 | info->pending_bh |= BH_RECEIVE; | |
4488 | spin_unlock_irqrestore(&info->lock, flags); | |
4489 | bh_handler(info); | |
4490 | } | |
4491 |