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Commit | Line | Data |
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705b6c7b | 1 | /* |
705b6c7b PF |
2 | * Device driver for Microgate SyncLink GT serial adapters. |
3 | * | |
4 | * written by Paul Fulghum for Microgate Corporation | |
5 | * paulkf@microgate.com | |
6 | * | |
7 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
8 | * | |
9 | * This code is released under the GNU General Public License (GPL) | |
10 | * | |
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
13 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
14 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
15 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
16 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
17 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
18 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
19 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
20 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
21 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
22 | */ | |
23 | ||
24 | /* | |
25 | * DEBUG OUTPUT DEFINITIONS | |
26 | * | |
27 | * uncomment lines below to enable specific types of debug output | |
28 | * | |
29 | * DBGINFO information - most verbose output | |
30 | * DBGERR serious errors | |
31 | * DBGBH bottom half service routine debugging | |
32 | * DBGISR interrupt service routine debugging | |
33 | * DBGDATA output receive and transmit data | |
34 | * DBGTBUF output transmit DMA buffers and registers | |
35 | * DBGRBUF output receive DMA buffers and registers | |
36 | */ | |
37 | ||
38 | #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt | |
39 | #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt | |
40 | #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt | |
41 | #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt | |
42 | #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) | |
f602501d AC |
43 | /*#define DBGTBUF(info) dump_tbufs(info)*/ |
44 | /*#define DBGRBUF(info) dump_rbufs(info)*/ | |
705b6c7b PF |
45 | |
46 | ||
705b6c7b | 47 | #include <linux/module.h> |
705b6c7b PF |
48 | #include <linux/errno.h> |
49 | #include <linux/signal.h> | |
50 | #include <linux/sched.h> | |
51 | #include <linux/timer.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/tty.h> | |
55 | #include <linux/tty_flip.h> | |
56 | #include <linux/serial.h> | |
57 | #include <linux/major.h> | |
58 | #include <linux/string.h> | |
59 | #include <linux/fcntl.h> | |
60 | #include <linux/ptrace.h> | |
61 | #include <linux/ioport.h> | |
62 | #include <linux/mm.h> | |
a18c56e5 | 63 | #include <linux/seq_file.h> |
705b6c7b PF |
64 | #include <linux/slab.h> |
65 | #include <linux/netdevice.h> | |
66 | #include <linux/vmalloc.h> | |
67 | #include <linux/init.h> | |
68 | #include <linux/delay.h> | |
69 | #include <linux/ioctl.h> | |
70 | #include <linux/termios.h> | |
71 | #include <linux/bitops.h> | |
72 | #include <linux/workqueue.h> | |
73 | #include <linux/hdlc.h> | |
3dd1247f | 74 | #include <linux/synclink.h> |
705b6c7b | 75 | |
705b6c7b PF |
76 | #include <asm/system.h> |
77 | #include <asm/io.h> | |
78 | #include <asm/irq.h> | |
79 | #include <asm/dma.h> | |
80 | #include <asm/types.h> | |
81 | #include <asm/uaccess.h> | |
82 | ||
af69c7f9 PF |
83 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) |
84 | #define SYNCLINK_GENERIC_HDLC 1 | |
85 | #else | |
86 | #define SYNCLINK_GENERIC_HDLC 0 | |
705b6c7b PF |
87 | #endif |
88 | ||
89 | /* | |
90 | * module identification | |
91 | */ | |
92 | static char *driver_name = "SyncLink GT"; | |
705b6c7b PF |
93 | static char *tty_driver_name = "synclink_gt"; |
94 | static char *tty_dev_prefix = "ttySLG"; | |
95 | MODULE_LICENSE("GPL"); | |
96 | #define MGSL_MAGIC 0x5401 | |
a077c1a0 | 97 | #define MAX_DEVICES 32 |
705b6c7b PF |
98 | |
99 | static struct pci_device_id pci_table[] = { | |
100 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
6f84be84 | 101 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
705b6c7b PF |
102 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
103 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
104 | {0,}, /* terminate list */ | |
105 | }; | |
106 | MODULE_DEVICE_TABLE(pci, pci_table); | |
107 | ||
108 | static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); | |
109 | static void remove_one(struct pci_dev *dev); | |
110 | static struct pci_driver pci_driver = { | |
111 | .name = "synclink_gt", | |
112 | .id_table = pci_table, | |
113 | .probe = init_one, | |
114 | .remove = __devexit_p(remove_one), | |
115 | }; | |
116 | ||
0fab6de0 | 117 | static bool pci_registered; |
705b6c7b PF |
118 | |
119 | /* | |
120 | * module configuration and status | |
121 | */ | |
122 | static struct slgt_info *slgt_device_list; | |
123 | static int slgt_device_count; | |
124 | ||
125 | static int ttymajor; | |
126 | static int debug_level; | |
127 | static int maxframe[MAX_DEVICES]; | |
705b6c7b PF |
128 | |
129 | module_param(ttymajor, int, 0); | |
130 | module_param(debug_level, int, 0); | |
131 | module_param_array(maxframe, int, NULL, 0); | |
705b6c7b PF |
132 | |
133 | MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); | |
134 | MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); | |
135 | MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); | |
705b6c7b PF |
136 | |
137 | /* | |
138 | * tty support and callbacks | |
139 | */ | |
705b6c7b PF |
140 | static struct tty_driver *serial_driver; |
141 | ||
142 | static int open(struct tty_struct *tty, struct file * filp); | |
143 | static void close(struct tty_struct *tty, struct file * filp); | |
144 | static void hangup(struct tty_struct *tty); | |
606d099c | 145 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); |
705b6c7b PF |
146 | |
147 | static int write(struct tty_struct *tty, const unsigned char *buf, int count); | |
55da7789 | 148 | static int put_char(struct tty_struct *tty, unsigned char ch); |
705b6c7b PF |
149 | static void send_xchar(struct tty_struct *tty, char ch); |
150 | static void wait_until_sent(struct tty_struct *tty, int timeout); | |
151 | static int write_room(struct tty_struct *tty); | |
152 | static void flush_chars(struct tty_struct *tty); | |
153 | static void flush_buffer(struct tty_struct *tty); | |
154 | static void tx_hold(struct tty_struct *tty); | |
155 | static void tx_release(struct tty_struct *tty); | |
156 | ||
157 | static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg); | |
705b6c7b PF |
158 | static int chars_in_buffer(struct tty_struct *tty); |
159 | static void throttle(struct tty_struct * tty); | |
160 | static void unthrottle(struct tty_struct * tty); | |
9e98966c | 161 | static int set_break(struct tty_struct *tty, int break_state); |
705b6c7b PF |
162 | |
163 | /* | |
164 | * generic HDLC support and callbacks | |
165 | */ | |
af69c7f9 | 166 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
167 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
168 | static void hdlcdev_tx_done(struct slgt_info *info); | |
169 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); | |
170 | static int hdlcdev_init(struct slgt_info *info); | |
171 | static void hdlcdev_exit(struct slgt_info *info); | |
172 | #endif | |
173 | ||
174 | ||
175 | /* | |
176 | * device specific structures, macros and functions | |
177 | */ | |
178 | ||
179 | #define SLGT_MAX_PORTS 4 | |
180 | #define SLGT_REG_SIZE 256 | |
181 | ||
0080b7aa PF |
182 | /* |
183 | * conditional wait facility | |
184 | */ | |
185 | struct cond_wait { | |
186 | struct cond_wait *next; | |
187 | wait_queue_head_t q; | |
188 | wait_queue_t wait; | |
189 | unsigned int data; | |
190 | }; | |
191 | static void init_cond_wait(struct cond_wait *w, unsigned int data); | |
192 | static void add_cond_wait(struct cond_wait **head, struct cond_wait *w); | |
193 | static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w); | |
194 | static void flush_cond_wait(struct cond_wait **head); | |
195 | ||
705b6c7b PF |
196 | /* |
197 | * DMA buffer descriptor and access macros | |
198 | */ | |
199 | struct slgt_desc | |
200 | { | |
51ef9c57 AV |
201 | __le16 count; |
202 | __le16 status; | |
203 | __le32 pbuf; /* physical address of data buffer */ | |
204 | __le32 next; /* physical address of next descriptor */ | |
705b6c7b PF |
205 | |
206 | /* driver book keeping */ | |
207 | char *buf; /* virtual address of data buffer */ | |
208 | unsigned int pdesc; /* physical address of this descriptor */ | |
209 | dma_addr_t buf_dma_addr; | |
403214d0 | 210 | unsigned short buf_count; |
705b6c7b PF |
211 | }; |
212 | ||
213 | #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) | |
214 | #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) | |
215 | #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) | |
216 | #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) | |
5ba5a5d2 | 217 | #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b)) |
705b6c7b PF |
218 | #define desc_count(a) (le16_to_cpu((a).count)) |
219 | #define desc_status(a) (le16_to_cpu((a).status)) | |
220 | #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) | |
221 | #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) | |
222 | #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) | |
223 | #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) | |
224 | #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) | |
225 | ||
226 | struct _input_signal_events { | |
227 | int ri_up; | |
228 | int ri_down; | |
229 | int dsr_up; | |
230 | int dsr_down; | |
231 | int dcd_up; | |
232 | int dcd_down; | |
233 | int cts_up; | |
234 | int cts_down; | |
235 | }; | |
236 | ||
237 | /* | |
238 | * device instance data structure | |
239 | */ | |
240 | struct slgt_info { | |
241 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | |
8fb06c77 | 242 | struct tty_port port; |
705b6c7b PF |
243 | |
244 | struct slgt_info *next_device; /* device list link */ | |
245 | ||
246 | int magic; | |
705b6c7b PF |
247 | |
248 | char device_name[25]; | |
249 | struct pci_dev *pdev; | |
250 | ||
251 | int port_count; /* count of ports on adapter */ | |
252 | int adapter_num; /* adapter instance number */ | |
253 | int port_num; /* port instance number */ | |
254 | ||
255 | /* array of pointers to port contexts on this adapter */ | |
256 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
257 | ||
705b6c7b | 258 | int line; /* tty line instance number */ |
705b6c7b PF |
259 | |
260 | struct mgsl_icount icount; | |
261 | ||
705b6c7b PF |
262 | int timeout; |
263 | int x_char; /* xon/xoff character */ | |
705b6c7b PF |
264 | unsigned int read_status_mask; |
265 | unsigned int ignore_status_mask; | |
266 | ||
705b6c7b PF |
267 | wait_queue_head_t status_event_wait_q; |
268 | wait_queue_head_t event_wait_q; | |
269 | struct timer_list tx_timer; | |
270 | struct timer_list rx_timer; | |
271 | ||
0080b7aa PF |
272 | unsigned int gpio_present; |
273 | struct cond_wait *gpio_wait_q; | |
274 | ||
705b6c7b PF |
275 | spinlock_t lock; /* spinlock for synchronizing with ISR */ |
276 | ||
277 | struct work_struct task; | |
278 | u32 pending_bh; | |
0fab6de0 JP |
279 | bool bh_requested; |
280 | bool bh_running; | |
705b6c7b PF |
281 | |
282 | int isr_overflow; | |
0fab6de0 JP |
283 | bool irq_requested; /* true if IRQ requested */ |
284 | bool irq_occurred; /* for diagnostics use */ | |
705b6c7b PF |
285 | |
286 | /* device configuration */ | |
287 | ||
288 | unsigned int bus_type; | |
289 | unsigned int irq_level; | |
290 | unsigned long irq_flags; | |
291 | ||
292 | unsigned char __iomem * reg_addr; /* memory mapped registers address */ | |
293 | u32 phys_reg_addr; | |
0fab6de0 | 294 | bool reg_addr_requested; |
705b6c7b PF |
295 | |
296 | MGSL_PARAMS params; /* communications parameters */ | |
297 | u32 idle_mode; | |
298 | u32 max_frame_size; /* as set by device config */ | |
299 | ||
814dae03 | 300 | unsigned int rbuf_fill_level; |
5ba5a5d2 | 301 | unsigned int rx_pio; |
705b6c7b | 302 | unsigned int if_mode; |
1f80769f | 303 | unsigned int base_clock; |
705b6c7b PF |
304 | |
305 | /* device status */ | |
306 | ||
0fab6de0 JP |
307 | bool rx_enabled; |
308 | bool rx_restart; | |
705b6c7b | 309 | |
0fab6de0 JP |
310 | bool tx_enabled; |
311 | bool tx_active; | |
705b6c7b PF |
312 | |
313 | unsigned char signals; /* serial signal states */ | |
2641dfd9 | 314 | int init_error; /* initialization error */ |
705b6c7b PF |
315 | |
316 | unsigned char *tx_buf; | |
317 | int tx_count; | |
318 | ||
319 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; | |
320 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; | |
0fab6de0 | 321 | bool drop_rts_on_tx_done; |
705b6c7b PF |
322 | struct _input_signal_events input_signal_events; |
323 | ||
324 | int dcd_chkcount; /* check counts to prevent */ | |
325 | int cts_chkcount; /* too many IRQs if a signal */ | |
326 | int dsr_chkcount; /* is floating */ | |
327 | int ri_chkcount; | |
328 | ||
329 | char *bufs; /* virtual address of DMA buffer lists */ | |
330 | dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ | |
331 | ||
332 | unsigned int rbuf_count; | |
333 | struct slgt_desc *rbufs; | |
334 | unsigned int rbuf_current; | |
335 | unsigned int rbuf_index; | |
5ba5a5d2 PF |
336 | unsigned int rbuf_fill_index; |
337 | unsigned short rbuf_fill_count; | |
705b6c7b PF |
338 | |
339 | unsigned int tbuf_count; | |
340 | struct slgt_desc *tbufs; | |
341 | unsigned int tbuf_current; | |
342 | unsigned int tbuf_start; | |
343 | ||
344 | unsigned char *tmp_rbuf; | |
345 | unsigned int tmp_rbuf_count; | |
346 | ||
347 | /* SPPP/Cisco HDLC device parts */ | |
348 | ||
349 | int netcount; | |
705b6c7b | 350 | spinlock_t netlock; |
af69c7f9 | 351 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
352 | struct net_device *netdev; |
353 | #endif | |
354 | ||
355 | }; | |
356 | ||
357 | static MGSL_PARAMS default_params = { | |
358 | .mode = MGSL_MODE_HDLC, | |
359 | .loopback = 0, | |
360 | .flags = HDLC_FLAG_UNDERRUN_ABORT15, | |
361 | .encoding = HDLC_ENCODING_NRZI_SPACE, | |
362 | .clock_speed = 0, | |
363 | .addr_filter = 0xff, | |
364 | .crc_type = HDLC_CRC_16_CCITT, | |
365 | .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, | |
366 | .preamble = HDLC_PREAMBLE_PATTERN_NONE, | |
367 | .data_rate = 9600, | |
368 | .data_bits = 8, | |
369 | .stop_bits = 1, | |
370 | .parity = ASYNC_PARITY_NONE | |
371 | }; | |
372 | ||
373 | ||
374 | #define BH_RECEIVE 1 | |
375 | #define BH_TRANSMIT 2 | |
376 | #define BH_STATUS 4 | |
377 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
378 | ||
379 | #define DMABUFSIZE 256 | |
380 | #define DESC_LIST_SIZE 4096 | |
381 | ||
382 | #define MASK_PARITY BIT1 | |
202af6d5 PF |
383 | #define MASK_FRAMING BIT0 |
384 | #define MASK_BREAK BIT14 | |
705b6c7b PF |
385 | #define MASK_OVERRUN BIT4 |
386 | ||
387 | #define GSR 0x00 /* global status */ | |
0080b7aa PF |
388 | #define JCR 0x04 /* JTAG control */ |
389 | #define IODR 0x08 /* GPIO direction */ | |
390 | #define IOER 0x0c /* GPIO interrupt enable */ | |
391 | #define IOVR 0x10 /* GPIO value */ | |
392 | #define IOSR 0x14 /* GPIO interrupt status */ | |
705b6c7b PF |
393 | #define TDR 0x80 /* tx data */ |
394 | #define RDR 0x80 /* rx data */ | |
395 | #define TCR 0x82 /* tx control */ | |
396 | #define TIR 0x84 /* tx idle */ | |
397 | #define TPR 0x85 /* tx preamble */ | |
398 | #define RCR 0x86 /* rx control */ | |
399 | #define VCR 0x88 /* V.24 control */ | |
400 | #define CCR 0x89 /* clock control */ | |
401 | #define BDR 0x8a /* baud divisor */ | |
402 | #define SCR 0x8c /* serial control */ | |
403 | #define SSR 0x8e /* serial status */ | |
404 | #define RDCSR 0x90 /* rx DMA control/status */ | |
405 | #define TDCSR 0x94 /* tx DMA control/status */ | |
406 | #define RDDAR 0x98 /* rx DMA descriptor address */ | |
407 | #define TDDAR 0x9c /* tx DMA descriptor address */ | |
408 | ||
409 | #define RXIDLE BIT14 | |
410 | #define RXBREAK BIT14 | |
411 | #define IRQ_TXDATA BIT13 | |
412 | #define IRQ_TXIDLE BIT12 | |
413 | #define IRQ_TXUNDER BIT11 /* HDLC */ | |
414 | #define IRQ_RXDATA BIT10 | |
415 | #define IRQ_RXIDLE BIT9 /* HDLC */ | |
416 | #define IRQ_RXBREAK BIT9 /* async */ | |
417 | #define IRQ_RXOVER BIT8 | |
418 | #define IRQ_DSR BIT7 | |
419 | #define IRQ_CTS BIT6 | |
420 | #define IRQ_DCD BIT5 | |
421 | #define IRQ_RI BIT4 | |
422 | #define IRQ_ALL 0x3ff0 | |
423 | #define IRQ_MASTER BIT0 | |
424 | ||
425 | #define slgt_irq_on(info, mask) \ | |
426 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) | |
427 | #define slgt_irq_off(info, mask) \ | |
428 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) | |
429 | ||
430 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); | |
431 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); | |
432 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); | |
433 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); | |
434 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); | |
435 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); | |
436 | ||
437 | static void msc_set_vcr(struct slgt_info *info); | |
438 | ||
439 | static int startup(struct slgt_info *info); | |
440 | static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); | |
441 | static void shutdown(struct slgt_info *info); | |
442 | static void program_hw(struct slgt_info *info); | |
443 | static void change_params(struct slgt_info *info); | |
444 | ||
445 | static int register_test(struct slgt_info *info); | |
446 | static int irq_test(struct slgt_info *info); | |
447 | static int loopback_test(struct slgt_info *info); | |
448 | static int adapter_test(struct slgt_info *info); | |
449 | ||
450 | static void reset_adapter(struct slgt_info *info); | |
451 | static void reset_port(struct slgt_info *info); | |
452 | static void async_mode(struct slgt_info *info); | |
cb10dc9a | 453 | static void sync_mode(struct slgt_info *info); |
705b6c7b PF |
454 | |
455 | static void rx_stop(struct slgt_info *info); | |
456 | static void rx_start(struct slgt_info *info); | |
457 | static void reset_rbufs(struct slgt_info *info); | |
458 | static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); | |
459 | static void rdma_reset(struct slgt_info *info); | |
0fab6de0 JP |
460 | static bool rx_get_frame(struct slgt_info *info); |
461 | static bool rx_get_buf(struct slgt_info *info); | |
705b6c7b PF |
462 | |
463 | static void tx_start(struct slgt_info *info); | |
464 | static void tx_stop(struct slgt_info *info); | |
465 | static void tx_set_idle(struct slgt_info *info); | |
466 | static unsigned int free_tbuf_count(struct slgt_info *info); | |
403214d0 | 467 | static unsigned int tbuf_bytes(struct slgt_info *info); |
705b6c7b PF |
468 | static void reset_tbufs(struct slgt_info *info); |
469 | static void tdma_reset(struct slgt_info *info); | |
de538eb3 | 470 | static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count); |
705b6c7b PF |
471 | |
472 | static void get_signals(struct slgt_info *info); | |
473 | static void set_signals(struct slgt_info *info); | |
474 | static void enable_loopback(struct slgt_info *info); | |
475 | static void set_rate(struct slgt_info *info, u32 data_rate); | |
476 | ||
477 | static int bh_action(struct slgt_info *info); | |
c4028958 | 478 | static void bh_handler(struct work_struct *work); |
705b6c7b PF |
479 | static void bh_transmit(struct slgt_info *info); |
480 | static void isr_serial(struct slgt_info *info); | |
481 | static void isr_rdma(struct slgt_info *info); | |
482 | static void isr_txeom(struct slgt_info *info, unsigned short status); | |
483 | static void isr_tdma(struct slgt_info *info); | |
705b6c7b PF |
484 | |
485 | static int alloc_dma_bufs(struct slgt_info *info); | |
486 | static void free_dma_bufs(struct slgt_info *info); | |
487 | static int alloc_desc(struct slgt_info *info); | |
488 | static void free_desc(struct slgt_info *info); | |
489 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
490 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
491 | ||
492 | static int alloc_tmp_rbuf(struct slgt_info *info); | |
493 | static void free_tmp_rbuf(struct slgt_info *info); | |
494 | ||
495 | static void tx_timeout(unsigned long context); | |
496 | static void rx_timeout(unsigned long context); | |
497 | ||
498 | /* | |
499 | * ioctl handlers | |
500 | */ | |
501 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); | |
502 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
503 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
504 | static int get_txidle(struct slgt_info *info, int __user *idle_mode); | |
505 | static int set_txidle(struct slgt_info *info, int idle_mode); | |
506 | static int tx_enable(struct slgt_info *info, int enable); | |
507 | static int tx_abort(struct slgt_info *info); | |
508 | static int rx_enable(struct slgt_info *info, int enable); | |
509 | static int modem_input_wait(struct slgt_info *info,int arg); | |
510 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); | |
511 | static int tiocmget(struct tty_struct *tty, struct file *file); | |
512 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
513 | unsigned int set, unsigned int clear); | |
9e98966c | 514 | static int set_break(struct tty_struct *tty, int break_state); |
705b6c7b PF |
515 | static int get_interface(struct slgt_info *info, int __user *if_mode); |
516 | static int set_interface(struct slgt_info *info, int if_mode); | |
0080b7aa PF |
517 | static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); |
518 | static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); | |
519 | static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); | |
705b6c7b PF |
520 | |
521 | /* | |
522 | * driver functions | |
523 | */ | |
524 | static void add_device(struct slgt_info *info); | |
525 | static void device_init(int adapter_num, struct pci_dev *pdev); | |
526 | static int claim_resources(struct slgt_info *info); | |
527 | static void release_resources(struct slgt_info *info); | |
528 | ||
529 | /* | |
530 | * DEBUG OUTPUT CODE | |
531 | */ | |
532 | #ifndef DBGINFO | |
533 | #define DBGINFO(fmt) | |
534 | #endif | |
535 | #ifndef DBGERR | |
536 | #define DBGERR(fmt) | |
537 | #endif | |
538 | #ifndef DBGBH | |
539 | #define DBGBH(fmt) | |
540 | #endif | |
541 | #ifndef DBGISR | |
542 | #define DBGISR(fmt) | |
543 | #endif | |
544 | ||
545 | #ifdef DBGDATA | |
546 | static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) | |
547 | { | |
548 | int i; | |
549 | int linecount; | |
550 | printk("%s %s data:\n",info->device_name, label); | |
551 | while(count) { | |
552 | linecount = (count > 16) ? 16 : count; | |
553 | for(i=0; i < linecount; i++) | |
554 | printk("%02X ",(unsigned char)data[i]); | |
555 | for(;i<17;i++) | |
556 | printk(" "); | |
557 | for(i=0;i<linecount;i++) { | |
558 | if (data[i]>=040 && data[i]<=0176) | |
559 | printk("%c",data[i]); | |
560 | else | |
561 | printk("."); | |
562 | } | |
563 | printk("\n"); | |
564 | data += linecount; | |
565 | count -= linecount; | |
566 | } | |
567 | } | |
568 | #else | |
569 | #define DBGDATA(info, buf, size, label) | |
570 | #endif | |
571 | ||
572 | #ifdef DBGTBUF | |
573 | static void dump_tbufs(struct slgt_info *info) | |
574 | { | |
575 | int i; | |
576 | printk("tbuf_current=%d\n", info->tbuf_current); | |
577 | for (i=0 ; i < info->tbuf_count ; i++) { | |
578 | printk("%d: count=%04X status=%04X\n", | |
579 | i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); | |
580 | } | |
581 | } | |
582 | #else | |
583 | #define DBGTBUF(info) | |
584 | #endif | |
585 | ||
586 | #ifdef DBGRBUF | |
587 | static void dump_rbufs(struct slgt_info *info) | |
588 | { | |
589 | int i; | |
590 | printk("rbuf_current=%d\n", info->rbuf_current); | |
591 | for (i=0 ; i < info->rbuf_count ; i++) { | |
592 | printk("%d: count=%04X status=%04X\n", | |
593 | i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); | |
594 | } | |
595 | } | |
596 | #else | |
597 | #define DBGRBUF(info) | |
598 | #endif | |
599 | ||
600 | static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) | |
601 | { | |
602 | #ifdef SANITY_CHECK | |
603 | if (!info) { | |
604 | printk("null struct slgt_info for (%s) in %s\n", devname, name); | |
605 | return 1; | |
606 | } | |
607 | if (info->magic != MGSL_MAGIC) { | |
608 | printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); | |
609 | return 1; | |
610 | } | |
611 | #else | |
612 | if (!info) | |
613 | return 1; | |
614 | #endif | |
615 | return 0; | |
616 | } | |
617 | ||
618 | /** | |
619 | * line discipline callback wrappers | |
620 | * | |
621 | * The wrappers maintain line discipline references | |
622 | * while calling into the line discipline. | |
623 | * | |
624 | * ldisc_receive_buf - pass receive data to line discipline | |
625 | */ | |
626 | static void ldisc_receive_buf(struct tty_struct *tty, | |
627 | const __u8 *data, char *flags, int count) | |
628 | { | |
629 | struct tty_ldisc *ld; | |
630 | if (!tty) | |
631 | return; | |
632 | ld = tty_ldisc_ref(tty); | |
633 | if (ld) { | |
a352def2 AC |
634 | if (ld->ops->receive_buf) |
635 | ld->ops->receive_buf(tty, data, flags, count); | |
705b6c7b PF |
636 | tty_ldisc_deref(ld); |
637 | } | |
638 | } | |
639 | ||
640 | /* tty callbacks */ | |
641 | ||
642 | static int open(struct tty_struct *tty, struct file *filp) | |
643 | { | |
644 | struct slgt_info *info; | |
645 | int retval, line; | |
646 | unsigned long flags; | |
647 | ||
648 | line = tty->index; | |
649 | if ((line < 0) || (line >= slgt_device_count)) { | |
650 | DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); | |
651 | return -ENODEV; | |
652 | } | |
653 | ||
654 | info = slgt_device_list; | |
655 | while(info && info->line != line) | |
656 | info = info->next_device; | |
657 | if (sanity_check(info, tty->name, "open")) | |
658 | return -ENODEV; | |
659 | if (info->init_error) { | |
660 | DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); | |
661 | return -ENODEV; | |
662 | } | |
663 | ||
664 | tty->driver_data = info; | |
8fb06c77 | 665 | info->port.tty = tty; |
705b6c7b | 666 | |
8fb06c77 | 667 | DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count)); |
705b6c7b PF |
668 | |
669 | /* If port is closing, signal caller to try again */ | |
8fb06c77 AC |
670 | if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){ |
671 | if (info->port.flags & ASYNC_CLOSING) | |
672 | interruptible_sleep_on(&info->port.close_wait); | |
673 | retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ? | |
705b6c7b PF |
674 | -EAGAIN : -ERESTARTSYS); |
675 | goto cleanup; | |
676 | } | |
677 | ||
a360fae6 | 678 | mutex_lock(&info->port.mutex); |
8fb06c77 | 679 | info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; |
705b6c7b PF |
680 | |
681 | spin_lock_irqsave(&info->netlock, flags); | |
682 | if (info->netcount) { | |
683 | retval = -EBUSY; | |
684 | spin_unlock_irqrestore(&info->netlock, flags); | |
a360fae6 | 685 | mutex_unlock(&info->port.mutex); |
705b6c7b PF |
686 | goto cleanup; |
687 | } | |
8fb06c77 | 688 | info->port.count++; |
705b6c7b PF |
689 | spin_unlock_irqrestore(&info->netlock, flags); |
690 | ||
8fb06c77 | 691 | if (info->port.count == 1) { |
705b6c7b PF |
692 | /* 1st open on this device, init hardware */ |
693 | retval = startup(info); | |
80d04f22 DC |
694 | if (retval < 0) { |
695 | mutex_unlock(&info->port.mutex); | |
705b6c7b | 696 | goto cleanup; |
80d04f22 | 697 | } |
705b6c7b | 698 | } |
a360fae6 | 699 | mutex_unlock(&info->port.mutex); |
705b6c7b PF |
700 | retval = block_til_ready(tty, filp, info); |
701 | if (retval) { | |
702 | DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); | |
703 | goto cleanup; | |
704 | } | |
705 | ||
706 | retval = 0; | |
707 | ||
708 | cleanup: | |
709 | if (retval) { | |
710 | if (tty->count == 1) | |
8fb06c77 AC |
711 | info->port.tty = NULL; /* tty layer will release tty struct */ |
712 | if(info->port.count) | |
713 | info->port.count--; | |
705b6c7b PF |
714 | } |
715 | ||
716 | DBGINFO(("%s open rc=%d\n", info->device_name, retval)); | |
717 | return retval; | |
718 | } | |
719 | ||
720 | static void close(struct tty_struct *tty, struct file *filp) | |
721 | { | |
722 | struct slgt_info *info = tty->driver_data; | |
723 | ||
724 | if (sanity_check(info, tty->name, "close")) | |
725 | return; | |
8fb06c77 | 726 | DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count)); |
705b6c7b | 727 | |
a6614999 | 728 | if (tty_port_close_start(&info->port, tty, filp) == 0) |
705b6c7b PF |
729 | goto cleanup; |
730 | ||
a360fae6 | 731 | mutex_lock(&info->port.mutex); |
8fb06c77 | 732 | if (info->port.flags & ASYNC_INITIALIZED) |
705b6c7b | 733 | wait_until_sent(tty, info->timeout); |
978e595f | 734 | flush_buffer(tty); |
705b6c7b PF |
735 | tty_ldisc_flush(tty); |
736 | ||
737 | shutdown(info); | |
a360fae6 | 738 | mutex_unlock(&info->port.mutex); |
705b6c7b | 739 | |
a6614999 | 740 | tty_port_close_end(&info->port, tty); |
8fb06c77 | 741 | info->port.tty = NULL; |
705b6c7b | 742 | cleanup: |
8fb06c77 | 743 | DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count)); |
705b6c7b PF |
744 | } |
745 | ||
746 | static void hangup(struct tty_struct *tty) | |
747 | { | |
748 | struct slgt_info *info = tty->driver_data; | |
a360fae6 | 749 | unsigned long flags; |
705b6c7b PF |
750 | |
751 | if (sanity_check(info, tty->name, "hangup")) | |
752 | return; | |
753 | DBGINFO(("%s hangup\n", info->device_name)); | |
754 | ||
755 | flush_buffer(tty); | |
a360fae6 AC |
756 | |
757 | mutex_lock(&info->port.mutex); | |
705b6c7b PF |
758 | shutdown(info); |
759 | ||
a360fae6 | 760 | spin_lock_irqsave(&info->port.lock, flags); |
8fb06c77 AC |
761 | info->port.count = 0; |
762 | info->port.flags &= ~ASYNC_NORMAL_ACTIVE; | |
763 | info->port.tty = NULL; | |
a360fae6 AC |
764 | spin_unlock_irqrestore(&info->port.lock, flags); |
765 | mutex_unlock(&info->port.mutex); | |
705b6c7b | 766 | |
8fb06c77 | 767 | wake_up_interruptible(&info->port.open_wait); |
705b6c7b PF |
768 | } |
769 | ||
606d099c | 770 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
705b6c7b PF |
771 | { |
772 | struct slgt_info *info = tty->driver_data; | |
773 | unsigned long flags; | |
774 | ||
775 | DBGINFO(("%s set_termios\n", tty->driver->name)); | |
776 | ||
705b6c7b PF |
777 | change_params(info); |
778 | ||
779 | /* Handle transition to B0 status */ | |
780 | if (old_termios->c_cflag & CBAUD && | |
781 | !(tty->termios->c_cflag & CBAUD)) { | |
782 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
783 | spin_lock_irqsave(&info->lock,flags); | |
784 | set_signals(info); | |
785 | spin_unlock_irqrestore(&info->lock,flags); | |
786 | } | |
787 | ||
788 | /* Handle transition away from B0 status */ | |
789 | if (!(old_termios->c_cflag & CBAUD) && | |
790 | tty->termios->c_cflag & CBAUD) { | |
791 | info->signals |= SerialSignal_DTR; | |
792 | if (!(tty->termios->c_cflag & CRTSCTS) || | |
793 | !test_bit(TTY_THROTTLED, &tty->flags)) { | |
794 | info->signals |= SerialSignal_RTS; | |
795 | } | |
796 | spin_lock_irqsave(&info->lock,flags); | |
797 | set_signals(info); | |
798 | spin_unlock_irqrestore(&info->lock,flags); | |
799 | } | |
800 | ||
801 | /* Handle turning off CRTSCTS */ | |
802 | if (old_termios->c_cflag & CRTSCTS && | |
803 | !(tty->termios->c_cflag & CRTSCTS)) { | |
804 | tty->hw_stopped = 0; | |
805 | tx_release(tty); | |
806 | } | |
807 | } | |
808 | ||
ce89294c PF |
809 | static void update_tx_timer(struct slgt_info *info) |
810 | { | |
811 | /* | |
812 | * use worst case speed of 1200bps to calculate transmit timeout | |
813 | * based on data in buffers (tbuf_bytes) and FIFO (128 bytes) | |
814 | */ | |
815 | if (info->params.mode == MGSL_MODE_HDLC) { | |
816 | int timeout = (tbuf_bytes(info) * 7) + 1000; | |
817 | mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout)); | |
818 | } | |
819 | } | |
820 | ||
705b6c7b PF |
821 | static int write(struct tty_struct *tty, |
822 | const unsigned char *buf, int count) | |
823 | { | |
824 | int ret = 0; | |
825 | struct slgt_info *info = tty->driver_data; | |
826 | unsigned long flags; | |
827 | ||
828 | if (sanity_check(info, tty->name, "write")) | |
de538eb3 PF |
829 | return -EIO; |
830 | ||
705b6c7b PF |
831 | DBGINFO(("%s write count=%d\n", info->device_name, count)); |
832 | ||
de538eb3 PF |
833 | if (!info->tx_buf || (count > info->max_frame_size)) |
834 | return -EIO; | |
705b6c7b | 835 | |
de538eb3 PF |
836 | if (!count || tty->stopped || tty->hw_stopped) |
837 | return 0; | |
705b6c7b | 838 | |
de538eb3 | 839 | spin_lock_irqsave(&info->lock, flags); |
705b6c7b | 840 | |
de538eb3 | 841 | if (info->tx_count) { |
8a38c285 | 842 | /* send accumulated data from send_char() */ |
de538eb3 PF |
843 | if (!tx_load(info, info->tx_buf, info->tx_count)) |
844 | goto cleanup; | |
845 | info->tx_count = 0; | |
705b6c7b PF |
846 | } |
847 | ||
de538eb3 PF |
848 | if (tx_load(info, buf, count)) |
849 | ret = count; | |
705b6c7b PF |
850 | |
851 | cleanup: | |
de538eb3 | 852 | spin_unlock_irqrestore(&info->lock, flags); |
705b6c7b PF |
853 | DBGINFO(("%s write rc=%d\n", info->device_name, ret)); |
854 | return ret; | |
855 | } | |
856 | ||
55da7789 | 857 | static int put_char(struct tty_struct *tty, unsigned char ch) |
705b6c7b PF |
858 | { |
859 | struct slgt_info *info = tty->driver_data; | |
860 | unsigned long flags; | |
6c82c415 | 861 | int ret = 0; |
705b6c7b PF |
862 | |
863 | if (sanity_check(info, tty->name, "put_char")) | |
55da7789 | 864 | return 0; |
705b6c7b | 865 | DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); |
326f28e9 | 866 | if (!info->tx_buf) |
55da7789 | 867 | return 0; |
705b6c7b | 868 | spin_lock_irqsave(&info->lock,flags); |
de538eb3 | 869 | if (info->tx_count < info->max_frame_size) { |
705b6c7b | 870 | info->tx_buf[info->tx_count++] = ch; |
55da7789 AC |
871 | ret = 1; |
872 | } | |
705b6c7b | 873 | spin_unlock_irqrestore(&info->lock,flags); |
55da7789 | 874 | return ret; |
705b6c7b PF |
875 | } |
876 | ||
877 | static void send_xchar(struct tty_struct *tty, char ch) | |
878 | { | |
879 | struct slgt_info *info = tty->driver_data; | |
880 | unsigned long flags; | |
881 | ||
882 | if (sanity_check(info, tty->name, "send_xchar")) | |
883 | return; | |
884 | DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); | |
885 | info->x_char = ch; | |
886 | if (ch) { | |
887 | spin_lock_irqsave(&info->lock,flags); | |
888 | if (!info->tx_enabled) | |
889 | tx_start(info); | |
890 | spin_unlock_irqrestore(&info->lock,flags); | |
891 | } | |
892 | } | |
893 | ||
894 | static void wait_until_sent(struct tty_struct *tty, int timeout) | |
895 | { | |
896 | struct slgt_info *info = tty->driver_data; | |
897 | unsigned long orig_jiffies, char_time; | |
898 | ||
899 | if (!info ) | |
900 | return; | |
901 | if (sanity_check(info, tty->name, "wait_until_sent")) | |
902 | return; | |
903 | DBGINFO(("%s wait_until_sent entry\n", info->device_name)); | |
8fb06c77 | 904 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
705b6c7b PF |
905 | goto exit; |
906 | ||
907 | orig_jiffies = jiffies; | |
908 | ||
909 | /* Set check interval to 1/5 of estimated time to | |
910 | * send a character, and make it at least 1. The check | |
911 | * interval should also be less than the timeout. | |
912 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
913 | */ | |
914 | ||
915 | if (info->params.data_rate) { | |
916 | char_time = info->timeout/(32 * 5); | |
917 | if (!char_time) | |
918 | char_time++; | |
919 | } else | |
920 | char_time = 1; | |
921 | ||
922 | if (timeout) | |
923 | char_time = min_t(unsigned long, char_time, timeout); | |
924 | ||
925 | while (info->tx_active) { | |
926 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
927 | if (signal_pending(current)) | |
928 | break; | |
929 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
930 | break; | |
931 | } | |
705b6c7b PF |
932 | exit: |
933 | DBGINFO(("%s wait_until_sent exit\n", info->device_name)); | |
934 | } | |
935 | ||
936 | static int write_room(struct tty_struct *tty) | |
937 | { | |
938 | struct slgt_info *info = tty->driver_data; | |
939 | int ret; | |
940 | ||
941 | if (sanity_check(info, tty->name, "write_room")) | |
942 | return 0; | |
943 | ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; | |
944 | DBGINFO(("%s write_room=%d\n", info->device_name, ret)); | |
945 | return ret; | |
946 | } | |
947 | ||
948 | static void flush_chars(struct tty_struct *tty) | |
949 | { | |
950 | struct slgt_info *info = tty->driver_data; | |
951 | unsigned long flags; | |
952 | ||
953 | if (sanity_check(info, tty->name, "flush_chars")) | |
954 | return; | |
955 | DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); | |
956 | ||
957 | if (info->tx_count <= 0 || tty->stopped || | |
958 | tty->hw_stopped || !info->tx_buf) | |
959 | return; | |
960 | ||
961 | DBGINFO(("%s flush_chars start transmit\n", info->device_name)); | |
962 | ||
963 | spin_lock_irqsave(&info->lock,flags); | |
de538eb3 PF |
964 | if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) |
965 | info->tx_count = 0; | |
705b6c7b PF |
966 | spin_unlock_irqrestore(&info->lock,flags); |
967 | } | |
968 | ||
969 | static void flush_buffer(struct tty_struct *tty) | |
970 | { | |
971 | struct slgt_info *info = tty->driver_data; | |
972 | unsigned long flags; | |
973 | ||
974 | if (sanity_check(info, tty->name, "flush_buffer")) | |
975 | return; | |
976 | DBGINFO(("%s flush_buffer\n", info->device_name)); | |
977 | ||
de538eb3 PF |
978 | spin_lock_irqsave(&info->lock, flags); |
979 | info->tx_count = 0; | |
980 | spin_unlock_irqrestore(&info->lock, flags); | |
705b6c7b | 981 | |
705b6c7b PF |
982 | tty_wakeup(tty); |
983 | } | |
984 | ||
985 | /* | |
986 | * throttle (stop) transmitter | |
987 | */ | |
988 | static void tx_hold(struct tty_struct *tty) | |
989 | { | |
990 | struct slgt_info *info = tty->driver_data; | |
991 | unsigned long flags; | |
992 | ||
993 | if (sanity_check(info, tty->name, "tx_hold")) | |
994 | return; | |
995 | DBGINFO(("%s tx_hold\n", info->device_name)); | |
996 | spin_lock_irqsave(&info->lock,flags); | |
997 | if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) | |
998 | tx_stop(info); | |
999 | spin_unlock_irqrestore(&info->lock,flags); | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * release (start) transmitter | |
1004 | */ | |
1005 | static void tx_release(struct tty_struct *tty) | |
1006 | { | |
1007 | struct slgt_info *info = tty->driver_data; | |
1008 | unsigned long flags; | |
1009 | ||
1010 | if (sanity_check(info, tty->name, "tx_release")) | |
1011 | return; | |
1012 | DBGINFO(("%s tx_release\n", info->device_name)); | |
de538eb3 PF |
1013 | spin_lock_irqsave(&info->lock, flags); |
1014 | if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) | |
1015 | info->tx_count = 0; | |
1016 | spin_unlock_irqrestore(&info->lock, flags); | |
705b6c7b PF |
1017 | } |
1018 | ||
1019 | /* | |
1020 | * Service an IOCTL request | |
1021 | * | |
1022 | * Arguments | |
1023 | * | |
1024 | * tty pointer to tty instance data | |
1025 | * file pointer to associated file object for device | |
1026 | * cmd IOCTL command code | |
1027 | * arg command argument/context | |
1028 | * | |
1029 | * Return 0 if success, otherwise error code | |
1030 | */ | |
1031 | static int ioctl(struct tty_struct *tty, struct file *file, | |
1032 | unsigned int cmd, unsigned long arg) | |
1033 | { | |
1034 | struct slgt_info *info = tty->driver_data; | |
705b6c7b | 1035 | void __user *argp = (void __user *)arg; |
1f8cabb7 | 1036 | int ret; |
705b6c7b PF |
1037 | |
1038 | if (sanity_check(info, tty->name, "ioctl")) | |
1039 | return -ENODEV; | |
1040 | DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1041 | ||
1042 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
0587102c | 1043 | (cmd != TIOCMIWAIT)) { |
705b6c7b PF |
1044 | if (tty->flags & (1 << TTY_IO_ERROR)) |
1045 | return -EIO; | |
1046 | } | |
1047 | ||
f602501d AC |
1048 | switch (cmd) { |
1049 | case MGSL_IOCWAITEVENT: | |
1050 | return wait_mgsl_event(info, argp); | |
1051 | case TIOCMIWAIT: | |
1052 | return modem_input_wait(info,(int)arg); | |
f602501d AC |
1053 | case MGSL_IOCSGPIO: |
1054 | return set_gpio(info, argp); | |
1055 | case MGSL_IOCGGPIO: | |
1056 | return get_gpio(info, argp); | |
1057 | case MGSL_IOCWAITGPIO: | |
1058 | return wait_gpio(info, argp); | |
1059 | } | |
1060 | mutex_lock(&info->port.mutex); | |
705b6c7b PF |
1061 | switch (cmd) { |
1062 | case MGSL_IOCGPARAMS: | |
1f8cabb7 AC |
1063 | ret = get_params(info, argp); |
1064 | break; | |
705b6c7b | 1065 | case MGSL_IOCSPARAMS: |
1f8cabb7 AC |
1066 | ret = set_params(info, argp); |
1067 | break; | |
705b6c7b | 1068 | case MGSL_IOCGTXIDLE: |
1f8cabb7 AC |
1069 | ret = get_txidle(info, argp); |
1070 | break; | |
705b6c7b | 1071 | case MGSL_IOCSTXIDLE: |
1f8cabb7 AC |
1072 | ret = set_txidle(info, (int)arg); |
1073 | break; | |
705b6c7b | 1074 | case MGSL_IOCTXENABLE: |
1f8cabb7 AC |
1075 | ret = tx_enable(info, (int)arg); |
1076 | break; | |
705b6c7b | 1077 | case MGSL_IOCRXENABLE: |
1f8cabb7 AC |
1078 | ret = rx_enable(info, (int)arg); |
1079 | break; | |
705b6c7b | 1080 | case MGSL_IOCTXABORT: |
1f8cabb7 AC |
1081 | ret = tx_abort(info); |
1082 | break; | |
705b6c7b | 1083 | case MGSL_IOCGSTATS: |
1f8cabb7 AC |
1084 | ret = get_stats(info, argp); |
1085 | break; | |
705b6c7b | 1086 | case MGSL_IOCGIF: |
1f8cabb7 AC |
1087 | ret = get_interface(info, argp); |
1088 | break; | |
705b6c7b | 1089 | case MGSL_IOCSIF: |
1f8cabb7 AC |
1090 | ret = set_interface(info,(int)arg); |
1091 | break; | |
705b6c7b | 1092 | default: |
1f8cabb7 | 1093 | ret = -ENOIOCTLCMD; |
705b6c7b | 1094 | } |
f602501d | 1095 | mutex_unlock(&info->port.mutex); |
1f8cabb7 | 1096 | return ret; |
705b6c7b PF |
1097 | } |
1098 | ||
0587102c AC |
1099 | static int get_icount(struct tty_struct *tty, |
1100 | struct serial_icounter_struct *icount) | |
1101 | ||
1102 | { | |
1103 | struct slgt_info *info = tty->driver_data; | |
1104 | struct mgsl_icount cnow; /* kernel counter temps */ | |
1105 | unsigned long flags; | |
1106 | ||
1107 | spin_lock_irqsave(&info->lock,flags); | |
1108 | cnow = info->icount; | |
1109 | spin_unlock_irqrestore(&info->lock,flags); | |
1110 | ||
1111 | icount->cts = cnow.cts; | |
1112 | icount->dsr = cnow.dsr; | |
1113 | icount->rng = cnow.rng; | |
1114 | icount->dcd = cnow.dcd; | |
1115 | icount->rx = cnow.rx; | |
1116 | icount->tx = cnow.tx; | |
1117 | icount->frame = cnow.frame; | |
1118 | icount->overrun = cnow.overrun; | |
1119 | icount->parity = cnow.parity; | |
1120 | icount->brk = cnow.brk; | |
1121 | icount->buf_overrun = cnow.buf_overrun; | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
2acdb169 PF |
1126 | /* |
1127 | * support for 32 bit ioctl calls on 64 bit systems | |
1128 | */ | |
1129 | #ifdef CONFIG_COMPAT | |
1130 | static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) | |
1131 | { | |
1132 | struct MGSL_PARAMS32 tmp_params; | |
1133 | ||
1134 | DBGINFO(("%s get_params32\n", info->device_name)); | |
ed77ed61 | 1135 | memset(&tmp_params, 0, sizeof(tmp_params)); |
2acdb169 PF |
1136 | tmp_params.mode = (compat_ulong_t)info->params.mode; |
1137 | tmp_params.loopback = info->params.loopback; | |
1138 | tmp_params.flags = info->params.flags; | |
1139 | tmp_params.encoding = info->params.encoding; | |
1140 | tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; | |
1141 | tmp_params.addr_filter = info->params.addr_filter; | |
1142 | tmp_params.crc_type = info->params.crc_type; | |
1143 | tmp_params.preamble_length = info->params.preamble_length; | |
1144 | tmp_params.preamble = info->params.preamble; | |
1145 | tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; | |
1146 | tmp_params.data_bits = info->params.data_bits; | |
1147 | tmp_params.stop_bits = info->params.stop_bits; | |
1148 | tmp_params.parity = info->params.parity; | |
1149 | if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) | |
1150 | return -EFAULT; | |
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) | |
1155 | { | |
1156 | struct MGSL_PARAMS32 tmp_params; | |
1157 | ||
1158 | DBGINFO(("%s set_params32\n", info->device_name)); | |
1159 | if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) | |
1160 | return -EFAULT; | |
1161 | ||
1162 | spin_lock(&info->lock); | |
1f80769f PF |
1163 | if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) { |
1164 | info->base_clock = tmp_params.clock_speed; | |
1165 | } else { | |
1166 | info->params.mode = tmp_params.mode; | |
1167 | info->params.loopback = tmp_params.loopback; | |
1168 | info->params.flags = tmp_params.flags; | |
1169 | info->params.encoding = tmp_params.encoding; | |
1170 | info->params.clock_speed = tmp_params.clock_speed; | |
1171 | info->params.addr_filter = tmp_params.addr_filter; | |
1172 | info->params.crc_type = tmp_params.crc_type; | |
1173 | info->params.preamble_length = tmp_params.preamble_length; | |
1174 | info->params.preamble = tmp_params.preamble; | |
1175 | info->params.data_rate = tmp_params.data_rate; | |
1176 | info->params.data_bits = tmp_params.data_bits; | |
1177 | info->params.stop_bits = tmp_params.stop_bits; | |
1178 | info->params.parity = tmp_params.parity; | |
1179 | } | |
2acdb169 PF |
1180 | spin_unlock(&info->lock); |
1181 | ||
1f80769f | 1182 | program_hw(info); |
2acdb169 PF |
1183 | |
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file, | |
1188 | unsigned int cmd, unsigned long arg) | |
1189 | { | |
1190 | struct slgt_info *info = tty->driver_data; | |
1191 | int rc = -ENOIOCTLCMD; | |
1192 | ||
1193 | if (sanity_check(info, tty->name, "compat_ioctl")) | |
1194 | return -ENODEV; | |
1195 | DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1196 | ||
1197 | switch (cmd) { | |
1198 | ||
1199 | case MGSL_IOCSPARAMS32: | |
1200 | rc = set_params32(info, compat_ptr(arg)); | |
1201 | break; | |
1202 | ||
1203 | case MGSL_IOCGPARAMS32: | |
1204 | rc = get_params32(info, compat_ptr(arg)); | |
1205 | break; | |
1206 | ||
1207 | case MGSL_IOCGPARAMS: | |
1208 | case MGSL_IOCSPARAMS: | |
1209 | case MGSL_IOCGTXIDLE: | |
1210 | case MGSL_IOCGSTATS: | |
1211 | case MGSL_IOCWAITEVENT: | |
1212 | case MGSL_IOCGIF: | |
1213 | case MGSL_IOCSGPIO: | |
1214 | case MGSL_IOCGGPIO: | |
1215 | case MGSL_IOCWAITGPIO: | |
2acdb169 PF |
1216 | case MGSL_IOCSTXIDLE: |
1217 | case MGSL_IOCTXENABLE: | |
1218 | case MGSL_IOCRXENABLE: | |
1219 | case MGSL_IOCTXABORT: | |
1220 | case TIOCMIWAIT: | |
1221 | case MGSL_IOCSIF: | |
1222 | rc = ioctl(tty, file, cmd, arg); | |
1223 | break; | |
1224 | } | |
1225 | ||
1226 | DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); | |
1227 | return rc; | |
1228 | } | |
1229 | #else | |
1230 | #define slgt_compat_ioctl NULL | |
1231 | #endif /* ifdef CONFIG_COMPAT */ | |
1232 | ||
705b6c7b PF |
1233 | /* |
1234 | * proc fs support | |
1235 | */ | |
a18c56e5 | 1236 | static inline void line_info(struct seq_file *m, struct slgt_info *info) |
705b6c7b PF |
1237 | { |
1238 | char stat_buf[30]; | |
705b6c7b PF |
1239 | unsigned long flags; |
1240 | ||
a18c56e5 | 1241 | seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", |
705b6c7b PF |
1242 | info->device_name, info->phys_reg_addr, |
1243 | info->irq_level, info->max_frame_size); | |
1244 | ||
1245 | /* output current serial signal states */ | |
1246 | spin_lock_irqsave(&info->lock,flags); | |
1247 | get_signals(info); | |
1248 | spin_unlock_irqrestore(&info->lock,flags); | |
1249 | ||
1250 | stat_buf[0] = 0; | |
1251 | stat_buf[1] = 0; | |
1252 | if (info->signals & SerialSignal_RTS) | |
1253 | strcat(stat_buf, "|RTS"); | |
1254 | if (info->signals & SerialSignal_CTS) | |
1255 | strcat(stat_buf, "|CTS"); | |
1256 | if (info->signals & SerialSignal_DTR) | |
1257 | strcat(stat_buf, "|DTR"); | |
1258 | if (info->signals & SerialSignal_DSR) | |
1259 | strcat(stat_buf, "|DSR"); | |
1260 | if (info->signals & SerialSignal_DCD) | |
1261 | strcat(stat_buf, "|CD"); | |
1262 | if (info->signals & SerialSignal_RI) | |
1263 | strcat(stat_buf, "|RI"); | |
1264 | ||
1265 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
a18c56e5 | 1266 | seq_printf(m, "\tHDLC txok:%d rxok:%d", |
705b6c7b PF |
1267 | info->icount.txok, info->icount.rxok); |
1268 | if (info->icount.txunder) | |
a18c56e5 | 1269 | seq_printf(m, " txunder:%d", info->icount.txunder); |
705b6c7b | 1270 | if (info->icount.txabort) |
a18c56e5 | 1271 | seq_printf(m, " txabort:%d", info->icount.txabort); |
705b6c7b | 1272 | if (info->icount.rxshort) |
a18c56e5 | 1273 | seq_printf(m, " rxshort:%d", info->icount.rxshort); |
705b6c7b | 1274 | if (info->icount.rxlong) |
a18c56e5 | 1275 | seq_printf(m, " rxlong:%d", info->icount.rxlong); |
705b6c7b | 1276 | if (info->icount.rxover) |
a18c56e5 | 1277 | seq_printf(m, " rxover:%d", info->icount.rxover); |
705b6c7b | 1278 | if (info->icount.rxcrc) |
a18c56e5 | 1279 | seq_printf(m, " rxcrc:%d", info->icount.rxcrc); |
705b6c7b | 1280 | } else { |
a18c56e5 | 1281 | seq_printf(m, "\tASYNC tx:%d rx:%d", |
705b6c7b PF |
1282 | info->icount.tx, info->icount.rx); |
1283 | if (info->icount.frame) | |
a18c56e5 | 1284 | seq_printf(m, " fe:%d", info->icount.frame); |
705b6c7b | 1285 | if (info->icount.parity) |
a18c56e5 | 1286 | seq_printf(m, " pe:%d", info->icount.parity); |
705b6c7b | 1287 | if (info->icount.brk) |
a18c56e5 | 1288 | seq_printf(m, " brk:%d", info->icount.brk); |
705b6c7b | 1289 | if (info->icount.overrun) |
a18c56e5 | 1290 | seq_printf(m, " oe:%d", info->icount.overrun); |
705b6c7b PF |
1291 | } |
1292 | ||
1293 | /* Append serial signal status to end */ | |
a18c56e5 | 1294 | seq_printf(m, " %s\n", stat_buf+1); |
705b6c7b | 1295 | |
a18c56e5 | 1296 | seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", |
705b6c7b PF |
1297 | info->tx_active,info->bh_requested,info->bh_running, |
1298 | info->pending_bh); | |
705b6c7b PF |
1299 | } |
1300 | ||
1301 | /* Called to print information about devices | |
1302 | */ | |
a18c56e5 | 1303 | static int synclink_gt_proc_show(struct seq_file *m, void *v) |
705b6c7b | 1304 | { |
705b6c7b PF |
1305 | struct slgt_info *info; |
1306 | ||
a18c56e5 | 1307 | seq_puts(m, "synclink_gt driver\n"); |
705b6c7b PF |
1308 | |
1309 | info = slgt_device_list; | |
1310 | while( info ) { | |
a18c56e5 | 1311 | line_info(m, info); |
705b6c7b PF |
1312 | info = info->next_device; |
1313 | } | |
a18c56e5 AD |
1314 | return 0; |
1315 | } | |
705b6c7b | 1316 | |
a18c56e5 AD |
1317 | static int synclink_gt_proc_open(struct inode *inode, struct file *file) |
1318 | { | |
1319 | return single_open(file, synclink_gt_proc_show, NULL); | |
705b6c7b PF |
1320 | } |
1321 | ||
a18c56e5 AD |
1322 | static const struct file_operations synclink_gt_proc_fops = { |
1323 | .owner = THIS_MODULE, | |
1324 | .open = synclink_gt_proc_open, | |
1325 | .read = seq_read, | |
1326 | .llseek = seq_lseek, | |
1327 | .release = single_release, | |
1328 | }; | |
1329 | ||
705b6c7b PF |
1330 | /* |
1331 | * return count of bytes in transmit buffer | |
1332 | */ | |
1333 | static int chars_in_buffer(struct tty_struct *tty) | |
1334 | { | |
1335 | struct slgt_info *info = tty->driver_data; | |
403214d0 | 1336 | int count; |
705b6c7b PF |
1337 | if (sanity_check(info, tty->name, "chars_in_buffer")) |
1338 | return 0; | |
403214d0 PF |
1339 | count = tbuf_bytes(info); |
1340 | DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count)); | |
1341 | return count; | |
705b6c7b PF |
1342 | } |
1343 | ||
1344 | /* | |
1345 | * signal remote device to throttle send data (our receive data) | |
1346 | */ | |
1347 | static void throttle(struct tty_struct * tty) | |
1348 | { | |
1349 | struct slgt_info *info = tty->driver_data; | |
1350 | unsigned long flags; | |
1351 | ||
1352 | if (sanity_check(info, tty->name, "throttle")) | |
1353 | return; | |
1354 | DBGINFO(("%s throttle\n", info->device_name)); | |
1355 | if (I_IXOFF(tty)) | |
1356 | send_xchar(tty, STOP_CHAR(tty)); | |
1357 | if (tty->termios->c_cflag & CRTSCTS) { | |
1358 | spin_lock_irqsave(&info->lock,flags); | |
1359 | info->signals &= ~SerialSignal_RTS; | |
1360 | set_signals(info); | |
1361 | spin_unlock_irqrestore(&info->lock,flags); | |
1362 | } | |
1363 | } | |
1364 | ||
1365 | /* | |
1366 | * signal remote device to stop throttling send data (our receive data) | |
1367 | */ | |
1368 | static void unthrottle(struct tty_struct * tty) | |
1369 | { | |
1370 | struct slgt_info *info = tty->driver_data; | |
1371 | unsigned long flags; | |
1372 | ||
1373 | if (sanity_check(info, tty->name, "unthrottle")) | |
1374 | return; | |
1375 | DBGINFO(("%s unthrottle\n", info->device_name)); | |
1376 | if (I_IXOFF(tty)) { | |
1377 | if (info->x_char) | |
1378 | info->x_char = 0; | |
1379 | else | |
1380 | send_xchar(tty, START_CHAR(tty)); | |
1381 | } | |
1382 | if (tty->termios->c_cflag & CRTSCTS) { | |
1383 | spin_lock_irqsave(&info->lock,flags); | |
1384 | info->signals |= SerialSignal_RTS; | |
1385 | set_signals(info); | |
1386 | spin_unlock_irqrestore(&info->lock,flags); | |
1387 | } | |
1388 | } | |
1389 | ||
1390 | /* | |
1391 | * set or clear transmit break condition | |
1392 | * break_state -1=set break condition, 0=clear | |
1393 | */ | |
9e98966c | 1394 | static int set_break(struct tty_struct *tty, int break_state) |
705b6c7b PF |
1395 | { |
1396 | struct slgt_info *info = tty->driver_data; | |
1397 | unsigned short value; | |
1398 | unsigned long flags; | |
1399 | ||
1400 | if (sanity_check(info, tty->name, "set_break")) | |
9e98966c | 1401 | return -EINVAL; |
705b6c7b PF |
1402 | DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); |
1403 | ||
1404 | spin_lock_irqsave(&info->lock,flags); | |
1405 | value = rd_reg16(info, TCR); | |
1406 | if (break_state == -1) | |
1407 | value |= BIT6; | |
1408 | else | |
1409 | value &= ~BIT6; | |
1410 | wr_reg16(info, TCR, value); | |
1411 | spin_unlock_irqrestore(&info->lock,flags); | |
9e98966c | 1412 | return 0; |
705b6c7b PF |
1413 | } |
1414 | ||
af69c7f9 | 1415 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
1416 | |
1417 | /** | |
1418 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
1419 | * set encoding and frame check sequence (FCS) options | |
1420 | * | |
1421 | * dev pointer to network device structure | |
1422 | * encoding serial encoding setting | |
1423 | * parity FCS setting | |
1424 | * | |
1425 | * returns 0 if success, otherwise error code | |
1426 | */ | |
1427 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
1428 | unsigned short parity) | |
1429 | { | |
1430 | struct slgt_info *info = dev_to_port(dev); | |
1431 | unsigned char new_encoding; | |
1432 | unsigned short new_crctype; | |
1433 | ||
1434 | /* return error if TTY interface open */ | |
8fb06c77 | 1435 | if (info->port.count) |
705b6c7b PF |
1436 | return -EBUSY; |
1437 | ||
1438 | DBGINFO(("%s hdlcdev_attach\n", info->device_name)); | |
1439 | ||
1440 | switch (encoding) | |
1441 | { | |
1442 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
1443 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
1444 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
1445 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
1446 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
1447 | default: return -EINVAL; | |
1448 | } | |
1449 | ||
1450 | switch (parity) | |
1451 | { | |
1452 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
1453 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
1454 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
1455 | default: return -EINVAL; | |
1456 | } | |
1457 | ||
1458 | info->params.encoding = new_encoding; | |
53b3531b | 1459 | info->params.crc_type = new_crctype; |
705b6c7b PF |
1460 | |
1461 | /* if network interface up, reprogram hardware */ | |
1462 | if (info->netcount) | |
1463 | program_hw(info); | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | /** | |
1469 | * called by generic HDLC layer to send frame | |
1470 | * | |
1471 | * skb socket buffer containing HDLC frame | |
1472 | * dev pointer to network device structure | |
705b6c7b | 1473 | */ |
4c5d502d SH |
1474 | static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, |
1475 | struct net_device *dev) | |
705b6c7b PF |
1476 | { |
1477 | struct slgt_info *info = dev_to_port(dev); | |
705b6c7b PF |
1478 | unsigned long flags; |
1479 | ||
1480 | DBGINFO(("%s hdlc_xmit\n", dev->name)); | |
1481 | ||
de538eb3 PF |
1482 | if (!skb->len) |
1483 | return NETDEV_TX_OK; | |
1484 | ||
705b6c7b PF |
1485 | /* stop sending until this frame completes */ |
1486 | netif_stop_queue(dev); | |
1487 | ||
705b6c7b | 1488 | /* update network statistics */ |
198191c4 KH |
1489 | dev->stats.tx_packets++; |
1490 | dev->stats.tx_bytes += skb->len; | |
705b6c7b | 1491 | |
705b6c7b PF |
1492 | /* save start time for transmit timeout detection */ |
1493 | dev->trans_start = jiffies; | |
1494 | ||
de538eb3 PF |
1495 | spin_lock_irqsave(&info->lock, flags); |
1496 | tx_load(info, skb->data, skb->len); | |
1497 | spin_unlock_irqrestore(&info->lock, flags); | |
1498 | ||
1499 | /* done with socket buffer, so free it */ | |
1500 | dev_kfree_skb(skb); | |
705b6c7b | 1501 | |
4c5d502d | 1502 | return NETDEV_TX_OK; |
705b6c7b PF |
1503 | } |
1504 | ||
1505 | /** | |
1506 | * called by network layer when interface enabled | |
1507 | * claim resources and initialize hardware | |
1508 | * | |
1509 | * dev pointer to network device structure | |
1510 | * | |
1511 | * returns 0 if success, otherwise error code | |
1512 | */ | |
1513 | static int hdlcdev_open(struct net_device *dev) | |
1514 | { | |
1515 | struct slgt_info *info = dev_to_port(dev); | |
1516 | int rc; | |
1517 | unsigned long flags; | |
1518 | ||
d4c63b7c PF |
1519 | if (!try_module_get(THIS_MODULE)) |
1520 | return -EBUSY; | |
1521 | ||
705b6c7b PF |
1522 | DBGINFO(("%s hdlcdev_open\n", dev->name)); |
1523 | ||
1524 | /* generic HDLC layer open processing */ | |
1525 | if ((rc = hdlc_open(dev))) | |
1526 | return rc; | |
1527 | ||
1528 | /* arbitrate between network and tty opens */ | |
1529 | spin_lock_irqsave(&info->netlock, flags); | |
8fb06c77 | 1530 | if (info->port.count != 0 || info->netcount != 0) { |
705b6c7b PF |
1531 | DBGINFO(("%s hdlc_open busy\n", dev->name)); |
1532 | spin_unlock_irqrestore(&info->netlock, flags); | |
1533 | return -EBUSY; | |
1534 | } | |
1535 | info->netcount=1; | |
1536 | spin_unlock_irqrestore(&info->netlock, flags); | |
1537 | ||
1538 | /* claim resources and init adapter */ | |
1539 | if ((rc = startup(info)) != 0) { | |
1540 | spin_lock_irqsave(&info->netlock, flags); | |
1541 | info->netcount=0; | |
1542 | spin_unlock_irqrestore(&info->netlock, flags); | |
1543 | return rc; | |
1544 | } | |
1545 | ||
1546 | /* assert DTR and RTS, apply hardware settings */ | |
1547 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
1548 | program_hw(info); | |
1549 | ||
1550 | /* enable network layer transmit */ | |
1551 | dev->trans_start = jiffies; | |
1552 | netif_start_queue(dev); | |
1553 | ||
1554 | /* inform generic HDLC layer of current DCD status */ | |
1555 | spin_lock_irqsave(&info->lock, flags); | |
1556 | get_signals(info); | |
1557 | spin_unlock_irqrestore(&info->lock, flags); | |
fbeff3c1 KH |
1558 | if (info->signals & SerialSignal_DCD) |
1559 | netif_carrier_on(dev); | |
1560 | else | |
1561 | netif_carrier_off(dev); | |
705b6c7b PF |
1562 | return 0; |
1563 | } | |
1564 | ||
1565 | /** | |
1566 | * called by network layer when interface is disabled | |
1567 | * shutdown hardware and release resources | |
1568 | * | |
1569 | * dev pointer to network device structure | |
1570 | * | |
1571 | * returns 0 if success, otherwise error code | |
1572 | */ | |
1573 | static int hdlcdev_close(struct net_device *dev) | |
1574 | { | |
1575 | struct slgt_info *info = dev_to_port(dev); | |
1576 | unsigned long flags; | |
1577 | ||
1578 | DBGINFO(("%s hdlcdev_close\n", dev->name)); | |
1579 | ||
1580 | netif_stop_queue(dev); | |
1581 | ||
1582 | /* shutdown adapter and release resources */ | |
1583 | shutdown(info); | |
1584 | ||
1585 | hdlc_close(dev); | |
1586 | ||
1587 | spin_lock_irqsave(&info->netlock, flags); | |
1588 | info->netcount=0; | |
1589 | spin_unlock_irqrestore(&info->netlock, flags); | |
1590 | ||
d4c63b7c | 1591 | module_put(THIS_MODULE); |
705b6c7b PF |
1592 | return 0; |
1593 | } | |
1594 | ||
1595 | /** | |
1596 | * called by network layer to process IOCTL call to network device | |
1597 | * | |
1598 | * dev pointer to network device structure | |
1599 | * ifr pointer to network interface request structure | |
1600 | * cmd IOCTL command code | |
1601 | * | |
1602 | * returns 0 if success, otherwise error code | |
1603 | */ | |
1604 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1605 | { | |
1606 | const size_t size = sizeof(sync_serial_settings); | |
1607 | sync_serial_settings new_line; | |
1608 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1609 | struct slgt_info *info = dev_to_port(dev); | |
1610 | unsigned int flags; | |
1611 | ||
1612 | DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); | |
1613 | ||
1614 | /* return error if TTY interface open */ | |
8fb06c77 | 1615 | if (info->port.count) |
705b6c7b PF |
1616 | return -EBUSY; |
1617 | ||
1618 | if (cmd != SIOCWANDEV) | |
1619 | return hdlc_ioctl(dev, ifr, cmd); | |
1620 | ||
ed77ed61 VK |
1621 | memset(&new_line, 0, sizeof(new_line)); |
1622 | ||
705b6c7b PF |
1623 | switch(ifr->ifr_settings.type) { |
1624 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
1625 | ||
1626 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1627 | if (ifr->ifr_settings.size < size) { | |
1628 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1629 | return -ENOBUFS; | |
1630 | } | |
1631 | ||
1632 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1633 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1634 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1635 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1636 | ||
1637 | switch (flags){ | |
1638 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
1639 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
1640 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
1641 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
1642 | default: new_line.clock_type = CLOCK_DEFAULT; | |
1643 | } | |
1644 | ||
1645 | new_line.clock_rate = info->params.clock_speed; | |
1646 | new_line.loopback = info->params.loopback ? 1:0; | |
1647 | ||
1648 | if (copy_to_user(line, &new_line, size)) | |
1649 | return -EFAULT; | |
1650 | return 0; | |
1651 | ||
1652 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
1653 | ||
1654 | if(!capable(CAP_NET_ADMIN)) | |
1655 | return -EPERM; | |
1656 | if (copy_from_user(&new_line, line, size)) | |
1657 | return -EFAULT; | |
1658 | ||
1659 | switch (new_line.clock_type) | |
1660 | { | |
1661 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
1662 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
1663 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
1664 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
1665 | case CLOCK_DEFAULT: flags = info->params.flags & | |
1666 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1667 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1668 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1669 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
1670 | default: return -EINVAL; | |
1671 | } | |
1672 | ||
1673 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
1674 | return -EINVAL; | |
1675 | ||
1676 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1677 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1678 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1679 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1680 | info->params.flags |= flags; | |
1681 | ||
1682 | info->params.loopback = new_line.loopback; | |
1683 | ||
1684 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
1685 | info->params.clock_speed = new_line.clock_rate; | |
1686 | else | |
1687 | info->params.clock_speed = 0; | |
1688 | ||
1689 | /* if network interface up, reprogram hardware */ | |
1690 | if (info->netcount) | |
1691 | program_hw(info); | |
1692 | return 0; | |
1693 | ||
1694 | default: | |
1695 | return hdlc_ioctl(dev, ifr, cmd); | |
1696 | } | |
1697 | } | |
1698 | ||
1699 | /** | |
1700 | * called by network layer when transmit timeout is detected | |
1701 | * | |
1702 | * dev pointer to network device structure | |
1703 | */ | |
1704 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
1705 | { | |
1706 | struct slgt_info *info = dev_to_port(dev); | |
705b6c7b PF |
1707 | unsigned long flags; |
1708 | ||
1709 | DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); | |
1710 | ||
198191c4 KH |
1711 | dev->stats.tx_errors++; |
1712 | dev->stats.tx_aborted_errors++; | |
705b6c7b PF |
1713 | |
1714 | spin_lock_irqsave(&info->lock,flags); | |
1715 | tx_stop(info); | |
1716 | spin_unlock_irqrestore(&info->lock,flags); | |
1717 | ||
1718 | netif_wake_queue(dev); | |
1719 | } | |
1720 | ||
1721 | /** | |
1722 | * called by device driver when transmit completes | |
1723 | * reenable network layer transmit if stopped | |
1724 | * | |
1725 | * info pointer to device instance information | |
1726 | */ | |
1727 | static void hdlcdev_tx_done(struct slgt_info *info) | |
1728 | { | |
1729 | if (netif_queue_stopped(info->netdev)) | |
1730 | netif_wake_queue(info->netdev); | |
1731 | } | |
1732 | ||
1733 | /** | |
1734 | * called by device driver when frame received | |
1735 | * pass frame to network layer | |
1736 | * | |
1737 | * info pointer to device instance information | |
1738 | * buf pointer to buffer contianing frame data | |
1739 | * size count of data bytes in buf | |
1740 | */ | |
1741 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) | |
1742 | { | |
1743 | struct sk_buff *skb = dev_alloc_skb(size); | |
1744 | struct net_device *dev = info->netdev; | |
705b6c7b PF |
1745 | |
1746 | DBGINFO(("%s hdlcdev_rx\n", dev->name)); | |
1747 | ||
1748 | if (skb == NULL) { | |
1749 | DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); | |
198191c4 | 1750 | dev->stats.rx_dropped++; |
705b6c7b PF |
1751 | return; |
1752 | } | |
1753 | ||
198191c4 | 1754 | memcpy(skb_put(skb, size), buf, size); |
705b6c7b | 1755 | |
198191c4 | 1756 | skb->protocol = hdlc_type_trans(skb, dev); |
705b6c7b | 1757 | |
198191c4 KH |
1758 | dev->stats.rx_packets++; |
1759 | dev->stats.rx_bytes += size; | |
705b6c7b PF |
1760 | |
1761 | netif_rx(skb); | |
705b6c7b PF |
1762 | } |
1763 | ||
991990a1 KH |
1764 | static const struct net_device_ops hdlcdev_ops = { |
1765 | .ndo_open = hdlcdev_open, | |
1766 | .ndo_stop = hdlcdev_close, | |
1767 | .ndo_change_mtu = hdlc_change_mtu, | |
1768 | .ndo_start_xmit = hdlc_start_xmit, | |
1769 | .ndo_do_ioctl = hdlcdev_ioctl, | |
1770 | .ndo_tx_timeout = hdlcdev_tx_timeout, | |
1771 | }; | |
1772 | ||
705b6c7b PF |
1773 | /** |
1774 | * called by device driver when adding device instance | |
1775 | * do generic HDLC initialization | |
1776 | * | |
1777 | * info pointer to device instance information | |
1778 | * | |
1779 | * returns 0 if success, otherwise error code | |
1780 | */ | |
1781 | static int hdlcdev_init(struct slgt_info *info) | |
1782 | { | |
1783 | int rc; | |
1784 | struct net_device *dev; | |
1785 | hdlc_device *hdlc; | |
1786 | ||
1787 | /* allocate and initialize network and HDLC layer objects */ | |
1788 | ||
1789 | if (!(dev = alloc_hdlcdev(info))) { | |
1790 | printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); | |
1791 | return -ENOMEM; | |
1792 | } | |
1793 | ||
1794 | /* for network layer reporting purposes only */ | |
1795 | dev->mem_start = info->phys_reg_addr; | |
1796 | dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; | |
1797 | dev->irq = info->irq_level; | |
1798 | ||
1799 | /* network layer callbacks and settings */ | |
991990a1 KH |
1800 | dev->netdev_ops = &hdlcdev_ops; |
1801 | dev->watchdog_timeo = 10 * HZ; | |
705b6c7b PF |
1802 | dev->tx_queue_len = 50; |
1803 | ||
1804 | /* generic HDLC layer callbacks and settings */ | |
1805 | hdlc = dev_to_hdlc(dev); | |
1806 | hdlc->attach = hdlcdev_attach; | |
1807 | hdlc->xmit = hdlcdev_xmit; | |
1808 | ||
1809 | /* register objects with HDLC layer */ | |
1810 | if ((rc = register_hdlc_device(dev))) { | |
1811 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); | |
1812 | free_netdev(dev); | |
1813 | return rc; | |
1814 | } | |
1815 | ||
1816 | info->netdev = dev; | |
1817 | return 0; | |
1818 | } | |
1819 | ||
1820 | /** | |
1821 | * called by device driver when removing device instance | |
1822 | * do generic HDLC cleanup | |
1823 | * | |
1824 | * info pointer to device instance information | |
1825 | */ | |
1826 | static void hdlcdev_exit(struct slgt_info *info) | |
1827 | { | |
1828 | unregister_hdlc_device(info->netdev); | |
1829 | free_netdev(info->netdev); | |
1830 | info->netdev = NULL; | |
1831 | } | |
1832 | ||
1833 | #endif /* ifdef CONFIG_HDLC */ | |
1834 | ||
1835 | /* | |
1836 | * get async data from rx DMA buffers | |
1837 | */ | |
1838 | static void rx_async(struct slgt_info *info) | |
1839 | { | |
8fb06c77 | 1840 | struct tty_struct *tty = info->port.tty; |
705b6c7b PF |
1841 | struct mgsl_icount *icount = &info->icount; |
1842 | unsigned int start, end; | |
1843 | unsigned char *p; | |
1844 | unsigned char status; | |
1845 | struct slgt_desc *bufs = info->rbufs; | |
1846 | int i, count; | |
33f0f88f AC |
1847 | int chars = 0; |
1848 | int stat; | |
1849 | unsigned char ch; | |
705b6c7b PF |
1850 | |
1851 | start = end = info->rbuf_current; | |
1852 | ||
1853 | while(desc_complete(bufs[end])) { | |
1854 | count = desc_count(bufs[end]) - info->rbuf_index; | |
1855 | p = bufs[end].buf + info->rbuf_index; | |
1856 | ||
1857 | DBGISR(("%s rx_async count=%d\n", info->device_name, count)); | |
1858 | DBGDATA(info, p, count, "rx"); | |
1859 | ||
1860 | for(i=0 ; i < count; i+=2, p+=2) { | |
33f0f88f | 1861 | ch = *p; |
705b6c7b PF |
1862 | icount->rx++; |
1863 | ||
33f0f88f AC |
1864 | stat = 0; |
1865 | ||
202af6d5 PF |
1866 | if ((status = *(p+1) & (BIT1 + BIT0))) { |
1867 | if (status & BIT1) | |
705b6c7b | 1868 | icount->parity++; |
202af6d5 | 1869 | else if (status & BIT0) |
705b6c7b PF |
1870 | icount->frame++; |
1871 | /* discard char if tty control flags say so */ | |
1872 | if (status & info->ignore_status_mask) | |
1873 | continue; | |
202af6d5 | 1874 | if (status & BIT1) |
33f0f88f | 1875 | stat = TTY_PARITY; |
202af6d5 | 1876 | else if (status & BIT0) |
33f0f88f | 1877 | stat = TTY_FRAME; |
705b6c7b PF |
1878 | } |
1879 | if (tty) { | |
33f0f88f AC |
1880 | tty_insert_flip_char(tty, ch, stat); |
1881 | chars++; | |
705b6c7b PF |
1882 | } |
1883 | } | |
1884 | ||
1885 | if (i < count) { | |
1886 | /* receive buffer not completed */ | |
1887 | info->rbuf_index += i; | |
40565f19 | 1888 | mod_timer(&info->rx_timer, jiffies + 1); |
705b6c7b PF |
1889 | break; |
1890 | } | |
1891 | ||
1892 | info->rbuf_index = 0; | |
1893 | free_rbufs(info, end, end); | |
1894 | ||
1895 | if (++end == info->rbuf_count) | |
1896 | end = 0; | |
1897 | ||
1898 | /* if entire list searched then no frame available */ | |
1899 | if (end == start) | |
1900 | break; | |
1901 | } | |
1902 | ||
33f0f88f | 1903 | if (tty && chars) |
705b6c7b PF |
1904 | tty_flip_buffer_push(tty); |
1905 | } | |
1906 | ||
1907 | /* | |
1908 | * return next bottom half action to perform | |
1909 | */ | |
1910 | static int bh_action(struct slgt_info *info) | |
1911 | { | |
1912 | unsigned long flags; | |
1913 | int rc; | |
1914 | ||
1915 | spin_lock_irqsave(&info->lock,flags); | |
1916 | ||
1917 | if (info->pending_bh & BH_RECEIVE) { | |
1918 | info->pending_bh &= ~BH_RECEIVE; | |
1919 | rc = BH_RECEIVE; | |
1920 | } else if (info->pending_bh & BH_TRANSMIT) { | |
1921 | info->pending_bh &= ~BH_TRANSMIT; | |
1922 | rc = BH_TRANSMIT; | |
1923 | } else if (info->pending_bh & BH_STATUS) { | |
1924 | info->pending_bh &= ~BH_STATUS; | |
1925 | rc = BH_STATUS; | |
1926 | } else { | |
1927 | /* Mark BH routine as complete */ | |
0fab6de0 JP |
1928 | info->bh_running = false; |
1929 | info->bh_requested = false; | |
705b6c7b PF |
1930 | rc = 0; |
1931 | } | |
1932 | ||
1933 | spin_unlock_irqrestore(&info->lock,flags); | |
1934 | ||
1935 | return rc; | |
1936 | } | |
1937 | ||
1938 | /* | |
1939 | * perform bottom half processing | |
1940 | */ | |
c4028958 | 1941 | static void bh_handler(struct work_struct *work) |
705b6c7b | 1942 | { |
c4028958 | 1943 | struct slgt_info *info = container_of(work, struct slgt_info, task); |
705b6c7b PF |
1944 | int action; |
1945 | ||
1946 | if (!info) | |
1947 | return; | |
0fab6de0 | 1948 | info->bh_running = true; |
705b6c7b PF |
1949 | |
1950 | while((action = bh_action(info))) { | |
1951 | switch (action) { | |
1952 | case BH_RECEIVE: | |
1953 | DBGBH(("%s bh receive\n", info->device_name)); | |
1954 | switch(info->params.mode) { | |
1955 | case MGSL_MODE_ASYNC: | |
1956 | rx_async(info); | |
1957 | break; | |
1958 | case MGSL_MODE_HDLC: | |
1959 | while(rx_get_frame(info)); | |
1960 | break; | |
1961 | case MGSL_MODE_RAW: | |
cb10dc9a PF |
1962 | case MGSL_MODE_MONOSYNC: |
1963 | case MGSL_MODE_BISYNC: | |
705b6c7b PF |
1964 | while(rx_get_buf(info)); |
1965 | break; | |
1966 | } | |
1967 | /* restart receiver if rx DMA buffers exhausted */ | |
1968 | if (info->rx_restart) | |
1969 | rx_start(info); | |
1970 | break; | |
1971 | case BH_TRANSMIT: | |
1972 | bh_transmit(info); | |
1973 | break; | |
1974 | case BH_STATUS: | |
1975 | DBGBH(("%s bh status\n", info->device_name)); | |
1976 | info->ri_chkcount = 0; | |
1977 | info->dsr_chkcount = 0; | |
1978 | info->dcd_chkcount = 0; | |
1979 | info->cts_chkcount = 0; | |
1980 | break; | |
1981 | default: | |
1982 | DBGBH(("%s unknown action\n", info->device_name)); | |
1983 | break; | |
1984 | } | |
1985 | } | |
1986 | DBGBH(("%s bh_handler exit\n", info->device_name)); | |
1987 | } | |
1988 | ||
1989 | static void bh_transmit(struct slgt_info *info) | |
1990 | { | |
8fb06c77 | 1991 | struct tty_struct *tty = info->port.tty; |
705b6c7b PF |
1992 | |
1993 | DBGBH(("%s bh_transmit\n", info->device_name)); | |
b963a844 | 1994 | if (tty) |
705b6c7b | 1995 | tty_wakeup(tty); |
705b6c7b PF |
1996 | } |
1997 | ||
ed8485fb | 1998 | static void dsr_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 1999 | { |
ed8485fb PF |
2000 | if (status & BIT3) { |
2001 | info->signals |= SerialSignal_DSR; | |
2002 | info->input_signal_events.dsr_up++; | |
2003 | } else { | |
2004 | info->signals &= ~SerialSignal_DSR; | |
2005 | info->input_signal_events.dsr_down++; | |
2006 | } | |
705b6c7b PF |
2007 | DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); |
2008 | if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2009 | slgt_irq_off(info, IRQ_DSR); | |
2010 | return; | |
2011 | } | |
2012 | info->icount.dsr++; | |
705b6c7b PF |
2013 | wake_up_interruptible(&info->status_event_wait_q); |
2014 | wake_up_interruptible(&info->event_wait_q); | |
2015 | info->pending_bh |= BH_STATUS; | |
2016 | } | |
2017 | ||
ed8485fb | 2018 | static void cts_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2019 | { |
ed8485fb PF |
2020 | if (status & BIT2) { |
2021 | info->signals |= SerialSignal_CTS; | |
2022 | info->input_signal_events.cts_up++; | |
2023 | } else { | |
2024 | info->signals &= ~SerialSignal_CTS; | |
2025 | info->input_signal_events.cts_down++; | |
2026 | } | |
705b6c7b PF |
2027 | DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); |
2028 | if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2029 | slgt_irq_off(info, IRQ_CTS); | |
2030 | return; | |
2031 | } | |
2032 | info->icount.cts++; | |
705b6c7b PF |
2033 | wake_up_interruptible(&info->status_event_wait_q); |
2034 | wake_up_interruptible(&info->event_wait_q); | |
2035 | info->pending_bh |= BH_STATUS; | |
2036 | ||
8fb06c77 AC |
2037 | if (info->port.flags & ASYNC_CTS_FLOW) { |
2038 | if (info->port.tty) { | |
2039 | if (info->port.tty->hw_stopped) { | |
705b6c7b | 2040 | if (info->signals & SerialSignal_CTS) { |
8fb06c77 | 2041 | info->port.tty->hw_stopped = 0; |
705b6c7b PF |
2042 | info->pending_bh |= BH_TRANSMIT; |
2043 | return; | |
2044 | } | |
2045 | } else { | |
2046 | if (!(info->signals & SerialSignal_CTS)) | |
8fb06c77 | 2047 | info->port.tty->hw_stopped = 1; |
705b6c7b PF |
2048 | } |
2049 | } | |
2050 | } | |
2051 | } | |
2052 | ||
ed8485fb | 2053 | static void dcd_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2054 | { |
ed8485fb PF |
2055 | if (status & BIT1) { |
2056 | info->signals |= SerialSignal_DCD; | |
2057 | info->input_signal_events.dcd_up++; | |
2058 | } else { | |
2059 | info->signals &= ~SerialSignal_DCD; | |
2060 | info->input_signal_events.dcd_down++; | |
2061 | } | |
705b6c7b PF |
2062 | DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); |
2063 | if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2064 | slgt_irq_off(info, IRQ_DCD); | |
2065 | return; | |
2066 | } | |
2067 | info->icount.dcd++; | |
af69c7f9 | 2068 | #if SYNCLINK_GENERIC_HDLC |
fbeff3c1 KH |
2069 | if (info->netcount) { |
2070 | if (info->signals & SerialSignal_DCD) | |
2071 | netif_carrier_on(info->netdev); | |
2072 | else | |
2073 | netif_carrier_off(info->netdev); | |
2074 | } | |
705b6c7b PF |
2075 | #endif |
2076 | wake_up_interruptible(&info->status_event_wait_q); | |
2077 | wake_up_interruptible(&info->event_wait_q); | |
2078 | info->pending_bh |= BH_STATUS; | |
2079 | ||
8fb06c77 | 2080 | if (info->port.flags & ASYNC_CHECK_CD) { |
705b6c7b | 2081 | if (info->signals & SerialSignal_DCD) |
8fb06c77 | 2082 | wake_up_interruptible(&info->port.open_wait); |
705b6c7b | 2083 | else { |
8fb06c77 AC |
2084 | if (info->port.tty) |
2085 | tty_hangup(info->port.tty); | |
705b6c7b PF |
2086 | } |
2087 | } | |
2088 | } | |
2089 | ||
ed8485fb | 2090 | static void ri_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2091 | { |
ed8485fb PF |
2092 | if (status & BIT0) { |
2093 | info->signals |= SerialSignal_RI; | |
2094 | info->input_signal_events.ri_up++; | |
2095 | } else { | |
2096 | info->signals &= ~SerialSignal_RI; | |
2097 | info->input_signal_events.ri_down++; | |
2098 | } | |
705b6c7b PF |
2099 | DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); |
2100 | if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2101 | slgt_irq_off(info, IRQ_RI); | |
2102 | return; | |
2103 | } | |
ed8485fb | 2104 | info->icount.rng++; |
705b6c7b PF |
2105 | wake_up_interruptible(&info->status_event_wait_q); |
2106 | wake_up_interruptible(&info->event_wait_q); | |
2107 | info->pending_bh |= BH_STATUS; | |
2108 | } | |
2109 | ||
5ba5a5d2 PF |
2110 | static void isr_rxdata(struct slgt_info *info) |
2111 | { | |
2112 | unsigned int count = info->rbuf_fill_count; | |
2113 | unsigned int i = info->rbuf_fill_index; | |
2114 | unsigned short reg; | |
2115 | ||
2116 | while (rd_reg16(info, SSR) & IRQ_RXDATA) { | |
2117 | reg = rd_reg16(info, RDR); | |
2118 | DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg)); | |
2119 | if (desc_complete(info->rbufs[i])) { | |
2120 | /* all buffers full */ | |
2121 | rx_stop(info); | |
2122 | info->rx_restart = 1; | |
2123 | continue; | |
2124 | } | |
2125 | info->rbufs[i].buf[count++] = (unsigned char)reg; | |
2126 | /* async mode saves status byte to buffer for each data byte */ | |
2127 | if (info->params.mode == MGSL_MODE_ASYNC) | |
2128 | info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8); | |
2129 | if (count == info->rbuf_fill_level || (reg & BIT10)) { | |
2130 | /* buffer full or end of frame */ | |
2131 | set_desc_count(info->rbufs[i], count); | |
2132 | set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); | |
2133 | info->rbuf_fill_count = count = 0; | |
2134 | if (++i == info->rbuf_count) | |
2135 | i = 0; | |
2136 | info->pending_bh |= BH_RECEIVE; | |
2137 | } | |
2138 | } | |
2139 | ||
2140 | info->rbuf_fill_index = i; | |
2141 | info->rbuf_fill_count = count; | |
2142 | } | |
2143 | ||
705b6c7b PF |
2144 | static void isr_serial(struct slgt_info *info) |
2145 | { | |
2146 | unsigned short status = rd_reg16(info, SSR); | |
2147 | ||
2148 | DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); | |
2149 | ||
2150 | wr_reg16(info, SSR, status); /* clear pending */ | |
2151 | ||
0fab6de0 | 2152 | info->irq_occurred = true; |
705b6c7b PF |
2153 | |
2154 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
2155 | if (status & IRQ_TXIDLE) { | |
de538eb3 | 2156 | if (info->tx_active) |
705b6c7b PF |
2157 | isr_txeom(info, status); |
2158 | } | |
5ba5a5d2 PF |
2159 | if (info->rx_pio && (status & IRQ_RXDATA)) |
2160 | isr_rxdata(info); | |
705b6c7b PF |
2161 | if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { |
2162 | info->icount.brk++; | |
2163 | /* process break detection if tty control allows */ | |
8fb06c77 | 2164 | if (info->port.tty) { |
705b6c7b PF |
2165 | if (!(status & info->ignore_status_mask)) { |
2166 | if (info->read_status_mask & MASK_BREAK) { | |
8fb06c77 AC |
2167 | tty_insert_flip_char(info->port.tty, 0, TTY_BREAK); |
2168 | if (info->port.flags & ASYNC_SAK) | |
2169 | do_SAK(info->port.tty); | |
705b6c7b PF |
2170 | } |
2171 | } | |
2172 | } | |
2173 | } | |
2174 | } else { | |
2175 | if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) | |
2176 | isr_txeom(info, status); | |
5ba5a5d2 PF |
2177 | if (info->rx_pio && (status & IRQ_RXDATA)) |
2178 | isr_rxdata(info); | |
705b6c7b PF |
2179 | if (status & IRQ_RXIDLE) { |
2180 | if (status & RXIDLE) | |
2181 | info->icount.rxidle++; | |
2182 | else | |
2183 | info->icount.exithunt++; | |
2184 | wake_up_interruptible(&info->event_wait_q); | |
2185 | } | |
2186 | ||
2187 | if (status & IRQ_RXOVER) | |
2188 | rx_start(info); | |
2189 | } | |
2190 | ||
2191 | if (status & IRQ_DSR) | |
ed8485fb | 2192 | dsr_change(info, status); |
705b6c7b | 2193 | if (status & IRQ_CTS) |
ed8485fb | 2194 | cts_change(info, status); |
705b6c7b | 2195 | if (status & IRQ_DCD) |
ed8485fb | 2196 | dcd_change(info, status); |
705b6c7b | 2197 | if (status & IRQ_RI) |
ed8485fb | 2198 | ri_change(info, status); |
705b6c7b PF |
2199 | } |
2200 | ||
2201 | static void isr_rdma(struct slgt_info *info) | |
2202 | { | |
2203 | unsigned int status = rd_reg32(info, RDCSR); | |
2204 | ||
2205 | DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); | |
2206 | ||
2207 | /* RDCSR (rx DMA control/status) | |
2208 | * | |
2209 | * 31..07 reserved | |
2210 | * 06 save status byte to DMA buffer | |
2211 | * 05 error | |
2212 | * 04 eol (end of list) | |
2213 | * 03 eob (end of buffer) | |
2214 | * 02 IRQ enable | |
2215 | * 01 reset | |
2216 | * 00 enable | |
2217 | */ | |
2218 | wr_reg32(info, RDCSR, status); /* clear pending */ | |
2219 | ||
2220 | if (status & (BIT5 + BIT4)) { | |
2221 | DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); | |
0fab6de0 | 2222 | info->rx_restart = true; |
705b6c7b PF |
2223 | } |
2224 | info->pending_bh |= BH_RECEIVE; | |
2225 | } | |
2226 | ||
2227 | static void isr_tdma(struct slgt_info *info) | |
2228 | { | |
2229 | unsigned int status = rd_reg32(info, TDCSR); | |
2230 | ||
2231 | DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); | |
2232 | ||
2233 | /* TDCSR (tx DMA control/status) | |
2234 | * | |
2235 | * 31..06 reserved | |
2236 | * 05 error | |
2237 | * 04 eol (end of list) | |
2238 | * 03 eob (end of buffer) | |
2239 | * 02 IRQ enable | |
2240 | * 01 reset | |
2241 | * 00 enable | |
2242 | */ | |
2243 | wr_reg32(info, TDCSR, status); /* clear pending */ | |
2244 | ||
2245 | if (status & (BIT5 + BIT4 + BIT3)) { | |
2246 | // another transmit buffer has completed | |
2247 | // run bottom half to get more send data from user | |
2248 | info->pending_bh |= BH_TRANSMIT; | |
2249 | } | |
2250 | } | |
2251 | ||
de538eb3 PF |
2252 | /* |
2253 | * return true if there are unsent tx DMA buffers, otherwise false | |
2254 | * | |
2255 | * if there are unsent buffers then info->tbuf_start | |
2256 | * is set to index of first unsent buffer | |
2257 | */ | |
2258 | static bool unsent_tbufs(struct slgt_info *info) | |
2259 | { | |
2260 | unsigned int i = info->tbuf_current; | |
2261 | bool rc = false; | |
2262 | ||
2263 | /* | |
2264 | * search backwards from last loaded buffer (precedes tbuf_current) | |
2265 | * for first unsent buffer (desc_count > 0) | |
2266 | */ | |
2267 | ||
2268 | do { | |
2269 | if (i) | |
2270 | i--; | |
2271 | else | |
2272 | i = info->tbuf_count - 1; | |
2273 | if (!desc_count(info->tbufs[i])) | |
2274 | break; | |
2275 | info->tbuf_start = i; | |
2276 | rc = true; | |
2277 | } while (i != info->tbuf_current); | |
2278 | ||
2279 | return rc; | |
2280 | } | |
2281 | ||
705b6c7b PF |
2282 | static void isr_txeom(struct slgt_info *info, unsigned short status) |
2283 | { | |
2284 | DBGISR(("%s txeom status=%04x\n", info->device_name, status)); | |
2285 | ||
2286 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
2287 | tdma_reset(info); | |
705b6c7b PF |
2288 | if (status & IRQ_TXUNDER) { |
2289 | unsigned short val = rd_reg16(info, TCR); | |
2290 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
2291 | wr_reg16(info, TCR, val); /* clear reset bit */ | |
2292 | } | |
2293 | ||
2294 | if (info->tx_active) { | |
2295 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2296 | if (status & IRQ_TXUNDER) | |
2297 | info->icount.txunder++; | |
2298 | else if (status & IRQ_TXIDLE) | |
2299 | info->icount.txok++; | |
2300 | } | |
2301 | ||
de538eb3 PF |
2302 | if (unsent_tbufs(info)) { |
2303 | tx_start(info); | |
2304 | update_tx_timer(info); | |
2305 | return; | |
2306 | } | |
0fab6de0 | 2307 | info->tx_active = false; |
705b6c7b PF |
2308 | |
2309 | del_timer(&info->tx_timer); | |
2310 | ||
2311 | if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { | |
2312 | info->signals &= ~SerialSignal_RTS; | |
0fab6de0 | 2313 | info->drop_rts_on_tx_done = false; |
705b6c7b PF |
2314 | set_signals(info); |
2315 | } | |
2316 | ||
af69c7f9 | 2317 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
2318 | if (info->netcount) |
2319 | hdlcdev_tx_done(info); | |
2320 | else | |
2321 | #endif | |
2322 | { | |
8fb06c77 | 2323 | if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { |
705b6c7b PF |
2324 | tx_stop(info); |
2325 | return; | |
2326 | } | |
2327 | info->pending_bh |= BH_TRANSMIT; | |
2328 | } | |
2329 | } | |
2330 | } | |
2331 | ||
0080b7aa PF |
2332 | static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) |
2333 | { | |
2334 | struct cond_wait *w, *prev; | |
2335 | ||
2336 | /* wake processes waiting for specific transitions */ | |
2337 | for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { | |
2338 | if (w->data & changed) { | |
2339 | w->data = state; | |
2340 | wake_up_interruptible(&w->q); | |
2341 | if (prev != NULL) | |
2342 | prev->next = w->next; | |
2343 | else | |
2344 | info->gpio_wait_q = w->next; | |
2345 | } else | |
2346 | prev = w; | |
2347 | } | |
2348 | } | |
2349 | ||
705b6c7b PF |
2350 | /* interrupt service routine |
2351 | * | |
2352 | * irq interrupt number | |
2353 | * dev_id device ID supplied during interrupt registration | |
705b6c7b | 2354 | */ |
a6f97b29 | 2355 | static irqreturn_t slgt_interrupt(int dummy, void *dev_id) |
705b6c7b | 2356 | { |
a6f97b29 | 2357 | struct slgt_info *info = dev_id; |
705b6c7b PF |
2358 | unsigned int gsr; |
2359 | unsigned int i; | |
2360 | ||
a6f97b29 | 2361 | DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); |
705b6c7b | 2362 | |
705b6c7b PF |
2363 | while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { |
2364 | DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); | |
0fab6de0 | 2365 | info->irq_occurred = true; |
705b6c7b PF |
2366 | for(i=0; i < info->port_count ; i++) { |
2367 | if (info->port_array[i] == NULL) | |
2368 | continue; | |
ffd7d6ba | 2369 | spin_lock(&info->port_array[i]->lock); |
705b6c7b PF |
2370 | if (gsr & (BIT8 << i)) |
2371 | isr_serial(info->port_array[i]); | |
2372 | if (gsr & (BIT16 << (i*2))) | |
2373 | isr_rdma(info->port_array[i]); | |
2374 | if (gsr & (BIT17 << (i*2))) | |
2375 | isr_tdma(info->port_array[i]); | |
ffd7d6ba | 2376 | spin_unlock(&info->port_array[i]->lock); |
705b6c7b PF |
2377 | } |
2378 | } | |
2379 | ||
0080b7aa PF |
2380 | if (info->gpio_present) { |
2381 | unsigned int state; | |
2382 | unsigned int changed; | |
ffd7d6ba | 2383 | spin_lock(&info->lock); |
0080b7aa PF |
2384 | while ((changed = rd_reg32(info, IOSR)) != 0) { |
2385 | DBGISR(("%s iosr=%08x\n", info->device_name, changed)); | |
2386 | /* read latched state of GPIO signals */ | |
2387 | state = rd_reg32(info, IOVR); | |
2388 | /* clear pending GPIO interrupt bits */ | |
2389 | wr_reg32(info, IOSR, changed); | |
2390 | for (i=0 ; i < info->port_count ; i++) { | |
2391 | if (info->port_array[i] != NULL) | |
2392 | isr_gpio(info->port_array[i], changed, state); | |
2393 | } | |
2394 | } | |
ffd7d6ba | 2395 | spin_unlock(&info->lock); |
0080b7aa PF |
2396 | } |
2397 | ||
705b6c7b PF |
2398 | for(i=0; i < info->port_count ; i++) { |
2399 | struct slgt_info *port = info->port_array[i]; | |
ffd7d6ba PF |
2400 | if (port == NULL) |
2401 | continue; | |
2402 | spin_lock(&port->lock); | |
2403 | if ((port->port.count || port->netcount) && | |
705b6c7b PF |
2404 | port->pending_bh && !port->bh_running && |
2405 | !port->bh_requested) { | |
2406 | DBGISR(("%s bh queued\n", port->device_name)); | |
2407 | schedule_work(&port->task); | |
0fab6de0 | 2408 | port->bh_requested = true; |
705b6c7b | 2409 | } |
ffd7d6ba | 2410 | spin_unlock(&port->lock); |
705b6c7b PF |
2411 | } |
2412 | ||
a6f97b29 | 2413 | DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); |
705b6c7b PF |
2414 | return IRQ_HANDLED; |
2415 | } | |
2416 | ||
2417 | static int startup(struct slgt_info *info) | |
2418 | { | |
2419 | DBGINFO(("%s startup\n", info->device_name)); | |
2420 | ||
8fb06c77 | 2421 | if (info->port.flags & ASYNC_INITIALIZED) |
705b6c7b PF |
2422 | return 0; |
2423 | ||
2424 | if (!info->tx_buf) { | |
2425 | info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); | |
2426 | if (!info->tx_buf) { | |
2427 | DBGERR(("%s can't allocate tx buffer\n", info->device_name)); | |
2428 | return -ENOMEM; | |
2429 | } | |
2430 | } | |
2431 | ||
2432 | info->pending_bh = 0; | |
2433 | ||
2434 | memset(&info->icount, 0, sizeof(info->icount)); | |
2435 | ||
2436 | /* program hardware for current parameters */ | |
2437 | change_params(info); | |
2438 | ||
8fb06c77 AC |
2439 | if (info->port.tty) |
2440 | clear_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
705b6c7b | 2441 | |
8fb06c77 | 2442 | info->port.flags |= ASYNC_INITIALIZED; |
705b6c7b PF |
2443 | |
2444 | return 0; | |
2445 | } | |
2446 | ||
2447 | /* | |
2448 | * called by close() and hangup() to shutdown hardware | |
2449 | */ | |
2450 | static void shutdown(struct slgt_info *info) | |
2451 | { | |
2452 | unsigned long flags; | |
2453 | ||
8fb06c77 | 2454 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
705b6c7b PF |
2455 | return; |
2456 | ||
2457 | DBGINFO(("%s shutdown\n", info->device_name)); | |
2458 | ||
2459 | /* clear status wait queue because status changes */ | |
2460 | /* can't happen after shutting down the hardware */ | |
2461 | wake_up_interruptible(&info->status_event_wait_q); | |
2462 | wake_up_interruptible(&info->event_wait_q); | |
2463 | ||
2464 | del_timer_sync(&info->tx_timer); | |
2465 | del_timer_sync(&info->rx_timer); | |
2466 | ||
2467 | kfree(info->tx_buf); | |
2468 | info->tx_buf = NULL; | |
2469 | ||
2470 | spin_lock_irqsave(&info->lock,flags); | |
2471 | ||
2472 | tx_stop(info); | |
2473 | rx_stop(info); | |
2474 | ||
2475 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
2476 | ||
8fb06c77 | 2477 | if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) { |
705b6c7b PF |
2478 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); |
2479 | set_signals(info); | |
2480 | } | |
2481 | ||
0080b7aa PF |
2482 | flush_cond_wait(&info->gpio_wait_q); |
2483 | ||
705b6c7b PF |
2484 | spin_unlock_irqrestore(&info->lock,flags); |
2485 | ||
8fb06c77 AC |
2486 | if (info->port.tty) |
2487 | set_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
705b6c7b | 2488 | |
8fb06c77 | 2489 | info->port.flags &= ~ASYNC_INITIALIZED; |
705b6c7b PF |
2490 | } |
2491 | ||
2492 | static void program_hw(struct slgt_info *info) | |
2493 | { | |
2494 | unsigned long flags; | |
2495 | ||
2496 | spin_lock_irqsave(&info->lock,flags); | |
2497 | ||
2498 | rx_stop(info); | |
2499 | tx_stop(info); | |
2500 | ||
cb10dc9a | 2501 | if (info->params.mode != MGSL_MODE_ASYNC || |
705b6c7b | 2502 | info->netcount) |
cb10dc9a | 2503 | sync_mode(info); |
705b6c7b PF |
2504 | else |
2505 | async_mode(info); | |
2506 | ||
2507 | set_signals(info); | |
2508 | ||
2509 | info->dcd_chkcount = 0; | |
2510 | info->cts_chkcount = 0; | |
2511 | info->ri_chkcount = 0; | |
2512 | info->dsr_chkcount = 0; | |
2513 | ||
a6b2f87b | 2514 | slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI); |
705b6c7b PF |
2515 | get_signals(info); |
2516 | ||
2517 | if (info->netcount || | |
8fb06c77 | 2518 | (info->port.tty && info->port.tty->termios->c_cflag & CREAD)) |
705b6c7b PF |
2519 | rx_start(info); |
2520 | ||
2521 | spin_unlock_irqrestore(&info->lock,flags); | |
2522 | } | |
2523 | ||
2524 | /* | |
2525 | * reconfigure adapter based on new parameters | |
2526 | */ | |
2527 | static void change_params(struct slgt_info *info) | |
2528 | { | |
2529 | unsigned cflag; | |
2530 | int bits_per_char; | |
2531 | ||
8fb06c77 | 2532 | if (!info->port.tty || !info->port.tty->termios) |
705b6c7b PF |
2533 | return; |
2534 | DBGINFO(("%s change_params\n", info->device_name)); | |
2535 | ||
8fb06c77 | 2536 | cflag = info->port.tty->termios->c_cflag; |
705b6c7b PF |
2537 | |
2538 | /* if B0 rate (hangup) specified then negate DTR and RTS */ | |
2539 | /* otherwise assert DTR and RTS */ | |
2540 | if (cflag & CBAUD) | |
2541 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
2542 | else | |
2543 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
2544 | ||
2545 | /* byte size and parity */ | |
2546 | ||
2547 | switch (cflag & CSIZE) { | |
2548 | case CS5: info->params.data_bits = 5; break; | |
2549 | case CS6: info->params.data_bits = 6; break; | |
2550 | case CS7: info->params.data_bits = 7; break; | |
2551 | case CS8: info->params.data_bits = 8; break; | |
2552 | default: info->params.data_bits = 7; break; | |
2553 | } | |
2554 | ||
2555 | info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; | |
2556 | ||
2557 | if (cflag & PARENB) | |
2558 | info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; | |
2559 | else | |
2560 | info->params.parity = ASYNC_PARITY_NONE; | |
2561 | ||
2562 | /* calculate number of jiffies to transmit a full | |
2563 | * FIFO (32 bytes) at specified data rate | |
2564 | */ | |
2565 | bits_per_char = info->params.data_bits + | |
2566 | info->params.stop_bits + 1; | |
2567 | ||
8fb06c77 | 2568 | info->params.data_rate = tty_get_baud_rate(info->port.tty); |
705b6c7b PF |
2569 | |
2570 | if (info->params.data_rate) { | |
2571 | info->timeout = (32*HZ*bits_per_char) / | |
2572 | info->params.data_rate; | |
2573 | } | |
2574 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
2575 | ||
2576 | if (cflag & CRTSCTS) | |
8fb06c77 | 2577 | info->port.flags |= ASYNC_CTS_FLOW; |
705b6c7b | 2578 | else |
8fb06c77 | 2579 | info->port.flags &= ~ASYNC_CTS_FLOW; |
705b6c7b PF |
2580 | |
2581 | if (cflag & CLOCAL) | |
8fb06c77 | 2582 | info->port.flags &= ~ASYNC_CHECK_CD; |
705b6c7b | 2583 | else |
8fb06c77 | 2584 | info->port.flags |= ASYNC_CHECK_CD; |
705b6c7b PF |
2585 | |
2586 | /* process tty input control flags */ | |
2587 | ||
2588 | info->read_status_mask = IRQ_RXOVER; | |
8fb06c77 | 2589 | if (I_INPCK(info->port.tty)) |
705b6c7b | 2590 | info->read_status_mask |= MASK_PARITY | MASK_FRAMING; |
8fb06c77 | 2591 | if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) |
705b6c7b | 2592 | info->read_status_mask |= MASK_BREAK; |
8fb06c77 | 2593 | if (I_IGNPAR(info->port.tty)) |
705b6c7b | 2594 | info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; |
8fb06c77 | 2595 | if (I_IGNBRK(info->port.tty)) { |
705b6c7b PF |
2596 | info->ignore_status_mask |= MASK_BREAK; |
2597 | /* If ignoring parity and break indicators, ignore | |
2598 | * overruns too. (For real raw support). | |
2599 | */ | |
8fb06c77 | 2600 | if (I_IGNPAR(info->port.tty)) |
705b6c7b PF |
2601 | info->ignore_status_mask |= MASK_OVERRUN; |
2602 | } | |
2603 | ||
2604 | program_hw(info); | |
2605 | } | |
2606 | ||
2607 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) | |
2608 | { | |
2609 | DBGINFO(("%s get_stats\n", info->device_name)); | |
2610 | if (!user_icount) { | |
2611 | memset(&info->icount, 0, sizeof(info->icount)); | |
2612 | } else { | |
2613 | if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) | |
2614 | return -EFAULT; | |
2615 | } | |
2616 | return 0; | |
2617 | } | |
2618 | ||
2619 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) | |
2620 | { | |
2621 | DBGINFO(("%s get_params\n", info->device_name)); | |
2622 | if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) | |
2623 | return -EFAULT; | |
2624 | return 0; | |
2625 | } | |
2626 | ||
2627 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) | |
2628 | { | |
2629 | unsigned long flags; | |
2630 | MGSL_PARAMS tmp_params; | |
2631 | ||
2632 | DBGINFO(("%s set_params\n", info->device_name)); | |
2633 | if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) | |
2634 | return -EFAULT; | |
2635 | ||
2636 | spin_lock_irqsave(&info->lock, flags); | |
1f80769f PF |
2637 | if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) |
2638 | info->base_clock = tmp_params.clock_speed; | |
2639 | else | |
2640 | memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); | |
705b6c7b PF |
2641 | spin_unlock_irqrestore(&info->lock, flags); |
2642 | ||
1f80769f | 2643 | program_hw(info); |
705b6c7b PF |
2644 | |
2645 | return 0; | |
2646 | } | |
2647 | ||
2648 | static int get_txidle(struct slgt_info *info, int __user *idle_mode) | |
2649 | { | |
2650 | DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); | |
2651 | if (put_user(info->idle_mode, idle_mode)) | |
2652 | return -EFAULT; | |
2653 | return 0; | |
2654 | } | |
2655 | ||
2656 | static int set_txidle(struct slgt_info *info, int idle_mode) | |
2657 | { | |
2658 | unsigned long flags; | |
2659 | DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); | |
2660 | spin_lock_irqsave(&info->lock,flags); | |
2661 | info->idle_mode = idle_mode; | |
643f3319 PF |
2662 | if (info->params.mode != MGSL_MODE_ASYNC) |
2663 | tx_set_idle(info); | |
705b6c7b PF |
2664 | spin_unlock_irqrestore(&info->lock,flags); |
2665 | return 0; | |
2666 | } | |
2667 | ||
2668 | static int tx_enable(struct slgt_info *info, int enable) | |
2669 | { | |
2670 | unsigned long flags; | |
2671 | DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); | |
2672 | spin_lock_irqsave(&info->lock,flags); | |
2673 | if (enable) { | |
2674 | if (!info->tx_enabled) | |
2675 | tx_start(info); | |
2676 | } else { | |
2677 | if (info->tx_enabled) | |
2678 | tx_stop(info); | |
2679 | } | |
2680 | spin_unlock_irqrestore(&info->lock,flags); | |
2681 | return 0; | |
2682 | } | |
2683 | ||
2684 | /* | |
2685 | * abort transmit HDLC frame | |
2686 | */ | |
2687 | static int tx_abort(struct slgt_info *info) | |
2688 | { | |
2689 | unsigned long flags; | |
2690 | DBGINFO(("%s tx_abort\n", info->device_name)); | |
2691 | spin_lock_irqsave(&info->lock,flags); | |
2692 | tdma_reset(info); | |
2693 | spin_unlock_irqrestore(&info->lock,flags); | |
2694 | return 0; | |
2695 | } | |
2696 | ||
2697 | static int rx_enable(struct slgt_info *info, int enable) | |
2698 | { | |
2699 | unsigned long flags; | |
814dae03 PF |
2700 | unsigned int rbuf_fill_level; |
2701 | DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable)); | |
705b6c7b | 2702 | spin_lock_irqsave(&info->lock,flags); |
814dae03 PF |
2703 | /* |
2704 | * enable[31..16] = receive DMA buffer fill level | |
2705 | * 0 = noop (leave fill level unchanged) | |
2706 | * fill level must be multiple of 4 and <= buffer size | |
2707 | */ | |
2708 | rbuf_fill_level = ((unsigned int)enable) >> 16; | |
2709 | if (rbuf_fill_level) { | |
c68a99cd PF |
2710 | if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) { |
2711 | spin_unlock_irqrestore(&info->lock, flags); | |
814dae03 | 2712 | return -EINVAL; |
c68a99cd | 2713 | } |
814dae03 | 2714 | info->rbuf_fill_level = rbuf_fill_level; |
5ba5a5d2 PF |
2715 | if (rbuf_fill_level < 128) |
2716 | info->rx_pio = 1; /* PIO mode */ | |
2717 | else | |
2718 | info->rx_pio = 0; /* DMA mode */ | |
814dae03 PF |
2719 | rx_stop(info); /* restart receiver to use new fill level */ |
2720 | } | |
2721 | ||
2722 | /* | |
2723 | * enable[1..0] = receiver enable command | |
2724 | * 0 = disable | |
2725 | * 1 = enable | |
2726 | * 2 = enable or force hunt mode if already enabled | |
2727 | */ | |
2728 | enable &= 3; | |
705b6c7b PF |
2729 | if (enable) { |
2730 | if (!info->rx_enabled) | |
2731 | rx_start(info); | |
cb10dc9a PF |
2732 | else if (enable == 2) { |
2733 | /* force hunt mode (write 1 to RCR[3]) */ | |
2734 | wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); | |
2735 | } | |
705b6c7b PF |
2736 | } else { |
2737 | if (info->rx_enabled) | |
2738 | rx_stop(info); | |
2739 | } | |
2740 | spin_unlock_irqrestore(&info->lock,flags); | |
2741 | return 0; | |
2742 | } | |
2743 | ||
2744 | /* | |
2745 | * wait for specified event to occur | |
2746 | */ | |
2747 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) | |
2748 | { | |
2749 | unsigned long flags; | |
2750 | int s; | |
2751 | int rc=0; | |
2752 | struct mgsl_icount cprev, cnow; | |
2753 | int events; | |
2754 | int mask; | |
2755 | struct _input_signal_events oldsigs, newsigs; | |
2756 | DECLARE_WAITQUEUE(wait, current); | |
2757 | ||
2758 | if (get_user(mask, mask_ptr)) | |
2759 | return -EFAULT; | |
2760 | ||
2761 | DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); | |
2762 | ||
2763 | spin_lock_irqsave(&info->lock,flags); | |
2764 | ||
2765 | /* return immediately if state matches requested events */ | |
2766 | get_signals(info); | |
2767 | s = info->signals; | |
2768 | ||
2769 | events = mask & | |
2770 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
2771 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
2772 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
2773 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
2774 | if (events) { | |
2775 | spin_unlock_irqrestore(&info->lock,flags); | |
2776 | goto exit; | |
2777 | } | |
2778 | ||
2779 | /* save current irq counts */ | |
2780 | cprev = info->icount; | |
2781 | oldsigs = info->input_signal_events; | |
2782 | ||
2783 | /* enable hunt and idle irqs if needed */ | |
2784 | if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { | |
2785 | unsigned short val = rd_reg16(info, SCR); | |
2786 | if (!(val & IRQ_RXIDLE)) | |
2787 | wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); | |
2788 | } | |
2789 | ||
2790 | set_current_state(TASK_INTERRUPTIBLE); | |
2791 | add_wait_queue(&info->event_wait_q, &wait); | |
2792 | ||
2793 | spin_unlock_irqrestore(&info->lock,flags); | |
2794 | ||
2795 | for(;;) { | |
2796 | schedule(); | |
2797 | if (signal_pending(current)) { | |
2798 | rc = -ERESTARTSYS; | |
2799 | break; | |
2800 | } | |
2801 | ||
2802 | /* get current irq counts */ | |
2803 | spin_lock_irqsave(&info->lock,flags); | |
2804 | cnow = info->icount; | |
2805 | newsigs = info->input_signal_events; | |
2806 | set_current_state(TASK_INTERRUPTIBLE); | |
2807 | spin_unlock_irqrestore(&info->lock,flags); | |
2808 | ||
2809 | /* if no change, wait aborted for some reason */ | |
2810 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
2811 | newsigs.dsr_down == oldsigs.dsr_down && | |
2812 | newsigs.dcd_up == oldsigs.dcd_up && | |
2813 | newsigs.dcd_down == oldsigs.dcd_down && | |
2814 | newsigs.cts_up == oldsigs.cts_up && | |
2815 | newsigs.cts_down == oldsigs.cts_down && | |
2816 | newsigs.ri_up == oldsigs.ri_up && | |
2817 | newsigs.ri_down == oldsigs.ri_down && | |
2818 | cnow.exithunt == cprev.exithunt && | |
2819 | cnow.rxidle == cprev.rxidle) { | |
2820 | rc = -EIO; | |
2821 | break; | |
2822 | } | |
2823 | ||
2824 | events = mask & | |
2825 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
2826 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
2827 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
2828 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
2829 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
2830 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
2831 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
2832 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
2833 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
2834 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
2835 | if (events) | |
2836 | break; | |
2837 | ||
2838 | cprev = cnow; | |
2839 | oldsigs = newsigs; | |
2840 | } | |
2841 | ||
2842 | remove_wait_queue(&info->event_wait_q, &wait); | |
2843 | set_current_state(TASK_RUNNING); | |
2844 | ||
2845 | ||
2846 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
2847 | spin_lock_irqsave(&info->lock,flags); | |
2848 | if (!waitqueue_active(&info->event_wait_q)) { | |
2849 | /* disable enable exit hunt mode/idle rcvd IRQs */ | |
2850 | wr_reg16(info, SCR, | |
2851 | (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); | |
2852 | } | |
2853 | spin_unlock_irqrestore(&info->lock,flags); | |
2854 | } | |
2855 | exit: | |
2856 | if (rc == 0) | |
2857 | rc = put_user(events, mask_ptr); | |
2858 | return rc; | |
2859 | } | |
2860 | ||
2861 | static int get_interface(struct slgt_info *info, int __user *if_mode) | |
2862 | { | |
2863 | DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); | |
2864 | if (put_user(info->if_mode, if_mode)) | |
2865 | return -EFAULT; | |
2866 | return 0; | |
2867 | } | |
2868 | ||
2869 | static int set_interface(struct slgt_info *info, int if_mode) | |
2870 | { | |
2871 | unsigned long flags; | |
35fbd397 | 2872 | unsigned short val; |
705b6c7b PF |
2873 | |
2874 | DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); | |
2875 | spin_lock_irqsave(&info->lock,flags); | |
2876 | info->if_mode = if_mode; | |
2877 | ||
2878 | msc_set_vcr(info); | |
2879 | ||
2880 | /* TCR (tx control) 07 1=RTS driver control */ | |
2881 | val = rd_reg16(info, TCR); | |
2882 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
2883 | val |= BIT7; | |
2884 | else | |
2885 | val &= ~BIT7; | |
2886 | wr_reg16(info, TCR, val); | |
2887 | ||
2888 | spin_unlock_irqrestore(&info->lock,flags); | |
2889 | return 0; | |
2890 | } | |
2891 | ||
0080b7aa PF |
2892 | /* |
2893 | * set general purpose IO pin state and direction | |
2894 | * | |
2895 | * user_gpio fields: | |
2896 | * state each bit indicates a pin state | |
2897 | * smask set bit indicates pin state to set | |
2898 | * dir each bit indicates a pin direction (0=input, 1=output) | |
2899 | * dmask set bit indicates pin direction to set | |
2900 | */ | |
2901 | static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2902 | { | |
2903 | unsigned long flags; | |
2904 | struct gpio_desc gpio; | |
2905 | __u32 data; | |
2906 | ||
2907 | if (!info->gpio_present) | |
2908 | return -EINVAL; | |
2909 | if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) | |
2910 | return -EFAULT; | |
2911 | DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", | |
2912 | info->device_name, gpio.state, gpio.smask, | |
2913 | gpio.dir, gpio.dmask)); | |
2914 | ||
ffd7d6ba | 2915 | spin_lock_irqsave(&info->port_array[0]->lock, flags); |
0080b7aa PF |
2916 | if (gpio.dmask) { |
2917 | data = rd_reg32(info, IODR); | |
2918 | data |= gpio.dmask & gpio.dir; | |
2919 | data &= ~(gpio.dmask & ~gpio.dir); | |
2920 | wr_reg32(info, IODR, data); | |
2921 | } | |
2922 | if (gpio.smask) { | |
2923 | data = rd_reg32(info, IOVR); | |
2924 | data |= gpio.smask & gpio.state; | |
2925 | data &= ~(gpio.smask & ~gpio.state); | |
2926 | wr_reg32(info, IOVR, data); | |
2927 | } | |
ffd7d6ba | 2928 | spin_unlock_irqrestore(&info->port_array[0]->lock, flags); |
0080b7aa PF |
2929 | |
2930 | return 0; | |
2931 | } | |
2932 | ||
2933 | /* | |
2934 | * get general purpose IO pin state and direction | |
2935 | */ | |
2936 | static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2937 | { | |
2938 | struct gpio_desc gpio; | |
2939 | if (!info->gpio_present) | |
2940 | return -EINVAL; | |
2941 | gpio.state = rd_reg32(info, IOVR); | |
2942 | gpio.smask = 0xffffffff; | |
2943 | gpio.dir = rd_reg32(info, IODR); | |
2944 | gpio.dmask = 0xffffffff; | |
2945 | if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) | |
2946 | return -EFAULT; | |
2947 | DBGINFO(("%s get_gpio state=%08x dir=%08x\n", | |
2948 | info->device_name, gpio.state, gpio.dir)); | |
2949 | return 0; | |
2950 | } | |
2951 | ||
2952 | /* | |
2953 | * conditional wait facility | |
2954 | */ | |
2955 | static void init_cond_wait(struct cond_wait *w, unsigned int data) | |
2956 | { | |
2957 | init_waitqueue_head(&w->q); | |
2958 | init_waitqueue_entry(&w->wait, current); | |
2959 | w->data = data; | |
2960 | } | |
2961 | ||
2962 | static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) | |
2963 | { | |
2964 | set_current_state(TASK_INTERRUPTIBLE); | |
2965 | add_wait_queue(&w->q, &w->wait); | |
2966 | w->next = *head; | |
2967 | *head = w; | |
2968 | } | |
2969 | ||
2970 | static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) | |
2971 | { | |
2972 | struct cond_wait *w, *prev; | |
2973 | remove_wait_queue(&cw->q, &cw->wait); | |
2974 | set_current_state(TASK_RUNNING); | |
2975 | for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { | |
2976 | if (w == cw) { | |
2977 | if (prev != NULL) | |
2978 | prev->next = w->next; | |
2979 | else | |
2980 | *head = w->next; | |
2981 | break; | |
2982 | } | |
2983 | } | |
2984 | } | |
2985 | ||
2986 | static void flush_cond_wait(struct cond_wait **head) | |
2987 | { | |
2988 | while (*head != NULL) { | |
2989 | wake_up_interruptible(&(*head)->q); | |
2990 | *head = (*head)->next; | |
2991 | } | |
2992 | } | |
2993 | ||
2994 | /* | |
2995 | * wait for general purpose I/O pin(s) to enter specified state | |
2996 | * | |
2997 | * user_gpio fields: | |
2998 | * state - bit indicates target pin state | |
2999 | * smask - set bit indicates watched pin | |
3000 | * | |
3001 | * The wait ends when at least one watched pin enters the specified | |
3002 | * state. When 0 (no error) is returned, user_gpio->state is set to the | |
3003 | * state of all GPIO pins when the wait ends. | |
3004 | * | |
3005 | * Note: Each pin may be a dedicated input, dedicated output, or | |
3006 | * configurable input/output. The number and configuration of pins | |
3007 | * varies with the specific adapter model. Only input pins (dedicated | |
3008 | * or configured) can be monitored with this function. | |
3009 | */ | |
3010 | static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
3011 | { | |
3012 | unsigned long flags; | |
3013 | int rc = 0; | |
3014 | struct gpio_desc gpio; | |
3015 | struct cond_wait wait; | |
3016 | u32 state; | |
3017 | ||
3018 | if (!info->gpio_present) | |
3019 | return -EINVAL; | |
3020 | if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) | |
3021 | return -EFAULT; | |
3022 | DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", | |
3023 | info->device_name, gpio.state, gpio.smask)); | |
3024 | /* ignore output pins identified by set IODR bit */ | |
3025 | if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) | |
3026 | return -EINVAL; | |
3027 | init_cond_wait(&wait, gpio.smask); | |
3028 | ||
ffd7d6ba | 3029 | spin_lock_irqsave(&info->port_array[0]->lock, flags); |
0080b7aa PF |
3030 | /* enable interrupts for watched pins */ |
3031 | wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); | |
3032 | /* get current pin states */ | |
3033 | state = rd_reg32(info, IOVR); | |
3034 | ||
3035 | if (gpio.smask & ~(state ^ gpio.state)) { | |
3036 | /* already in target state */ | |
3037 | gpio.state = state; | |
3038 | } else { | |
3039 | /* wait for target state */ | |
3040 | add_cond_wait(&info->gpio_wait_q, &wait); | |
ffd7d6ba | 3041 | spin_unlock_irqrestore(&info->port_array[0]->lock, flags); |
0080b7aa PF |
3042 | schedule(); |
3043 | if (signal_pending(current)) | |
3044 | rc = -ERESTARTSYS; | |
3045 | else | |
3046 | gpio.state = wait.data; | |
ffd7d6ba | 3047 | spin_lock_irqsave(&info->port_array[0]->lock, flags); |
0080b7aa PF |
3048 | remove_cond_wait(&info->gpio_wait_q, &wait); |
3049 | } | |
3050 | ||
3051 | /* disable all GPIO interrupts if no waiting processes */ | |
3052 | if (info->gpio_wait_q == NULL) | |
3053 | wr_reg32(info, IOER, 0); | |
ffd7d6ba | 3054 | spin_unlock_irqrestore(&info->port_array[0]->lock, flags); |
0080b7aa PF |
3055 | |
3056 | if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) | |
3057 | rc = -EFAULT; | |
3058 | return rc; | |
3059 | } | |
3060 | ||
705b6c7b PF |
3061 | static int modem_input_wait(struct slgt_info *info,int arg) |
3062 | { | |
3063 | unsigned long flags; | |
3064 | int rc; | |
3065 | struct mgsl_icount cprev, cnow; | |
3066 | DECLARE_WAITQUEUE(wait, current); | |
3067 | ||
3068 | /* save current irq counts */ | |
3069 | spin_lock_irqsave(&info->lock,flags); | |
3070 | cprev = info->icount; | |
3071 | add_wait_queue(&info->status_event_wait_q, &wait); | |
3072 | set_current_state(TASK_INTERRUPTIBLE); | |
3073 | spin_unlock_irqrestore(&info->lock,flags); | |
3074 | ||
3075 | for(;;) { | |
3076 | schedule(); | |
3077 | if (signal_pending(current)) { | |
3078 | rc = -ERESTARTSYS; | |
3079 | break; | |
3080 | } | |
3081 | ||
3082 | /* get new irq counts */ | |
3083 | spin_lock_irqsave(&info->lock,flags); | |
3084 | cnow = info->icount; | |
3085 | set_current_state(TASK_INTERRUPTIBLE); | |
3086 | spin_unlock_irqrestore(&info->lock,flags); | |
3087 | ||
3088 | /* if no change, wait aborted for some reason */ | |
3089 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
3090 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
3091 | rc = -EIO; | |
3092 | break; | |
3093 | } | |
3094 | ||
3095 | /* check for change in caller specified modem input */ | |
3096 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
3097 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
3098 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
3099 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
3100 | rc = 0; | |
3101 | break; | |
3102 | } | |
3103 | ||
3104 | cprev = cnow; | |
3105 | } | |
3106 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
3107 | set_current_state(TASK_RUNNING); | |
3108 | return rc; | |
3109 | } | |
3110 | ||
3111 | /* | |
3112 | * return state of serial control and status signals | |
3113 | */ | |
3114 | static int tiocmget(struct tty_struct *tty, struct file *file) | |
3115 | { | |
3116 | struct slgt_info *info = tty->driver_data; | |
3117 | unsigned int result; | |
3118 | unsigned long flags; | |
3119 | ||
3120 | spin_lock_irqsave(&info->lock,flags); | |
3121 | get_signals(info); | |
3122 | spin_unlock_irqrestore(&info->lock,flags); | |
3123 | ||
3124 | result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + | |
3125 | ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + | |
3126 | ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + | |
3127 | ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + | |
3128 | ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + | |
3129 | ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); | |
3130 | ||
3131 | DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); | |
3132 | return result; | |
3133 | } | |
3134 | ||
3135 | /* | |
3136 | * set modem control signals (DTR/RTS) | |
3137 | * | |
3138 | * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit | |
3139 | * TIOCMSET = set/clear signal values | |
3140 | * value bit mask for command | |
3141 | */ | |
3142 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
3143 | unsigned int set, unsigned int clear) | |
3144 | { | |
3145 | struct slgt_info *info = tty->driver_data; | |
3146 | unsigned long flags; | |
3147 | ||
3148 | DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); | |
3149 | ||
3150 | if (set & TIOCM_RTS) | |
3151 | info->signals |= SerialSignal_RTS; | |
3152 | if (set & TIOCM_DTR) | |
3153 | info->signals |= SerialSignal_DTR; | |
3154 | if (clear & TIOCM_RTS) | |
3155 | info->signals &= ~SerialSignal_RTS; | |
3156 | if (clear & TIOCM_DTR) | |
3157 | info->signals &= ~SerialSignal_DTR; | |
3158 | ||
3159 | spin_lock_irqsave(&info->lock,flags); | |
3160 | set_signals(info); | |
3161 | spin_unlock_irqrestore(&info->lock,flags); | |
3162 | return 0; | |
3163 | } | |
3164 | ||
31f35939 AC |
3165 | static int carrier_raised(struct tty_port *port) |
3166 | { | |
3167 | unsigned long flags; | |
3168 | struct slgt_info *info = container_of(port, struct slgt_info, port); | |
3169 | ||
3170 | spin_lock_irqsave(&info->lock,flags); | |
3171 | get_signals(info); | |
3172 | spin_unlock_irqrestore(&info->lock,flags); | |
3173 | return (info->signals & SerialSignal_DCD) ? 1 : 0; | |
3174 | } | |
3175 | ||
fcc8ac18 | 3176 | static void dtr_rts(struct tty_port *port, int on) |
5d951fb4 AC |
3177 | { |
3178 | unsigned long flags; | |
3179 | struct slgt_info *info = container_of(port, struct slgt_info, port); | |
3180 | ||
3181 | spin_lock_irqsave(&info->lock,flags); | |
fcc8ac18 AC |
3182 | if (on) |
3183 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
3184 | else | |
3185 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
5d951fb4 AC |
3186 | set_signals(info); |
3187 | spin_unlock_irqrestore(&info->lock,flags); | |
3188 | } | |
3189 | ||
3190 | ||
705b6c7b PF |
3191 | /* |
3192 | * block current process until the device is ready to open | |
3193 | */ | |
3194 | static int block_til_ready(struct tty_struct *tty, struct file *filp, | |
3195 | struct slgt_info *info) | |
3196 | { | |
3197 | DECLARE_WAITQUEUE(wait, current); | |
3198 | int retval; | |
0fab6de0 JP |
3199 | bool do_clocal = false; |
3200 | bool extra_count = false; | |
705b6c7b | 3201 | unsigned long flags; |
31f35939 AC |
3202 | int cd; |
3203 | struct tty_port *port = &info->port; | |
705b6c7b PF |
3204 | |
3205 | DBGINFO(("%s block_til_ready\n", tty->driver->name)); | |
3206 | ||
3207 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ | |
3208 | /* nonblock mode is set or port is not enabled */ | |
31f35939 | 3209 | port->flags |= ASYNC_NORMAL_ACTIVE; |
705b6c7b PF |
3210 | return 0; |
3211 | } | |
3212 | ||
3213 | if (tty->termios->c_cflag & CLOCAL) | |
0fab6de0 | 3214 | do_clocal = true; |
705b6c7b PF |
3215 | |
3216 | /* Wait for carrier detect and the line to become | |
3217 | * free (i.e., not in use by the callout). While we are in | |
31f35939 | 3218 | * this loop, port->count is dropped by one, so that |
705b6c7b PF |
3219 | * close() knows when to free things. We restore it upon |
3220 | * exit, either normal or abnormal. | |
3221 | */ | |
3222 | ||
3223 | retval = 0; | |
31f35939 | 3224 | add_wait_queue(&port->open_wait, &wait); |
705b6c7b PF |
3225 | |
3226 | spin_lock_irqsave(&info->lock, flags); | |
3227 | if (!tty_hung_up_p(filp)) { | |
0fab6de0 | 3228 | extra_count = true; |
31f35939 | 3229 | port->count--; |
705b6c7b PF |
3230 | } |
3231 | spin_unlock_irqrestore(&info->lock, flags); | |
31f35939 | 3232 | port->blocked_open++; |
705b6c7b PF |
3233 | |
3234 | while (1) { | |
5d951fb4 AC |
3235 | if ((tty->termios->c_cflag & CBAUD)) |
3236 | tty_port_raise_dtr_rts(port); | |
705b6c7b PF |
3237 | |
3238 | set_current_state(TASK_INTERRUPTIBLE); | |
3239 | ||
31f35939 AC |
3240 | if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ |
3241 | retval = (port->flags & ASYNC_HUP_NOTIFY) ? | |
705b6c7b PF |
3242 | -EAGAIN : -ERESTARTSYS; |
3243 | break; | |
3244 | } | |
3245 | ||
31f35939 | 3246 | cd = tty_port_carrier_raised(port); |
705b6c7b | 3247 | |
31f35939 | 3248 | if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd )) |
705b6c7b | 3249 | break; |
705b6c7b PF |
3250 | |
3251 | if (signal_pending(current)) { | |
3252 | retval = -ERESTARTSYS; | |
3253 | break; | |
3254 | } | |
3255 | ||
3256 | DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); | |
e142a31d | 3257 | tty_unlock(); |
705b6c7b | 3258 | schedule(); |
e142a31d | 3259 | tty_lock(); |
705b6c7b PF |
3260 | } |
3261 | ||
3262 | set_current_state(TASK_RUNNING); | |
31f35939 | 3263 | remove_wait_queue(&port->open_wait, &wait); |
705b6c7b PF |
3264 | |
3265 | if (extra_count) | |
31f35939 AC |
3266 | port->count++; |
3267 | port->blocked_open--; | |
705b6c7b PF |
3268 | |
3269 | if (!retval) | |
31f35939 | 3270 | port->flags |= ASYNC_NORMAL_ACTIVE; |
705b6c7b PF |
3271 | |
3272 | DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); | |
3273 | return retval; | |
3274 | } | |
3275 | ||
3276 | static int alloc_tmp_rbuf(struct slgt_info *info) | |
3277 | { | |
04b374d0 | 3278 | info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); |
705b6c7b PF |
3279 | if (info->tmp_rbuf == NULL) |
3280 | return -ENOMEM; | |
3281 | return 0; | |
3282 | } | |
3283 | ||
3284 | static void free_tmp_rbuf(struct slgt_info *info) | |
3285 | { | |
3286 | kfree(info->tmp_rbuf); | |
3287 | info->tmp_rbuf = NULL; | |
3288 | } | |
3289 | ||
3290 | /* | |
3291 | * allocate DMA descriptor lists. | |
3292 | */ | |
3293 | static int alloc_desc(struct slgt_info *info) | |
3294 | { | |
3295 | unsigned int i; | |
3296 | unsigned int pbufs; | |
3297 | ||
3298 | /* allocate memory to hold descriptor lists */ | |
3299 | info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr); | |
3300 | if (info->bufs == NULL) | |
3301 | return -ENOMEM; | |
3302 | ||
3303 | memset(info->bufs, 0, DESC_LIST_SIZE); | |
3304 | ||
3305 | info->rbufs = (struct slgt_desc*)info->bufs; | |
3306 | info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; | |
3307 | ||
3308 | pbufs = (unsigned int)info->bufs_dma_addr; | |
3309 | ||
3310 | /* | |
3311 | * Build circular lists of descriptors | |
3312 | */ | |
3313 | ||
3314 | for (i=0; i < info->rbuf_count; i++) { | |
3315 | /* physical address of this descriptor */ | |
3316 | info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); | |
3317 | ||
3318 | /* physical address of next descriptor */ | |
3319 | if (i == info->rbuf_count - 1) | |
3320 | info->rbufs[i].next = cpu_to_le32(pbufs); | |
3321 | else | |
3322 | info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); | |
3323 | set_desc_count(info->rbufs[i], DMABUFSIZE); | |
3324 | } | |
3325 | ||
3326 | for (i=0; i < info->tbuf_count; i++) { | |
3327 | /* physical address of this descriptor */ | |
3328 | info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); | |
3329 | ||
3330 | /* physical address of next descriptor */ | |
3331 | if (i == info->tbuf_count - 1) | |
3332 | info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); | |
3333 | else | |
3334 | info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); | |
3335 | } | |
3336 | ||
3337 | return 0; | |
3338 | } | |
3339 | ||
3340 | static void free_desc(struct slgt_info *info) | |
3341 | { | |
3342 | if (info->bufs != NULL) { | |
3343 | pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr); | |
3344 | info->bufs = NULL; | |
3345 | info->rbufs = NULL; | |
3346 | info->tbufs = NULL; | |
3347 | } | |
3348 | } | |
3349 | ||
3350 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
3351 | { | |
3352 | int i; | |
3353 | for (i=0; i < count; i++) { | |
3354 | if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL) | |
3355 | return -ENOMEM; | |
3356 | bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); | |
3357 | } | |
3358 | return 0; | |
3359 | } | |
3360 | ||
3361 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
3362 | { | |
3363 | int i; | |
3364 | for (i=0; i < count; i++) { | |
3365 | if (bufs[i].buf == NULL) | |
3366 | continue; | |
3367 | pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr); | |
3368 | bufs[i].buf = NULL; | |
3369 | } | |
3370 | } | |
3371 | ||
3372 | static int alloc_dma_bufs(struct slgt_info *info) | |
3373 | { | |
3374 | info->rbuf_count = 32; | |
3375 | info->tbuf_count = 32; | |
3376 | ||
3377 | if (alloc_desc(info) < 0 || | |
3378 | alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || | |
3379 | alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || | |
3380 | alloc_tmp_rbuf(info) < 0) { | |
3381 | DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); | |
3382 | return -ENOMEM; | |
3383 | } | |
3384 | reset_rbufs(info); | |
3385 | return 0; | |
3386 | } | |
3387 | ||
3388 | static void free_dma_bufs(struct slgt_info *info) | |
3389 | { | |
3390 | if (info->bufs) { | |
3391 | free_bufs(info, info->rbufs, info->rbuf_count); | |
3392 | free_bufs(info, info->tbufs, info->tbuf_count); | |
3393 | free_desc(info); | |
3394 | } | |
3395 | free_tmp_rbuf(info); | |
3396 | } | |
3397 | ||
3398 | static int claim_resources(struct slgt_info *info) | |
3399 | { | |
3400 | if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { | |
3401 | DBGERR(("%s reg addr conflict, addr=%08X\n", | |
3402 | info->device_name, info->phys_reg_addr)); | |
3403 | info->init_error = DiagStatus_AddressConflict; | |
3404 | goto errout; | |
3405 | } | |
3406 | else | |
0fab6de0 | 3407 | info->reg_addr_requested = true; |
705b6c7b | 3408 | |
24cb2335 | 3409 | info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE); |
705b6c7b PF |
3410 | if (!info->reg_addr) { |
3411 | DBGERR(("%s cant map device registers, addr=%08X\n", | |
3412 | info->device_name, info->phys_reg_addr)); | |
3413 | info->init_error = DiagStatus_CantAssignPciResources; | |
3414 | goto errout; | |
3415 | } | |
705b6c7b PF |
3416 | return 0; |
3417 | ||
3418 | errout: | |
3419 | release_resources(info); | |
3420 | return -ENODEV; | |
3421 | } | |
3422 | ||
3423 | static void release_resources(struct slgt_info *info) | |
3424 | { | |
3425 | if (info->irq_requested) { | |
3426 | free_irq(info->irq_level, info); | |
0fab6de0 | 3427 | info->irq_requested = false; |
705b6c7b PF |
3428 | } |
3429 | ||
3430 | if (info->reg_addr_requested) { | |
3431 | release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); | |
0fab6de0 | 3432 | info->reg_addr_requested = false; |
705b6c7b PF |
3433 | } |
3434 | ||
3435 | if (info->reg_addr) { | |
0c8365ec | 3436 | iounmap(info->reg_addr); |
705b6c7b PF |
3437 | info->reg_addr = NULL; |
3438 | } | |
3439 | } | |
3440 | ||
3441 | /* Add the specified device instance data structure to the | |
3442 | * global linked list of devices and increment the device count. | |
3443 | */ | |
3444 | static void add_device(struct slgt_info *info) | |
3445 | { | |
3446 | char *devstr; | |
3447 | ||
3448 | info->next_device = NULL; | |
3449 | info->line = slgt_device_count; | |
3450 | sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); | |
3451 | ||
3452 | if (info->line < MAX_DEVICES) { | |
3453 | if (maxframe[info->line]) | |
3454 | info->max_frame_size = maxframe[info->line]; | |
705b6c7b PF |
3455 | } |
3456 | ||
3457 | slgt_device_count++; | |
3458 | ||
3459 | if (!slgt_device_list) | |
3460 | slgt_device_list = info; | |
3461 | else { | |
3462 | struct slgt_info *current_dev = slgt_device_list; | |
3463 | while(current_dev->next_device) | |
3464 | current_dev = current_dev->next_device; | |
3465 | current_dev->next_device = info; | |
3466 | } | |
3467 | ||
3468 | if (info->max_frame_size < 4096) | |
3469 | info->max_frame_size = 4096; | |
3470 | else if (info->max_frame_size > 65535) | |
3471 | info->max_frame_size = 65535; | |
3472 | ||
3473 | switch(info->pdev->device) { | |
3474 | case SYNCLINK_GT_DEVICE_ID: | |
3475 | devstr = "GT"; | |
3476 | break; | |
6f84be84 PF |
3477 | case SYNCLINK_GT2_DEVICE_ID: |
3478 | devstr = "GT2"; | |
3479 | break; | |
705b6c7b PF |
3480 | case SYNCLINK_GT4_DEVICE_ID: |
3481 | devstr = "GT4"; | |
3482 | break; | |
3483 | case SYNCLINK_AC_DEVICE_ID: | |
3484 | devstr = "AC"; | |
3485 | info->params.mode = MGSL_MODE_ASYNC; | |
3486 | break; | |
3487 | default: | |
3488 | devstr = "(unknown model)"; | |
3489 | } | |
3490 | printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", | |
3491 | devstr, info->device_name, info->phys_reg_addr, | |
3492 | info->irq_level, info->max_frame_size); | |
3493 | ||
af69c7f9 | 3494 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
3495 | hdlcdev_init(info); |
3496 | #endif | |
3497 | } | |
3498 | ||
31f35939 AC |
3499 | static const struct tty_port_operations slgt_port_ops = { |
3500 | .carrier_raised = carrier_raised, | |
fcc8ac18 | 3501 | .dtr_rts = dtr_rts, |
31f35939 AC |
3502 | }; |
3503 | ||
705b6c7b PF |
3504 | /* |
3505 | * allocate device instance structure, return NULL on failure | |
3506 | */ | |
3507 | static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) | |
3508 | { | |
3509 | struct slgt_info *info; | |
3510 | ||
dd00cc48 | 3511 | info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); |
705b6c7b PF |
3512 | |
3513 | if (!info) { | |
3514 | DBGERR(("%s device alloc failed adapter=%d port=%d\n", | |
3515 | driver_name, adapter_num, port_num)); | |
3516 | } else { | |
44b7d1b3 | 3517 | tty_port_init(&info->port); |
31f35939 | 3518 | info->port.ops = &slgt_port_ops; |
705b6c7b | 3519 | info->magic = MGSL_MAGIC; |
c4028958 | 3520 | INIT_WORK(&info->task, bh_handler); |
705b6c7b | 3521 | info->max_frame_size = 4096; |
1f80769f | 3522 | info->base_clock = 14745600; |
814dae03 | 3523 | info->rbuf_fill_level = DMABUFSIZE; |
44b7d1b3 AC |
3524 | info->port.close_delay = 5*HZ/10; |
3525 | info->port.closing_wait = 30*HZ; | |
705b6c7b PF |
3526 | init_waitqueue_head(&info->status_event_wait_q); |
3527 | init_waitqueue_head(&info->event_wait_q); | |
3528 | spin_lock_init(&info->netlock); | |
3529 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
3530 | info->idle_mode = HDLC_TXIDLE_FLAGS; | |
3531 | info->adapter_num = adapter_num; | |
3532 | info->port_num = port_num; | |
3533 | ||
40565f19 JS |
3534 | setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); |
3535 | setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info); | |
705b6c7b PF |
3536 | |
3537 | /* Copy configuration info to device instance data */ | |
3538 | info->pdev = pdev; | |
3539 | info->irq_level = pdev->irq; | |
3540 | info->phys_reg_addr = pci_resource_start(pdev,0); | |
3541 | ||
705b6c7b | 3542 | info->bus_type = MGSL_BUS_TYPE_PCI; |
0f2ed4c6 | 3543 | info->irq_flags = IRQF_SHARED; |
705b6c7b PF |
3544 | |
3545 | info->init_error = -1; /* assume error, set to 0 on successful init */ | |
3546 | } | |
3547 | ||
3548 | return info; | |
3549 | } | |
3550 | ||
3551 | static void device_init(int adapter_num, struct pci_dev *pdev) | |
3552 | { | |
3553 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
3554 | int i; | |
3555 | int port_count = 1; | |
3556 | ||
6f84be84 PF |
3557 | if (pdev->device == SYNCLINK_GT2_DEVICE_ID) |
3558 | port_count = 2; | |
3559 | else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) | |
705b6c7b PF |
3560 | port_count = 4; |
3561 | ||
3562 | /* allocate device instances for all ports */ | |
3563 | for (i=0; i < port_count; ++i) { | |
3564 | port_array[i] = alloc_dev(adapter_num, i, pdev); | |
3565 | if (port_array[i] == NULL) { | |
3566 | for (--i; i >= 0; --i) | |
3567 | kfree(port_array[i]); | |
3568 | return; | |
3569 | } | |
3570 | } | |
3571 | ||
3572 | /* give copy of port_array to all ports and add to device list */ | |
3573 | for (i=0; i < port_count; ++i) { | |
3574 | memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); | |
3575 | add_device(port_array[i]); | |
3576 | port_array[i]->port_count = port_count; | |
3577 | spin_lock_init(&port_array[i]->lock); | |
3578 | } | |
3579 | ||
3580 | /* Allocate and claim adapter resources */ | |
3581 | if (!claim_resources(port_array[0])) { | |
3582 | ||
3583 | alloc_dma_bufs(port_array[0]); | |
3584 | ||
3585 | /* copy resource information from first port to others */ | |
3586 | for (i = 1; i < port_count; ++i) { | |
705b6c7b PF |
3587 | port_array[i]->irq_level = port_array[0]->irq_level; |
3588 | port_array[i]->reg_addr = port_array[0]->reg_addr; | |
3589 | alloc_dma_bufs(port_array[i]); | |
3590 | } | |
3591 | ||
3592 | if (request_irq(port_array[0]->irq_level, | |
3593 | slgt_interrupt, | |
3594 | port_array[0]->irq_flags, | |
3595 | port_array[0]->device_name, | |
3596 | port_array[0]) < 0) { | |
3597 | DBGERR(("%s request_irq failed IRQ=%d\n", | |
3598 | port_array[0]->device_name, | |
3599 | port_array[0]->irq_level)); | |
3600 | } else { | |
0fab6de0 | 3601 | port_array[0]->irq_requested = true; |
705b6c7b | 3602 | adapter_test(port_array[0]); |
0080b7aa | 3603 | for (i=1 ; i < port_count ; i++) { |
705b6c7b | 3604 | port_array[i]->init_error = port_array[0]->init_error; |
0080b7aa PF |
3605 | port_array[i]->gpio_present = port_array[0]->gpio_present; |
3606 | } | |
705b6c7b PF |
3607 | } |
3608 | } | |
62eb5b1f PF |
3609 | |
3610 | for (i=0; i < port_count; ++i) | |
3611 | tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev)); | |
705b6c7b PF |
3612 | } |
3613 | ||
3614 | static int __devinit init_one(struct pci_dev *dev, | |
3615 | const struct pci_device_id *ent) | |
3616 | { | |
3617 | if (pci_enable_device(dev)) { | |
3618 | printk("error enabling pci device %p\n", dev); | |
3619 | return -EIO; | |
3620 | } | |
3621 | pci_set_master(dev); | |
3622 | device_init(slgt_device_count, dev); | |
3623 | return 0; | |
3624 | } | |
3625 | ||
3626 | static void __devexit remove_one(struct pci_dev *dev) | |
3627 | { | |
3628 | } | |
3629 | ||
b68e31d0 | 3630 | static const struct tty_operations ops = { |
705b6c7b PF |
3631 | .open = open, |
3632 | .close = close, | |
3633 | .write = write, | |
3634 | .put_char = put_char, | |
3635 | .flush_chars = flush_chars, | |
3636 | .write_room = write_room, | |
3637 | .chars_in_buffer = chars_in_buffer, | |
3638 | .flush_buffer = flush_buffer, | |
3639 | .ioctl = ioctl, | |
2acdb169 | 3640 | .compat_ioctl = slgt_compat_ioctl, |
705b6c7b PF |
3641 | .throttle = throttle, |
3642 | .unthrottle = unthrottle, | |
3643 | .send_xchar = send_xchar, | |
3644 | .break_ctl = set_break, | |
3645 | .wait_until_sent = wait_until_sent, | |
705b6c7b PF |
3646 | .set_termios = set_termios, |
3647 | .stop = tx_hold, | |
3648 | .start = tx_release, | |
3649 | .hangup = hangup, | |
3650 | .tiocmget = tiocmget, | |
3651 | .tiocmset = tiocmset, | |
0587102c | 3652 | .get_icount = get_icount, |
a18c56e5 | 3653 | .proc_fops = &synclink_gt_proc_fops, |
705b6c7b PF |
3654 | }; |
3655 | ||
3656 | static void slgt_cleanup(void) | |
3657 | { | |
3658 | int rc; | |
3659 | struct slgt_info *info; | |
3660 | struct slgt_info *tmp; | |
3661 | ||
a6b2f87b | 3662 | printk(KERN_INFO "unload %s\n", driver_name); |
705b6c7b PF |
3663 | |
3664 | if (serial_driver) { | |
62eb5b1f PF |
3665 | for (info=slgt_device_list ; info != NULL ; info=info->next_device) |
3666 | tty_unregister_device(serial_driver, info->line); | |
705b6c7b PF |
3667 | if ((rc = tty_unregister_driver(serial_driver))) |
3668 | DBGERR(("tty_unregister_driver error=%d\n", rc)); | |
3669 | put_tty_driver(serial_driver); | |
3670 | } | |
3671 | ||
3672 | /* reset devices */ | |
3673 | info = slgt_device_list; | |
3674 | while(info) { | |
3675 | reset_port(info); | |
3676 | info = info->next_device; | |
3677 | } | |
3678 | ||
3679 | /* release devices */ | |
3680 | info = slgt_device_list; | |
3681 | while(info) { | |
af69c7f9 | 3682 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
3683 | hdlcdev_exit(info); |
3684 | #endif | |
3685 | free_dma_bufs(info); | |
3686 | free_tmp_rbuf(info); | |
3687 | if (info->port_num == 0) | |
3688 | release_resources(info); | |
3689 | tmp = info; | |
3690 | info = info->next_device; | |
3691 | kfree(tmp); | |
3692 | } | |
3693 | ||
3694 | if (pci_registered) | |
3695 | pci_unregister_driver(&pci_driver); | |
3696 | } | |
3697 | ||
3698 | /* | |
3699 | * Driver initialization entry point. | |
3700 | */ | |
3701 | static int __init slgt_init(void) | |
3702 | { | |
3703 | int rc; | |
3704 | ||
a6b2f87b | 3705 | printk(KERN_INFO "%s\n", driver_name); |
705b6c7b | 3706 | |
705b6c7b PF |
3707 | serial_driver = alloc_tty_driver(MAX_DEVICES); |
3708 | if (!serial_driver) { | |
62eb5b1f PF |
3709 | printk("%s can't allocate tty driver\n", driver_name); |
3710 | return -ENOMEM; | |
705b6c7b PF |
3711 | } |
3712 | ||
3713 | /* Initialize the tty_driver structure */ | |
3714 | ||
3715 | serial_driver->owner = THIS_MODULE; | |
3716 | serial_driver->driver_name = tty_driver_name; | |
3717 | serial_driver->name = tty_dev_prefix; | |
3718 | serial_driver->major = ttymajor; | |
3719 | serial_driver->minor_start = 64; | |
3720 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
3721 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
3722 | serial_driver->init_termios = tty_std_termios; | |
3723 | serial_driver->init_termios.c_cflag = | |
3724 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
606d099c AC |
3725 | serial_driver->init_termios.c_ispeed = 9600; |
3726 | serial_driver->init_termios.c_ospeed = 9600; | |
62eb5b1f | 3727 | serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; |
705b6c7b PF |
3728 | tty_set_operations(serial_driver, &ops); |
3729 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
3730 | DBGERR(("%s can't register serial driver\n", driver_name)); | |
3731 | put_tty_driver(serial_driver); | |
3732 | serial_driver = NULL; | |
3733 | goto error; | |
3734 | } | |
3735 | ||
a6b2f87b PF |
3736 | printk(KERN_INFO "%s, tty major#%d\n", |
3737 | driver_name, serial_driver->major); | |
705b6c7b | 3738 | |
62eb5b1f PF |
3739 | slgt_device_count = 0; |
3740 | if ((rc = pci_register_driver(&pci_driver)) < 0) { | |
3741 | printk("%s pci_register_driver error=%d\n", driver_name, rc); | |
3742 | goto error; | |
3743 | } | |
0fab6de0 | 3744 | pci_registered = true; |
62eb5b1f PF |
3745 | |
3746 | if (!slgt_device_list) | |
3747 | printk("%s no devices found\n",driver_name); | |
3748 | ||
705b6c7b PF |
3749 | return 0; |
3750 | ||
3751 | error: | |
3752 | slgt_cleanup(); | |
3753 | return rc; | |
3754 | } | |
3755 | ||
3756 | static void __exit slgt_exit(void) | |
3757 | { | |
3758 | slgt_cleanup(); | |
3759 | } | |
3760 | ||
3761 | module_init(slgt_init); | |
3762 | module_exit(slgt_exit); | |
3763 | ||
3764 | /* | |
3765 | * register access routines | |
3766 | */ | |
3767 | ||
3768 | #define CALC_REGADDR() \ | |
3769 | unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ | |
3770 | if (addr >= 0x80) \ | |
3771 | reg_addr += (info->port_num) * 32; | |
3772 | ||
3773 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) | |
3774 | { | |
3775 | CALC_REGADDR(); | |
3776 | return readb((void __iomem *)reg_addr); | |
3777 | } | |
3778 | ||
3779 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) | |
3780 | { | |
3781 | CALC_REGADDR(); | |
3782 | writeb(value, (void __iomem *)reg_addr); | |
3783 | } | |
3784 | ||
3785 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) | |
3786 | { | |
3787 | CALC_REGADDR(); | |
3788 | return readw((void __iomem *)reg_addr); | |
3789 | } | |
3790 | ||
3791 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) | |
3792 | { | |
3793 | CALC_REGADDR(); | |
3794 | writew(value, (void __iomem *)reg_addr); | |
3795 | } | |
3796 | ||
3797 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) | |
3798 | { | |
3799 | CALC_REGADDR(); | |
3800 | return readl((void __iomem *)reg_addr); | |
3801 | } | |
3802 | ||
3803 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) | |
3804 | { | |
3805 | CALC_REGADDR(); | |
3806 | writel(value, (void __iomem *)reg_addr); | |
3807 | } | |
3808 | ||
3809 | static void rdma_reset(struct slgt_info *info) | |
3810 | { | |
3811 | unsigned int i; | |
3812 | ||
3813 | /* set reset bit */ | |
3814 | wr_reg32(info, RDCSR, BIT1); | |
3815 | ||
3816 | /* wait for enable bit cleared */ | |
3817 | for(i=0 ; i < 1000 ; i++) | |
3818 | if (!(rd_reg32(info, RDCSR) & BIT0)) | |
3819 | break; | |
3820 | } | |
3821 | ||
3822 | static void tdma_reset(struct slgt_info *info) | |
3823 | { | |
3824 | unsigned int i; | |
3825 | ||
3826 | /* set reset bit */ | |
3827 | wr_reg32(info, TDCSR, BIT1); | |
3828 | ||
3829 | /* wait for enable bit cleared */ | |
3830 | for(i=0 ; i < 1000 ; i++) | |
3831 | if (!(rd_reg32(info, TDCSR) & BIT0)) | |
3832 | break; | |
3833 | } | |
3834 | ||
3835 | /* | |
3836 | * enable internal loopback | |
3837 | * TxCLK and RxCLK are generated from BRG | |
3838 | * and TxD is looped back to RxD internally. | |
3839 | */ | |
3840 | static void enable_loopback(struct slgt_info *info) | |
3841 | { | |
3842 | /* SCR (serial control) BIT2=looopback enable */ | |
3843 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); | |
3844 | ||
3845 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3846 | /* CCR (clock control) | |
3847 | * 07..05 tx clock source (010 = BRG) | |
3848 | * 04..02 rx clock source (010 = BRG) | |
3849 | * 01 auxclk enable (0 = disable) | |
3850 | * 00 BRG enable (1 = enable) | |
3851 | * | |
3852 | * 0100 1001 | |
3853 | */ | |
3854 | wr_reg8(info, CCR, 0x49); | |
3855 | ||
3856 | /* set speed if available, otherwise use default */ | |
3857 | if (info->params.clock_speed) | |
3858 | set_rate(info, info->params.clock_speed); | |
3859 | else | |
3860 | set_rate(info, 3686400); | |
3861 | } | |
3862 | } | |
3863 | ||
3864 | /* | |
3865 | * set baud rate generator to specified rate | |
3866 | */ | |
3867 | static void set_rate(struct slgt_info *info, u32 rate) | |
3868 | { | |
3869 | unsigned int div; | |
1f80769f | 3870 | unsigned int osc = info->base_clock; |
705b6c7b PF |
3871 | |
3872 | /* div = osc/rate - 1 | |
3873 | * | |
3874 | * Round div up if osc/rate is not integer to | |
3875 | * force to next slowest rate. | |
3876 | */ | |
3877 | ||
3878 | if (rate) { | |
3879 | div = osc/rate; | |
3880 | if (!(osc % rate) && div) | |
3881 | div--; | |
3882 | wr_reg16(info, BDR, (unsigned short)div); | |
3883 | } | |
3884 | } | |
3885 | ||
3886 | static void rx_stop(struct slgt_info *info) | |
3887 | { | |
3888 | unsigned short val; | |
3889 | ||
3890 | /* disable and reset receiver */ | |
3891 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3892 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3893 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3894 | ||
3895 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); | |
3896 | ||
3897 | /* clear pending rx interrupts */ | |
3898 | wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); | |
3899 | ||
3900 | rdma_reset(info); | |
3901 | ||
0fab6de0 JP |
3902 | info->rx_enabled = false; |
3903 | info->rx_restart = false; | |
705b6c7b PF |
3904 | } |
3905 | ||
3906 | static void rx_start(struct slgt_info *info) | |
3907 | { | |
3908 | unsigned short val; | |
3909 | ||
3910 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); | |
3911 | ||
3912 | /* clear pending rx overrun IRQ */ | |
3913 | wr_reg16(info, SSR, IRQ_RXOVER); | |
3914 | ||
3915 | /* reset and disable receiver */ | |
3916 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3917 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3918 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3919 | ||
3920 | rdma_reset(info); | |
3921 | reset_rbufs(info); | |
3922 | ||
5ba5a5d2 PF |
3923 | if (info->rx_pio) { |
3924 | /* rx request when rx FIFO not empty */ | |
3925 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); | |
3926 | slgt_irq_on(info, IRQ_RXDATA); | |
3927 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
3928 | /* enable saving of rx status */ | |
3929 | wr_reg32(info, RDCSR, BIT6); | |
3930 | } | |
705b6c7b | 3931 | } else { |
5ba5a5d2 PF |
3932 | /* rx request when rx FIFO half full */ |
3933 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); | |
3934 | /* set 1st descriptor address */ | |
3935 | wr_reg32(info, RDDAR, info->rbufs[0].pdesc); | |
3936 | ||
3937 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3938 | /* enable rx DMA and DMA interrupt */ | |
3939 | wr_reg32(info, RDCSR, (BIT2 + BIT0)); | |
3940 | } else { | |
3941 | /* enable saving of rx status, rx DMA and DMA interrupt */ | |
3942 | wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); | |
3943 | } | |
705b6c7b PF |
3944 | } |
3945 | ||
3946 | slgt_irq_on(info, IRQ_RXOVER); | |
3947 | ||
3948 | /* enable receiver */ | |
3949 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); | |
3950 | ||
0fab6de0 JP |
3951 | info->rx_restart = false; |
3952 | info->rx_enabled = true; | |
705b6c7b PF |
3953 | } |
3954 | ||
3955 | static void tx_start(struct slgt_info *info) | |
3956 | { | |
3957 | if (!info->tx_enabled) { | |
3958 | wr_reg16(info, TCR, | |
cb10dc9a | 3959 | (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); |
0fab6de0 | 3960 | info->tx_enabled = true; |
705b6c7b PF |
3961 | } |
3962 | ||
de538eb3 | 3963 | if (desc_count(info->tbufs[info->tbuf_start])) { |
0fab6de0 | 3964 | info->drop_rts_on_tx_done = false; |
705b6c7b PF |
3965 | |
3966 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3967 | if (info->params.flags & HDLC_FLAG_AUTO_RTS) { | |
3968 | get_signals(info); | |
3969 | if (!(info->signals & SerialSignal_RTS)) { | |
3970 | info->signals |= SerialSignal_RTS; | |
3971 | set_signals(info); | |
0fab6de0 | 3972 | info->drop_rts_on_tx_done = true; |
705b6c7b PF |
3973 | } |
3974 | } | |
3975 | ||
3976 | slgt_irq_off(info, IRQ_TXDATA); | |
3977 | slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); | |
3978 | /* clear tx idle and underrun status bits */ | |
3979 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
705b6c7b | 3980 | } else { |
705b6c7b PF |
3981 | slgt_irq_off(info, IRQ_TXDATA); |
3982 | slgt_irq_on(info, IRQ_TXIDLE); | |
3983 | /* clear tx idle status bit */ | |
3984 | wr_reg16(info, SSR, IRQ_TXIDLE); | |
705b6c7b | 3985 | } |
ce89294c PF |
3986 | /* set 1st descriptor address and start DMA */ |
3987 | wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); | |
3988 | wr_reg32(info, TDCSR, BIT2 + BIT0); | |
0fab6de0 | 3989 | info->tx_active = true; |
705b6c7b PF |
3990 | } |
3991 | } | |
3992 | ||
3993 | static void tx_stop(struct slgt_info *info) | |
3994 | { | |
3995 | unsigned short val; | |
3996 | ||
3997 | del_timer(&info->tx_timer); | |
3998 | ||
3999 | tdma_reset(info); | |
4000 | ||
4001 | /* reset and disable transmitter */ | |
4002 | val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ | |
4003 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
705b6c7b PF |
4004 | |
4005 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
4006 | ||
4007 | /* clear tx idle and underrun status bit */ | |
4008 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
4009 | ||
4010 | reset_tbufs(info); | |
4011 | ||
0fab6de0 JP |
4012 | info->tx_enabled = false; |
4013 | info->tx_active = false; | |
705b6c7b PF |
4014 | } |
4015 | ||
4016 | static void reset_port(struct slgt_info *info) | |
4017 | { | |
4018 | if (!info->reg_addr) | |
4019 | return; | |
4020 | ||
4021 | tx_stop(info); | |
4022 | rx_stop(info); | |
4023 | ||
4024 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
4025 | set_signals(info); | |
4026 | ||
4027 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
4028 | } | |
4029 | ||
4030 | static void reset_adapter(struct slgt_info *info) | |
4031 | { | |
4032 | int i; | |
4033 | for (i=0; i < info->port_count; ++i) { | |
4034 | if (info->port_array[i]) | |
4035 | reset_port(info->port_array[i]); | |
4036 | } | |
4037 | } | |
4038 | ||
4039 | static void async_mode(struct slgt_info *info) | |
4040 | { | |
4041 | unsigned short val; | |
4042 | ||
4043 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
4044 | tx_stop(info); | |
4045 | rx_stop(info); | |
4046 | ||
4047 | /* TCR (tx control) | |
4048 | * | |
4049 | * 15..13 mode, 010=async | |
4050 | * 12..10 encoding, 000=NRZ | |
4051 | * 09 parity enable | |
4052 | * 08 1=odd parity, 0=even parity | |
4053 | * 07 1=RTS driver control | |
4054 | * 06 1=break enable | |
4055 | * 05..04 character length | |
4056 | * 00=5 bits | |
4057 | * 01=6 bits | |
4058 | * 10=7 bits | |
4059 | * 11=8 bits | |
4060 | * 03 0=1 stop bit, 1=2 stop bits | |
4061 | * 02 reset | |
4062 | * 01 enable | |
4063 | * 00 auto-CTS enable | |
4064 | */ | |
4065 | val = 0x4000; | |
4066 | ||
4067 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
4068 | val |= BIT7; | |
4069 | ||
4070 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4071 | val |= BIT9; | |
4072 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4073 | val |= BIT8; | |
4074 | } | |
4075 | ||
4076 | switch (info->params.data_bits) | |
4077 | { | |
4078 | case 6: val |= BIT4; break; | |
4079 | case 7: val |= BIT5; break; | |
4080 | case 8: val |= BIT5 + BIT4; break; | |
4081 | } | |
4082 | ||
4083 | if (info->params.stop_bits != 1) | |
4084 | val |= BIT3; | |
4085 | ||
4086 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4087 | val |= BIT0; | |
4088 | ||
4089 | wr_reg16(info, TCR, val); | |
4090 | ||
4091 | /* RCR (rx control) | |
4092 | * | |
4093 | * 15..13 mode, 010=async | |
4094 | * 12..10 encoding, 000=NRZ | |
4095 | * 09 parity enable | |
4096 | * 08 1=odd parity, 0=even parity | |
4097 | * 07..06 reserved, must be 0 | |
4098 | * 05..04 character length | |
4099 | * 00=5 bits | |
4100 | * 01=6 bits | |
4101 | * 10=7 bits | |
4102 | * 11=8 bits | |
4103 | * 03 reserved, must be zero | |
4104 | * 02 reset | |
4105 | * 01 enable | |
4106 | * 00 auto-DCD enable | |
4107 | */ | |
4108 | val = 0x4000; | |
4109 | ||
4110 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4111 | val |= BIT9; | |
4112 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4113 | val |= BIT8; | |
4114 | } | |
4115 | ||
4116 | switch (info->params.data_bits) | |
4117 | { | |
4118 | case 6: val |= BIT4; break; | |
4119 | case 7: val |= BIT5; break; | |
4120 | case 8: val |= BIT5 + BIT4; break; | |
4121 | } | |
4122 | ||
4123 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4124 | val |= BIT0; | |
4125 | ||
4126 | wr_reg16(info, RCR, val); | |
4127 | ||
4128 | /* CCR (clock control) | |
4129 | * | |
4130 | * 07..05 011 = tx clock source is BRG/16 | |
4131 | * 04..02 010 = rx clock source is BRG | |
4132 | * 01 0 = auxclk disabled | |
4133 | * 00 1 = BRG enabled | |
4134 | * | |
4135 | * 0110 1001 | |
4136 | */ | |
4137 | wr_reg8(info, CCR, 0x69); | |
4138 | ||
4139 | msc_set_vcr(info); | |
4140 | ||
705b6c7b PF |
4141 | /* SCR (serial control) |
4142 | * | |
4143 | * 15 1=tx req on FIFO half empty | |
4144 | * 14 1=rx req on FIFO half full | |
4145 | * 13 tx data IRQ enable | |
4146 | * 12 tx idle IRQ enable | |
4147 | * 11 rx break on IRQ enable | |
4148 | * 10 rx data IRQ enable | |
4149 | * 09 rx break off IRQ enable | |
4150 | * 08 overrun IRQ enable | |
4151 | * 07 DSR IRQ enable | |
4152 | * 06 CTS IRQ enable | |
4153 | * 05 DCD IRQ enable | |
4154 | * 04 RI IRQ enable | |
1f80769f | 4155 | * 03 0=16x sampling, 1=8x sampling |
705b6c7b PF |
4156 | * 02 1=txd->rxd internal loopback enable |
4157 | * 01 reserved, must be zero | |
4158 | * 00 1=master IRQ enable | |
4159 | */ | |
4160 | val = BIT15 + BIT14 + BIT0; | |
1f80769f PF |
4161 | /* JCR[8] : 1 = x8 async mode feature available */ |
4162 | if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && | |
4163 | ((info->base_clock < (info->params.data_rate * 16)) || | |
4164 | (info->base_clock % (info->params.data_rate * 16)))) { | |
4165 | /* use 8x sampling */ | |
4166 | val |= BIT3; | |
4167 | set_rate(info, info->params.data_rate * 8); | |
4168 | } else { | |
4169 | /* use 16x sampling */ | |
4170 | set_rate(info, info->params.data_rate * 16); | |
4171 | } | |
705b6c7b PF |
4172 | wr_reg16(info, SCR, val); |
4173 | ||
4174 | slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); | |
4175 | ||
705b6c7b PF |
4176 | if (info->params.loopback) |
4177 | enable_loopback(info); | |
4178 | } | |
4179 | ||
cb10dc9a | 4180 | static void sync_mode(struct slgt_info *info) |
705b6c7b PF |
4181 | { |
4182 | unsigned short val; | |
4183 | ||
4184 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
4185 | tx_stop(info); | |
4186 | rx_stop(info); | |
4187 | ||
4188 | /* TCR (tx control) | |
4189 | * | |
cb10dc9a | 4190 | * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync |
705b6c7b PF |
4191 | * 12..10 encoding |
4192 | * 09 CRC enable | |
4193 | * 08 CRC32 | |
4194 | * 07 1=RTS driver control | |
4195 | * 06 preamble enable | |
4196 | * 05..04 preamble length | |
4197 | * 03 share open/close flag | |
4198 | * 02 reset | |
4199 | * 01 enable | |
4200 | * 00 auto-CTS enable | |
4201 | */ | |
993456cd | 4202 | val = BIT2; |
705b6c7b | 4203 | |
cb10dc9a PF |
4204 | switch(info->params.mode) { |
4205 | case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; | |
4206 | case MGSL_MODE_BISYNC: val |= BIT15; break; | |
4207 | case MGSL_MODE_RAW: val |= BIT13; break; | |
4208 | } | |
705b6c7b PF |
4209 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) |
4210 | val |= BIT7; | |
4211 | ||
4212 | switch(info->params.encoding) | |
4213 | { | |
4214 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
4215 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
4216 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
4217 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
4218 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
4219 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
4220 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
4221 | } | |
4222 | ||
04b374d0 | 4223 | switch (info->params.crc_type & HDLC_CRC_MASK) |
705b6c7b PF |
4224 | { |
4225 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
4226 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
4227 | } | |
4228 | ||
4229 | if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) | |
4230 | val |= BIT6; | |
4231 | ||
4232 | switch (info->params.preamble_length) | |
4233 | { | |
4234 | case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; | |
4235 | case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; | |
4236 | case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; | |
4237 | } | |
4238 | ||
4239 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4240 | val |= BIT0; | |
4241 | ||
4242 | wr_reg16(info, TCR, val); | |
4243 | ||
4244 | /* TPR (transmit preamble) */ | |
4245 | ||
4246 | switch (info->params.preamble) | |
4247 | { | |
4248 | case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; | |
4249 | case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; | |
4250 | case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; | |
4251 | case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; | |
4252 | case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; | |
4253 | default: val = 0x7e; break; | |
4254 | } | |
4255 | wr_reg8(info, TPR, (unsigned char)val); | |
4256 | ||
4257 | /* RCR (rx control) | |
4258 | * | |
cb10dc9a | 4259 | * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync |
705b6c7b PF |
4260 | * 12..10 encoding |
4261 | * 09 CRC enable | |
4262 | * 08 CRC32 | |
4263 | * 07..03 reserved, must be 0 | |
4264 | * 02 reset | |
4265 | * 01 enable | |
4266 | * 00 auto-DCD enable | |
4267 | */ | |
4268 | val = 0; | |
4269 | ||
cb10dc9a PF |
4270 | switch(info->params.mode) { |
4271 | case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; | |
4272 | case MGSL_MODE_BISYNC: val |= BIT15; break; | |
4273 | case MGSL_MODE_RAW: val |= BIT13; break; | |
4274 | } | |
705b6c7b PF |
4275 | |
4276 | switch(info->params.encoding) | |
4277 | { | |
4278 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
4279 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
4280 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
4281 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
4282 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
4283 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
4284 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
4285 | } | |
4286 | ||
04b374d0 | 4287 | switch (info->params.crc_type & HDLC_CRC_MASK) |
705b6c7b PF |
4288 | { |
4289 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
4290 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
4291 | } | |
4292 | ||
4293 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4294 | val |= BIT0; | |
4295 | ||
4296 | wr_reg16(info, RCR, val); | |
4297 | ||
4298 | /* CCR (clock control) | |
4299 | * | |
4300 | * 07..05 tx clock source | |
4301 | * 04..02 rx clock source | |
4302 | * 01 auxclk enable | |
4303 | * 00 BRG enable | |
4304 | */ | |
4305 | val = 0; | |
4306 | ||
4307 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
4308 | { | |
4309 | // when RxC source is DPLL, BRG generates 16X DPLL | |
4310 | // reference clock, so take TxC from BRG/16 to get | |
4311 | // transmit clock at actual data rate | |
4312 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4313 | val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ | |
4314 | else | |
4315 | val |= BIT6; /* 010, txclk = BRG */ | |
4316 | } | |
4317 | else if (info->params.flags & HDLC_FLAG_TXC_DPLL) | |
4318 | val |= BIT7; /* 100, txclk = DPLL Input */ | |
4319 | else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) | |
4320 | val |= BIT5; /* 001, txclk = RXC Input */ | |
4321 | ||
4322 | if (info->params.flags & HDLC_FLAG_RXC_BRG) | |
4323 | val |= BIT3; /* 010, rxclk = BRG */ | |
4324 | else if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4325 | val |= BIT4; /* 100, rxclk = DPLL */ | |
4326 | else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) | |
4327 | val |= BIT2; /* 001, rxclk = TXC Input */ | |
4328 | ||
4329 | if (info->params.clock_speed) | |
4330 | val |= BIT1 + BIT0; | |
4331 | ||
4332 | wr_reg8(info, CCR, (unsigned char)val); | |
4333 | ||
4334 | if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) | |
4335 | { | |
4336 | // program DPLL mode | |
4337 | switch(info->params.encoding) | |
4338 | { | |
4339 | case HDLC_ENCODING_BIPHASE_MARK: | |
4340 | case HDLC_ENCODING_BIPHASE_SPACE: | |
4341 | val = BIT7; break; | |
4342 | case HDLC_ENCODING_BIPHASE_LEVEL: | |
4343 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: | |
4344 | val = BIT7 + BIT6; break; | |
4345 | default: val = BIT6; // NRZ encodings | |
4346 | } | |
4347 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); | |
4348 | ||
4349 | // DPLL requires a 16X reference clock from BRG | |
4350 | set_rate(info, info->params.clock_speed * 16); | |
4351 | } | |
4352 | else | |
4353 | set_rate(info, info->params.clock_speed); | |
4354 | ||
4355 | tx_set_idle(info); | |
4356 | ||
4357 | msc_set_vcr(info); | |
4358 | ||
4359 | /* SCR (serial control) | |
4360 | * | |
4361 | * 15 1=tx req on FIFO half empty | |
4362 | * 14 1=rx req on FIFO half full | |
4363 | * 13 tx data IRQ enable | |
4364 | * 12 tx idle IRQ enable | |
4365 | * 11 underrun IRQ enable | |
4366 | * 10 rx data IRQ enable | |
4367 | * 09 rx idle IRQ enable | |
4368 | * 08 overrun IRQ enable | |
4369 | * 07 DSR IRQ enable | |
4370 | * 06 CTS IRQ enable | |
4371 | * 05 DCD IRQ enable | |
4372 | * 04 RI IRQ enable | |
4373 | * 03 reserved, must be zero | |
4374 | * 02 1=txd->rxd internal loopback enable | |
4375 | * 01 reserved, must be zero | |
4376 | * 00 1=master IRQ enable | |
4377 | */ | |
4378 | wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); | |
4379 | ||
4380 | if (info->params.loopback) | |
4381 | enable_loopback(info); | |
4382 | } | |
4383 | ||
4384 | /* | |
4385 | * set transmit idle mode | |
4386 | */ | |
4387 | static void tx_set_idle(struct slgt_info *info) | |
4388 | { | |
643f3319 PF |
4389 | unsigned char val; |
4390 | unsigned short tcr; | |
705b6c7b | 4391 | |
643f3319 PF |
4392 | /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits |
4393 | * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits | |
4394 | */ | |
4395 | tcr = rd_reg16(info, TCR); | |
4396 | if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { | |
4397 | /* disable preamble, set idle size to 16 bits */ | |
4398 | tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; | |
4399 | /* MSB of 16 bit idle specified in tx preamble register (TPR) */ | |
4400 | wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); | |
4401 | } else if (!(tcr & BIT6)) { | |
4402 | /* preamble is disabled, set idle size to 8 bits */ | |
4403 | tcr &= ~(BIT5 + BIT4); | |
4404 | } | |
4405 | wr_reg16(info, TCR, tcr); | |
4406 | ||
4407 | if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { | |
4408 | /* LSB of custom tx idle specified in tx idle register */ | |
4409 | val = (unsigned char)(info->idle_mode & 0xff); | |
4410 | } else { | |
4411 | /* standard 8 bit idle patterns */ | |
4412 | switch(info->idle_mode) | |
4413 | { | |
4414 | case HDLC_TXIDLE_FLAGS: val = 0x7e; break; | |
4415 | case HDLC_TXIDLE_ALT_ZEROS_ONES: | |
4416 | case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; | |
4417 | case HDLC_TXIDLE_ZEROS: | |
4418 | case HDLC_TXIDLE_SPACE: val = 0x00; break; | |
4419 | default: val = 0xff; | |
4420 | } | |
705b6c7b PF |
4421 | } |
4422 | ||
4423 | wr_reg8(info, TIR, val); | |
4424 | } | |
4425 | ||
4426 | /* | |
4427 | * get state of V24 status (input) signals | |
4428 | */ | |
4429 | static void get_signals(struct slgt_info *info) | |
4430 | { | |
4431 | unsigned short status = rd_reg16(info, SSR); | |
4432 | ||
4433 | /* clear all serial signals except DTR and RTS */ | |
4434 | info->signals &= SerialSignal_DTR + SerialSignal_RTS; | |
4435 | ||
4436 | if (status & BIT3) | |
4437 | info->signals |= SerialSignal_DSR; | |
4438 | if (status & BIT2) | |
4439 | info->signals |= SerialSignal_CTS; | |
4440 | if (status & BIT1) | |
4441 | info->signals |= SerialSignal_DCD; | |
4442 | if (status & BIT0) | |
4443 | info->signals |= SerialSignal_RI; | |
4444 | } | |
4445 | ||
4446 | /* | |
4447 | * set V.24 Control Register based on current configuration | |
4448 | */ | |
4449 | static void msc_set_vcr(struct slgt_info *info) | |
4450 | { | |
4451 | unsigned char val = 0; | |
4452 | ||
4453 | /* VCR (V.24 control) | |
4454 | * | |
4455 | * 07..04 serial IF select | |
4456 | * 03 DTR | |
4457 | * 02 RTS | |
4458 | * 01 LL | |
4459 | * 00 RL | |
4460 | */ | |
4461 | ||
4462 | switch(info->if_mode & MGSL_INTERFACE_MASK) | |
4463 | { | |
4464 | case MGSL_INTERFACE_RS232: | |
4465 | val |= BIT5; /* 0010 */ | |
4466 | break; | |
4467 | case MGSL_INTERFACE_V35: | |
4468 | val |= BIT7 + BIT6 + BIT5; /* 1110 */ | |
4469 | break; | |
4470 | case MGSL_INTERFACE_RS422: | |
4471 | val |= BIT6; /* 0100 */ | |
4472 | break; | |
4473 | } | |
4474 | ||
e5590717 PF |
4475 | if (info->if_mode & MGSL_INTERFACE_MSB_FIRST) |
4476 | val |= BIT4; | |
705b6c7b PF |
4477 | if (info->signals & SerialSignal_DTR) |
4478 | val |= BIT3; | |
4479 | if (info->signals & SerialSignal_RTS) | |
4480 | val |= BIT2; | |
4481 | if (info->if_mode & MGSL_INTERFACE_LL) | |
4482 | val |= BIT1; | |
4483 | if (info->if_mode & MGSL_INTERFACE_RL) | |
4484 | val |= BIT0; | |
4485 | wr_reg8(info, VCR, val); | |
4486 | } | |
4487 | ||
4488 | /* | |
4489 | * set state of V24 control (output) signals | |
4490 | */ | |
4491 | static void set_signals(struct slgt_info *info) | |
4492 | { | |
4493 | unsigned char val = rd_reg8(info, VCR); | |
4494 | if (info->signals & SerialSignal_DTR) | |
4495 | val |= BIT3; | |
4496 | else | |
4497 | val &= ~BIT3; | |
4498 | if (info->signals & SerialSignal_RTS) | |
4499 | val |= BIT2; | |
4500 | else | |
4501 | val &= ~BIT2; | |
4502 | wr_reg8(info, VCR, val); | |
4503 | } | |
4504 | ||
4505 | /* | |
4506 | * free range of receive DMA buffers (i to last) | |
4507 | */ | |
4508 | static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) | |
4509 | { | |
4510 | int done = 0; | |
4511 | ||
4512 | while(!done) { | |
4513 | /* reset current buffer for reuse */ | |
4514 | info->rbufs[i].status = 0; | |
814dae03 | 4515 | set_desc_count(info->rbufs[i], info->rbuf_fill_level); |
705b6c7b PF |
4516 | if (i == last) |
4517 | done = 1; | |
4518 | if (++i == info->rbuf_count) | |
4519 | i = 0; | |
4520 | } | |
4521 | info->rbuf_current = i; | |
4522 | } | |
4523 | ||
4524 | /* | |
4525 | * mark all receive DMA buffers as free | |
4526 | */ | |
4527 | static void reset_rbufs(struct slgt_info *info) | |
4528 | { | |
4529 | free_rbufs(info, 0, info->rbuf_count - 1); | |
5ba5a5d2 PF |
4530 | info->rbuf_fill_index = 0; |
4531 | info->rbuf_fill_count = 0; | |
705b6c7b PF |
4532 | } |
4533 | ||
4534 | /* | |
4535 | * pass receive HDLC frame to upper layer | |
4536 | * | |
0fab6de0 | 4537 | * return true if frame available, otherwise false |
705b6c7b | 4538 | */ |
0fab6de0 | 4539 | static bool rx_get_frame(struct slgt_info *info) |
705b6c7b PF |
4540 | { |
4541 | unsigned int start, end; | |
4542 | unsigned short status; | |
4543 | unsigned int framesize = 0; | |
705b6c7b | 4544 | unsigned long flags; |
8fb06c77 | 4545 | struct tty_struct *tty = info->port.tty; |
705b6c7b | 4546 | unsigned char addr_field = 0xff; |
04b374d0 PF |
4547 | unsigned int crc_size = 0; |
4548 | ||
4549 | switch (info->params.crc_type & HDLC_CRC_MASK) { | |
4550 | case HDLC_CRC_16_CCITT: crc_size = 2; break; | |
4551 | case HDLC_CRC_32_CCITT: crc_size = 4; break; | |
4552 | } | |
705b6c7b PF |
4553 | |
4554 | check_again: | |
4555 | ||
4556 | framesize = 0; | |
4557 | addr_field = 0xff; | |
4558 | start = end = info->rbuf_current; | |
4559 | ||
4560 | for (;;) { | |
4561 | if (!desc_complete(info->rbufs[end])) | |
4562 | goto cleanup; | |
4563 | ||
4564 | if (framesize == 0 && info->params.addr_filter != 0xff) | |
4565 | addr_field = info->rbufs[end].buf[0]; | |
4566 | ||
4567 | framesize += desc_count(info->rbufs[end]); | |
4568 | ||
4569 | if (desc_eof(info->rbufs[end])) | |
4570 | break; | |
4571 | ||
4572 | if (++end == info->rbuf_count) | |
4573 | end = 0; | |
4574 | ||
4575 | if (end == info->rbuf_current) { | |
4576 | if (info->rx_enabled){ | |
4577 | spin_lock_irqsave(&info->lock,flags); | |
4578 | rx_start(info); | |
4579 | spin_unlock_irqrestore(&info->lock,flags); | |
4580 | } | |
4581 | goto cleanup; | |
4582 | } | |
4583 | } | |
4584 | ||
4585 | /* status | |
4586 | * | |
4587 | * 15 buffer complete | |
4588 | * 14..06 reserved | |
4589 | * 05..04 residue | |
4590 | * 02 eof (end of frame) | |
4591 | * 01 CRC error | |
4592 | * 00 abort | |
4593 | */ | |
4594 | status = desc_status(info->rbufs[end]); | |
4595 | ||
4596 | /* ignore CRC bit if not using CRC (bit is undefined) */ | |
04b374d0 | 4597 | if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) |
705b6c7b PF |
4598 | status &= ~BIT1; |
4599 | ||
4600 | if (framesize == 0 || | |
4601 | (addr_field != 0xff && addr_field != info->params.addr_filter)) { | |
4602 | free_rbufs(info, start, end); | |
4603 | goto check_again; | |
4604 | } | |
4605 | ||
04b374d0 PF |
4606 | if (framesize < (2 + crc_size) || status & BIT0) { |
4607 | info->icount.rxshort++; | |
705b6c7b | 4608 | framesize = 0; |
04b374d0 PF |
4609 | } else if (status & BIT1) { |
4610 | info->icount.rxcrc++; | |
4611 | if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) | |
4612 | framesize = 0; | |
4613 | } | |
705b6c7b | 4614 | |
af69c7f9 | 4615 | #if SYNCLINK_GENERIC_HDLC |
04b374d0 | 4616 | if (framesize == 0) { |
198191c4 KH |
4617 | info->netdev->stats.rx_errors++; |
4618 | info->netdev->stats.rx_frame_errors++; | |
705b6c7b | 4619 | } |
04b374d0 | 4620 | #endif |
705b6c7b PF |
4621 | |
4622 | DBGBH(("%s rx frame status=%04X size=%d\n", | |
4623 | info->device_name, status, framesize)); | |
814dae03 | 4624 | DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx"); |
705b6c7b PF |
4625 | |
4626 | if (framesize) { | |
04b374d0 PF |
4627 | if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { |
4628 | framesize -= crc_size; | |
4629 | crc_size = 0; | |
4630 | } | |
4631 | ||
4632 | if (framesize > info->max_frame_size + crc_size) | |
705b6c7b PF |
4633 | info->icount.rxlong++; |
4634 | else { | |
4635 | /* copy dma buffer(s) to contiguous temp buffer */ | |
4636 | int copy_count = framesize; | |
4637 | int i = start; | |
4638 | unsigned char *p = info->tmp_rbuf; | |
4639 | info->tmp_rbuf_count = framesize; | |
4640 | ||
4641 | info->icount.rxok++; | |
4642 | ||
4643 | while(copy_count) { | |
814dae03 | 4644 | int partial_count = min_t(int, copy_count, info->rbuf_fill_level); |
705b6c7b PF |
4645 | memcpy(p, info->rbufs[i].buf, partial_count); |
4646 | p += partial_count; | |
4647 | copy_count -= partial_count; | |
4648 | if (++i == info->rbuf_count) | |
4649 | i = 0; | |
4650 | } | |
4651 | ||
04b374d0 PF |
4652 | if (info->params.crc_type & HDLC_CRC_RETURN_EX) { |
4653 | *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; | |
4654 | framesize++; | |
4655 | } | |
4656 | ||
af69c7f9 | 4657 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
4658 | if (info->netcount) |
4659 | hdlcdev_rx(info,info->tmp_rbuf, framesize); | |
4660 | else | |
4661 | #endif | |
4662 | ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); | |
4663 | } | |
4664 | } | |
4665 | free_rbufs(info, start, end); | |
0fab6de0 | 4666 | return true; |
705b6c7b PF |
4667 | |
4668 | cleanup: | |
0fab6de0 | 4669 | return false; |
705b6c7b PF |
4670 | } |
4671 | ||
4672 | /* | |
4673 | * pass receive buffer (RAW synchronous mode) to tty layer | |
0fab6de0 | 4674 | * return true if buffer available, otherwise false |
705b6c7b | 4675 | */ |
0fab6de0 | 4676 | static bool rx_get_buf(struct slgt_info *info) |
705b6c7b PF |
4677 | { |
4678 | unsigned int i = info->rbuf_current; | |
cb10dc9a | 4679 | unsigned int count; |
705b6c7b PF |
4680 | |
4681 | if (!desc_complete(info->rbufs[i])) | |
0fab6de0 | 4682 | return false; |
cb10dc9a PF |
4683 | count = desc_count(info->rbufs[i]); |
4684 | switch(info->params.mode) { | |
4685 | case MGSL_MODE_MONOSYNC: | |
4686 | case MGSL_MODE_BISYNC: | |
4687 | /* ignore residue in byte synchronous modes */ | |
4688 | if (desc_residue(info->rbufs[i])) | |
4689 | count--; | |
4690 | break; | |
4691 | } | |
4692 | DBGDATA(info, info->rbufs[i].buf, count, "rx"); | |
4693 | DBGINFO(("rx_get_buf size=%d\n", count)); | |
4694 | if (count) | |
8fb06c77 | 4695 | ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, |
cb10dc9a | 4696 | info->flag_buf, count); |
705b6c7b | 4697 | free_rbufs(info, i, i); |
0fab6de0 | 4698 | return true; |
705b6c7b PF |
4699 | } |
4700 | ||
4701 | static void reset_tbufs(struct slgt_info *info) | |
4702 | { | |
4703 | unsigned int i; | |
4704 | info->tbuf_current = 0; | |
4705 | for (i=0 ; i < info->tbuf_count ; i++) { | |
4706 | info->tbufs[i].status = 0; | |
4707 | info->tbufs[i].count = 0; | |
4708 | } | |
4709 | } | |
4710 | ||
4711 | /* | |
4712 | * return number of free transmit DMA buffers | |
4713 | */ | |
4714 | static unsigned int free_tbuf_count(struct slgt_info *info) | |
4715 | { | |
4716 | unsigned int count = 0; | |
4717 | unsigned int i = info->tbuf_current; | |
4718 | ||
4719 | do | |
4720 | { | |
4721 | if (desc_count(info->tbufs[i])) | |
4722 | break; /* buffer in use */ | |
4723 | ++count; | |
4724 | if (++i == info->tbuf_count) | |
4725 | i=0; | |
4726 | } while (i != info->tbuf_current); | |
4727 | ||
bb029c67 PF |
4728 | /* if tx DMA active, last zero count buffer is in use */ |
4729 | if (count && (rd_reg32(info, TDCSR) & BIT0)) | |
705b6c7b PF |
4730 | --count; |
4731 | ||
4732 | return count; | |
4733 | } | |
4734 | ||
403214d0 PF |
4735 | /* |
4736 | * return number of bytes in unsent transmit DMA buffers | |
4737 | * and the serial controller tx FIFO | |
4738 | */ | |
4739 | static unsigned int tbuf_bytes(struct slgt_info *info) | |
4740 | { | |
4741 | unsigned int total_count = 0; | |
4742 | unsigned int i = info->tbuf_current; | |
4743 | unsigned int reg_value; | |
4744 | unsigned int count; | |
4745 | unsigned int active_buf_count = 0; | |
4746 | ||
4747 | /* | |
4748 | * Add descriptor counts for all tx DMA buffers. | |
4749 | * If count is zero (cleared by DMA controller after read), | |
4750 | * the buffer is complete or is actively being read from. | |
4751 | * | |
4752 | * Record buf_count of last buffer with zero count starting | |
4753 | * from current ring position. buf_count is mirror | |
4754 | * copy of count and is not cleared by serial controller. | |
4755 | * If DMA controller is active, that buffer is actively | |
4756 | * being read so add to total. | |
4757 | */ | |
4758 | do { | |
4759 | count = desc_count(info->tbufs[i]); | |
4760 | if (count) | |
4761 | total_count += count; | |
4762 | else if (!total_count) | |
4763 | active_buf_count = info->tbufs[i].buf_count; | |
4764 | if (++i == info->tbuf_count) | |
4765 | i = 0; | |
4766 | } while (i != info->tbuf_current); | |
4767 | ||
4768 | /* read tx DMA status register */ | |
4769 | reg_value = rd_reg32(info, TDCSR); | |
4770 | ||
4771 | /* if tx DMA active, last zero count buffer is in use */ | |
4772 | if (reg_value & BIT0) | |
4773 | total_count += active_buf_count; | |
4774 | ||
4775 | /* add tx FIFO count = reg_value[15..8] */ | |
4776 | total_count += (reg_value >> 8) & 0xff; | |
4777 | ||
4778 | /* if transmitter active add one byte for shift register */ | |
4779 | if (info->tx_active) | |
4780 | total_count++; | |
4781 | ||
4782 | return total_count; | |
4783 | } | |
4784 | ||
705b6c7b | 4785 | /* |
de538eb3 PF |
4786 | * load data into transmit DMA buffer ring and start transmitter if needed |
4787 | * return true if data accepted, otherwise false (buffers full) | |
705b6c7b | 4788 | */ |
de538eb3 | 4789 | static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size) |
705b6c7b PF |
4790 | { |
4791 | unsigned short count; | |
4792 | unsigned int i; | |
4793 | struct slgt_desc *d; | |
4794 | ||
de538eb3 PF |
4795 | /* check required buffer space */ |
4796 | if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info)) | |
4797 | return false; | |
705b6c7b PF |
4798 | |
4799 | DBGDATA(info, buf, size, "tx"); | |
4800 | ||
de538eb3 PF |
4801 | /* |
4802 | * copy data to one or more DMA buffers in circular ring | |
4803 | * tbuf_start = first buffer for this data | |
4804 | * tbuf_current = next free buffer | |
4805 | * | |
4806 | * Copy all data before making data visible to DMA controller by | |
4807 | * setting descriptor count of the first buffer. | |
4808 | * This prevents an active DMA controller from reading the first DMA | |
4809 | * buffers of a frame and stopping before the final buffers are filled. | |
4810 | */ | |
4811 | ||
705b6c7b PF |
4812 | info->tbuf_start = i = info->tbuf_current; |
4813 | ||
4814 | while (size) { | |
4815 | d = &info->tbufs[i]; | |
705b6c7b PF |
4816 | |
4817 | count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); | |
4818 | memcpy(d->buf, buf, count); | |
4819 | ||
4820 | size -= count; | |
4821 | buf += count; | |
4822 | ||
cb10dc9a PF |
4823 | /* |
4824 | * set EOF bit for last buffer of HDLC frame or | |
4825 | * for every buffer in raw mode | |
4826 | */ | |
4827 | if ((!size && info->params.mode == MGSL_MODE_HDLC) || | |
4828 | info->params.mode == MGSL_MODE_RAW) | |
4829 | set_desc_eof(*d, 1); | |
705b6c7b PF |
4830 | else |
4831 | set_desc_eof(*d, 0); | |
4832 | ||
de538eb3 PF |
4833 | /* set descriptor count for all but first buffer */ |
4834 | if (i != info->tbuf_start) | |
4835 | set_desc_count(*d, count); | |
403214d0 | 4836 | d->buf_count = count; |
de538eb3 PF |
4837 | |
4838 | if (++i == info->tbuf_count) | |
4839 | i = 0; | |
705b6c7b PF |
4840 | } |
4841 | ||
4842 | info->tbuf_current = i; | |
de538eb3 PF |
4843 | |
4844 | /* set first buffer count to make new data visible to DMA controller */ | |
4845 | d = &info->tbufs[info->tbuf_start]; | |
4846 | set_desc_count(*d, d->buf_count); | |
4847 | ||
4848 | /* start transmitter if needed and update transmit timeout */ | |
4849 | if (!info->tx_active) | |
4850 | tx_start(info); | |
4851 | update_tx_timer(info); | |
4852 | ||
4853 | return true; | |
705b6c7b PF |
4854 | } |
4855 | ||
4856 | static int register_test(struct slgt_info *info) | |
4857 | { | |
4858 | static unsigned short patterns[] = | |
4859 | {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; | |
7ea7c6d5 | 4860 | static unsigned int count = ARRAY_SIZE(patterns); |
705b6c7b PF |
4861 | unsigned int i; |
4862 | int rc = 0; | |
4863 | ||
4864 | for (i=0 ; i < count ; i++) { | |
4865 | wr_reg16(info, TIR, patterns[i]); | |
4866 | wr_reg16(info, BDR, patterns[(i+1)%count]); | |
4867 | if ((rd_reg16(info, TIR) != patterns[i]) || | |
4868 | (rd_reg16(info, BDR) != patterns[(i+1)%count])) { | |
4869 | rc = -ENODEV; | |
4870 | break; | |
4871 | } | |
4872 | } | |
0080b7aa | 4873 | info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; |
705b6c7b PF |
4874 | info->init_error = rc ? 0 : DiagStatus_AddressFailure; |
4875 | return rc; | |
4876 | } | |
4877 | ||
4878 | static int irq_test(struct slgt_info *info) | |
4879 | { | |
4880 | unsigned long timeout; | |
4881 | unsigned long flags; | |
8fb06c77 | 4882 | struct tty_struct *oldtty = info->port.tty; |
705b6c7b PF |
4883 | u32 speed = info->params.data_rate; |
4884 | ||
4885 | info->params.data_rate = 921600; | |
8fb06c77 | 4886 | info->port.tty = NULL; |
705b6c7b PF |
4887 | |
4888 | spin_lock_irqsave(&info->lock, flags); | |
4889 | async_mode(info); | |
4890 | slgt_irq_on(info, IRQ_TXIDLE); | |
4891 | ||
4892 | /* enable transmitter */ | |
4893 | wr_reg16(info, TCR, | |
4894 | (unsigned short)(rd_reg16(info, TCR) | BIT1)); | |
4895 | ||
4896 | /* write one byte and wait for tx idle */ | |
4897 | wr_reg16(info, TDR, 0); | |
4898 | ||
4899 | /* assume failure */ | |
4900 | info->init_error = DiagStatus_IrqFailure; | |
0fab6de0 | 4901 | info->irq_occurred = false; |
705b6c7b PF |
4902 | |
4903 | spin_unlock_irqrestore(&info->lock, flags); | |
4904 | ||
4905 | timeout=100; | |
4906 | while(timeout-- && !info->irq_occurred) | |
4907 | msleep_interruptible(10); | |
4908 | ||
4909 | spin_lock_irqsave(&info->lock,flags); | |
4910 | reset_port(info); | |
4911 | spin_unlock_irqrestore(&info->lock,flags); | |
4912 | ||
4913 | info->params.data_rate = speed; | |
8fb06c77 | 4914 | info->port.tty = oldtty; |
705b6c7b PF |
4915 | |
4916 | info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; | |
4917 | return info->irq_occurred ? 0 : -ENODEV; | |
4918 | } | |
4919 | ||
4920 | static int loopback_test_rx(struct slgt_info *info) | |
4921 | { | |
4922 | unsigned char *src, *dest; | |
4923 | int count; | |
4924 | ||
4925 | if (desc_complete(info->rbufs[0])) { | |
4926 | count = desc_count(info->rbufs[0]); | |
4927 | src = info->rbufs[0].buf; | |
4928 | dest = info->tmp_rbuf; | |
4929 | ||
4930 | for( ; count ; count-=2, src+=2) { | |
4931 | /* src=data byte (src+1)=status byte */ | |
4932 | if (!(*(src+1) & (BIT9 + BIT8))) { | |
4933 | *dest = *src; | |
4934 | dest++; | |
4935 | info->tmp_rbuf_count++; | |
4936 | } | |
4937 | } | |
4938 | DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); | |
4939 | return 1; | |
4940 | } | |
4941 | return 0; | |
4942 | } | |
4943 | ||
4944 | static int loopback_test(struct slgt_info *info) | |
4945 | { | |
4946 | #define TESTFRAMESIZE 20 | |
4947 | ||
4948 | unsigned long timeout; | |
4949 | u16 count = TESTFRAMESIZE; | |
4950 | unsigned char buf[TESTFRAMESIZE]; | |
4951 | int rc = -ENODEV; | |
4952 | unsigned long flags; | |
4953 | ||
8fb06c77 | 4954 | struct tty_struct *oldtty = info->port.tty; |
705b6c7b PF |
4955 | MGSL_PARAMS params; |
4956 | ||
4957 | memcpy(¶ms, &info->params, sizeof(params)); | |
4958 | ||
4959 | info->params.mode = MGSL_MODE_ASYNC; | |
4960 | info->params.data_rate = 921600; | |
4961 | info->params.loopback = 1; | |
8fb06c77 | 4962 | info->port.tty = NULL; |
705b6c7b PF |
4963 | |
4964 | /* build and send transmit frame */ | |
4965 | for (count = 0; count < TESTFRAMESIZE; ++count) | |
4966 | buf[count] = (unsigned char)count; | |
4967 | ||
4968 | info->tmp_rbuf_count = 0; | |
4969 | memset(info->tmp_rbuf, 0, TESTFRAMESIZE); | |
4970 | ||
4971 | /* program hardware for HDLC and enabled receiver */ | |
4972 | spin_lock_irqsave(&info->lock,flags); | |
4973 | async_mode(info); | |
4974 | rx_start(info); | |
705b6c7b | 4975 | tx_load(info, buf, count); |
705b6c7b PF |
4976 | spin_unlock_irqrestore(&info->lock, flags); |
4977 | ||
4978 | /* wait for receive complete */ | |
4979 | for (timeout = 100; timeout; --timeout) { | |
4980 | msleep_interruptible(10); | |
4981 | if (loopback_test_rx(info)) { | |
4982 | rc = 0; | |
4983 | break; | |
4984 | } | |
4985 | } | |
4986 | ||
4987 | /* verify received frame length and contents */ | |
4988 | if (!rc && (info->tmp_rbuf_count != count || | |
4989 | memcmp(buf, info->tmp_rbuf, count))) { | |
4990 | rc = -ENODEV; | |
4991 | } | |
4992 | ||
4993 | spin_lock_irqsave(&info->lock,flags); | |
4994 | reset_adapter(info); | |
4995 | spin_unlock_irqrestore(&info->lock,flags); | |
4996 | ||
4997 | memcpy(&info->params, ¶ms, sizeof(info->params)); | |
8fb06c77 | 4998 | info->port.tty = oldtty; |
705b6c7b PF |
4999 | |
5000 | info->init_error = rc ? DiagStatus_DmaFailure : 0; | |
5001 | return rc; | |
5002 | } | |
5003 | ||
5004 | static int adapter_test(struct slgt_info *info) | |
5005 | { | |
5006 | DBGINFO(("testing %s\n", info->device_name)); | |
294dad05 | 5007 | if (register_test(info) < 0) { |
705b6c7b PF |
5008 | printk("register test failure %s addr=%08X\n", |
5009 | info->device_name, info->phys_reg_addr); | |
294dad05 | 5010 | } else if (irq_test(info) < 0) { |
705b6c7b PF |
5011 | printk("IRQ test failure %s IRQ=%d\n", |
5012 | info->device_name, info->irq_level); | |
294dad05 | 5013 | } else if (loopback_test(info) < 0) { |
705b6c7b PF |
5014 | printk("loopback test failure %s\n", info->device_name); |
5015 | } | |
5016 | return info->init_error; | |
5017 | } | |
5018 | ||
5019 | /* | |
5020 | * transmit timeout handler | |
5021 | */ | |
5022 | static void tx_timeout(unsigned long context) | |
5023 | { | |
5024 | struct slgt_info *info = (struct slgt_info*)context; | |
5025 | unsigned long flags; | |
5026 | ||
5027 | DBGINFO(("%s tx_timeout\n", info->device_name)); | |
5028 | if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { | |
5029 | info->icount.txtimeout++; | |
5030 | } | |
5031 | spin_lock_irqsave(&info->lock,flags); | |
ce89294c | 5032 | tx_stop(info); |
705b6c7b PF |
5033 | spin_unlock_irqrestore(&info->lock,flags); |
5034 | ||
af69c7f9 | 5035 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
5036 | if (info->netcount) |
5037 | hdlcdev_tx_done(info); | |
5038 | else | |
5039 | #endif | |
5040 | bh_transmit(info); | |
5041 | } | |
5042 | ||
5043 | /* | |
5044 | * receive buffer polling timer | |
5045 | */ | |
5046 | static void rx_timeout(unsigned long context) | |
5047 | { | |
5048 | struct slgt_info *info = (struct slgt_info*)context; | |
5049 | unsigned long flags; | |
5050 | ||
5051 | DBGINFO(("%s rx_timeout\n", info->device_name)); | |
5052 | spin_lock_irqsave(&info->lock, flags); | |
5053 | info->pending_bh |= BH_RECEIVE; | |
5054 | spin_unlock_irqrestore(&info->lock, flags); | |
c4028958 | 5055 | bh_handler(&info->task); |
705b6c7b PF |
5056 | } |
5057 |