[mirror_ubuntu-focal-kernel.git] / drivers / char / tpm / tpm_nsc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2004 IBM Corporation
 *
 * Authors:
 * Leendert van Doorn <leendert@watson.ibm.com>
 * Dave Safford <safford@watson.ibm.com>
 * Reiner Sailer <sailer@watson.ibm.com>
 * Kylene Hall <kjhall@us.ibm.com>
 *
 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
 *
 * Device driver for TCG/TCPA TPM (trusted platform module).
 * Specifications at www.trustedcomputinggroup.org	 
 */

#include <linux/platform_device.h>
#include <linux/slab.h>
#include "tpm.h"

/* National definitions */
enum tpm_nsc_addr{
	TPM_NSC_IRQ = 0x07,
	TPM_NSC_BASE0_HI = 0x60,
	TPM_NSC_BASE0_LO = 0x61,
	TPM_NSC_BASE1_HI = 0x62,
	TPM_NSC_BASE1_LO = 0x63
};

enum tpm_nsc_index {
	NSC_LDN_INDEX = 0x07,
	NSC_SID_INDEX = 0x20,
	NSC_LDC_INDEX = 0x30,
	NSC_DIO_INDEX = 0x60,
	NSC_CIO_INDEX = 0x62,
	NSC_IRQ_INDEX = 0x70,
	NSC_ITS_INDEX = 0x71
};

enum tpm_nsc_status_loc {
	NSC_STATUS = 0x01,
	NSC_COMMAND = 0x01,
	NSC_DATA = 0x00
};

/* status bits */
enum tpm_nsc_status {
	NSC_STATUS_OBF = 0x01,	/* output buffer full */
	NSC_STATUS_IBF = 0x02,	/* input buffer full */
	NSC_STATUS_F0 = 0x04,	/* F0 */
	NSC_STATUS_A2 = 0x08,	/* A2 */
	NSC_STATUS_RDY = 0x10,	/* ready to receive command */
	NSC_STATUS_IBR = 0x20	/* ready to receive data */
};

/* command bits */
enum tpm_nsc_cmd_mode {
	NSC_COMMAND_NORMAL = 0x01,	/* normal mode */
	NSC_COMMAND_EOC = 0x03,
	NSC_COMMAND_CANCEL = 0x22
};

struct tpm_nsc_priv {
	unsigned long base;
};

/*
 * Wait for a certain status to appear
 */
static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
{
	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
	unsigned long stop;

	/* status immediately available check */
	*data = inb(priv->base + NSC_STATUS);
	if ((*data & mask) == val)
		return 0;

	/* wait for status */
	stop = jiffies + 10 * HZ;
	do {
		msleep(TPM_TIMEOUT);
		*data = inb(priv->base + 1);
		if ((*data & mask) == val)
			return 0;
	}
	while (time_before(jiffies, stop));

	return -EBUSY;
}

static int nsc_wait_for_ready(struct tpm_chip *chip)
{
	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
	int status;
	unsigned long stop;

	/* status immediately available check */
	status = inb(priv->base + NSC_STATUS);
	if (status & NSC_STATUS_OBF)
		status = inb(priv->base + NSC_DATA);
	if (status & NSC_STATUS_RDY)
		return 0;

	/* wait for status */
	stop = jiffies + 100;
	do {
		msleep(TPM_TIMEOUT);
		status = inb(priv->base + NSC_STATUS);
		if (status & NSC_STATUS_OBF)
			status = inb(priv->base + NSC_DATA);
		if (status & NSC_STATUS_RDY)
			return 0;
	}
	while (time_before(jiffies, stop));

	dev_info(&chip->dev, "wait for ready failed\n");
	return -EBUSY;
}


static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
{
	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
	u8 *buffer = buf;
	u8 data, *p;
	u32 size;
	__be32 *native_size;

	if (count < 6)
		return -EIO;

	if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
		dev_err(&chip->dev, "F0 timeout\n");
		return -EIO;
	}

	data = inb(priv->base + NSC_DATA);
	if (data != NSC_COMMAND_NORMAL) {
		dev_err(&chip->dev, "not in normal mode (0x%x)\n",
			data);
		return -EIO;
	}

	/* read the whole packet */
	for (p = buffer; p < &buffer[count]; p++) {
		if (wait_for_stat
		    (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
			dev_err(&chip->dev,
				"OBF timeout (while reading data)\n");
			return -EIO;
		}
		if (data & NSC_STATUS_F0)
			break;
		*p = inb(priv->base + NSC_DATA);
	}

	if ((data & NSC_STATUS_F0) == 0 &&
	(wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
		dev_err(&chip->dev, "F0 not set\n");
		return -EIO;
	}

	data = inb(priv->base + NSC_DATA);
	if (data != NSC_COMMAND_EOC) {
		dev_err(&chip->dev,
			"expected end of command(0x%x)\n", data);
		return -EIO;
	}

	native_size = (__force __be32 *) (buf + 2);
	size = be32_to_cpu(*native_size);

	if (count < size)
		return -EIO;

	return size;
}

static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
{
	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
	u8 data;
	int i;

	/*
	 * If we hit the chip with back to back commands it locks up
	 * and never set IBF. Hitting it with this "hammer" seems to
	 * fix it. Not sure why this is needed, we followed the flow
	 * chart in the manual to the letter.
	 */
	outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND);

	if (nsc_wait_for_ready(chip) != 0)
		return -EIO;

	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
		dev_err(&chip->dev, "IBF timeout\n");
		return -EIO;
	}

	outb(NSC_COMMAND_NORMAL, priv->base + NSC_COMMAND);
	if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
		dev_err(&chip->dev, "IBR timeout\n");
		return -EIO;
	}

	for (i = 0; i < count; i++) {
		if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
			dev_err(&chip->dev,
				"IBF timeout (while writing data)\n");
			return -EIO;
		}
		outb(buf[i], priv->base + NSC_DATA);
	}

	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
		dev_err(&chip->dev, "IBF timeout\n");
		return -EIO;
	}
	outb(NSC_COMMAND_EOC, priv->base + NSC_COMMAND);

	return 0;
}

static void tpm_nsc_cancel(struct tpm_chip *chip)
{
	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);

	outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND);
}

static u8 tpm_nsc_status(struct tpm_chip *chip)
{
	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);

	return inb(priv->base + NSC_STATUS);
}

static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status)
{
	return (status == NSC_STATUS_RDY);
}

static const struct tpm_class_ops tpm_nsc = {
	.recv = tpm_nsc_recv,
	.send = tpm_nsc_send,
	.cancel = tpm_nsc_cancel,
	.status = tpm_nsc_status,
	.req_complete_mask = NSC_STATUS_OBF,
	.req_complete_val = NSC_STATUS_OBF,
	.req_canceled = tpm_nsc_req_canceled,
};

static struct platform_device *pdev = NULL;

static void tpm_nsc_remove(struct device *dev)
{
	struct tpm_chip *chip = dev_get_drvdata(dev);
	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);

	tpm_chip_unregister(chip);
	release_region(priv->base, 2);
}

static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume);

static struct platform_driver nsc_drv = {
	.driver          = {
		.name    = "tpm_nsc",
		.pm      = &tpm_nsc_pm,
	},
};

static inline int tpm_read_index(int base, int index)
{
	outb(index, base);
	return inb(base+1) & 0xFF;
}

static inline void tpm_write_index(int base, int index, int value)
{
	outb(index, base);
	outb(value & 0xFF, base+1);
}

static int __init init_nsc(void)
{
	int rc = 0;
	int lo, hi, err;
	int nscAddrBase = TPM_ADDR;
	struct tpm_chip *chip;
	unsigned long base;
	struct tpm_nsc_priv *priv;

	/* verify that it is a National part (SID) */
	if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
		nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
			(tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
		if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
			return -ENODEV;
	}

	err = platform_driver_register(&nsc_drv);
	if (err)
		return err;

	hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
	lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
	base = (hi<<8) | lo;

	/* enable the DPM module */
	tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);

	pdev = platform_device_alloc("tpm_nscl0", -1);
	if (!pdev) {
		rc = -ENOMEM;
		goto err_unreg_drv;
	}

	pdev->num_resources = 0;
	pdev->dev.driver = &nsc_drv.driver;
	pdev->dev.release = tpm_nsc_remove;

	if ((rc = platform_device_add(pdev)) < 0)
		goto err_put_dev;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		rc = -ENOMEM;
		goto err_del_dev;
	}

	priv->base = base;

	if (request_region(base, 2, "tpm_nsc0") == NULL ) {
		rc = -EBUSY;
		goto err_del_dev;
	}

	chip = tpmm_chip_alloc(&pdev->dev, &tpm_nsc);
	if (IS_ERR(chip)) {
		rc = -ENODEV;
		goto err_rel_reg;
	}

	dev_set_drvdata(&chip->dev, priv);

	rc = tpm_chip_register(chip);
	if (rc)
		goto err_rel_reg;

	dev_dbg(&pdev->dev, "NSC TPM detected\n");
	dev_dbg(&pdev->dev,
		"NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
		tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
		tpm_read_index(nscAddrBase,0x27));
	dev_dbg(&pdev->dev,
		"NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
		tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
		tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
	dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
		(tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
	dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
		(tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
	dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
		tpm_read_index(nscAddrBase,0x70));
	dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
		tpm_read_index(nscAddrBase,0x71));
	dev_dbg(&pdev->dev,
		"NSC DMA channel select0 0x%x, select1 0x%x\n",
		tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
	dev_dbg(&pdev->dev,
		"NSC Config "
		"0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
		tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
		tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
		tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
		tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
		tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));

	dev_info(&pdev->dev,
		 "NSC TPM revision %d\n",
		 tpm_read_index(nscAddrBase, 0x27) & 0x1F);

	return 0;

err_rel_reg:
	release_region(base, 2);
err_del_dev:
	platform_device_del(pdev);
err_put_dev:
	platform_device_put(pdev);
err_unreg_drv:
	platform_driver_unregister(&nsc_drv);
	return rc;
}

static void __exit cleanup_nsc(void)
{
	if (pdev) {
		tpm_nsc_remove(&pdev->dev);
		platform_device_unregister(pdev);
	}

	platform_driver_unregister(&nsc_drv);
}

module_init(init_nsc);
module_exit(cleanup_nsc);

MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
MODULE_DESCRIPTION("TPM Driver");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
Commit	Line	Data
b886d83c	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4 LT	2	/*
	3	* Copyright (C) 2004 IBM Corporation
	4	*
	5	* Authors:
	6	* Leendert van Doorn <leendert@watson.ibm.com>
	7	* Dave Safford <safford@watson.ibm.com>
	8	* Reiner Sailer <sailer@watson.ibm.com>
	9	* Kylene Hall <kjhall@us.ibm.com>
	10	*
8e81cc13	11	* Maintained by: <tpmdd-devel@lists.sourceforge.net>
1da177e4 LT	12	*
	13	* Device driver for TCG/TCPA TPM (trusted platform module).
	14	* Specifications at www.trustedcomputinggroup.org
1da177e4 LT	15	*/
1da177e4 LT	16
faba278f	17	#include <linux/platform_device.h>
5a0e3ad6	18	#include <linux/slab.h>
1da177e4 LT	19	#include "tpm.h"
	20
	21	/* National definitions */
e1a23c66	22	enum tpm_nsc_addr{
e1a23c66 KH	23	TPM_NSC_IRQ = 0x07,
	24	TPM_NSC_BASE0_HI = 0x60,
	25	TPM_NSC_BASE0_LO = 0x61,
	26	TPM_NSC_BASE1_HI = 0x62,
	27	TPM_NSC_BASE1_LO = 0x63
3122a88a	28	};
1da177e4	29
3122a88a KH	30	enum tpm_nsc_index {
	31	NSC_LDN_INDEX = 0x07,
	32	NSC_SID_INDEX = 0x20,
	33	NSC_LDC_INDEX = 0x30,
	34	NSC_DIO_INDEX = 0x60,
	35	NSC_CIO_INDEX = 0x62,
	36	NSC_IRQ_INDEX = 0x70,
	37	NSC_ITS_INDEX = 0x71
	38	};
1da177e4	39
3122a88a KH	40	enum tpm_nsc_status_loc {
	41	NSC_STATUS = 0x01,
	42	NSC_COMMAND = 0x01,
	43	NSC_DATA = 0x00
	44	};
1da177e4 LT	45
1da177e4 LT	46	/* status bits */
e1a23c66	47	enum tpm_nsc_status {
3122a88a KH	48	NSC_STATUS_OBF = 0x01, /* output buffer full */
	49	NSC_STATUS_IBF = 0x02, /* input buffer full */
	50	NSC_STATUS_F0 = 0x04, /* F0 */
	51	NSC_STATUS_A2 = 0x08, /* A2 */
	52	NSC_STATUS_RDY = 0x10, /* ready to receive command */
	53	NSC_STATUS_IBR = 0x20 /* ready to receive data */
	54	};
daacdfa6	55
1da177e4	56	/* command bits */
3122a88a KH	57	enum tpm_nsc_cmd_mode {
	58	NSC_COMMAND_NORMAL = 0x01, /* normal mode */
	59	NSC_COMMAND_EOC = 0x03,
	60	NSC_COMMAND_CANCEL = 0x22
	61	};
ee177984 JS	62
	63	struct tpm_nsc_priv {
	64	unsigned long base;
	65	};
	66
1da177e4 LT	67	/*
	68	* Wait for a certain status to appear
	69	*/
	70	static int wait_for_stat(struct tpm_chip chip, u8 mask, u8 val, u8 data)
	71	{
9e0d39d8	72	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
700d8bdc	73	unsigned long stop;
1da177e4 LT	74
1da177e4 LT	75	/* status immediately available check */
9e0d39d8	76	*data = inb(priv->base + NSC_STATUS);
1da177e4 LT	77	if ((*data & mask) == val)
	78	return 0;
	79
	80	/* wait for status */
700d8bdc	81	stop = jiffies + 10 * HZ;
1da177e4	82	do {
700d8bdc	83	msleep(TPM_TIMEOUT);
9e0d39d8	84	*data = inb(priv->base + 1);
700d8bdc	85	if ((*data & mask) == val)
1da177e4	86	return 0;
1da177e4	87	}
700d8bdc	88	while (time_before(jiffies, stop));
1da177e4 LT	89
	90	return -EBUSY;
	91	}
	92
	93	static int nsc_wait_for_ready(struct tpm_chip *chip)
	94	{
9e0d39d8	95	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
1da177e4	96	int status;
700d8bdc	97	unsigned long stop;
1da177e4 LT	98
1da177e4 LT	99	/* status immediately available check */
9e0d39d8	100	status = inb(priv->base + NSC_STATUS);
1da177e4	101	if (status & NSC_STATUS_OBF)
9e0d39d8	102	status = inb(priv->base + NSC_DATA);
1da177e4 LT	103	if (status & NSC_STATUS_RDY)
	104	return 0;
	105
	106	/* wait for status */
700d8bdc	107	stop = jiffies + 100;
1da177e4	108	do {
700d8bdc	109	msleep(TPM_TIMEOUT);
9e0d39d8	110	status = inb(priv->base + NSC_STATUS);
1da177e4	111	if (status & NSC_STATUS_OBF)
9e0d39d8	112	status = inb(priv->base + NSC_DATA);
700d8bdc	113	if (status & NSC_STATUS_RDY)
1da177e4	114	return 0;
1da177e4	115	}
700d8bdc	116	while (time_before(jiffies, stop));
1da177e4	117
8cfffc9d	118	dev_info(&chip->dev, "wait for ready failed\n");
1da177e4 LT	119	return -EBUSY;
	120	}
	121
	122
	123	static int tpm_nsc_recv(struct tpm_chip chip, u8 buf, size_t count)
	124	{
9e0d39d8	125	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
1da177e4 LT	126	u8 *buffer = buf;
	127	u8 data, *p;
	128	u32 size;
	129	__be32 *native_size;
	130
	131	if (count < 6)
	132	return -EIO;
	133
	134	if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
8cfffc9d	135	dev_err(&chip->dev, "F0 timeout\n");
1da177e4 LT	136	return -EIO;
1da177e4 LT	137	}
ee177984	138
9e0d39d8	139	data = inb(priv->base + NSC_DATA);
ee177984	140	if (data != NSC_COMMAND_NORMAL) {
8cfffc9d	141	dev_err(&chip->dev, "not in normal mode (0x%x)\n",
1da177e4 LT	142	data);
	143	return -EIO;
	144	}
	145
	146	/* read the whole packet */
	147	for (p = buffer; p < &buffer[count]; p++) {
	148	if (wait_for_stat
	149	(chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
8cfffc9d	150	dev_err(&chip->dev,
1da177e4 LT	151	"OBF timeout (while reading data)\n");
	152	return -EIO;
	153	}
	154	if (data & NSC_STATUS_F0)
	155	break;
9e0d39d8	156	*p = inb(priv->base + NSC_DATA);
1da177e4 LT	157	}
1da177e4 LT	158
daacdfa6 KJH	159	if ((data & NSC_STATUS_F0) == 0 &&
daacdfa6 KJH	160	(wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
8cfffc9d	161	dev_err(&chip->dev, "F0 not set\n");
1da177e4 LT	162	return -EIO;
1da177e4 LT	163	}
ee177984	164
9e0d39d8	165	data = inb(priv->base + NSC_DATA);
ee177984	166	if (data != NSC_COMMAND_EOC) {
8cfffc9d	167	dev_err(&chip->dev,
1da177e4 LT	168	"expected end of command(0x%x)\n", data);
	169	return -EIO;
	170	}
	171
	172	native_size = (__force __be32 *) (buf + 2);
	173	size = be32_to_cpu(*native_size);
	174
	175	if (count < size)
	176	return -EIO;
	177
	178	return size;
	179	}
	180
	181	static int tpm_nsc_send(struct tpm_chip chip, u8 buf, size_t count)
	182	{
9e0d39d8	183	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
1da177e4 LT	184	u8 data;
	185	int i;
	186
	187	/*
	188	* If we hit the chip with back to back commands it locks up
	189	* and never set IBF. Hitting it with this "hammer" seems to
	190	* fix it. Not sure why this is needed, we followed the flow
	191	* chart in the manual to the letter.
	192	*/
9e0d39d8	193	outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND);
1da177e4 LT	194
	195	if (nsc_wait_for_ready(chip) != 0)
	196	return -EIO;
	197
	198	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
8cfffc9d	199	dev_err(&chip->dev, "IBF timeout\n");
1da177e4 LT	200	return -EIO;
	201	}
	202
9e0d39d8	203	outb(NSC_COMMAND_NORMAL, priv->base + NSC_COMMAND);
1da177e4	204	if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
8cfffc9d	205	dev_err(&chip->dev, "IBR timeout\n");
1da177e4 LT	206	return -EIO;
	207	}
	208
	209	for (i = 0; i < count; i++) {
	210	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
8cfffc9d	211	dev_err(&chip->dev,
1da177e4 LT	212	"IBF timeout (while writing data)\n");
	213	return -EIO;
	214	}
9e0d39d8	215	outb(buf[i], priv->base + NSC_DATA);
1da177e4 LT	216	}
	217
	218	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
8cfffc9d	219	dev_err(&chip->dev, "IBF timeout\n");
1da177e4 LT	220	return -EIO;
1da177e4 LT	221	}
9e0d39d8	222	outb(NSC_COMMAND_EOC, priv->base + NSC_COMMAND);
1da177e4	223
f5595f5b	224	return 0;
1da177e4 LT	225	}
	226
	227	static void tpm_nsc_cancel(struct tpm_chip *chip)
	228	{
9e0d39d8 CR	229	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
	230
	231	outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND);
1da177e4 LT	232	}
1da177e4 LT	233
b4ed3e3c KJH	234	static u8 tpm_nsc_status(struct tpm_chip *chip)
b4ed3e3c KJH	235	{
9e0d39d8 CR	236	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
	237
	238	return inb(priv->base + NSC_STATUS);
b4ed3e3c KJH	239	}
b4ed3e3c KJH	240
1f866057 SB	241	static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status)
	242	{
	243	return (status == NSC_STATUS_RDY);
	244	}
	245
01ad1fa7	246	static const struct tpm_class_ops tpm_nsc = {
1da177e4 LT	247	.recv = tpm_nsc_recv,
	248	.send = tpm_nsc_send,
	249	.cancel = tpm_nsc_cancel,
b4ed3e3c	250	.status = tpm_nsc_status,
1da177e4 LT	251	.req_complete_mask = NSC_STATUS_OBF,
1da177e4 LT	252	.req_complete_val = NSC_STATUS_OBF,
1f866057	253	.req_canceled = tpm_nsc_req_canceled,
1da177e4 LT	254	};
1da177e4 LT	255
570302a3 KJH	256	static struct platform_device *pdev = NULL;
570302a3 KJH	257
4821cd11	258	static void tpm_nsc_remove(struct device *dev)
570302a3 KJH	259	{
570302a3 KJH	260	struct tpm_chip *chip = dev_get_drvdata(dev);
9e0d39d8	261	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
afb5abc2 JS	262
afb5abc2 JS	263	tpm_chip_unregister(chip);
9e0d39d8	264	release_region(priv->base, 2);
570302a3 KJH	265	}
570302a3 KJH	266
ca9a2054	267	static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume);
09f50c95 DS	268
09f50c95 DS	269	static struct platform_driver nsc_drv = {
09f50c95 DS	270	.driver = {
09f50c95 DS	271	.name = "tpm_nsc",
ca9a2054	272	.pm = &tpm_nsc_pm,
09f50c95	273	},
570302a3 KJH	274	};
570302a3 KJH	275
1d191553 JS	276	static inline int tpm_read_index(int base, int index)
	277	{
	278	outb(index, base);
	279	return inb(base+1) & 0xFF;
	280	}
	281
	282	static inline void tpm_write_index(int base, int index, int value)
	283	{
	284	outb(index, base);
	285	outb(value & 0xFF, base+1);
	286	}
	287
570302a3	288	static int __init init_nsc(void)
1da177e4 LT	289	{
1da177e4 LT	290	int rc = 0;
f33d9bd5	291	int lo, hi, err;
daacdfa6	292	int nscAddrBase = TPM_ADDR;
e0dd03ca KJH	293	struct tpm_chip *chip;
e0dd03ca KJH	294	unsigned long base;
ee177984	295	struct tpm_nsc_priv *priv;
daacdfa6	296
1da177e4	297	/* verify that it is a National part (SID) */
daacdfa6 KJH	298	if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
	299	nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)\|
	300	(tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
570302a3 KJH	301	if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
570302a3 KJH	302	return -ENODEV;
1da177e4 LT	303	}
1da177e4 LT	304
09f50c95	305	err = platform_driver_register(&nsc_drv);
f33d9bd5 JG	306	if (err)
f33d9bd5 JG	307	return err;
e2a8f7a1	308
daacdfa6 KJH	309	hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
daacdfa6 KJH	310	lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
e0dd03ca	311	base = (hi<<8) \| lo;
daacdfa6	312
570302a3 KJH	313	/* enable the DPM module */
	314	tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
	315
09f50c95	316	pdev = platform_device_alloc("tpm_nscl0", -1);
e2a8f7a1 KJH	317	if (!pdev) {
	318	rc = -ENOMEM;
	319	goto err_unreg_drv;
	320	}
570302a3	321
570302a3	322	pdev->num_resources = 0;
09f50c95	323	pdev->dev.driver = &nsc_drv.driver;
570302a3	324	pdev->dev.release = tpm_nsc_remove;
570302a3	325
29412f0f SB	326	if ((rc = platform_device_add(pdev)) < 0)
29412f0f SB	327	goto err_put_dev;
570302a3	328
ee177984 JS	329	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	330	if (!priv) {
	331	rc = -ENOMEM;
	332	goto err_del_dev;
	333	}
	334
	335	priv->base = base;
	336
e0dd03ca	337	if (request_region(base, 2, "tpm_nsc0") == NULL ) {
e2a8f7a1	338	rc = -EBUSY;
29412f0f	339	goto err_del_dev;
570302a3 KJH	340	}
570302a3 KJH	341
afb5abc2 JS	342	chip = tpmm_chip_alloc(&pdev->dev, &tpm_nsc);
afb5abc2 JS	343	if (IS_ERR(chip)) {
e0dd03ca	344	rc = -ENODEV;
e2a8f7a1	345	goto err_rel_reg;
e0dd03ca	346	}
570302a3	347
9e0d39d8	348	dev_set_drvdata(&chip->dev, priv);
ee177984	349
afb5abc2 JS	350	rc = tpm_chip_register(chip);
	351	if (rc)
	352	goto err_rel_reg;
	353
570302a3 KJH	354	dev_dbg(&pdev->dev, "NSC TPM detected\n");
570302a3 KJH	355	dev_dbg(&pdev->dev,
1da177e4	356	"NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
daacdfa6 KJH	357	tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
daacdfa6 KJH	358	tpm_read_index(nscAddrBase,0x27));
570302a3	359	dev_dbg(&pdev->dev,
1da177e4	360	"NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
daacdfa6 KJH	361	tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
daacdfa6 KJH	362	tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
570302a3	363	dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
daacdfa6	364	(tpm_read_index(nscAddrBase,0x60) << 8) \| tpm_read_index(nscAddrBase,0x61));
570302a3	365	dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
daacdfa6	366	(tpm_read_index(nscAddrBase,0x62) << 8) \| tpm_read_index(nscAddrBase,0x63));
570302a3	367	dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
daacdfa6	368	tpm_read_index(nscAddrBase,0x70));
570302a3	369	dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
daacdfa6	370	tpm_read_index(nscAddrBase,0x71));
570302a3	371	dev_dbg(&pdev->dev,
1da177e4	372	"NSC DMA channel select0 0x%x, select1 0x%x\n",
daacdfa6	373	tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
570302a3	374	dev_dbg(&pdev->dev,
1da177e4 LT	375	"NSC Config "
1da177e4 LT	376	"0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
daacdfa6 KJH	377	tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
	378	tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
	379	tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
	380	tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
	381	tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
1da177e4	382
570302a3	383	dev_info(&pdev->dev,
daacdfa6 KJH	384	"NSC TPM revision %d\n",
daacdfa6 KJH	385	tpm_read_index(nscAddrBase, 0x27) & 0x1F);
1da177e4	386
1da177e4	387	return 0;
e2a8f7a1 KJH	388
e2a8f7a1 KJH	389	err_rel_reg:
e0dd03ca	390	release_region(base, 2);
29412f0f SB	391	err_del_dev:
	392	platform_device_del(pdev);
	393	err_put_dev:
	394	platform_device_put(pdev);
e2a8f7a1	395	err_unreg_drv:
09f50c95	396	platform_driver_unregister(&nsc_drv);
e2a8f7a1	397	return rc;
1da177e4 LT	398	}
	399
	400	static void __exit cleanup_nsc(void)
	401	{
570302a3 KJH	402	if (pdev) {
	403	tpm_nsc_remove(&pdev->dev);
	404	platform_device_unregister(pdev);
570302a3 KJH	405	}
570302a3 KJH	406
09f50c95	407	platform_driver_unregister(&nsc_drv);
1da177e4 LT	408	}
	409
	410	module_init(init_nsc);
	411	module_exit(cleanup_nsc);
	412
	413	MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
	414	MODULE_DESCRIPTION("TPM Driver");
	415	MODULE_VERSION("2.0");
	416	MODULE_LICENSE("GPL");