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Commit | Line | Data |
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27084efe LD |
1 | /* |
2 | * Copyright (C) 2005, 2006 IBM Corporation | |
399235dc | 3 | * Copyright (C) 2014, 2015 Intel Corporation |
27084efe LD |
4 | * |
5 | * Authors: | |
6 | * Leendert van Doorn <leendert@watson.ibm.com> | |
7 | * Kylene Hall <kjhall@us.ibm.com> | |
8 | * | |
8e81cc13 KY |
9 | * Maintained by: <tpmdd-devel@lists.sourceforge.net> |
10 | * | |
27084efe LD |
11 | * Device driver for TCG/TCPA TPM (trusted platform module). |
12 | * Specifications at www.trustedcomputinggroup.org | |
13 | * | |
14 | * This device driver implements the TPM interface as defined in | |
15 | * the TCG TPM Interface Spec version 1.2, revision 1.0. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation, version 2 of the | |
20 | * License. | |
21 | */ | |
57135568 KJH |
22 | #include <linux/init.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
27084efe | 25 | #include <linux/pnp.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
27084efe LD |
27 | #include <linux/interrupt.h> |
28 | #include <linux/wait.h> | |
3f0d3d01 | 29 | #include <linux/acpi.h> |
20b87bbf | 30 | #include <linux/freezer.h> |
27084efe LD |
31 | #include "tpm.h" |
32 | ||
27084efe LD |
33 | enum tis_access { |
34 | TPM_ACCESS_VALID = 0x80, | |
35 | TPM_ACCESS_ACTIVE_LOCALITY = 0x20, | |
36 | TPM_ACCESS_REQUEST_PENDING = 0x04, | |
37 | TPM_ACCESS_REQUEST_USE = 0x02, | |
38 | }; | |
39 | ||
40 | enum tis_status { | |
41 | TPM_STS_VALID = 0x80, | |
42 | TPM_STS_COMMAND_READY = 0x40, | |
43 | TPM_STS_GO = 0x20, | |
44 | TPM_STS_DATA_AVAIL = 0x10, | |
45 | TPM_STS_DATA_EXPECT = 0x08, | |
46 | }; | |
47 | ||
48 | enum tis_int_flags { | |
49 | TPM_GLOBAL_INT_ENABLE = 0x80000000, | |
50 | TPM_INTF_BURST_COUNT_STATIC = 0x100, | |
51 | TPM_INTF_CMD_READY_INT = 0x080, | |
52 | TPM_INTF_INT_EDGE_FALLING = 0x040, | |
53 | TPM_INTF_INT_EDGE_RISING = 0x020, | |
54 | TPM_INTF_INT_LEVEL_LOW = 0x010, | |
55 | TPM_INTF_INT_LEVEL_HIGH = 0x008, | |
56 | TPM_INTF_LOCALITY_CHANGE_INT = 0x004, | |
57 | TPM_INTF_STS_VALID_INT = 0x002, | |
58 | TPM_INTF_DATA_AVAIL_INT = 0x001, | |
59 | }; | |
60 | ||
36b20020 | 61 | enum tis_defaults { |
b09d5300 | 62 | TIS_MEM_LEN = 0x5000, |
cb535425 KJH |
63 | TIS_SHORT_TIMEOUT = 750, /* ms */ |
64 | TIS_LONG_TIMEOUT = 2000, /* 2 sec */ | |
36b20020 KJH |
65 | }; |
66 | ||
399235dc | 67 | struct tpm_info { |
51dd43df | 68 | struct resource res; |
ef7b81dc JG |
69 | /* irq > 0 means: use irq $irq; |
70 | * irq = 0 means: autoprobe for an irq; | |
71 | * irq = -1 means: no irq support | |
72 | */ | |
73 | int irq; | |
399235dc JS |
74 | }; |
75 | ||
aec04cbd JS |
76 | /* Some timeout values are needed before it is known whether the chip is |
77 | * TPM 1.0 or TPM 2.0. | |
78 | */ | |
79 | #define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A) | |
80 | #define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B) | |
81 | #define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C) | |
82 | #define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D) | |
83 | ||
27084efe LD |
84 | #define TPM_ACCESS(l) (0x0000 | ((l) << 12)) |
85 | #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) | |
86 | #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12)) | |
87 | #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12)) | |
88 | #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) | |
89 | #define TPM_STS(l) (0x0018 | ((l) << 12)) | |
aec04cbd | 90 | #define TPM_STS3(l) (0x001b | ((l) << 12)) |
27084efe LD |
91 | #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) |
92 | ||
93 | #define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) | |
94 | #define TPM_RID(l) (0x0F04 | ((l) << 12)) | |
95 | ||
448e9c55 | 96 | struct priv_data { |
d4956524 | 97 | u16 manufacturer_id; |
448e9c55 | 98 | bool irq_tested; |
ec5fd99d | 99 | wait_queue_head_t int_queue; |
448e9c55 SD |
100 | }; |
101 | ||
1560ffe6 | 102 | #if defined(CONFIG_PNP) && defined(CONFIG_ACPI) |
399235dc | 103 | static int has_hid(struct acpi_device *dev, const char *hid) |
3f0d3d01 | 104 | { |
3f0d3d01 MG |
105 | struct acpi_hardware_id *id; |
106 | ||
399235dc JS |
107 | list_for_each_entry(id, &dev->pnp.ids, list) |
108 | if (!strcmp(hid, id->id)) | |
3f0d3d01 | 109 | return 1; |
3f0d3d01 MG |
110 | |
111 | return 0; | |
112 | } | |
399235dc JS |
113 | |
114 | static inline int is_itpm(struct acpi_device *dev) | |
115 | { | |
116 | return has_hid(dev, "INTC0102"); | |
117 | } | |
1560ffe6 | 118 | #else |
399235dc | 119 | static inline int is_itpm(struct acpi_device *dev) |
1560ffe6 RD |
120 | { |
121 | return 0; | |
122 | } | |
3f0d3d01 MG |
123 | #endif |
124 | ||
7240b983 JG |
125 | /* Before we attempt to access the TPM we must see that the valid bit is set. |
126 | * The specification says that this bit is 0 at reset and remains 0 until the | |
127 | * 'TPM has gone through its self test and initialization and has established | |
128 | * correct values in the other bits.' */ | |
129 | static int wait_startup(struct tpm_chip *chip, int l) | |
130 | { | |
131 | unsigned long stop = jiffies + chip->vendor.timeout_a; | |
132 | do { | |
133 | if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
134 | TPM_ACCESS_VALID) | |
135 | return 0; | |
136 | msleep(TPM_TIMEOUT); | |
137 | } while (time_before(jiffies, stop)); | |
138 | return -1; | |
139 | } | |
140 | ||
27084efe LD |
141 | static int check_locality(struct tpm_chip *chip, int l) |
142 | { | |
143 | if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
144 | (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == | |
145 | (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) | |
146 | return chip->vendor.locality = l; | |
147 | ||
148 | return -1; | |
149 | } | |
150 | ||
151 | static void release_locality(struct tpm_chip *chip, int l, int force) | |
152 | { | |
153 | if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
154 | (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) == | |
155 | (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) | |
156 | iowrite8(TPM_ACCESS_ACTIVE_LOCALITY, | |
157 | chip->vendor.iobase + TPM_ACCESS(l)); | |
158 | } | |
159 | ||
160 | static int request_locality(struct tpm_chip *chip, int l) | |
161 | { | |
ec5fd99d | 162 | struct priv_data *priv = chip->vendor.priv; |
20b87bbf | 163 | unsigned long stop, timeout; |
27084efe LD |
164 | long rc; |
165 | ||
166 | if (check_locality(chip, l) >= 0) | |
167 | return l; | |
168 | ||
169 | iowrite8(TPM_ACCESS_REQUEST_USE, | |
170 | chip->vendor.iobase + TPM_ACCESS(l)); | |
171 | ||
20b87bbf SB |
172 | stop = jiffies + chip->vendor.timeout_a; |
173 | ||
27084efe | 174 | if (chip->vendor.irq) { |
20b87bbf SB |
175 | again: |
176 | timeout = stop - jiffies; | |
177 | if ((long)timeout <= 0) | |
178 | return -1; | |
ec5fd99d | 179 | rc = wait_event_interruptible_timeout(priv->int_queue, |
27084efe LD |
180 | (check_locality |
181 | (chip, l) >= 0), | |
20b87bbf | 182 | timeout); |
27084efe LD |
183 | if (rc > 0) |
184 | return l; | |
20b87bbf SB |
185 | if (rc == -ERESTARTSYS && freezing(current)) { |
186 | clear_thread_flag(TIF_SIGPENDING); | |
187 | goto again; | |
188 | } | |
27084efe LD |
189 | } else { |
190 | /* wait for burstcount */ | |
27084efe LD |
191 | do { |
192 | if (check_locality(chip, l) >= 0) | |
193 | return l; | |
194 | msleep(TPM_TIMEOUT); | |
195 | } | |
196 | while (time_before(jiffies, stop)); | |
197 | } | |
198 | return -1; | |
199 | } | |
200 | ||
201 | static u8 tpm_tis_status(struct tpm_chip *chip) | |
202 | { | |
203 | return ioread8(chip->vendor.iobase + | |
204 | TPM_STS(chip->vendor.locality)); | |
205 | } | |
206 | ||
207 | static void tpm_tis_ready(struct tpm_chip *chip) | |
208 | { | |
209 | /* this causes the current command to be aborted */ | |
210 | iowrite8(TPM_STS_COMMAND_READY, | |
211 | chip->vendor.iobase + TPM_STS(chip->vendor.locality)); | |
212 | } | |
213 | ||
214 | static int get_burstcount(struct tpm_chip *chip) | |
215 | { | |
216 | unsigned long stop; | |
217 | int burstcnt; | |
218 | ||
219 | /* wait for burstcount */ | |
220 | /* which timeout value, spec has 2 answers (c & d) */ | |
36b20020 | 221 | stop = jiffies + chip->vendor.timeout_d; |
27084efe LD |
222 | do { |
223 | burstcnt = ioread8(chip->vendor.iobase + | |
224 | TPM_STS(chip->vendor.locality) + 1); | |
225 | burstcnt += ioread8(chip->vendor.iobase + | |
226 | TPM_STS(chip->vendor.locality) + | |
227 | 2) << 8; | |
228 | if (burstcnt) | |
229 | return burstcnt; | |
230 | msleep(TPM_TIMEOUT); | |
231 | } while (time_before(jiffies, stop)); | |
232 | return -EBUSY; | |
233 | } | |
234 | ||
cb535425 | 235 | static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count) |
27084efe LD |
236 | { |
237 | int size = 0, burstcnt; | |
238 | while (size < count && | |
fd048866 RA |
239 | wait_for_tpm_stat(chip, |
240 | TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
241 | chip->vendor.timeout_c, | |
78f09cc2 | 242 | &chip->vendor.read_queue, true) |
27084efe LD |
243 | == 0) { |
244 | burstcnt = get_burstcount(chip); | |
245 | for (; burstcnt > 0 && size < count; burstcnt--) | |
246 | buf[size++] = ioread8(chip->vendor.iobase + | |
247 | TPM_DATA_FIFO(chip->vendor. | |
248 | locality)); | |
249 | } | |
250 | return size; | |
251 | } | |
252 | ||
cb535425 | 253 | static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) |
27084efe | 254 | { |
ec5fd99d | 255 | struct priv_data *priv = chip->vendor.priv; |
27084efe LD |
256 | int size = 0; |
257 | int expected, status; | |
258 | ||
259 | if (count < TPM_HEADER_SIZE) { | |
260 | size = -EIO; | |
261 | goto out; | |
262 | } | |
263 | ||
264 | /* read first 10 bytes, including tag, paramsize, and result */ | |
265 | if ((size = | |
266 | recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) { | |
8cfffc9d | 267 | dev_err(&chip->dev, "Unable to read header\n"); |
27084efe LD |
268 | goto out; |
269 | } | |
270 | ||
271 | expected = be32_to_cpu(*(__be32 *) (buf + 2)); | |
272 | if (expected > count) { | |
273 | size = -EIO; | |
274 | goto out; | |
275 | } | |
276 | ||
277 | if ((size += | |
278 | recv_data(chip, &buf[TPM_HEADER_SIZE], | |
279 | expected - TPM_HEADER_SIZE)) < expected) { | |
8cfffc9d | 280 | dev_err(&chip->dev, "Unable to read remainder of result\n"); |
27084efe LD |
281 | size = -ETIME; |
282 | goto out; | |
283 | } | |
284 | ||
fd048866 | 285 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
ec5fd99d | 286 | &priv->int_queue, false); |
27084efe LD |
287 | status = tpm_tis_status(chip); |
288 | if (status & TPM_STS_DATA_AVAIL) { /* retry? */ | |
8cfffc9d | 289 | dev_err(&chip->dev, "Error left over data\n"); |
27084efe LD |
290 | size = -EIO; |
291 | goto out; | |
292 | } | |
293 | ||
294 | out: | |
295 | tpm_tis_ready(chip); | |
296 | release_locality(chip, chip->vendor.locality, 0); | |
297 | return size; | |
298 | } | |
299 | ||
90ab5ee9 | 300 | static bool itpm; |
3507d612 RA |
301 | module_param(itpm, bool, 0444); |
302 | MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)"); | |
303 | ||
27084efe LD |
304 | /* |
305 | * If interrupts are used (signaled by an irq set in the vendor structure) | |
306 | * tpm.c can skip polling for the data to be available as the interrupt is | |
307 | * waited for here | |
308 | */ | |
9519de3f | 309 | static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len) |
27084efe | 310 | { |
ec5fd99d | 311 | struct priv_data *priv = chip->vendor.priv; |
27084efe LD |
312 | int rc, status, burstcnt; |
313 | size_t count = 0; | |
27084efe LD |
314 | |
315 | if (request_locality(chip, 0) < 0) | |
316 | return -EBUSY; | |
317 | ||
318 | status = tpm_tis_status(chip); | |
319 | if ((status & TPM_STS_COMMAND_READY) == 0) { | |
320 | tpm_tis_ready(chip); | |
fd048866 | 321 | if (wait_for_tpm_stat |
27084efe | 322 | (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b, |
ec5fd99d | 323 | &priv->int_queue, false) < 0) { |
27084efe LD |
324 | rc = -ETIME; |
325 | goto out_err; | |
326 | } | |
327 | } | |
328 | ||
329 | while (count < len - 1) { | |
330 | burstcnt = get_burstcount(chip); | |
331 | for (; burstcnt > 0 && count < len - 1; burstcnt--) { | |
332 | iowrite8(buf[count], chip->vendor.iobase + | |
333 | TPM_DATA_FIFO(chip->vendor.locality)); | |
334 | count++; | |
335 | } | |
336 | ||
fd048866 | 337 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
ec5fd99d | 338 | &priv->int_queue, false); |
27084efe | 339 | status = tpm_tis_status(chip); |
3507d612 | 340 | if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) { |
27084efe LD |
341 | rc = -EIO; |
342 | goto out_err; | |
343 | } | |
344 | } | |
345 | ||
346 | /* write last byte */ | |
347 | iowrite8(buf[count], | |
9519de3f | 348 | chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality)); |
fd048866 | 349 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
ec5fd99d | 350 | &priv->int_queue, false); |
27084efe LD |
351 | status = tpm_tis_status(chip); |
352 | if ((status & TPM_STS_DATA_EXPECT) != 0) { | |
353 | rc = -EIO; | |
354 | goto out_err; | |
355 | } | |
356 | ||
9519de3f SB |
357 | return 0; |
358 | ||
359 | out_err: | |
360 | tpm_tis_ready(chip); | |
361 | release_locality(chip, chip->vendor.locality, 0); | |
362 | return rc; | |
363 | } | |
364 | ||
448e9c55 SD |
365 | static void disable_interrupts(struct tpm_chip *chip) |
366 | { | |
367 | u32 intmask; | |
368 | ||
369 | intmask = | |
370 | ioread32(chip->vendor.iobase + | |
371 | TPM_INT_ENABLE(chip->vendor.locality)); | |
372 | intmask &= ~TPM_GLOBAL_INT_ENABLE; | |
373 | iowrite32(intmask, | |
374 | chip->vendor.iobase + | |
375 | TPM_INT_ENABLE(chip->vendor.locality)); | |
8cfffc9d | 376 | devm_free_irq(&chip->dev, chip->vendor.irq, chip); |
448e9c55 SD |
377 | chip->vendor.irq = 0; |
378 | } | |
379 | ||
9519de3f SB |
380 | /* |
381 | * If interrupts are used (signaled by an irq set in the vendor structure) | |
382 | * tpm.c can skip polling for the data to be available as the interrupt is | |
383 | * waited for here | |
384 | */ | |
448e9c55 | 385 | static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len) |
9519de3f SB |
386 | { |
387 | int rc; | |
388 | u32 ordinal; | |
aec04cbd | 389 | unsigned long dur; |
9519de3f SB |
390 | |
391 | rc = tpm_tis_send_data(chip, buf, len); | |
392 | if (rc < 0) | |
393 | return rc; | |
394 | ||
27084efe LD |
395 | /* go and do it */ |
396 | iowrite8(TPM_STS_GO, | |
397 | chip->vendor.iobase + TPM_STS(chip->vendor.locality)); | |
398 | ||
399 | if (chip->vendor.irq) { | |
400 | ordinal = be32_to_cpu(*((__be32 *) (buf + 6))); | |
aec04cbd JS |
401 | |
402 | if (chip->flags & TPM_CHIP_FLAG_TPM2) | |
403 | dur = tpm2_calc_ordinal_duration(chip, ordinal); | |
404 | else | |
405 | dur = tpm_calc_ordinal_duration(chip, ordinal); | |
406 | ||
fd048866 | 407 | if (wait_for_tpm_stat |
aec04cbd | 408 | (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur, |
78f09cc2 | 409 | &chip->vendor.read_queue, false) < 0) { |
27084efe LD |
410 | rc = -ETIME; |
411 | goto out_err; | |
412 | } | |
413 | } | |
414 | return len; | |
415 | out_err: | |
416 | tpm_tis_ready(chip); | |
417 | release_locality(chip, chip->vendor.locality, 0); | |
418 | return rc; | |
419 | } | |
420 | ||
448e9c55 SD |
421 | static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len) |
422 | { | |
423 | int rc, irq; | |
424 | struct priv_data *priv = chip->vendor.priv; | |
425 | ||
426 | if (!chip->vendor.irq || priv->irq_tested) | |
427 | return tpm_tis_send_main(chip, buf, len); | |
428 | ||
429 | /* Verify receipt of the expected IRQ */ | |
430 | irq = chip->vendor.irq; | |
431 | chip->vendor.irq = 0; | |
432 | rc = tpm_tis_send_main(chip, buf, len); | |
433 | chip->vendor.irq = irq; | |
434 | if (!priv->irq_tested) | |
435 | msleep(1); | |
e3837e74 | 436 | if (!priv->irq_tested) |
448e9c55 | 437 | disable_interrupts(chip); |
448e9c55 SD |
438 | priv->irq_tested = true; |
439 | return rc; | |
440 | } | |
441 | ||
8e54caf4 JG |
442 | struct tis_vendor_timeout_override { |
443 | u32 did_vid; | |
444 | unsigned long timeout_us[4]; | |
445 | }; | |
446 | ||
447 | static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = { | |
448 | /* Atmel 3204 */ | |
449 | { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000), | |
450 | (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } }, | |
451 | }; | |
452 | ||
453 | static bool tpm_tis_update_timeouts(struct tpm_chip *chip, | |
454 | unsigned long *timeout_cap) | |
455 | { | |
456 | int i; | |
457 | u32 did_vid; | |
458 | ||
459 | did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0)); | |
460 | ||
461 | for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) { | |
462 | if (vendor_timeout_overrides[i].did_vid != did_vid) | |
463 | continue; | |
464 | memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us, | |
465 | sizeof(vendor_timeout_overrides[i].timeout_us)); | |
466 | return true; | |
467 | } | |
468 | ||
469 | return false; | |
470 | } | |
471 | ||
9519de3f SB |
472 | /* |
473 | * Early probing for iTPM with STS_DATA_EXPECT flaw. | |
474 | * Try sending command without itpm flag set and if that | |
475 | * fails, repeat with itpm flag set. | |
476 | */ | |
477 | static int probe_itpm(struct tpm_chip *chip) | |
478 | { | |
479 | int rc = 0; | |
480 | u8 cmd_getticks[] = { | |
481 | 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a, | |
482 | 0x00, 0x00, 0x00, 0xf1 | |
483 | }; | |
484 | size_t len = sizeof(cmd_getticks); | |
968de8e2 | 485 | bool rem_itpm = itpm; |
4e401fb0 SB |
486 | u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0)); |
487 | ||
488 | /* probe only iTPMS */ | |
489 | if (vendor != TPM_VID_INTEL) | |
490 | return 0; | |
9519de3f | 491 | |
73249695 | 492 | itpm = false; |
9519de3f SB |
493 | |
494 | rc = tpm_tis_send_data(chip, cmd_getticks, len); | |
495 | if (rc == 0) | |
496 | goto out; | |
497 | ||
498 | tpm_tis_ready(chip); | |
499 | release_locality(chip, chip->vendor.locality, 0); | |
500 | ||
73249695 | 501 | itpm = true; |
9519de3f SB |
502 | |
503 | rc = tpm_tis_send_data(chip, cmd_getticks, len); | |
504 | if (rc == 0) { | |
8cfffc9d | 505 | dev_info(&chip->dev, "Detected an iTPM.\n"); |
9519de3f SB |
506 | rc = 1; |
507 | } else | |
508 | rc = -EFAULT; | |
509 | ||
510 | out: | |
511 | itpm = rem_itpm; | |
512 | tpm_tis_ready(chip); | |
513 | release_locality(chip, chip->vendor.locality, 0); | |
514 | ||
515 | return rc; | |
516 | } | |
517 | ||
1f866057 SB |
518 | static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status) |
519 | { | |
d4956524 JS |
520 | struct priv_data *priv = chip->vendor.priv; |
521 | ||
522 | switch (priv->manufacturer_id) { | |
1f866057 SB |
523 | case TPM_VID_WINBOND: |
524 | return ((status == TPM_STS_VALID) || | |
525 | (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY))); | |
526 | case TPM_VID_STM: | |
527 | return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)); | |
528 | default: | |
529 | return (status == TPM_STS_COMMAND_READY); | |
530 | } | |
531 | } | |
532 | ||
01ad1fa7 | 533 | static const struct tpm_class_ops tpm_tis = { |
27084efe LD |
534 | .status = tpm_tis_status, |
535 | .recv = tpm_tis_recv, | |
536 | .send = tpm_tis_send, | |
537 | .cancel = tpm_tis_ready, | |
8e54caf4 | 538 | .update_timeouts = tpm_tis_update_timeouts, |
27084efe LD |
539 | .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID, |
540 | .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
1f866057 | 541 | .req_canceled = tpm_tis_req_canceled, |
27084efe LD |
542 | }; |
543 | ||
a6f97b29 | 544 | static irqreturn_t tis_int_handler(int dummy, void *dev_id) |
27084efe | 545 | { |
06efcad0 | 546 | struct tpm_chip *chip = dev_id; |
ec5fd99d | 547 | struct priv_data *priv = chip->vendor.priv; |
27084efe LD |
548 | u32 interrupt; |
549 | int i; | |
550 | ||
551 | interrupt = ioread32(chip->vendor.iobase + | |
552 | TPM_INT_STATUS(chip->vendor.locality)); | |
553 | ||
554 | if (interrupt == 0) | |
555 | return IRQ_NONE; | |
556 | ||
448e9c55 | 557 | ((struct priv_data *)chip->vendor.priv)->irq_tested = true; |
27084efe LD |
558 | if (interrupt & TPM_INTF_DATA_AVAIL_INT) |
559 | wake_up_interruptible(&chip->vendor.read_queue); | |
560 | if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT) | |
561 | for (i = 0; i < 5; i++) | |
562 | if (check_locality(chip, i) >= 0) | |
563 | break; | |
564 | if (interrupt & | |
565 | (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT | | |
566 | TPM_INTF_CMD_READY_INT)) | |
ec5fd99d | 567 | wake_up_interruptible(&priv->int_queue); |
27084efe LD |
568 | |
569 | /* Clear interrupts handled with TPM_EOI */ | |
570 | iowrite32(interrupt, | |
571 | chip->vendor.iobase + | |
572 | TPM_INT_STATUS(chip->vendor.locality)); | |
cab091ea | 573 | ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality)); |
27084efe LD |
574 | return IRQ_HANDLED; |
575 | } | |
576 | ||
e3837e74 JG |
577 | /* Register the IRQ and issue a command that will cause an interrupt. If an |
578 | * irq is seen then leave the chip setup for IRQ operation, otherwise reverse | |
579 | * everything and leave in polling mode. Returns 0 on success. | |
580 | */ | |
b8ba1e74 JG |
581 | static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask, |
582 | int flags, int irq) | |
e3837e74 JG |
583 | { |
584 | struct priv_data *priv = chip->vendor.priv; | |
585 | u8 original_int_vec; | |
586 | ||
8cfffc9d | 587 | if (devm_request_irq(&chip->dev, irq, tis_int_handler, flags, |
3635e2ec | 588 | dev_name(&chip->dev), chip) != 0) { |
8cfffc9d | 589 | dev_info(&chip->dev, "Unable to request irq: %d for probe\n", |
e3837e74 JG |
590 | irq); |
591 | return -1; | |
592 | } | |
593 | chip->vendor.irq = irq; | |
594 | ||
595 | original_int_vec = ioread8(chip->vendor.iobase + | |
596 | TPM_INT_VECTOR(chip->vendor.locality)); | |
597 | iowrite8(irq, | |
598 | chip->vendor.iobase + TPM_INT_VECTOR(chip->vendor.locality)); | |
599 | ||
600 | /* Clear all existing */ | |
601 | iowrite32(ioread32(chip->vendor.iobase + | |
602 | TPM_INT_STATUS(chip->vendor.locality)), | |
603 | chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality)); | |
604 | ||
605 | /* Turn on */ | |
606 | iowrite32(intmask | TPM_GLOBAL_INT_ENABLE, | |
607 | chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality)); | |
608 | ||
609 | priv->irq_tested = false; | |
610 | ||
611 | /* Generate an interrupt by having the core call through to | |
612 | * tpm_tis_send | |
613 | */ | |
614 | if (chip->flags & TPM_CHIP_FLAG_TPM2) | |
615 | tpm2_gen_interrupt(chip); | |
616 | else | |
617 | tpm_gen_interrupt(chip); | |
618 | ||
619 | /* tpm_tis_send will either confirm the interrupt is working or it | |
620 | * will call disable_irq which undoes all of the above. | |
621 | */ | |
622 | if (!chip->vendor.irq) { | |
623 | iowrite8(original_int_vec, | |
624 | chip->vendor.iobase + | |
625 | TPM_INT_VECTOR(chip->vendor.locality)); | |
626 | return 1; | |
627 | } | |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
632 | /* Try to find the IRQ the TPM is using. This is for legacy x86 systems that | |
633 | * do not have ACPI/etc. We typically expect the interrupt to be declared if | |
634 | * present. | |
635 | */ | |
636 | static void tpm_tis_probe_irq(struct tpm_chip *chip, u32 intmask) | |
637 | { | |
638 | u8 original_int_vec; | |
639 | int i; | |
640 | ||
641 | original_int_vec = ioread8(chip->vendor.iobase + | |
642 | TPM_INT_VECTOR(chip->vendor.locality)); | |
643 | ||
644 | if (!original_int_vec) { | |
b8ba1e74 JG |
645 | if (IS_ENABLED(CONFIG_X86)) |
646 | for (i = 3; i <= 15; i++) | |
647 | if (!tpm_tis_probe_irq_single(chip, intmask, 0, | |
648 | i)) | |
649 | return; | |
650 | } else if (!tpm_tis_probe_irq_single(chip, intmask, 0, | |
651 | original_int_vec)) | |
e3837e74 JG |
652 | return; |
653 | } | |
654 | ||
73249695 | 655 | static bool interrupts = true; |
57135568 KJH |
656 | module_param(interrupts, bool, 0444); |
657 | MODULE_PARM_DESC(interrupts, "Enable interrupts"); | |
658 | ||
afb5abc2 JS |
659 | static void tpm_tis_remove(struct tpm_chip *chip) |
660 | { | |
d30b8e4f JS |
661 | void __iomem *reg = chip->vendor.iobase + |
662 | TPM_INT_ENABLE(chip->vendor.locality); | |
663 | ||
d30b8e4f | 664 | iowrite32(~TPM_GLOBAL_INT_ENABLE & ioread32(reg), reg); |
afb5abc2 JS |
665 | release_locality(chip, chip->vendor.locality, 1); |
666 | } | |
667 | ||
399235dc JS |
668 | static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info, |
669 | acpi_handle acpi_dev_handle) | |
27084efe LD |
670 | { |
671 | u32 vendor, intfcaps, intmask; | |
e3837e74 | 672 | int rc, probe; |
27084efe | 673 | struct tpm_chip *chip; |
448e9c55 | 674 | struct priv_data *priv; |
27084efe | 675 | |
448e9c55 SD |
676 | priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL); |
677 | if (priv == NULL) | |
678 | return -ENOMEM; | |
afb5abc2 JS |
679 | |
680 | chip = tpmm_chip_alloc(dev, &tpm_tis); | |
681 | if (IS_ERR(chip)) | |
682 | return PTR_ERR(chip); | |
683 | ||
448e9c55 | 684 | chip->vendor.priv = priv; |
aec04cbd | 685 | #ifdef CONFIG_ACPI |
0dc55365 | 686 | chip->acpi_dev_handle = acpi_dev_handle; |
aec04cbd | 687 | #endif |
27084efe | 688 | |
51dd43df JG |
689 | chip->vendor.iobase = devm_ioremap_resource(dev, &tpm_info->res); |
690 | if (IS_ERR(chip->vendor.iobase)) | |
691 | return PTR_ERR(chip->vendor.iobase); | |
27084efe | 692 | |
aec04cbd JS |
693 | /* Maximum timeouts */ |
694 | chip->vendor.timeout_a = TIS_TIMEOUT_A_MAX; | |
695 | chip->vendor.timeout_b = TIS_TIMEOUT_B_MAX; | |
696 | chip->vendor.timeout_c = TIS_TIMEOUT_C_MAX; | |
697 | chip->vendor.timeout_d = TIS_TIMEOUT_D_MAX; | |
ec579358 | 698 | |
7240b983 JG |
699 | if (wait_startup(chip, 0) != 0) { |
700 | rc = -ENODEV; | |
701 | goto out_err; | |
702 | } | |
703 | ||
036bb38f JG |
704 | /* Take control of the TPM's interrupt hardware and shut it off */ |
705 | intmask = ioread32(chip->vendor.iobase + | |
706 | TPM_INT_ENABLE(chip->vendor.locality)); | |
707 | intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT | | |
708 | TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT; | |
709 | intmask &= ~TPM_GLOBAL_INT_ENABLE; | |
710 | iowrite32(intmask, | |
711 | chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality)); | |
712 | ||
05a462af MS |
713 | if (request_locality(chip, 0) != 0) { |
714 | rc = -ENODEV; | |
715 | goto out_err; | |
716 | } | |
717 | ||
4d5f2051 JS |
718 | rc = tpm2_probe(chip); |
719 | if (rc) | |
720 | goto out_err; | |
aec04cbd | 721 | |
27084efe | 722 | vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0)); |
d4956524 | 723 | priv->manufacturer_id = vendor; |
27084efe | 724 | |
aec04cbd JS |
725 | dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n", |
726 | (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2", | |
27084efe LD |
727 | vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0))); |
728 | ||
9519de3f | 729 | if (!itpm) { |
968de8e2 SB |
730 | probe = probe_itpm(chip); |
731 | if (probe < 0) { | |
9519de3f SB |
732 | rc = -ENODEV; |
733 | goto out_err; | |
734 | } | |
73249695 | 735 | itpm = !!probe; |
9519de3f SB |
736 | } |
737 | ||
3507d612 RA |
738 | if (itpm) |
739 | dev_info(dev, "Intel iTPM workaround enabled\n"); | |
740 | ||
741 | ||
27084efe LD |
742 | /* Figure out the capabilities */ |
743 | intfcaps = | |
744 | ioread32(chip->vendor.iobase + | |
745 | TPM_INTF_CAPS(chip->vendor.locality)); | |
9e323d3e | 746 | dev_dbg(dev, "TPM interface capabilities (0x%x):\n", |
27084efe LD |
747 | intfcaps); |
748 | if (intfcaps & TPM_INTF_BURST_COUNT_STATIC) | |
9e323d3e | 749 | dev_dbg(dev, "\tBurst Count Static\n"); |
27084efe | 750 | if (intfcaps & TPM_INTF_CMD_READY_INT) |
9e323d3e | 751 | dev_dbg(dev, "\tCommand Ready Int Support\n"); |
27084efe | 752 | if (intfcaps & TPM_INTF_INT_EDGE_FALLING) |
9e323d3e | 753 | dev_dbg(dev, "\tInterrupt Edge Falling\n"); |
27084efe | 754 | if (intfcaps & TPM_INTF_INT_EDGE_RISING) |
9e323d3e | 755 | dev_dbg(dev, "\tInterrupt Edge Rising\n"); |
27084efe | 756 | if (intfcaps & TPM_INTF_INT_LEVEL_LOW) |
9e323d3e | 757 | dev_dbg(dev, "\tInterrupt Level Low\n"); |
27084efe | 758 | if (intfcaps & TPM_INTF_INT_LEVEL_HIGH) |
9e323d3e | 759 | dev_dbg(dev, "\tInterrupt Level High\n"); |
27084efe | 760 | if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT) |
9e323d3e | 761 | dev_dbg(dev, "\tLocality Change Int Support\n"); |
27084efe | 762 | if (intfcaps & TPM_INTF_STS_VALID_INT) |
9e323d3e | 763 | dev_dbg(dev, "\tSts Valid Int Support\n"); |
27084efe | 764 | if (intfcaps & TPM_INTF_DATA_AVAIL_INT) |
9e323d3e | 765 | dev_dbg(dev, "\tData Avail Int Support\n"); |
27084efe | 766 | |
25112048 JG |
767 | /* Very early on issue a command to the TPM in polling mode to make |
768 | * sure it works. May as well use that command to set the proper | |
769 | * timeouts for the driver. | |
770 | */ | |
771 | if (tpm_get_timeouts(chip)) { | |
772 | dev_err(dev, "Could not get TPM timeouts and durations\n"); | |
773 | rc = -ENODEV; | |
774 | goto out_err; | |
775 | } | |
776 | ||
27084efe LD |
777 | /* INTERRUPT Setup */ |
778 | init_waitqueue_head(&chip->vendor.read_queue); | |
ec5fd99d | 779 | init_waitqueue_head(&priv->int_queue); |
ef7b81dc | 780 | if (interrupts && tpm_info->irq != -1) { |
e3837e74 | 781 | if (tpm_info->irq) { |
b8ba1e74 JG |
782 | tpm_tis_probe_irq_single(chip, intmask, IRQF_SHARED, |
783 | tpm_info->irq); | |
e3837e74 | 784 | if (!chip->vendor.irq) |
8cfffc9d | 785 | dev_err(&chip->dev, FW_BUG |
e3837e74 JG |
786 | "TPM interrupt not working, polling instead\n"); |
787 | } else | |
788 | tpm_tis_probe_irq(chip, intmask); | |
25112048 | 789 | } |
aec04cbd | 790 | |
25112048 | 791 | if (chip->flags & TPM_CHIP_FLAG_TPM2) { |
aec04cbd JS |
792 | rc = tpm2_do_selftest(chip); |
793 | if (rc == TPM2_RC_INITIALIZE) { | |
794 | dev_warn(dev, "Firmware has not started TPM\n"); | |
795 | rc = tpm2_startup(chip, TPM2_SU_CLEAR); | |
796 | if (!rc) | |
797 | rc = tpm2_do_selftest(chip); | |
798 | } | |
448e9c55 | 799 | |
aec04cbd JS |
800 | if (rc) { |
801 | dev_err(dev, "TPM self test failed\n"); | |
802 | if (rc > 0) | |
803 | rc = -ENODEV; | |
804 | goto out_err; | |
805 | } | |
806 | } else { | |
aec04cbd JS |
807 | if (tpm_do_selftest(chip)) { |
808 | dev_err(dev, "TPM self test failed\n"); | |
809 | rc = -ENODEV; | |
810 | goto out_err; | |
811 | } | |
448e9c55 SD |
812 | } |
813 | ||
afb5abc2 | 814 | return tpm_chip_register(chip); |
27084efe | 815 | out_err: |
afb5abc2 | 816 | tpm_tis_remove(chip); |
27084efe LD |
817 | return rc; |
818 | } | |
96854310 | 819 | |
2cb6d646 | 820 | #ifdef CONFIG_PM_SLEEP |
96854310 SB |
821 | static void tpm_tis_reenable_interrupts(struct tpm_chip *chip) |
822 | { | |
823 | u32 intmask; | |
824 | ||
825 | /* reenable interrupts that device may have lost or | |
826 | BIOS/firmware may have disabled */ | |
827 | iowrite8(chip->vendor.irq, chip->vendor.iobase + | |
828 | TPM_INT_VECTOR(chip->vendor.locality)); | |
829 | ||
830 | intmask = | |
831 | ioread32(chip->vendor.iobase + | |
832 | TPM_INT_ENABLE(chip->vendor.locality)); | |
833 | ||
834 | intmask |= TPM_INTF_CMD_READY_INT | |
835 | | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT | |
836 | | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE; | |
837 | ||
838 | iowrite32(intmask, | |
839 | chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality)); | |
840 | } | |
96854310 | 841 | |
a2fa3fb0 SK |
842 | static int tpm_tis_resume(struct device *dev) |
843 | { | |
844 | struct tpm_chip *chip = dev_get_drvdata(dev); | |
74d6b3ce | 845 | int ret; |
a2fa3fb0 SK |
846 | |
847 | if (chip->vendor.irq) | |
848 | tpm_tis_reenable_interrupts(chip); | |
849 | ||
74d6b3ce JS |
850 | ret = tpm_pm_resume(dev); |
851 | if (ret) | |
852 | return ret; | |
aec04cbd | 853 | |
74d6b3ce JS |
854 | /* TPM 1.2 requires self-test on resume. This function actually returns |
855 | * an error code but for unknown reason it isn't handled. | |
856 | */ | |
857 | if (!(chip->flags & TPM_CHIP_FLAG_TPM2)) | |
858 | tpm_do_selftest(chip); | |
a2fa3fb0 | 859 | |
74d6b3ce | 860 | return 0; |
a2fa3fb0 | 861 | } |
2cb6d646 | 862 | #endif |
a2fa3fb0 SK |
863 | |
864 | static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume); | |
865 | ||
afc6d369 | 866 | static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev, |
ef7b81dc | 867 | const struct pnp_device_id *pnp_id) |
9e323d3e | 868 | { |
ef7b81dc | 869 | struct tpm_info tpm_info = {}; |
0dc55365 | 870 | acpi_handle acpi_dev_handle = NULL; |
51dd43df | 871 | struct resource *res; |
7917ff9a | 872 | |
51dd43df JG |
873 | res = pnp_get_resource(pnp_dev, IORESOURCE_MEM, 0); |
874 | if (!res) | |
875 | return -ENODEV; | |
876 | tpm_info.res = *res; | |
9e323d3e | 877 | |
7917ff9a | 878 | if (pnp_irq_valid(pnp_dev, 0)) |
399235dc | 879 | tpm_info.irq = pnp_irq(pnp_dev, 0); |
7917ff9a | 880 | else |
ef7b81dc | 881 | tpm_info.irq = -1; |
7917ff9a | 882 | |
399235dc JS |
883 | if (pnp_acpi_device(pnp_dev)) { |
884 | if (is_itpm(pnp_acpi_device(pnp_dev))) | |
885 | itpm = true; | |
886 | ||
00194826 | 887 | acpi_dev_handle = ACPI_HANDLE(&pnp_dev->dev); |
399235dc | 888 | } |
0dc55365 | 889 | |
399235dc | 890 | return tpm_tis_init(&pnp_dev->dev, &tpm_info, acpi_dev_handle); |
9e323d3e KJH |
891 | } |
892 | ||
0bbed20e | 893 | static struct pnp_device_id tpm_pnp_tbl[] = { |
27084efe | 894 | {"PNP0C31", 0}, /* TPM */ |
93e1b7d4 KJH |
895 | {"ATM1200", 0}, /* Atmel */ |
896 | {"IFX0102", 0}, /* Infineon */ | |
897 | {"BCM0101", 0}, /* Broadcom */ | |
061991ec | 898 | {"BCM0102", 0}, /* Broadcom */ |
93e1b7d4 | 899 | {"NSC1200", 0}, /* National */ |
fb0e7e11 | 900 | {"ICO0102", 0}, /* Intel */ |
93e1b7d4 KJH |
901 | /* Add new here */ |
902 | {"", 0}, /* User Specified */ | |
903 | {"", 0} /* Terminator */ | |
27084efe | 904 | }; |
31bde71c | 905 | MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl); |
27084efe | 906 | |
39af33fc | 907 | static void tpm_tis_pnp_remove(struct pnp_dev *dev) |
253115b7 RA |
908 | { |
909 | struct tpm_chip *chip = pnp_get_drvdata(dev); | |
399235dc | 910 | |
afb5abc2 JS |
911 | tpm_chip_unregister(chip); |
912 | tpm_tis_remove(chip); | |
253115b7 RA |
913 | } |
914 | ||
27084efe LD |
915 | static struct pnp_driver tis_pnp_driver = { |
916 | .name = "tpm_tis", | |
917 | .id_table = tpm_pnp_tbl, | |
918 | .probe = tpm_tis_pnp_init, | |
253115b7 | 919 | .remove = tpm_tis_pnp_remove, |
a2fa3fb0 SK |
920 | .driver = { |
921 | .pm = &tpm_tis_pm, | |
922 | }, | |
27084efe LD |
923 | }; |
924 | ||
93e1b7d4 KJH |
925 | #define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2 |
926 | module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id, | |
927 | sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444); | |
928 | MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe"); | |
7a192ec3 | 929 | |
399235dc JS |
930 | #ifdef CONFIG_ACPI |
931 | static int tpm_check_resource(struct acpi_resource *ares, void *data) | |
932 | { | |
933 | struct tpm_info *tpm_info = (struct tpm_info *) data; | |
934 | struct resource res; | |
935 | ||
51dd43df | 936 | if (acpi_dev_resource_interrupt(ares, 0, &res)) |
399235dc | 937 | tpm_info->irq = res.start; |
30f9c8c9 | 938 | else if (acpi_dev_resource_memory(ares, &res)) { |
51dd43df | 939 | tpm_info->res = res; |
30f9c8c9 JS |
940 | tpm_info->res.name = NULL; |
941 | } | |
399235dc JS |
942 | |
943 | return 1; | |
944 | } | |
945 | ||
946 | static int tpm_tis_acpi_init(struct acpi_device *acpi_dev) | |
947 | { | |
4d627e67 JG |
948 | struct acpi_table_tpm2 *tbl; |
949 | acpi_status st; | |
399235dc | 950 | struct list_head resources; |
4d627e67 | 951 | struct tpm_info tpm_info = {}; |
399235dc JS |
952 | int ret; |
953 | ||
4d627e67 JG |
954 | st = acpi_get_table(ACPI_SIG_TPM2, 1, |
955 | (struct acpi_table_header **) &tbl); | |
956 | if (ACPI_FAILURE(st) || tbl->header.length < sizeof(*tbl)) { | |
957 | dev_err(&acpi_dev->dev, | |
958 | FW_BUG "failed to get TPM2 ACPI table\n"); | |
959 | return -EINVAL; | |
960 | } | |
961 | ||
962 | if (tbl->start_method != ACPI_TPM2_MEMORY_MAPPED) | |
399235dc JS |
963 | return -ENODEV; |
964 | ||
965 | INIT_LIST_HEAD(&resources); | |
ef7b81dc | 966 | tpm_info.irq = -1; |
399235dc JS |
967 | ret = acpi_dev_get_resources(acpi_dev, &resources, tpm_check_resource, |
968 | &tpm_info); | |
969 | if (ret < 0) | |
970 | return ret; | |
971 | ||
972 | acpi_dev_free_resource_list(&resources); | |
973 | ||
51dd43df | 974 | if (resource_type(&tpm_info.res) != IORESOURCE_MEM) { |
4d627e67 JG |
975 | dev_err(&acpi_dev->dev, |
976 | FW_BUG "TPM2 ACPI table does not define a memory resource\n"); | |
977 | return -EINVAL; | |
978 | } | |
979 | ||
399235dc JS |
980 | if (is_itpm(acpi_dev)) |
981 | itpm = true; | |
982 | ||
983 | return tpm_tis_init(&acpi_dev->dev, &tpm_info, acpi_dev->handle); | |
984 | } | |
985 | ||
986 | static int tpm_tis_acpi_remove(struct acpi_device *dev) | |
987 | { | |
988 | struct tpm_chip *chip = dev_get_drvdata(&dev->dev); | |
989 | ||
990 | tpm_chip_unregister(chip); | |
991 | tpm_tis_remove(chip); | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
996 | static struct acpi_device_id tpm_acpi_tbl[] = { | |
997 | {"MSFT0101", 0}, /* TPM 2.0 */ | |
998 | /* Add new here */ | |
999 | {"", 0}, /* User Specified */ | |
1000 | {"", 0} /* Terminator */ | |
1001 | }; | |
1002 | MODULE_DEVICE_TABLE(acpi, tpm_acpi_tbl); | |
1003 | ||
1004 | static struct acpi_driver tis_acpi_driver = { | |
1005 | .name = "tpm_tis", | |
1006 | .ids = tpm_acpi_tbl, | |
1007 | .ops = { | |
1008 | .add = tpm_tis_acpi_init, | |
1009 | .remove = tpm_tis_acpi_remove, | |
1010 | }, | |
1011 | .drv = { | |
1012 | .pm = &tpm_tis_pm, | |
1013 | }, | |
1014 | }; | |
1015 | #endif | |
1016 | ||
00194826 JG |
1017 | static struct platform_device *force_pdev; |
1018 | ||
1019 | static int tpm_tis_plat_probe(struct platform_device *pdev) | |
1020 | { | |
1021 | struct tpm_info tpm_info = {}; | |
1022 | struct resource *res; | |
1023 | ||
1024 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1025 | if (res == NULL) { | |
1026 | dev_err(&pdev->dev, "no memory resource defined\n"); | |
1027 | return -ENODEV; | |
1028 | } | |
1029 | tpm_info.res = *res; | |
1030 | ||
1031 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1032 | if (res) { | |
1033 | tpm_info.irq = res->start; | |
1034 | } else { | |
1035 | if (pdev == force_pdev) | |
1036 | tpm_info.irq = -1; | |
1037 | else | |
1038 | /* When forcing auto probe the IRQ */ | |
1039 | tpm_info.irq = 0; | |
1040 | } | |
1041 | ||
1042 | return tpm_tis_init(&pdev->dev, &tpm_info, NULL); | |
1043 | } | |
1044 | ||
1045 | static int tpm_tis_plat_remove(struct platform_device *pdev) | |
1046 | { | |
1047 | struct tpm_chip *chip = dev_get_drvdata(&pdev->dev); | |
1048 | ||
1049 | tpm_chip_unregister(chip); | |
1050 | tpm_tis_remove(chip); | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
7a192ec3 | 1055 | static struct platform_driver tis_drv = { |
00194826 JG |
1056 | .probe = tpm_tis_plat_probe, |
1057 | .remove = tpm_tis_plat_remove, | |
7a192ec3 | 1058 | .driver = { |
afb5abc2 | 1059 | .name = "tpm_tis", |
b633f050 | 1060 | .pm = &tpm_tis_pm, |
7a192ec3 | 1061 | }, |
9e323d3e KJH |
1062 | }; |
1063 | ||
90ab5ee9 | 1064 | static bool force; |
00194826 | 1065 | #ifdef CONFIG_X86 |
9e323d3e KJH |
1066 | module_param(force, bool, 0444); |
1067 | MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry"); | |
00194826 JG |
1068 | #endif |
1069 | ||
1070 | static int tpm_tis_force_device(void) | |
1071 | { | |
1072 | struct platform_device *pdev; | |
1073 | static const struct resource x86_resources[] = { | |
1074 | { | |
1075 | .start = 0xFED40000, | |
1076 | .end = 0xFED40000 + TIS_MEM_LEN - 1, | |
1077 | .flags = IORESOURCE_MEM, | |
1078 | }, | |
1079 | }; | |
1080 | ||
1081 | if (!force) | |
1082 | return 0; | |
1083 | ||
1084 | /* The driver core will match the name tpm_tis of the device to | |
1085 | * the tpm_tis platform driver and complete the setup via | |
1086 | * tpm_tis_plat_probe | |
1087 | */ | |
1088 | pdev = platform_device_register_simple("tpm_tis", -1, x86_resources, | |
1089 | ARRAY_SIZE(x86_resources)); | |
1090 | if (IS_ERR(pdev)) | |
1091 | return PTR_ERR(pdev); | |
1092 | force_pdev = pdev; | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
27084efe LD |
1097 | static int __init init_tis(void) |
1098 | { | |
9e323d3e | 1099 | int rc; |
00194826 JG |
1100 | |
1101 | rc = tpm_tis_force_device(); | |
1102 | if (rc) | |
1103 | goto err_force; | |
1104 | ||
1105 | rc = platform_driver_register(&tis_drv); | |
1106 | if (rc) | |
1107 | goto err_platform; | |
1108 | ||
399235dc | 1109 | #ifdef CONFIG_ACPI |
00194826 JG |
1110 | rc = acpi_bus_register_driver(&tis_acpi_driver); |
1111 | if (rc) | |
1112 | goto err_acpi; | |
399235dc | 1113 | #endif |
9e323d3e | 1114 | |
00194826 JG |
1115 | if (IS_ENABLED(CONFIG_PNP)) { |
1116 | rc = pnp_register_driver(&tis_pnp_driver); | |
1117 | if (rc) | |
1118 | goto err_pnp; | |
9e323d3e | 1119 | } |
00194826 | 1120 | |
4fba3c3b | 1121 | return 0; |
00194826 JG |
1122 | |
1123 | err_pnp: | |
1124 | #ifdef CONFIG_ACPI | |
1125 | acpi_bus_unregister_driver(&tis_acpi_driver); | |
1126 | err_acpi: | |
1127 | #endif | |
1128 | platform_device_unregister(force_pdev); | |
1129 | err_platform: | |
1130 | if (force_pdev) | |
1131 | platform_device_unregister(force_pdev); | |
1132 | err_force: | |
7f2ab000 | 1133 | return rc; |
27084efe LD |
1134 | } |
1135 | ||
1136 | static void __exit cleanup_tis(void) | |
1137 | { | |
00194826 | 1138 | pnp_unregister_driver(&tis_pnp_driver); |
399235dc | 1139 | #ifdef CONFIG_ACPI |
00194826 | 1140 | acpi_bus_unregister_driver(&tis_acpi_driver); |
7f2ab000 | 1141 | #endif |
7f2ab000 | 1142 | platform_driver_unregister(&tis_drv); |
00194826 JG |
1143 | |
1144 | if (force_pdev) | |
1145 | platform_device_unregister(force_pdev); | |
27084efe LD |
1146 | } |
1147 | ||
1148 | module_init(init_tis); | |
1149 | module_exit(cleanup_tis); | |
1150 | MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); | |
1151 | MODULE_DESCRIPTION("TPM Driver"); | |
1152 | MODULE_VERSION("2.0"); | |
1153 | MODULE_LICENSE("GPL"); |