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[mirror_ubuntu-artful-kernel.git] / drivers / char / tpm / tpm_tis.c
CommitLineData
27084efe
LD
1/*
2 * Copyright (C) 2005, 2006 IBM Corporation
399235dc 3 * Copyright (C) 2014, 2015 Intel Corporation
27084efe
LD
4 *
5 * Authors:
6 * Leendert van Doorn <leendert@watson.ibm.com>
7 * Kylene Hall <kjhall@us.ibm.com>
8 *
8e81cc13
KY
9 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
10 *
27084efe
LD
11 * Device driver for TCG/TCPA TPM (trusted platform module).
12 * Specifications at www.trustedcomputinggroup.org
13 *
14 * This device driver implements the TPM interface as defined in
15 * the TCG TPM Interface Spec version 1.2, revision 1.0.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation, version 2 of the
20 * License.
21 */
57135568
KJH
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
27084efe 25#include <linux/pnp.h>
5a0e3ad6 26#include <linux/slab.h>
27084efe
LD
27#include <linux/interrupt.h>
28#include <linux/wait.h>
3f0d3d01 29#include <linux/acpi.h>
20b87bbf 30#include <linux/freezer.h>
399235dc 31#include <acpi/actbl2.h>
27084efe
LD
32#include "tpm.h"
33
27084efe
LD
34enum tis_access {
35 TPM_ACCESS_VALID = 0x80,
36 TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
37 TPM_ACCESS_REQUEST_PENDING = 0x04,
38 TPM_ACCESS_REQUEST_USE = 0x02,
39};
40
41enum tis_status {
42 TPM_STS_VALID = 0x80,
43 TPM_STS_COMMAND_READY = 0x40,
44 TPM_STS_GO = 0x20,
45 TPM_STS_DATA_AVAIL = 0x10,
46 TPM_STS_DATA_EXPECT = 0x08,
47};
48
49enum tis_int_flags {
50 TPM_GLOBAL_INT_ENABLE = 0x80000000,
51 TPM_INTF_BURST_COUNT_STATIC = 0x100,
52 TPM_INTF_CMD_READY_INT = 0x080,
53 TPM_INTF_INT_EDGE_FALLING = 0x040,
54 TPM_INTF_INT_EDGE_RISING = 0x020,
55 TPM_INTF_INT_LEVEL_LOW = 0x010,
56 TPM_INTF_INT_LEVEL_HIGH = 0x008,
57 TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
58 TPM_INTF_STS_VALID_INT = 0x002,
59 TPM_INTF_DATA_AVAIL_INT = 0x001,
60};
61
36b20020 62enum tis_defaults {
2a7362f5 63 TIS_MEM_BASE = 0xFED40000,
b09d5300 64 TIS_MEM_LEN = 0x5000,
cb535425
KJH
65 TIS_SHORT_TIMEOUT = 750, /* ms */
66 TIS_LONG_TIMEOUT = 2000, /* 2 sec */
36b20020
KJH
67};
68
399235dc
JS
69struct tpm_info {
70 unsigned long start;
71 unsigned long len;
72 unsigned int irq;
73};
74
75static struct tpm_info tis_default_info = {
76 .start = TIS_MEM_BASE,
77 .len = TIS_MEM_LEN,
78 .irq = 0,
79};
aec04cbd
JS
80
81/* Some timeout values are needed before it is known whether the chip is
82 * TPM 1.0 or TPM 2.0.
83 */
84#define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
85#define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
86#define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
87#define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
88
27084efe
LD
89#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
90#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
91#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
92#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
93#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
94#define TPM_STS(l) (0x0018 | ((l) << 12))
aec04cbd 95#define TPM_STS3(l) (0x001b | ((l) << 12))
27084efe
LD
96#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
97
98#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
99#define TPM_RID(l) (0x0F04 | ((l) << 12))
100
448e9c55
SD
101struct priv_data {
102 bool irq_tested;
103};
104
1560ffe6 105#if defined(CONFIG_PNP) && defined(CONFIG_ACPI)
399235dc 106static int has_hid(struct acpi_device *dev, const char *hid)
3f0d3d01 107{
3f0d3d01
MG
108 struct acpi_hardware_id *id;
109
399235dc
JS
110 list_for_each_entry(id, &dev->pnp.ids, list)
111 if (!strcmp(hid, id->id))
3f0d3d01 112 return 1;
3f0d3d01
MG
113
114 return 0;
115}
399235dc
JS
116
117static inline int is_itpm(struct acpi_device *dev)
118{
119 return has_hid(dev, "INTC0102");
120}
121
122static inline int is_fifo(struct acpi_device *dev)
123{
124 struct acpi_table_tpm2 *tbl;
125 acpi_status st;
126
127 /* TPM 1.2 FIFO */
128 if (!has_hid(dev, "MSFT0101"))
129 return 1;
130
131 st = acpi_get_table(ACPI_SIG_TPM2, 1,
132 (struct acpi_table_header **) &tbl);
133 if (ACPI_FAILURE(st)) {
134 dev_err(&dev->dev, "failed to get TPM2 ACPI table\n");
135 return 0;
136 }
137
138 if (le32_to_cpu(tbl->start_method) != TPM2_START_FIFO)
139 return 0;
140
141 /* TPM 2.0 FIFO */
142 return 1;
143}
1560ffe6 144#else
399235dc 145static inline int is_itpm(struct acpi_device *dev)
1560ffe6
RD
146{
147 return 0;
148}
399235dc
JS
149
150static inline int is_fifo(struct acpi_device *dev)
151{
152 return 1;
153}
3f0d3d01
MG
154#endif
155
7240b983
JG
156/* Before we attempt to access the TPM we must see that the valid bit is set.
157 * The specification says that this bit is 0 at reset and remains 0 until the
158 * 'TPM has gone through its self test and initialization and has established
159 * correct values in the other bits.' */
160static int wait_startup(struct tpm_chip *chip, int l)
161{
162 unsigned long stop = jiffies + chip->vendor.timeout_a;
163 do {
164 if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
165 TPM_ACCESS_VALID)
166 return 0;
167 msleep(TPM_TIMEOUT);
168 } while (time_before(jiffies, stop));
169 return -1;
170}
171
27084efe
LD
172static int check_locality(struct tpm_chip *chip, int l)
173{
174 if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
175 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
176 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
177 return chip->vendor.locality = l;
178
179 return -1;
180}
181
182static void release_locality(struct tpm_chip *chip, int l, int force)
183{
184 if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
185 (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
186 (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
187 iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
188 chip->vendor.iobase + TPM_ACCESS(l));
189}
190
191static int request_locality(struct tpm_chip *chip, int l)
192{
20b87bbf 193 unsigned long stop, timeout;
27084efe
LD
194 long rc;
195
196 if (check_locality(chip, l) >= 0)
197 return l;
198
199 iowrite8(TPM_ACCESS_REQUEST_USE,
200 chip->vendor.iobase + TPM_ACCESS(l));
201
20b87bbf
SB
202 stop = jiffies + chip->vendor.timeout_a;
203
27084efe 204 if (chip->vendor.irq) {
20b87bbf
SB
205again:
206 timeout = stop - jiffies;
207 if ((long)timeout <= 0)
208 return -1;
36b20020 209 rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
27084efe
LD
210 (check_locality
211 (chip, l) >= 0),
20b87bbf 212 timeout);
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LD
213 if (rc > 0)
214 return l;
20b87bbf
SB
215 if (rc == -ERESTARTSYS && freezing(current)) {
216 clear_thread_flag(TIF_SIGPENDING);
217 goto again;
218 }
27084efe
LD
219 } else {
220 /* wait for burstcount */
27084efe
LD
221 do {
222 if (check_locality(chip, l) >= 0)
223 return l;
224 msleep(TPM_TIMEOUT);
225 }
226 while (time_before(jiffies, stop));
227 }
228 return -1;
229}
230
231static u8 tpm_tis_status(struct tpm_chip *chip)
232{
233 return ioread8(chip->vendor.iobase +
234 TPM_STS(chip->vendor.locality));
235}
236
237static void tpm_tis_ready(struct tpm_chip *chip)
238{
239 /* this causes the current command to be aborted */
240 iowrite8(TPM_STS_COMMAND_READY,
241 chip->vendor.iobase + TPM_STS(chip->vendor.locality));
242}
243
244static int get_burstcount(struct tpm_chip *chip)
245{
246 unsigned long stop;
247 int burstcnt;
248
249 /* wait for burstcount */
250 /* which timeout value, spec has 2 answers (c & d) */
36b20020 251 stop = jiffies + chip->vendor.timeout_d;
27084efe
LD
252 do {
253 burstcnt = ioread8(chip->vendor.iobase +
254 TPM_STS(chip->vendor.locality) + 1);
255 burstcnt += ioread8(chip->vendor.iobase +
256 TPM_STS(chip->vendor.locality) +
257 2) << 8;
258 if (burstcnt)
259 return burstcnt;
260 msleep(TPM_TIMEOUT);
261 } while (time_before(jiffies, stop));
262 return -EBUSY;
263}
264
cb535425 265static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
27084efe
LD
266{
267 int size = 0, burstcnt;
268 while (size < count &&
fd048866
RA
269 wait_for_tpm_stat(chip,
270 TPM_STS_DATA_AVAIL | TPM_STS_VALID,
271 chip->vendor.timeout_c,
78f09cc2 272 &chip->vendor.read_queue, true)
27084efe
LD
273 == 0) {
274 burstcnt = get_burstcount(chip);
275 for (; burstcnt > 0 && size < count; burstcnt--)
276 buf[size++] = ioread8(chip->vendor.iobase +
277 TPM_DATA_FIFO(chip->vendor.
278 locality));
279 }
280 return size;
281}
282
cb535425 283static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
27084efe
LD
284{
285 int size = 0;
286 int expected, status;
287
288 if (count < TPM_HEADER_SIZE) {
289 size = -EIO;
290 goto out;
291 }
292
293 /* read first 10 bytes, including tag, paramsize, and result */
294 if ((size =
295 recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
71ed848f 296 dev_err(chip->pdev, "Unable to read header\n");
27084efe
LD
297 goto out;
298 }
299
300 expected = be32_to_cpu(*(__be32 *) (buf + 2));
301 if (expected > count) {
302 size = -EIO;
303 goto out;
304 }
305
306 if ((size +=
307 recv_data(chip, &buf[TPM_HEADER_SIZE],
308 expected - TPM_HEADER_SIZE)) < expected) {
71ed848f 309 dev_err(chip->pdev, "Unable to read remainder of result\n");
27084efe
LD
310 size = -ETIME;
311 goto out;
312 }
313
fd048866 314 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 315 &chip->vendor.int_queue, false);
27084efe
LD
316 status = tpm_tis_status(chip);
317 if (status & TPM_STS_DATA_AVAIL) { /* retry? */
71ed848f 318 dev_err(chip->pdev, "Error left over data\n");
27084efe
LD
319 size = -EIO;
320 goto out;
321 }
322
323out:
324 tpm_tis_ready(chip);
325 release_locality(chip, chip->vendor.locality, 0);
326 return size;
327}
328
90ab5ee9 329static bool itpm;
3507d612
RA
330module_param(itpm, bool, 0444);
331MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)");
332
27084efe
LD
333/*
334 * If interrupts are used (signaled by an irq set in the vendor structure)
335 * tpm.c can skip polling for the data to be available as the interrupt is
336 * waited for here
337 */
9519de3f 338static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
27084efe
LD
339{
340 int rc, status, burstcnt;
341 size_t count = 0;
27084efe
LD
342
343 if (request_locality(chip, 0) < 0)
344 return -EBUSY;
345
346 status = tpm_tis_status(chip);
347 if ((status & TPM_STS_COMMAND_READY) == 0) {
348 tpm_tis_ready(chip);
fd048866 349 if (wait_for_tpm_stat
27084efe 350 (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
78f09cc2 351 &chip->vendor.int_queue, false) < 0) {
27084efe
LD
352 rc = -ETIME;
353 goto out_err;
354 }
355 }
356
357 while (count < len - 1) {
358 burstcnt = get_burstcount(chip);
359 for (; burstcnt > 0 && count < len - 1; burstcnt--) {
360 iowrite8(buf[count], chip->vendor.iobase +
361 TPM_DATA_FIFO(chip->vendor.locality));
362 count++;
363 }
364
fd048866 365 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 366 &chip->vendor.int_queue, false);
27084efe 367 status = tpm_tis_status(chip);
3507d612 368 if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
27084efe
LD
369 rc = -EIO;
370 goto out_err;
371 }
372 }
373
374 /* write last byte */
375 iowrite8(buf[count],
9519de3f 376 chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality));
fd048866 377 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 378 &chip->vendor.int_queue, false);
27084efe
LD
379 status = tpm_tis_status(chip);
380 if ((status & TPM_STS_DATA_EXPECT) != 0) {
381 rc = -EIO;
382 goto out_err;
383 }
384
9519de3f
SB
385 return 0;
386
387out_err:
388 tpm_tis_ready(chip);
389 release_locality(chip, chip->vendor.locality, 0);
390 return rc;
391}
392
448e9c55
SD
393static void disable_interrupts(struct tpm_chip *chip)
394{
395 u32 intmask;
396
397 intmask =
398 ioread32(chip->vendor.iobase +
399 TPM_INT_ENABLE(chip->vendor.locality));
400 intmask &= ~TPM_GLOBAL_INT_ENABLE;
401 iowrite32(intmask,
402 chip->vendor.iobase +
403 TPM_INT_ENABLE(chip->vendor.locality));
404 free_irq(chip->vendor.irq, chip);
405 chip->vendor.irq = 0;
406}
407
9519de3f
SB
408/*
409 * If interrupts are used (signaled by an irq set in the vendor structure)
410 * tpm.c can skip polling for the data to be available as the interrupt is
411 * waited for here
412 */
448e9c55 413static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len)
9519de3f
SB
414{
415 int rc;
416 u32 ordinal;
aec04cbd 417 unsigned long dur;
9519de3f
SB
418
419 rc = tpm_tis_send_data(chip, buf, len);
420 if (rc < 0)
421 return rc;
422
27084efe
LD
423 /* go and do it */
424 iowrite8(TPM_STS_GO,
425 chip->vendor.iobase + TPM_STS(chip->vendor.locality));
426
427 if (chip->vendor.irq) {
428 ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
aec04cbd
JS
429
430 if (chip->flags & TPM_CHIP_FLAG_TPM2)
431 dur = tpm2_calc_ordinal_duration(chip, ordinal);
432 else
433 dur = tpm_calc_ordinal_duration(chip, ordinal);
434
fd048866 435 if (wait_for_tpm_stat
aec04cbd 436 (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur,
78f09cc2 437 &chip->vendor.read_queue, false) < 0) {
27084efe
LD
438 rc = -ETIME;
439 goto out_err;
440 }
441 }
442 return len;
443out_err:
444 tpm_tis_ready(chip);
445 release_locality(chip, chip->vendor.locality, 0);
446 return rc;
447}
448
448e9c55
SD
449static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
450{
451 int rc, irq;
452 struct priv_data *priv = chip->vendor.priv;
453
454 if (!chip->vendor.irq || priv->irq_tested)
455 return tpm_tis_send_main(chip, buf, len);
456
457 /* Verify receipt of the expected IRQ */
458 irq = chip->vendor.irq;
459 chip->vendor.irq = 0;
460 rc = tpm_tis_send_main(chip, buf, len);
461 chip->vendor.irq = irq;
462 if (!priv->irq_tested)
463 msleep(1);
464 if (!priv->irq_tested) {
465 disable_interrupts(chip);
71ed848f 466 dev_err(chip->pdev,
448e9c55
SD
467 FW_BUG "TPM interrupt not working, polling instead\n");
468 }
469 priv->irq_tested = true;
470 return rc;
471}
472
8e54caf4
JG
473struct tis_vendor_timeout_override {
474 u32 did_vid;
475 unsigned long timeout_us[4];
476};
477
478static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
479 /* Atmel 3204 */
480 { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
481 (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
482};
483
484static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
485 unsigned long *timeout_cap)
486{
487 int i;
488 u32 did_vid;
489
490 did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
491
492 for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
493 if (vendor_timeout_overrides[i].did_vid != did_vid)
494 continue;
495 memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
496 sizeof(vendor_timeout_overrides[i].timeout_us));
497 return true;
498 }
499
500 return false;
501}
502
9519de3f
SB
503/*
504 * Early probing for iTPM with STS_DATA_EXPECT flaw.
505 * Try sending command without itpm flag set and if that
506 * fails, repeat with itpm flag set.
507 */
508static int probe_itpm(struct tpm_chip *chip)
509{
510 int rc = 0;
511 u8 cmd_getticks[] = {
512 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
513 0x00, 0x00, 0x00, 0xf1
514 };
515 size_t len = sizeof(cmd_getticks);
968de8e2 516 bool rem_itpm = itpm;
4e401fb0
SB
517 u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0));
518
519 /* probe only iTPMS */
520 if (vendor != TPM_VID_INTEL)
521 return 0;
9519de3f 522
73249695 523 itpm = false;
9519de3f
SB
524
525 rc = tpm_tis_send_data(chip, cmd_getticks, len);
526 if (rc == 0)
527 goto out;
528
529 tpm_tis_ready(chip);
530 release_locality(chip, chip->vendor.locality, 0);
531
73249695 532 itpm = true;
9519de3f
SB
533
534 rc = tpm_tis_send_data(chip, cmd_getticks, len);
535 if (rc == 0) {
71ed848f 536 dev_info(chip->pdev, "Detected an iTPM.\n");
9519de3f
SB
537 rc = 1;
538 } else
539 rc = -EFAULT;
540
541out:
542 itpm = rem_itpm;
543 tpm_tis_ready(chip);
544 release_locality(chip, chip->vendor.locality, 0);
545
546 return rc;
547}
548
1f866057
SB
549static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
550{
551 switch (chip->vendor.manufacturer_id) {
552 case TPM_VID_WINBOND:
553 return ((status == TPM_STS_VALID) ||
554 (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
555 case TPM_VID_STM:
556 return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
557 default:
558 return (status == TPM_STS_COMMAND_READY);
559 }
560}
561
01ad1fa7 562static const struct tpm_class_ops tpm_tis = {
27084efe
LD
563 .status = tpm_tis_status,
564 .recv = tpm_tis_recv,
565 .send = tpm_tis_send,
566 .cancel = tpm_tis_ready,
8e54caf4 567 .update_timeouts = tpm_tis_update_timeouts,
27084efe
LD
568 .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
569 .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
1f866057 570 .req_canceled = tpm_tis_req_canceled,
27084efe
LD
571};
572
7d12e780 573static irqreturn_t tis_int_probe(int irq, void *dev_id)
27084efe 574{
06efcad0 575 struct tpm_chip *chip = dev_id;
27084efe
LD
576 u32 interrupt;
577
578 interrupt = ioread32(chip->vendor.iobase +
579 TPM_INT_STATUS(chip->vendor.locality));
580
581 if (interrupt == 0)
582 return IRQ_NONE;
583
a7b66822 584 chip->vendor.probed_irq = irq;
27084efe
LD
585
586 /* Clear interrupts handled with TPM_EOI */
587 iowrite32(interrupt,
588 chip->vendor.iobase +
589 TPM_INT_STATUS(chip->vendor.locality));
590 return IRQ_HANDLED;
591}
592
a6f97b29 593static irqreturn_t tis_int_handler(int dummy, void *dev_id)
27084efe 594{
06efcad0 595 struct tpm_chip *chip = dev_id;
27084efe
LD
596 u32 interrupt;
597 int i;
598
599 interrupt = ioread32(chip->vendor.iobase +
600 TPM_INT_STATUS(chip->vendor.locality));
601
602 if (interrupt == 0)
603 return IRQ_NONE;
604
448e9c55 605 ((struct priv_data *)chip->vendor.priv)->irq_tested = true;
27084efe
LD
606 if (interrupt & TPM_INTF_DATA_AVAIL_INT)
607 wake_up_interruptible(&chip->vendor.read_queue);
608 if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
609 for (i = 0; i < 5; i++)
610 if (check_locality(chip, i) >= 0)
611 break;
612 if (interrupt &
613 (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
614 TPM_INTF_CMD_READY_INT))
615 wake_up_interruptible(&chip->vendor.int_queue);
616
617 /* Clear interrupts handled with TPM_EOI */
618 iowrite32(interrupt,
619 chip->vendor.iobase +
620 TPM_INT_STATUS(chip->vendor.locality));
cab091ea 621 ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
27084efe
LD
622 return IRQ_HANDLED;
623}
624
73249695 625static bool interrupts = true;
57135568
KJH
626module_param(interrupts, bool, 0444);
627MODULE_PARM_DESC(interrupts, "Enable interrupts");
628
afb5abc2
JS
629static void tpm_tis_remove(struct tpm_chip *chip)
630{
74d6b3ce
JS
631 if (chip->flags & TPM_CHIP_FLAG_TPM2)
632 tpm2_shutdown(chip, TPM2_SU_CLEAR);
633
afb5abc2
JS
634 iowrite32(~TPM_GLOBAL_INT_ENABLE &
635 ioread32(chip->vendor.iobase +
636 TPM_INT_ENABLE(chip->vendor.
637 locality)),
638 chip->vendor.iobase +
639 TPM_INT_ENABLE(chip->vendor.locality));
640 release_locality(chip, chip->vendor.locality, 1);
641}
642
399235dc
JS
643static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info,
644 acpi_handle acpi_dev_handle)
27084efe
LD
645{
646 u32 vendor, intfcaps, intmask;
968de8e2 647 int rc, i, irq_s, irq_e, probe;
27084efe 648 struct tpm_chip *chip;
448e9c55 649 struct priv_data *priv;
27084efe 650
448e9c55
SD
651 priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL);
652 if (priv == NULL)
653 return -ENOMEM;
afb5abc2
JS
654
655 chip = tpmm_chip_alloc(dev, &tpm_tis);
656 if (IS_ERR(chip))
657 return PTR_ERR(chip);
658
448e9c55 659 chip->vendor.priv = priv;
aec04cbd 660#ifdef CONFIG_ACPI
0dc55365 661 chip->acpi_dev_handle = acpi_dev_handle;
aec04cbd 662#endif
27084efe 663
399235dc 664 chip->vendor.iobase = devm_ioremap(dev, tpm_info->start, tpm_info->len);
afb5abc2
JS
665 if (!chip->vendor.iobase)
666 return -EIO;
27084efe 667
aec04cbd
JS
668 /* Maximum timeouts */
669 chip->vendor.timeout_a = TIS_TIMEOUT_A_MAX;
670 chip->vendor.timeout_b = TIS_TIMEOUT_B_MAX;
671 chip->vendor.timeout_c = TIS_TIMEOUT_C_MAX;
672 chip->vendor.timeout_d = TIS_TIMEOUT_D_MAX;
ec579358 673
7240b983
JG
674 if (wait_startup(chip, 0) != 0) {
675 rc = -ENODEV;
676 goto out_err;
677 }
678
05a462af
MS
679 if (request_locality(chip, 0) != 0) {
680 rc = -ENODEV;
681 goto out_err;
682 }
683
4d5f2051
JS
684 rc = tpm2_probe(chip);
685 if (rc)
686 goto out_err;
aec04cbd 687
27084efe 688 vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
3e3a5e90 689 chip->vendor.manufacturer_id = vendor;
27084efe 690
aec04cbd
JS
691 dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
692 (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
27084efe
LD
693 vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
694
9519de3f 695 if (!itpm) {
968de8e2
SB
696 probe = probe_itpm(chip);
697 if (probe < 0) {
9519de3f
SB
698 rc = -ENODEV;
699 goto out_err;
700 }
73249695 701 itpm = !!probe;
9519de3f
SB
702 }
703
3507d612
RA
704 if (itpm)
705 dev_info(dev, "Intel iTPM workaround enabled\n");
706
707
27084efe
LD
708 /* Figure out the capabilities */
709 intfcaps =
710 ioread32(chip->vendor.iobase +
711 TPM_INTF_CAPS(chip->vendor.locality));
9e323d3e 712 dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
27084efe
LD
713 intfcaps);
714 if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
9e323d3e 715 dev_dbg(dev, "\tBurst Count Static\n");
27084efe 716 if (intfcaps & TPM_INTF_CMD_READY_INT)
9e323d3e 717 dev_dbg(dev, "\tCommand Ready Int Support\n");
27084efe 718 if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
9e323d3e 719 dev_dbg(dev, "\tInterrupt Edge Falling\n");
27084efe 720 if (intfcaps & TPM_INTF_INT_EDGE_RISING)
9e323d3e 721 dev_dbg(dev, "\tInterrupt Edge Rising\n");
27084efe 722 if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
9e323d3e 723 dev_dbg(dev, "\tInterrupt Level Low\n");
27084efe 724 if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
9e323d3e 725 dev_dbg(dev, "\tInterrupt Level High\n");
27084efe 726 if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
9e323d3e 727 dev_dbg(dev, "\tLocality Change Int Support\n");
27084efe 728 if (intfcaps & TPM_INTF_STS_VALID_INT)
9e323d3e 729 dev_dbg(dev, "\tSts Valid Int Support\n");
27084efe 730 if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
9e323d3e 731 dev_dbg(dev, "\tData Avail Int Support\n");
27084efe 732
27084efe
LD
733 /* INTERRUPT Setup */
734 init_waitqueue_head(&chip->vendor.read_queue);
735 init_waitqueue_head(&chip->vendor.int_queue);
736
737 intmask =
738 ioread32(chip->vendor.iobase +
739 TPM_INT_ENABLE(chip->vendor.locality));
740
741 intmask |= TPM_INTF_CMD_READY_INT
742 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
743 | TPM_INTF_STS_VALID_INT;
744
745 iowrite32(intmask,
746 chip->vendor.iobase +
747 TPM_INT_ENABLE(chip->vendor.locality));
7917ff9a 748 if (interrupts)
399235dc 749 chip->vendor.irq = tpm_info->irq;
7917ff9a 750 if (interrupts && !chip->vendor.irq) {
a7b66822 751 irq_s =
57135568
KJH
752 ioread8(chip->vendor.iobase +
753 TPM_INT_VECTOR(chip->vendor.locality));
a7b66822
SB
754 if (irq_s) {
755 irq_e = irq_s;
756 } else {
757 irq_s = 3;
758 irq_e = 15;
759 }
57135568 760
a7b66822 761 for (i = irq_s; i <= irq_e && chip->vendor.irq == 0; i++) {
57135568 762 iowrite8(i, chip->vendor.iobase +
a7b66822 763 TPM_INT_VECTOR(chip->vendor.locality));
afb5abc2
JS
764 if (devm_request_irq
765 (dev, i, tis_int_probe, IRQF_SHARED,
313d21ee 766 chip->devname, chip) != 0) {
71ed848f 767 dev_info(chip->pdev,
57135568
KJH
768 "Unable to request irq: %d for probe\n",
769 i);
770 continue;
771 }
27084efe 772
57135568
KJH
773 /* Clear all existing */
774 iowrite32(ioread32
775 (chip->vendor.iobase +
776 TPM_INT_STATUS(chip->vendor.locality)),
777 chip->vendor.iobase +
778 TPM_INT_STATUS(chip->vendor.locality));
779
780 /* Turn on */
781 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
782 chip->vendor.iobase +
783 TPM_INT_ENABLE(chip->vendor.locality));
784
a7b66822
SB
785 chip->vendor.probed_irq = 0;
786
57135568 787 /* Generate Interrupts */
aec04cbd 788 if (chip->flags & TPM_CHIP_FLAG_TPM2)
4d5f2051 789 tpm2_gen_interrupt(chip);
aec04cbd
JS
790 else
791 tpm_gen_interrupt(chip);
57135568 792
a7b66822
SB
793 chip->vendor.irq = chip->vendor.probed_irq;
794
795 /* free_irq will call into tis_int_probe;
796 clear all irqs we haven't seen while doing
797 tpm_gen_interrupt */
798 iowrite32(ioread32
799 (chip->vendor.iobase +
800 TPM_INT_STATUS(chip->vendor.locality)),
801 chip->vendor.iobase +
802 TPM_INT_STATUS(chip->vendor.locality));
803
57135568
KJH
804 /* Turn off */
805 iowrite32(intmask,
806 chip->vendor.iobase +
807 TPM_INT_ENABLE(chip->vendor.locality));
27084efe 808 }
27084efe
LD
809 }
810 if (chip->vendor.irq) {
811 iowrite8(chip->vendor.irq,
812 chip->vendor.iobase +
813 TPM_INT_VECTOR(chip->vendor.locality));
afb5abc2
JS
814 if (devm_request_irq
815 (dev, chip->vendor.irq, tis_int_handler, IRQF_SHARED,
313d21ee 816 chip->devname, chip) != 0) {
71ed848f 817 dev_info(chip->pdev,
57135568
KJH
818 "Unable to request irq: %d for use\n",
819 chip->vendor.irq);
27084efe
LD
820 chip->vendor.irq = 0;
821 } else {
822 /* Clear all existing */
823 iowrite32(ioread32
824 (chip->vendor.iobase +
825 TPM_INT_STATUS(chip->vendor.locality)),
826 chip->vendor.iobase +
827 TPM_INT_STATUS(chip->vendor.locality));
828
829 /* Turn on */
830 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
831 chip->vendor.iobase +
832 TPM_INT_ENABLE(chip->vendor.locality));
833 }
834 }
835
aec04cbd
JS
836 if (chip->flags & TPM_CHIP_FLAG_TPM2) {
837 chip->vendor.timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
838 chip->vendor.timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
839 chip->vendor.timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
840 chip->vendor.timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
841 chip->vendor.duration[TPM_SHORT] =
842 msecs_to_jiffies(TPM2_DURATION_SHORT);
843 chip->vendor.duration[TPM_MEDIUM] =
844 msecs_to_jiffies(TPM2_DURATION_MEDIUM);
845 chip->vendor.duration[TPM_LONG] =
846 msecs_to_jiffies(TPM2_DURATION_LONG);
847
848 rc = tpm2_do_selftest(chip);
849 if (rc == TPM2_RC_INITIALIZE) {
850 dev_warn(dev, "Firmware has not started TPM\n");
851 rc = tpm2_startup(chip, TPM2_SU_CLEAR);
852 if (!rc)
853 rc = tpm2_do_selftest(chip);
854 }
448e9c55 855
aec04cbd
JS
856 if (rc) {
857 dev_err(dev, "TPM self test failed\n");
858 if (rc > 0)
859 rc = -ENODEV;
860 goto out_err;
861 }
862 } else {
863 if (tpm_get_timeouts(chip)) {
864 dev_err(dev, "Could not get TPM timeouts and durations\n");
865 rc = -ENODEV;
866 goto out_err;
867 }
868
869 if (tpm_do_selftest(chip)) {
870 dev_err(dev, "TPM self test failed\n");
871 rc = -ENODEV;
872 goto out_err;
873 }
448e9c55
SD
874 }
875
afb5abc2 876 return tpm_chip_register(chip);
27084efe 877out_err:
afb5abc2 878 tpm_tis_remove(chip);
27084efe
LD
879 return rc;
880}
96854310 881
19b94d2d 882#ifdef CONFIG_PM_SLEEP
96854310
SB
883static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
884{
885 u32 intmask;
886
887 /* reenable interrupts that device may have lost or
888 BIOS/firmware may have disabled */
889 iowrite8(chip->vendor.irq, chip->vendor.iobase +
890 TPM_INT_VECTOR(chip->vendor.locality));
891
892 intmask =
893 ioread32(chip->vendor.iobase +
894 TPM_INT_ENABLE(chip->vendor.locality));
895
896 intmask |= TPM_INTF_CMD_READY_INT
897 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
898 | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
899
900 iowrite32(intmask,
901 chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
902}
96854310 903
a2fa3fb0
SK
904static int tpm_tis_resume(struct device *dev)
905{
906 struct tpm_chip *chip = dev_get_drvdata(dev);
74d6b3ce 907 int ret;
a2fa3fb0
SK
908
909 if (chip->vendor.irq)
910 tpm_tis_reenable_interrupts(chip);
911
74d6b3ce
JS
912 ret = tpm_pm_resume(dev);
913 if (ret)
914 return ret;
aec04cbd 915
74d6b3ce
JS
916 /* TPM 1.2 requires self-test on resume. This function actually returns
917 * an error code but for unknown reason it isn't handled.
918 */
919 if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
920 tpm_do_selftest(chip);
a2fa3fb0 921
74d6b3ce 922 return 0;
a2fa3fb0
SK
923}
924#endif
925
926static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
927
7f2ab000 928#ifdef CONFIG_PNP
afc6d369 929static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
9e323d3e
KJH
930 const struct pnp_device_id *pnp_id)
931{
399235dc 932 struct tpm_info tpm_info = tis_default_info;
0dc55365 933 acpi_handle acpi_dev_handle = NULL;
7917ff9a 934
399235dc
JS
935 tpm_info.start = pnp_mem_start(pnp_dev, 0);
936 tpm_info.len = pnp_mem_len(pnp_dev, 0);
9e323d3e 937
7917ff9a 938 if (pnp_irq_valid(pnp_dev, 0))
399235dc 939 tpm_info.irq = pnp_irq(pnp_dev, 0);
7917ff9a 940 else
73249695 941 interrupts = false;
7917ff9a 942
961be7ef 943#ifdef CONFIG_ACPI
399235dc
JS
944 if (pnp_acpi_device(pnp_dev)) {
945 if (is_itpm(pnp_acpi_device(pnp_dev)))
946 itpm = true;
947
0dc55365 948 acpi_dev_handle = pnp_acpi_device(pnp_dev)->handle;
399235dc 949 }
961be7ef 950#endif
0dc55365 951
399235dc 952 return tpm_tis_init(&pnp_dev->dev, &tpm_info, acpi_dev_handle);
9e323d3e
KJH
953}
954
0bbed20e 955static struct pnp_device_id tpm_pnp_tbl[] = {
27084efe 956 {"PNP0C31", 0}, /* TPM */
93e1b7d4
KJH
957 {"ATM1200", 0}, /* Atmel */
958 {"IFX0102", 0}, /* Infineon */
959 {"BCM0101", 0}, /* Broadcom */
061991ec 960 {"BCM0102", 0}, /* Broadcom */
93e1b7d4 961 {"NSC1200", 0}, /* National */
fb0e7e11 962 {"ICO0102", 0}, /* Intel */
93e1b7d4
KJH
963 /* Add new here */
964 {"", 0}, /* User Specified */
965 {"", 0} /* Terminator */
27084efe 966};
31bde71c 967MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
27084efe 968
39af33fc 969static void tpm_tis_pnp_remove(struct pnp_dev *dev)
253115b7
RA
970{
971 struct tpm_chip *chip = pnp_get_drvdata(dev);
399235dc 972
afb5abc2
JS
973 tpm_chip_unregister(chip);
974 tpm_tis_remove(chip);
253115b7
RA
975}
976
27084efe
LD
977static struct pnp_driver tis_pnp_driver = {
978 .name = "tpm_tis",
979 .id_table = tpm_pnp_tbl,
980 .probe = tpm_tis_pnp_init,
253115b7 981 .remove = tpm_tis_pnp_remove,
a2fa3fb0
SK
982 .driver = {
983 .pm = &tpm_tis_pm,
984 },
27084efe
LD
985};
986
93e1b7d4
KJH
987#define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2
988module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id,
989 sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444);
990MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe");
7f2ab000 991#endif
7a192ec3 992
399235dc
JS
993#ifdef CONFIG_ACPI
994static int tpm_check_resource(struct acpi_resource *ares, void *data)
995{
996 struct tpm_info *tpm_info = (struct tpm_info *) data;
997 struct resource res;
998
999 if (acpi_dev_resource_interrupt(ares, 0, &res)) {
1000 tpm_info->irq = res.start;
1001 } else if (acpi_dev_resource_memory(ares, &res)) {
1002 tpm_info->start = res.start;
1003 tpm_info->len = resource_size(&res);
1004 }
1005
1006 return 1;
1007}
1008
1009static int tpm_tis_acpi_init(struct acpi_device *acpi_dev)
1010{
1011 struct list_head resources;
1012 struct tpm_info tpm_info = tis_default_info;
1013 int ret;
1014
1015 if (!is_fifo(acpi_dev))
1016 return -ENODEV;
1017
1018 INIT_LIST_HEAD(&resources);
1019 ret = acpi_dev_get_resources(acpi_dev, &resources, tpm_check_resource,
1020 &tpm_info);
1021 if (ret < 0)
1022 return ret;
1023
1024 acpi_dev_free_resource_list(&resources);
1025
1026 if (!tpm_info.irq)
1027 interrupts = false;
1028
1029 if (is_itpm(acpi_dev))
1030 itpm = true;
1031
1032 return tpm_tis_init(&acpi_dev->dev, &tpm_info, acpi_dev->handle);
1033}
1034
1035static int tpm_tis_acpi_remove(struct acpi_device *dev)
1036{
1037 struct tpm_chip *chip = dev_get_drvdata(&dev->dev);
1038
1039 tpm_chip_unregister(chip);
1040 tpm_tis_remove(chip);
1041
1042 return 0;
1043}
1044
1045static struct acpi_device_id tpm_acpi_tbl[] = {
1046 {"MSFT0101", 0}, /* TPM 2.0 */
1047 /* Add new here */
1048 {"", 0}, /* User Specified */
1049 {"", 0} /* Terminator */
1050};
1051MODULE_DEVICE_TABLE(acpi, tpm_acpi_tbl);
1052
1053static struct acpi_driver tis_acpi_driver = {
1054 .name = "tpm_tis",
1055 .ids = tpm_acpi_tbl,
1056 .ops = {
1057 .add = tpm_tis_acpi_init,
1058 .remove = tpm_tis_acpi_remove,
1059 },
1060 .drv = {
1061 .pm = &tpm_tis_pm,
1062 },
1063};
1064#endif
1065
7a192ec3
ML
1066static struct platform_driver tis_drv = {
1067 .driver = {
afb5abc2 1068 .name = "tpm_tis",
b633f050 1069 .pm = &tpm_tis_pm,
7a192ec3 1070 },
9e323d3e
KJH
1071};
1072
1073static struct platform_device *pdev;
1074
90ab5ee9 1075static bool force;
9e323d3e
KJH
1076module_param(force, bool, 0444);
1077MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry");
27084efe
LD
1078static int __init init_tis(void)
1079{
9e323d3e 1080 int rc;
7f2ab000 1081#ifdef CONFIG_PNP
399235dc
JS
1082 if (!force) {
1083 rc = pnp_register_driver(&tis_pnp_driver);
1084 if (rc)
1085 return rc;
1086 }
1087#endif
1088#ifdef CONFIG_ACPI
1089 if (!force) {
1090 rc = acpi_bus_register_driver(&tis_acpi_driver);
1091 if (rc) {
1092#ifdef CONFIG_PNP
1093 pnp_unregister_driver(&tis_pnp_driver);
7f2ab000 1094#endif
399235dc
JS
1095 return rc;
1096 }
1097 }
1098#endif
1099 if (!force)
1100 return 0;
9e323d3e 1101
7f2ab000
RA
1102 rc = platform_driver_register(&tis_drv);
1103 if (rc < 0)
9e323d3e 1104 return rc;
4fba3c3b
WY
1105 pdev = platform_device_register_simple("tpm_tis", -1, NULL, 0);
1106 if (IS_ERR(pdev)) {
1107 rc = PTR_ERR(pdev);
1108 goto err_dev;
9e323d3e 1109 }
399235dc 1110 rc = tpm_tis_init(&pdev->dev, &tis_default_info, NULL);
4fba3c3b
WY
1111 if (rc)
1112 goto err_init;
1113 return 0;
1114err_init:
1115 platform_device_unregister(pdev);
1116err_dev:
1117 platform_driver_unregister(&tis_drv);
7f2ab000 1118 return rc;
27084efe
LD
1119}
1120
1121static void __exit cleanup_tis(void)
1122{
27084efe 1123 struct tpm_chip *chip;
399235dc 1124#if defined(CONFIG_PNP) || defined(CONFIG_ACPI)
7f2ab000 1125 if (!force) {
399235dc
JS
1126#ifdef CONFIG_ACPI
1127 acpi_bus_unregister_driver(&tis_acpi_driver);
1128#endif
1129#ifdef CONFIG_PNP
9e323d3e 1130 pnp_unregister_driver(&tis_pnp_driver);
399235dc 1131#endif
7f2ab000
RA
1132 return;
1133 }
1134#endif
afb5abc2
JS
1135 chip = dev_get_drvdata(&pdev->dev);
1136 tpm_chip_unregister(chip);
1137 tpm_tis_remove(chip);
7f2ab000
RA
1138 platform_device_unregister(pdev);
1139 platform_driver_unregister(&tis_drv);
27084efe
LD
1140}
1141
1142module_init(init_tis);
1143module_exit(cleanup_tis);
1144MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
1145MODULE_DESCRIPTION("TPM Driver");
1146MODULE_VERSION("2.0");
1147MODULE_LICENSE("GPL");