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Commit | Line | Data |
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27084efe LD |
1 | /* |
2 | * Copyright (C) 2005, 2006 IBM Corporation | |
399235dc | 3 | * Copyright (C) 2014, 2015 Intel Corporation |
27084efe LD |
4 | * |
5 | * Authors: | |
6 | * Leendert van Doorn <leendert@watson.ibm.com> | |
7 | * Kylene Hall <kjhall@us.ibm.com> | |
8 | * | |
8e81cc13 KY |
9 | * Maintained by: <tpmdd-devel@lists.sourceforge.net> |
10 | * | |
27084efe LD |
11 | * Device driver for TCG/TCPA TPM (trusted platform module). |
12 | * Specifications at www.trustedcomputinggroup.org | |
13 | * | |
14 | * This device driver implements the TPM interface as defined in | |
15 | * the TCG TPM Interface Spec version 1.2, revision 1.0. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation, version 2 of the | |
20 | * License. | |
21 | */ | |
57135568 KJH |
22 | #include <linux/init.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
27084efe | 25 | #include <linux/pnp.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
27084efe LD |
27 | #include <linux/interrupt.h> |
28 | #include <linux/wait.h> | |
3f0d3d01 | 29 | #include <linux/acpi.h> |
20b87bbf | 30 | #include <linux/freezer.h> |
27084efe LD |
31 | #include "tpm.h" |
32 | ||
27084efe LD |
33 | enum tis_access { |
34 | TPM_ACCESS_VALID = 0x80, | |
35 | TPM_ACCESS_ACTIVE_LOCALITY = 0x20, | |
36 | TPM_ACCESS_REQUEST_PENDING = 0x04, | |
37 | TPM_ACCESS_REQUEST_USE = 0x02, | |
38 | }; | |
39 | ||
40 | enum tis_status { | |
41 | TPM_STS_VALID = 0x80, | |
42 | TPM_STS_COMMAND_READY = 0x40, | |
43 | TPM_STS_GO = 0x20, | |
44 | TPM_STS_DATA_AVAIL = 0x10, | |
45 | TPM_STS_DATA_EXPECT = 0x08, | |
46 | }; | |
47 | ||
48 | enum tis_int_flags { | |
49 | TPM_GLOBAL_INT_ENABLE = 0x80000000, | |
50 | TPM_INTF_BURST_COUNT_STATIC = 0x100, | |
51 | TPM_INTF_CMD_READY_INT = 0x080, | |
52 | TPM_INTF_INT_EDGE_FALLING = 0x040, | |
53 | TPM_INTF_INT_EDGE_RISING = 0x020, | |
54 | TPM_INTF_INT_LEVEL_LOW = 0x010, | |
55 | TPM_INTF_INT_LEVEL_HIGH = 0x008, | |
56 | TPM_INTF_LOCALITY_CHANGE_INT = 0x004, | |
57 | TPM_INTF_STS_VALID_INT = 0x002, | |
58 | TPM_INTF_DATA_AVAIL_INT = 0x001, | |
59 | }; | |
60 | ||
36b20020 | 61 | enum tis_defaults { |
2a7362f5 | 62 | TIS_MEM_BASE = 0xFED40000, |
b09d5300 | 63 | TIS_MEM_LEN = 0x5000, |
cb535425 KJH |
64 | TIS_SHORT_TIMEOUT = 750, /* ms */ |
65 | TIS_LONG_TIMEOUT = 2000, /* 2 sec */ | |
36b20020 KJH |
66 | }; |
67 | ||
399235dc JS |
68 | struct tpm_info { |
69 | unsigned long start; | |
70 | unsigned long len; | |
ef7b81dc JG |
71 | /* irq > 0 means: use irq $irq; |
72 | * irq = 0 means: autoprobe for an irq; | |
73 | * irq = -1 means: no irq support | |
74 | */ | |
75 | int irq; | |
399235dc JS |
76 | }; |
77 | ||
78 | static struct tpm_info tis_default_info = { | |
79 | .start = TIS_MEM_BASE, | |
80 | .len = TIS_MEM_LEN, | |
81 | .irq = 0, | |
82 | }; | |
aec04cbd JS |
83 | |
84 | /* Some timeout values are needed before it is known whether the chip is | |
85 | * TPM 1.0 or TPM 2.0. | |
86 | */ | |
87 | #define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A) | |
88 | #define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B) | |
89 | #define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C) | |
90 | #define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D) | |
91 | ||
27084efe LD |
92 | #define TPM_ACCESS(l) (0x0000 | ((l) << 12)) |
93 | #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) | |
94 | #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12)) | |
95 | #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12)) | |
96 | #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) | |
97 | #define TPM_STS(l) (0x0018 | ((l) << 12)) | |
aec04cbd | 98 | #define TPM_STS3(l) (0x001b | ((l) << 12)) |
27084efe LD |
99 | #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) |
100 | ||
101 | #define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) | |
102 | #define TPM_RID(l) (0x0F04 | ((l) << 12)) | |
103 | ||
448e9c55 SD |
104 | struct priv_data { |
105 | bool irq_tested; | |
106 | }; | |
107 | ||
1560ffe6 | 108 | #if defined(CONFIG_PNP) && defined(CONFIG_ACPI) |
399235dc | 109 | static int has_hid(struct acpi_device *dev, const char *hid) |
3f0d3d01 | 110 | { |
3f0d3d01 MG |
111 | struct acpi_hardware_id *id; |
112 | ||
399235dc JS |
113 | list_for_each_entry(id, &dev->pnp.ids, list) |
114 | if (!strcmp(hid, id->id)) | |
3f0d3d01 | 115 | return 1; |
3f0d3d01 MG |
116 | |
117 | return 0; | |
118 | } | |
399235dc JS |
119 | |
120 | static inline int is_itpm(struct acpi_device *dev) | |
121 | { | |
122 | return has_hid(dev, "INTC0102"); | |
123 | } | |
124 | ||
125 | static inline int is_fifo(struct acpi_device *dev) | |
126 | { | |
127 | struct acpi_table_tpm2 *tbl; | |
128 | acpi_status st; | |
129 | ||
130 | /* TPM 1.2 FIFO */ | |
131 | if (!has_hid(dev, "MSFT0101")) | |
132 | return 1; | |
133 | ||
134 | st = acpi_get_table(ACPI_SIG_TPM2, 1, | |
135 | (struct acpi_table_header **) &tbl); | |
136 | if (ACPI_FAILURE(st)) { | |
137 | dev_err(&dev->dev, "failed to get TPM2 ACPI table\n"); | |
138 | return 0; | |
139 | } | |
140 | ||
55a889c2 | 141 | if (tbl->start_method != ACPI_TPM2_MEMORY_MAPPED) |
399235dc JS |
142 | return 0; |
143 | ||
144 | /* TPM 2.0 FIFO */ | |
145 | return 1; | |
146 | } | |
1560ffe6 | 147 | #else |
399235dc | 148 | static inline int is_itpm(struct acpi_device *dev) |
1560ffe6 RD |
149 | { |
150 | return 0; | |
151 | } | |
399235dc JS |
152 | |
153 | static inline int is_fifo(struct acpi_device *dev) | |
154 | { | |
155 | return 1; | |
156 | } | |
3f0d3d01 MG |
157 | #endif |
158 | ||
7240b983 JG |
159 | /* Before we attempt to access the TPM we must see that the valid bit is set. |
160 | * The specification says that this bit is 0 at reset and remains 0 until the | |
161 | * 'TPM has gone through its self test and initialization and has established | |
162 | * correct values in the other bits.' */ | |
163 | static int wait_startup(struct tpm_chip *chip, int l) | |
164 | { | |
165 | unsigned long stop = jiffies + chip->vendor.timeout_a; | |
166 | do { | |
167 | if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
168 | TPM_ACCESS_VALID) | |
169 | return 0; | |
170 | msleep(TPM_TIMEOUT); | |
171 | } while (time_before(jiffies, stop)); | |
172 | return -1; | |
173 | } | |
174 | ||
27084efe LD |
175 | static int check_locality(struct tpm_chip *chip, int l) |
176 | { | |
177 | if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
178 | (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == | |
179 | (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) | |
180 | return chip->vendor.locality = l; | |
181 | ||
182 | return -1; | |
183 | } | |
184 | ||
185 | static void release_locality(struct tpm_chip *chip, int l, int force) | |
186 | { | |
187 | if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
188 | (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) == | |
189 | (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) | |
190 | iowrite8(TPM_ACCESS_ACTIVE_LOCALITY, | |
191 | chip->vendor.iobase + TPM_ACCESS(l)); | |
192 | } | |
193 | ||
194 | static int request_locality(struct tpm_chip *chip, int l) | |
195 | { | |
20b87bbf | 196 | unsigned long stop, timeout; |
27084efe LD |
197 | long rc; |
198 | ||
199 | if (check_locality(chip, l) >= 0) | |
200 | return l; | |
201 | ||
202 | iowrite8(TPM_ACCESS_REQUEST_USE, | |
203 | chip->vendor.iobase + TPM_ACCESS(l)); | |
204 | ||
20b87bbf SB |
205 | stop = jiffies + chip->vendor.timeout_a; |
206 | ||
27084efe | 207 | if (chip->vendor.irq) { |
20b87bbf SB |
208 | again: |
209 | timeout = stop - jiffies; | |
210 | if ((long)timeout <= 0) | |
211 | return -1; | |
36b20020 | 212 | rc = wait_event_interruptible_timeout(chip->vendor.int_queue, |
27084efe LD |
213 | (check_locality |
214 | (chip, l) >= 0), | |
20b87bbf | 215 | timeout); |
27084efe LD |
216 | if (rc > 0) |
217 | return l; | |
20b87bbf SB |
218 | if (rc == -ERESTARTSYS && freezing(current)) { |
219 | clear_thread_flag(TIF_SIGPENDING); | |
220 | goto again; | |
221 | } | |
27084efe LD |
222 | } else { |
223 | /* wait for burstcount */ | |
27084efe LD |
224 | do { |
225 | if (check_locality(chip, l) >= 0) | |
226 | return l; | |
227 | msleep(TPM_TIMEOUT); | |
228 | } | |
229 | while (time_before(jiffies, stop)); | |
230 | } | |
231 | return -1; | |
232 | } | |
233 | ||
234 | static u8 tpm_tis_status(struct tpm_chip *chip) | |
235 | { | |
236 | return ioread8(chip->vendor.iobase + | |
237 | TPM_STS(chip->vendor.locality)); | |
238 | } | |
239 | ||
240 | static void tpm_tis_ready(struct tpm_chip *chip) | |
241 | { | |
242 | /* this causes the current command to be aborted */ | |
243 | iowrite8(TPM_STS_COMMAND_READY, | |
244 | chip->vendor.iobase + TPM_STS(chip->vendor.locality)); | |
245 | } | |
246 | ||
247 | static int get_burstcount(struct tpm_chip *chip) | |
248 | { | |
249 | unsigned long stop; | |
250 | int burstcnt; | |
251 | ||
252 | /* wait for burstcount */ | |
253 | /* which timeout value, spec has 2 answers (c & d) */ | |
36b20020 | 254 | stop = jiffies + chip->vendor.timeout_d; |
27084efe LD |
255 | do { |
256 | burstcnt = ioread8(chip->vendor.iobase + | |
257 | TPM_STS(chip->vendor.locality) + 1); | |
258 | burstcnt += ioread8(chip->vendor.iobase + | |
259 | TPM_STS(chip->vendor.locality) + | |
260 | 2) << 8; | |
261 | if (burstcnt) | |
262 | return burstcnt; | |
263 | msleep(TPM_TIMEOUT); | |
264 | } while (time_before(jiffies, stop)); | |
265 | return -EBUSY; | |
266 | } | |
267 | ||
cb535425 | 268 | static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count) |
27084efe LD |
269 | { |
270 | int size = 0, burstcnt; | |
271 | while (size < count && | |
fd048866 RA |
272 | wait_for_tpm_stat(chip, |
273 | TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
274 | chip->vendor.timeout_c, | |
78f09cc2 | 275 | &chip->vendor.read_queue, true) |
27084efe LD |
276 | == 0) { |
277 | burstcnt = get_burstcount(chip); | |
278 | for (; burstcnt > 0 && size < count; burstcnt--) | |
279 | buf[size++] = ioread8(chip->vendor.iobase + | |
280 | TPM_DATA_FIFO(chip->vendor. | |
281 | locality)); | |
282 | } | |
283 | return size; | |
284 | } | |
285 | ||
cb535425 | 286 | static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) |
27084efe LD |
287 | { |
288 | int size = 0; | |
289 | int expected, status; | |
290 | ||
291 | if (count < TPM_HEADER_SIZE) { | |
292 | size = -EIO; | |
293 | goto out; | |
294 | } | |
295 | ||
296 | /* read first 10 bytes, including tag, paramsize, and result */ | |
297 | if ((size = | |
298 | recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) { | |
71ed848f | 299 | dev_err(chip->pdev, "Unable to read header\n"); |
27084efe LD |
300 | goto out; |
301 | } | |
302 | ||
303 | expected = be32_to_cpu(*(__be32 *) (buf + 2)); | |
304 | if (expected > count) { | |
305 | size = -EIO; | |
306 | goto out; | |
307 | } | |
308 | ||
309 | if ((size += | |
310 | recv_data(chip, &buf[TPM_HEADER_SIZE], | |
311 | expected - TPM_HEADER_SIZE)) < expected) { | |
71ed848f | 312 | dev_err(chip->pdev, "Unable to read remainder of result\n"); |
27084efe LD |
313 | size = -ETIME; |
314 | goto out; | |
315 | } | |
316 | ||
fd048866 | 317 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
78f09cc2 | 318 | &chip->vendor.int_queue, false); |
27084efe LD |
319 | status = tpm_tis_status(chip); |
320 | if (status & TPM_STS_DATA_AVAIL) { /* retry? */ | |
71ed848f | 321 | dev_err(chip->pdev, "Error left over data\n"); |
27084efe LD |
322 | size = -EIO; |
323 | goto out; | |
324 | } | |
325 | ||
326 | out: | |
327 | tpm_tis_ready(chip); | |
328 | release_locality(chip, chip->vendor.locality, 0); | |
329 | return size; | |
330 | } | |
331 | ||
90ab5ee9 | 332 | static bool itpm; |
3507d612 RA |
333 | module_param(itpm, bool, 0444); |
334 | MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)"); | |
335 | ||
27084efe LD |
336 | /* |
337 | * If interrupts are used (signaled by an irq set in the vendor structure) | |
338 | * tpm.c can skip polling for the data to be available as the interrupt is | |
339 | * waited for here | |
340 | */ | |
9519de3f | 341 | static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len) |
27084efe LD |
342 | { |
343 | int rc, status, burstcnt; | |
344 | size_t count = 0; | |
27084efe LD |
345 | |
346 | if (request_locality(chip, 0) < 0) | |
347 | return -EBUSY; | |
348 | ||
349 | status = tpm_tis_status(chip); | |
350 | if ((status & TPM_STS_COMMAND_READY) == 0) { | |
351 | tpm_tis_ready(chip); | |
fd048866 | 352 | if (wait_for_tpm_stat |
27084efe | 353 | (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b, |
78f09cc2 | 354 | &chip->vendor.int_queue, false) < 0) { |
27084efe LD |
355 | rc = -ETIME; |
356 | goto out_err; | |
357 | } | |
358 | } | |
359 | ||
360 | while (count < len - 1) { | |
361 | burstcnt = get_burstcount(chip); | |
362 | for (; burstcnt > 0 && count < len - 1; burstcnt--) { | |
363 | iowrite8(buf[count], chip->vendor.iobase + | |
364 | TPM_DATA_FIFO(chip->vendor.locality)); | |
365 | count++; | |
366 | } | |
367 | ||
fd048866 | 368 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
78f09cc2 | 369 | &chip->vendor.int_queue, false); |
27084efe | 370 | status = tpm_tis_status(chip); |
3507d612 | 371 | if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) { |
27084efe LD |
372 | rc = -EIO; |
373 | goto out_err; | |
374 | } | |
375 | } | |
376 | ||
377 | /* write last byte */ | |
378 | iowrite8(buf[count], | |
9519de3f | 379 | chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality)); |
fd048866 | 380 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
78f09cc2 | 381 | &chip->vendor.int_queue, false); |
27084efe LD |
382 | status = tpm_tis_status(chip); |
383 | if ((status & TPM_STS_DATA_EXPECT) != 0) { | |
384 | rc = -EIO; | |
385 | goto out_err; | |
386 | } | |
387 | ||
9519de3f SB |
388 | return 0; |
389 | ||
390 | out_err: | |
391 | tpm_tis_ready(chip); | |
392 | release_locality(chip, chip->vendor.locality, 0); | |
393 | return rc; | |
394 | } | |
395 | ||
448e9c55 SD |
396 | static void disable_interrupts(struct tpm_chip *chip) |
397 | { | |
398 | u32 intmask; | |
399 | ||
400 | intmask = | |
401 | ioread32(chip->vendor.iobase + | |
402 | TPM_INT_ENABLE(chip->vendor.locality)); | |
403 | intmask &= ~TPM_GLOBAL_INT_ENABLE; | |
404 | iowrite32(intmask, | |
405 | chip->vendor.iobase + | |
406 | TPM_INT_ENABLE(chip->vendor.locality)); | |
727f28b8 | 407 | devm_free_irq(chip->pdev, chip->vendor.irq, chip); |
448e9c55 SD |
408 | chip->vendor.irq = 0; |
409 | } | |
410 | ||
9519de3f SB |
411 | /* |
412 | * If interrupts are used (signaled by an irq set in the vendor structure) | |
413 | * tpm.c can skip polling for the data to be available as the interrupt is | |
414 | * waited for here | |
415 | */ | |
448e9c55 | 416 | static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len) |
9519de3f SB |
417 | { |
418 | int rc; | |
419 | u32 ordinal; | |
aec04cbd | 420 | unsigned long dur; |
9519de3f SB |
421 | |
422 | rc = tpm_tis_send_data(chip, buf, len); | |
423 | if (rc < 0) | |
424 | return rc; | |
425 | ||
27084efe LD |
426 | /* go and do it */ |
427 | iowrite8(TPM_STS_GO, | |
428 | chip->vendor.iobase + TPM_STS(chip->vendor.locality)); | |
429 | ||
430 | if (chip->vendor.irq) { | |
431 | ordinal = be32_to_cpu(*((__be32 *) (buf + 6))); | |
aec04cbd JS |
432 | |
433 | if (chip->flags & TPM_CHIP_FLAG_TPM2) | |
434 | dur = tpm2_calc_ordinal_duration(chip, ordinal); | |
435 | else | |
436 | dur = tpm_calc_ordinal_duration(chip, ordinal); | |
437 | ||
fd048866 | 438 | if (wait_for_tpm_stat |
aec04cbd | 439 | (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur, |
78f09cc2 | 440 | &chip->vendor.read_queue, false) < 0) { |
27084efe LD |
441 | rc = -ETIME; |
442 | goto out_err; | |
443 | } | |
444 | } | |
445 | return len; | |
446 | out_err: | |
447 | tpm_tis_ready(chip); | |
448 | release_locality(chip, chip->vendor.locality, 0); | |
449 | return rc; | |
450 | } | |
451 | ||
448e9c55 SD |
452 | static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len) |
453 | { | |
454 | int rc, irq; | |
455 | struct priv_data *priv = chip->vendor.priv; | |
456 | ||
457 | if (!chip->vendor.irq || priv->irq_tested) | |
458 | return tpm_tis_send_main(chip, buf, len); | |
459 | ||
460 | /* Verify receipt of the expected IRQ */ | |
461 | irq = chip->vendor.irq; | |
462 | chip->vendor.irq = 0; | |
463 | rc = tpm_tis_send_main(chip, buf, len); | |
464 | chip->vendor.irq = irq; | |
465 | if (!priv->irq_tested) | |
466 | msleep(1); | |
e3837e74 | 467 | if (!priv->irq_tested) |
448e9c55 | 468 | disable_interrupts(chip); |
448e9c55 SD |
469 | priv->irq_tested = true; |
470 | return rc; | |
471 | } | |
472 | ||
8e54caf4 JG |
473 | struct tis_vendor_timeout_override { |
474 | u32 did_vid; | |
475 | unsigned long timeout_us[4]; | |
476 | }; | |
477 | ||
478 | static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = { | |
479 | /* Atmel 3204 */ | |
480 | { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000), | |
481 | (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } }, | |
482 | }; | |
483 | ||
484 | static bool tpm_tis_update_timeouts(struct tpm_chip *chip, | |
485 | unsigned long *timeout_cap) | |
486 | { | |
487 | int i; | |
488 | u32 did_vid; | |
489 | ||
490 | did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0)); | |
491 | ||
492 | for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) { | |
493 | if (vendor_timeout_overrides[i].did_vid != did_vid) | |
494 | continue; | |
495 | memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us, | |
496 | sizeof(vendor_timeout_overrides[i].timeout_us)); | |
497 | return true; | |
498 | } | |
499 | ||
500 | return false; | |
501 | } | |
502 | ||
9519de3f SB |
503 | /* |
504 | * Early probing for iTPM with STS_DATA_EXPECT flaw. | |
505 | * Try sending command without itpm flag set and if that | |
506 | * fails, repeat with itpm flag set. | |
507 | */ | |
508 | static int probe_itpm(struct tpm_chip *chip) | |
509 | { | |
510 | int rc = 0; | |
511 | u8 cmd_getticks[] = { | |
512 | 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a, | |
513 | 0x00, 0x00, 0x00, 0xf1 | |
514 | }; | |
515 | size_t len = sizeof(cmd_getticks); | |
968de8e2 | 516 | bool rem_itpm = itpm; |
4e401fb0 SB |
517 | u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0)); |
518 | ||
519 | /* probe only iTPMS */ | |
520 | if (vendor != TPM_VID_INTEL) | |
521 | return 0; | |
9519de3f | 522 | |
73249695 | 523 | itpm = false; |
9519de3f SB |
524 | |
525 | rc = tpm_tis_send_data(chip, cmd_getticks, len); | |
526 | if (rc == 0) | |
527 | goto out; | |
528 | ||
529 | tpm_tis_ready(chip); | |
530 | release_locality(chip, chip->vendor.locality, 0); | |
531 | ||
73249695 | 532 | itpm = true; |
9519de3f SB |
533 | |
534 | rc = tpm_tis_send_data(chip, cmd_getticks, len); | |
535 | if (rc == 0) { | |
71ed848f | 536 | dev_info(chip->pdev, "Detected an iTPM.\n"); |
9519de3f SB |
537 | rc = 1; |
538 | } else | |
539 | rc = -EFAULT; | |
540 | ||
541 | out: | |
542 | itpm = rem_itpm; | |
543 | tpm_tis_ready(chip); | |
544 | release_locality(chip, chip->vendor.locality, 0); | |
545 | ||
546 | return rc; | |
547 | } | |
548 | ||
1f866057 SB |
549 | static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status) |
550 | { | |
551 | switch (chip->vendor.manufacturer_id) { | |
552 | case TPM_VID_WINBOND: | |
553 | return ((status == TPM_STS_VALID) || | |
554 | (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY))); | |
555 | case TPM_VID_STM: | |
556 | return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)); | |
557 | default: | |
558 | return (status == TPM_STS_COMMAND_READY); | |
559 | } | |
560 | } | |
561 | ||
01ad1fa7 | 562 | static const struct tpm_class_ops tpm_tis = { |
27084efe LD |
563 | .status = tpm_tis_status, |
564 | .recv = tpm_tis_recv, | |
565 | .send = tpm_tis_send, | |
566 | .cancel = tpm_tis_ready, | |
8e54caf4 | 567 | .update_timeouts = tpm_tis_update_timeouts, |
27084efe LD |
568 | .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID, |
569 | .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
1f866057 | 570 | .req_canceled = tpm_tis_req_canceled, |
27084efe LD |
571 | }; |
572 | ||
a6f97b29 | 573 | static irqreturn_t tis_int_handler(int dummy, void *dev_id) |
27084efe | 574 | { |
06efcad0 | 575 | struct tpm_chip *chip = dev_id; |
27084efe LD |
576 | u32 interrupt; |
577 | int i; | |
578 | ||
579 | interrupt = ioread32(chip->vendor.iobase + | |
580 | TPM_INT_STATUS(chip->vendor.locality)); | |
581 | ||
582 | if (interrupt == 0) | |
583 | return IRQ_NONE; | |
584 | ||
448e9c55 | 585 | ((struct priv_data *)chip->vendor.priv)->irq_tested = true; |
27084efe LD |
586 | if (interrupt & TPM_INTF_DATA_AVAIL_INT) |
587 | wake_up_interruptible(&chip->vendor.read_queue); | |
588 | if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT) | |
589 | for (i = 0; i < 5; i++) | |
590 | if (check_locality(chip, i) >= 0) | |
591 | break; | |
592 | if (interrupt & | |
593 | (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT | | |
594 | TPM_INTF_CMD_READY_INT)) | |
595 | wake_up_interruptible(&chip->vendor.int_queue); | |
596 | ||
597 | /* Clear interrupts handled with TPM_EOI */ | |
598 | iowrite32(interrupt, | |
599 | chip->vendor.iobase + | |
600 | TPM_INT_STATUS(chip->vendor.locality)); | |
cab091ea | 601 | ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality)); |
27084efe LD |
602 | return IRQ_HANDLED; |
603 | } | |
604 | ||
e3837e74 JG |
605 | /* Register the IRQ and issue a command that will cause an interrupt. If an |
606 | * irq is seen then leave the chip setup for IRQ operation, otherwise reverse | |
607 | * everything and leave in polling mode. Returns 0 on success. | |
608 | */ | |
b8ba1e74 JG |
609 | static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask, |
610 | int flags, int irq) | |
e3837e74 JG |
611 | { |
612 | struct priv_data *priv = chip->vendor.priv; | |
613 | u8 original_int_vec; | |
614 | ||
b8ba1e74 | 615 | if (devm_request_irq(chip->pdev, irq, tis_int_handler, flags, |
e3837e74 JG |
616 | chip->devname, chip) != 0) { |
617 | dev_info(chip->pdev, "Unable to request irq: %d for probe\n", | |
618 | irq); | |
619 | return -1; | |
620 | } | |
621 | chip->vendor.irq = irq; | |
622 | ||
623 | original_int_vec = ioread8(chip->vendor.iobase + | |
624 | TPM_INT_VECTOR(chip->vendor.locality)); | |
625 | iowrite8(irq, | |
626 | chip->vendor.iobase + TPM_INT_VECTOR(chip->vendor.locality)); | |
627 | ||
628 | /* Clear all existing */ | |
629 | iowrite32(ioread32(chip->vendor.iobase + | |
630 | TPM_INT_STATUS(chip->vendor.locality)), | |
631 | chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality)); | |
632 | ||
633 | /* Turn on */ | |
634 | iowrite32(intmask | TPM_GLOBAL_INT_ENABLE, | |
635 | chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality)); | |
636 | ||
637 | priv->irq_tested = false; | |
638 | ||
639 | /* Generate an interrupt by having the core call through to | |
640 | * tpm_tis_send | |
641 | */ | |
642 | if (chip->flags & TPM_CHIP_FLAG_TPM2) | |
643 | tpm2_gen_interrupt(chip); | |
644 | else | |
645 | tpm_gen_interrupt(chip); | |
646 | ||
647 | /* tpm_tis_send will either confirm the interrupt is working or it | |
648 | * will call disable_irq which undoes all of the above. | |
649 | */ | |
650 | if (!chip->vendor.irq) { | |
651 | iowrite8(original_int_vec, | |
652 | chip->vendor.iobase + | |
653 | TPM_INT_VECTOR(chip->vendor.locality)); | |
654 | return 1; | |
655 | } | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | /* Try to find the IRQ the TPM is using. This is for legacy x86 systems that | |
661 | * do not have ACPI/etc. We typically expect the interrupt to be declared if | |
662 | * present. | |
663 | */ | |
664 | static void tpm_tis_probe_irq(struct tpm_chip *chip, u32 intmask) | |
665 | { | |
666 | u8 original_int_vec; | |
667 | int i; | |
668 | ||
669 | original_int_vec = ioread8(chip->vendor.iobase + | |
670 | TPM_INT_VECTOR(chip->vendor.locality)); | |
671 | ||
672 | if (!original_int_vec) { | |
b8ba1e74 JG |
673 | if (IS_ENABLED(CONFIG_X86)) |
674 | for (i = 3; i <= 15; i++) | |
675 | if (!tpm_tis_probe_irq_single(chip, intmask, 0, | |
676 | i)) | |
677 | return; | |
678 | } else if (!tpm_tis_probe_irq_single(chip, intmask, 0, | |
679 | original_int_vec)) | |
e3837e74 JG |
680 | return; |
681 | } | |
682 | ||
73249695 | 683 | static bool interrupts = true; |
57135568 KJH |
684 | module_param(interrupts, bool, 0444); |
685 | MODULE_PARM_DESC(interrupts, "Enable interrupts"); | |
686 | ||
afb5abc2 JS |
687 | static void tpm_tis_remove(struct tpm_chip *chip) |
688 | { | |
74d6b3ce JS |
689 | if (chip->flags & TPM_CHIP_FLAG_TPM2) |
690 | tpm2_shutdown(chip, TPM2_SU_CLEAR); | |
691 | ||
afb5abc2 JS |
692 | iowrite32(~TPM_GLOBAL_INT_ENABLE & |
693 | ioread32(chip->vendor.iobase + | |
694 | TPM_INT_ENABLE(chip->vendor. | |
695 | locality)), | |
696 | chip->vendor.iobase + | |
697 | TPM_INT_ENABLE(chip->vendor.locality)); | |
698 | release_locality(chip, chip->vendor.locality, 1); | |
699 | } | |
700 | ||
399235dc JS |
701 | static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info, |
702 | acpi_handle acpi_dev_handle) | |
27084efe LD |
703 | { |
704 | u32 vendor, intfcaps, intmask; | |
e3837e74 | 705 | int rc, probe; |
27084efe | 706 | struct tpm_chip *chip; |
448e9c55 | 707 | struct priv_data *priv; |
27084efe | 708 | |
448e9c55 SD |
709 | priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL); |
710 | if (priv == NULL) | |
711 | return -ENOMEM; | |
afb5abc2 JS |
712 | |
713 | chip = tpmm_chip_alloc(dev, &tpm_tis); | |
714 | if (IS_ERR(chip)) | |
715 | return PTR_ERR(chip); | |
716 | ||
448e9c55 | 717 | chip->vendor.priv = priv; |
aec04cbd | 718 | #ifdef CONFIG_ACPI |
0dc55365 | 719 | chip->acpi_dev_handle = acpi_dev_handle; |
aec04cbd | 720 | #endif |
27084efe | 721 | |
399235dc | 722 | chip->vendor.iobase = devm_ioremap(dev, tpm_info->start, tpm_info->len); |
afb5abc2 JS |
723 | if (!chip->vendor.iobase) |
724 | return -EIO; | |
27084efe | 725 | |
aec04cbd JS |
726 | /* Maximum timeouts */ |
727 | chip->vendor.timeout_a = TIS_TIMEOUT_A_MAX; | |
728 | chip->vendor.timeout_b = TIS_TIMEOUT_B_MAX; | |
729 | chip->vendor.timeout_c = TIS_TIMEOUT_C_MAX; | |
730 | chip->vendor.timeout_d = TIS_TIMEOUT_D_MAX; | |
ec579358 | 731 | |
7240b983 JG |
732 | if (wait_startup(chip, 0) != 0) { |
733 | rc = -ENODEV; | |
734 | goto out_err; | |
735 | } | |
736 | ||
036bb38f JG |
737 | /* Take control of the TPM's interrupt hardware and shut it off */ |
738 | intmask = ioread32(chip->vendor.iobase + | |
739 | TPM_INT_ENABLE(chip->vendor.locality)); | |
740 | intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT | | |
741 | TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT; | |
742 | intmask &= ~TPM_GLOBAL_INT_ENABLE; | |
743 | iowrite32(intmask, | |
744 | chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality)); | |
745 | ||
05a462af MS |
746 | if (request_locality(chip, 0) != 0) { |
747 | rc = -ENODEV; | |
748 | goto out_err; | |
749 | } | |
750 | ||
4d5f2051 JS |
751 | rc = tpm2_probe(chip); |
752 | if (rc) | |
753 | goto out_err; | |
aec04cbd | 754 | |
27084efe | 755 | vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0)); |
3e3a5e90 | 756 | chip->vendor.manufacturer_id = vendor; |
27084efe | 757 | |
aec04cbd JS |
758 | dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n", |
759 | (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2", | |
27084efe LD |
760 | vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0))); |
761 | ||
9519de3f | 762 | if (!itpm) { |
968de8e2 SB |
763 | probe = probe_itpm(chip); |
764 | if (probe < 0) { | |
9519de3f SB |
765 | rc = -ENODEV; |
766 | goto out_err; | |
767 | } | |
73249695 | 768 | itpm = !!probe; |
9519de3f SB |
769 | } |
770 | ||
3507d612 RA |
771 | if (itpm) |
772 | dev_info(dev, "Intel iTPM workaround enabled\n"); | |
773 | ||
774 | ||
27084efe LD |
775 | /* Figure out the capabilities */ |
776 | intfcaps = | |
777 | ioread32(chip->vendor.iobase + | |
778 | TPM_INTF_CAPS(chip->vendor.locality)); | |
9e323d3e | 779 | dev_dbg(dev, "TPM interface capabilities (0x%x):\n", |
27084efe LD |
780 | intfcaps); |
781 | if (intfcaps & TPM_INTF_BURST_COUNT_STATIC) | |
9e323d3e | 782 | dev_dbg(dev, "\tBurst Count Static\n"); |
27084efe | 783 | if (intfcaps & TPM_INTF_CMD_READY_INT) |
9e323d3e | 784 | dev_dbg(dev, "\tCommand Ready Int Support\n"); |
27084efe | 785 | if (intfcaps & TPM_INTF_INT_EDGE_FALLING) |
9e323d3e | 786 | dev_dbg(dev, "\tInterrupt Edge Falling\n"); |
27084efe | 787 | if (intfcaps & TPM_INTF_INT_EDGE_RISING) |
9e323d3e | 788 | dev_dbg(dev, "\tInterrupt Edge Rising\n"); |
27084efe | 789 | if (intfcaps & TPM_INTF_INT_LEVEL_LOW) |
9e323d3e | 790 | dev_dbg(dev, "\tInterrupt Level Low\n"); |
27084efe | 791 | if (intfcaps & TPM_INTF_INT_LEVEL_HIGH) |
9e323d3e | 792 | dev_dbg(dev, "\tInterrupt Level High\n"); |
27084efe | 793 | if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT) |
9e323d3e | 794 | dev_dbg(dev, "\tLocality Change Int Support\n"); |
27084efe | 795 | if (intfcaps & TPM_INTF_STS_VALID_INT) |
9e323d3e | 796 | dev_dbg(dev, "\tSts Valid Int Support\n"); |
27084efe | 797 | if (intfcaps & TPM_INTF_DATA_AVAIL_INT) |
9e323d3e | 798 | dev_dbg(dev, "\tData Avail Int Support\n"); |
27084efe | 799 | |
25112048 JG |
800 | /* Very early on issue a command to the TPM in polling mode to make |
801 | * sure it works. May as well use that command to set the proper | |
802 | * timeouts for the driver. | |
803 | */ | |
804 | if (tpm_get_timeouts(chip)) { | |
805 | dev_err(dev, "Could not get TPM timeouts and durations\n"); | |
806 | rc = -ENODEV; | |
807 | goto out_err; | |
808 | } | |
809 | ||
27084efe LD |
810 | /* INTERRUPT Setup */ |
811 | init_waitqueue_head(&chip->vendor.read_queue); | |
812 | init_waitqueue_head(&chip->vendor.int_queue); | |
ef7b81dc | 813 | if (interrupts && tpm_info->irq != -1) { |
e3837e74 | 814 | if (tpm_info->irq) { |
b8ba1e74 JG |
815 | tpm_tis_probe_irq_single(chip, intmask, IRQF_SHARED, |
816 | tpm_info->irq); | |
e3837e74 JG |
817 | if (!chip->vendor.irq) |
818 | dev_err(chip->pdev, FW_BUG | |
819 | "TPM interrupt not working, polling instead\n"); | |
820 | } else | |
821 | tpm_tis_probe_irq(chip, intmask); | |
25112048 | 822 | } |
aec04cbd | 823 | |
25112048 | 824 | if (chip->flags & TPM_CHIP_FLAG_TPM2) { |
aec04cbd JS |
825 | rc = tpm2_do_selftest(chip); |
826 | if (rc == TPM2_RC_INITIALIZE) { | |
827 | dev_warn(dev, "Firmware has not started TPM\n"); | |
828 | rc = tpm2_startup(chip, TPM2_SU_CLEAR); | |
829 | if (!rc) | |
830 | rc = tpm2_do_selftest(chip); | |
831 | } | |
448e9c55 | 832 | |
aec04cbd JS |
833 | if (rc) { |
834 | dev_err(dev, "TPM self test failed\n"); | |
835 | if (rc > 0) | |
836 | rc = -ENODEV; | |
837 | goto out_err; | |
838 | } | |
839 | } else { | |
aec04cbd JS |
840 | if (tpm_do_selftest(chip)) { |
841 | dev_err(dev, "TPM self test failed\n"); | |
842 | rc = -ENODEV; | |
843 | goto out_err; | |
844 | } | |
448e9c55 SD |
845 | } |
846 | ||
afb5abc2 | 847 | return tpm_chip_register(chip); |
27084efe | 848 | out_err: |
afb5abc2 | 849 | tpm_tis_remove(chip); |
27084efe LD |
850 | return rc; |
851 | } | |
96854310 | 852 | |
19b94d2d | 853 | #ifdef CONFIG_PM_SLEEP |
96854310 SB |
854 | static void tpm_tis_reenable_interrupts(struct tpm_chip *chip) |
855 | { | |
856 | u32 intmask; | |
857 | ||
858 | /* reenable interrupts that device may have lost or | |
859 | BIOS/firmware may have disabled */ | |
860 | iowrite8(chip->vendor.irq, chip->vendor.iobase + | |
861 | TPM_INT_VECTOR(chip->vendor.locality)); | |
862 | ||
863 | intmask = | |
864 | ioread32(chip->vendor.iobase + | |
865 | TPM_INT_ENABLE(chip->vendor.locality)); | |
866 | ||
867 | intmask |= TPM_INTF_CMD_READY_INT | |
868 | | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT | |
869 | | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE; | |
870 | ||
871 | iowrite32(intmask, | |
872 | chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality)); | |
873 | } | |
96854310 | 874 | |
a2fa3fb0 SK |
875 | static int tpm_tis_resume(struct device *dev) |
876 | { | |
877 | struct tpm_chip *chip = dev_get_drvdata(dev); | |
74d6b3ce | 878 | int ret; |
a2fa3fb0 SK |
879 | |
880 | if (chip->vendor.irq) | |
881 | tpm_tis_reenable_interrupts(chip); | |
882 | ||
74d6b3ce JS |
883 | ret = tpm_pm_resume(dev); |
884 | if (ret) | |
885 | return ret; | |
aec04cbd | 886 | |
74d6b3ce JS |
887 | /* TPM 1.2 requires self-test on resume. This function actually returns |
888 | * an error code but for unknown reason it isn't handled. | |
889 | */ | |
890 | if (!(chip->flags & TPM_CHIP_FLAG_TPM2)) | |
891 | tpm_do_selftest(chip); | |
a2fa3fb0 | 892 | |
74d6b3ce | 893 | return 0; |
a2fa3fb0 SK |
894 | } |
895 | #endif | |
896 | ||
897 | static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume); | |
898 | ||
7f2ab000 | 899 | #ifdef CONFIG_PNP |
afc6d369 | 900 | static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev, |
ef7b81dc | 901 | const struct pnp_device_id *pnp_id) |
9e323d3e | 902 | { |
ef7b81dc | 903 | struct tpm_info tpm_info = {}; |
0dc55365 | 904 | acpi_handle acpi_dev_handle = NULL; |
7917ff9a | 905 | |
399235dc JS |
906 | tpm_info.start = pnp_mem_start(pnp_dev, 0); |
907 | tpm_info.len = pnp_mem_len(pnp_dev, 0); | |
9e323d3e | 908 | |
7917ff9a | 909 | if (pnp_irq_valid(pnp_dev, 0)) |
399235dc | 910 | tpm_info.irq = pnp_irq(pnp_dev, 0); |
7917ff9a | 911 | else |
ef7b81dc | 912 | tpm_info.irq = -1; |
7917ff9a | 913 | |
961be7ef | 914 | #ifdef CONFIG_ACPI |
399235dc JS |
915 | if (pnp_acpi_device(pnp_dev)) { |
916 | if (is_itpm(pnp_acpi_device(pnp_dev))) | |
917 | itpm = true; | |
918 | ||
0dc55365 | 919 | acpi_dev_handle = pnp_acpi_device(pnp_dev)->handle; |
399235dc | 920 | } |
961be7ef | 921 | #endif |
0dc55365 | 922 | |
399235dc | 923 | return tpm_tis_init(&pnp_dev->dev, &tpm_info, acpi_dev_handle); |
9e323d3e KJH |
924 | } |
925 | ||
0bbed20e | 926 | static struct pnp_device_id tpm_pnp_tbl[] = { |
27084efe | 927 | {"PNP0C31", 0}, /* TPM */ |
93e1b7d4 KJH |
928 | {"ATM1200", 0}, /* Atmel */ |
929 | {"IFX0102", 0}, /* Infineon */ | |
930 | {"BCM0101", 0}, /* Broadcom */ | |
061991ec | 931 | {"BCM0102", 0}, /* Broadcom */ |
93e1b7d4 | 932 | {"NSC1200", 0}, /* National */ |
fb0e7e11 | 933 | {"ICO0102", 0}, /* Intel */ |
93e1b7d4 KJH |
934 | /* Add new here */ |
935 | {"", 0}, /* User Specified */ | |
936 | {"", 0} /* Terminator */ | |
27084efe | 937 | }; |
31bde71c | 938 | MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl); |
27084efe | 939 | |
39af33fc | 940 | static void tpm_tis_pnp_remove(struct pnp_dev *dev) |
253115b7 RA |
941 | { |
942 | struct tpm_chip *chip = pnp_get_drvdata(dev); | |
399235dc | 943 | |
afb5abc2 JS |
944 | tpm_chip_unregister(chip); |
945 | tpm_tis_remove(chip); | |
253115b7 RA |
946 | } |
947 | ||
27084efe LD |
948 | static struct pnp_driver tis_pnp_driver = { |
949 | .name = "tpm_tis", | |
950 | .id_table = tpm_pnp_tbl, | |
951 | .probe = tpm_tis_pnp_init, | |
253115b7 | 952 | .remove = tpm_tis_pnp_remove, |
a2fa3fb0 SK |
953 | .driver = { |
954 | .pm = &tpm_tis_pm, | |
955 | }, | |
27084efe LD |
956 | }; |
957 | ||
93e1b7d4 KJH |
958 | #define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2 |
959 | module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id, | |
960 | sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444); | |
961 | MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe"); | |
7f2ab000 | 962 | #endif |
7a192ec3 | 963 | |
399235dc JS |
964 | #ifdef CONFIG_ACPI |
965 | static int tpm_check_resource(struct acpi_resource *ares, void *data) | |
966 | { | |
967 | struct tpm_info *tpm_info = (struct tpm_info *) data; | |
968 | struct resource res; | |
969 | ||
970 | if (acpi_dev_resource_interrupt(ares, 0, &res)) { | |
971 | tpm_info->irq = res.start; | |
972 | } else if (acpi_dev_resource_memory(ares, &res)) { | |
973 | tpm_info->start = res.start; | |
974 | tpm_info->len = resource_size(&res); | |
975 | } | |
976 | ||
977 | return 1; | |
978 | } | |
979 | ||
980 | static int tpm_tis_acpi_init(struct acpi_device *acpi_dev) | |
981 | { | |
982 | struct list_head resources; | |
983 | struct tpm_info tpm_info = tis_default_info; | |
984 | int ret; | |
985 | ||
986 | if (!is_fifo(acpi_dev)) | |
987 | return -ENODEV; | |
988 | ||
989 | INIT_LIST_HEAD(&resources); | |
ef7b81dc | 990 | tpm_info.irq = -1; |
399235dc JS |
991 | ret = acpi_dev_get_resources(acpi_dev, &resources, tpm_check_resource, |
992 | &tpm_info); | |
993 | if (ret < 0) | |
994 | return ret; | |
995 | ||
996 | acpi_dev_free_resource_list(&resources); | |
997 | ||
399235dc JS |
998 | if (is_itpm(acpi_dev)) |
999 | itpm = true; | |
1000 | ||
1001 | return tpm_tis_init(&acpi_dev->dev, &tpm_info, acpi_dev->handle); | |
1002 | } | |
1003 | ||
1004 | static int tpm_tis_acpi_remove(struct acpi_device *dev) | |
1005 | { | |
1006 | struct tpm_chip *chip = dev_get_drvdata(&dev->dev); | |
1007 | ||
1008 | tpm_chip_unregister(chip); | |
1009 | tpm_tis_remove(chip); | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | static struct acpi_device_id tpm_acpi_tbl[] = { | |
1015 | {"MSFT0101", 0}, /* TPM 2.0 */ | |
1016 | /* Add new here */ | |
1017 | {"", 0}, /* User Specified */ | |
1018 | {"", 0} /* Terminator */ | |
1019 | }; | |
1020 | MODULE_DEVICE_TABLE(acpi, tpm_acpi_tbl); | |
1021 | ||
1022 | static struct acpi_driver tis_acpi_driver = { | |
1023 | .name = "tpm_tis", | |
1024 | .ids = tpm_acpi_tbl, | |
1025 | .ops = { | |
1026 | .add = tpm_tis_acpi_init, | |
1027 | .remove = tpm_tis_acpi_remove, | |
1028 | }, | |
1029 | .drv = { | |
1030 | .pm = &tpm_tis_pm, | |
1031 | }, | |
1032 | }; | |
1033 | #endif | |
1034 | ||
7a192ec3 ML |
1035 | static struct platform_driver tis_drv = { |
1036 | .driver = { | |
afb5abc2 | 1037 | .name = "tpm_tis", |
b633f050 | 1038 | .pm = &tpm_tis_pm, |
7a192ec3 | 1039 | }, |
9e323d3e KJH |
1040 | }; |
1041 | ||
1042 | static struct platform_device *pdev; | |
1043 | ||
90ab5ee9 | 1044 | static bool force; |
9e323d3e KJH |
1045 | module_param(force, bool, 0444); |
1046 | MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry"); | |
27084efe LD |
1047 | static int __init init_tis(void) |
1048 | { | |
9e323d3e | 1049 | int rc; |
7f2ab000 | 1050 | #ifdef CONFIG_PNP |
399235dc JS |
1051 | if (!force) { |
1052 | rc = pnp_register_driver(&tis_pnp_driver); | |
1053 | if (rc) | |
1054 | return rc; | |
1055 | } | |
1056 | #endif | |
1057 | #ifdef CONFIG_ACPI | |
1058 | if (!force) { | |
1059 | rc = acpi_bus_register_driver(&tis_acpi_driver); | |
1060 | if (rc) { | |
1061 | #ifdef CONFIG_PNP | |
1062 | pnp_unregister_driver(&tis_pnp_driver); | |
7f2ab000 | 1063 | #endif |
399235dc JS |
1064 | return rc; |
1065 | } | |
1066 | } | |
1067 | #endif | |
1068 | if (!force) | |
1069 | return 0; | |
9e323d3e | 1070 | |
7f2ab000 RA |
1071 | rc = platform_driver_register(&tis_drv); |
1072 | if (rc < 0) | |
9e323d3e | 1073 | return rc; |
4fba3c3b WY |
1074 | pdev = platform_device_register_simple("tpm_tis", -1, NULL, 0); |
1075 | if (IS_ERR(pdev)) { | |
1076 | rc = PTR_ERR(pdev); | |
1077 | goto err_dev; | |
9e323d3e | 1078 | } |
399235dc | 1079 | rc = tpm_tis_init(&pdev->dev, &tis_default_info, NULL); |
4fba3c3b WY |
1080 | if (rc) |
1081 | goto err_init; | |
1082 | return 0; | |
1083 | err_init: | |
1084 | platform_device_unregister(pdev); | |
1085 | err_dev: | |
1086 | platform_driver_unregister(&tis_drv); | |
7f2ab000 | 1087 | return rc; |
27084efe LD |
1088 | } |
1089 | ||
1090 | static void __exit cleanup_tis(void) | |
1091 | { | |
27084efe | 1092 | struct tpm_chip *chip; |
399235dc | 1093 | #if defined(CONFIG_PNP) || defined(CONFIG_ACPI) |
7f2ab000 | 1094 | if (!force) { |
399235dc JS |
1095 | #ifdef CONFIG_ACPI |
1096 | acpi_bus_unregister_driver(&tis_acpi_driver); | |
1097 | #endif | |
1098 | #ifdef CONFIG_PNP | |
9e323d3e | 1099 | pnp_unregister_driver(&tis_pnp_driver); |
399235dc | 1100 | #endif |
7f2ab000 RA |
1101 | return; |
1102 | } | |
1103 | #endif | |
afb5abc2 JS |
1104 | chip = dev_get_drvdata(&pdev->dev); |
1105 | tpm_chip_unregister(chip); | |
1106 | tpm_tis_remove(chip); | |
7f2ab000 RA |
1107 | platform_device_unregister(pdev); |
1108 | platform_driver_unregister(&tis_drv); | |
27084efe LD |
1109 | } |
1110 | ||
1111 | module_init(init_tis); | |
1112 | module_exit(cleanup_tis); | |
1113 | MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); | |
1114 | MODULE_DESCRIPTION("TPM Driver"); | |
1115 | MODULE_VERSION("2.0"); | |
1116 | MODULE_LICENSE("GPL"); |