[mirror_ubuntu-bionic-kernel.git] / drivers / char / watchdog / ibmasr.c

/*
 * IBM Automatic Server Restart driver.
 *
 * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
 *
 * Based on driver written by Pete Reynolds.
 * Copyright (c) IBM Corporation, 1998-2004.
 *
 * This software may be used and distributed according to the terms
 * of the GNU Public License, incorporated herein by reference.
 */

#include <linux/config.h>
#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/timer.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/dmi.h>

#include <asm/io.h>
#include <asm/uaccess.h>


enum {
	ASMTYPE_UNKNOWN,
	ASMTYPE_TOPAZ,
	ASMTYPE_JASPER,
	ASMTYPE_PEARL,
	ASMTYPE_JUNIPER,
	ASMTYPE_SPRUCE,
};

#define PFX "ibmasr: "

#define TOPAZ_ASR_REG_OFFSET	4
#define TOPAZ_ASR_TOGGLE	0x40
#define TOPAZ_ASR_DISABLE	0x80

/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
#define PEARL_BASE	0xe04
#define PEARL_WRITE	0xe06
#define PEARL_READ	0xe07

#define PEARL_ASR_DISABLE_MASK	0x80	/* bit 7: disable = 1, enable = 0 */
#define PEARL_ASR_TOGGLE_MASK	0x40	/* bit 6: 0, then 1, then 0 */

/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
#define JASPER_ASR_REG_OFFSET	0x38

#define JASPER_ASR_DISABLE_MASK	0x01	/* bit 0: disable = 1, enable = 0 */
#define JASPER_ASR_TOGGLE_MASK	0x02	/* bit 1: 0, then 1, then 0 */

#define JUNIPER_BASE_ADDRESS	0x54b	/* Base address of Juniper ASR */
#define JUNIPER_ASR_DISABLE_MASK 0x01	/* bit 0: disable = 1 enable = 0 */
#define JUNIPER_ASR_TOGGLE_MASK	0x02	/* bit 1: 0, then 1, then 0 */

#define SPRUCE_BASE_ADDRESS	0x118e	/* Base address of Spruce ASR */
#define SPRUCE_ASR_DISABLE_MASK	0x01	/* bit 1: disable = 1 enable = 0 */
#define SPRUCE_ASR_TOGGLE_MASK	0x02	/* bit 0: 0, then 1, then 0 */


static int nowayout = WATCHDOG_NOWAYOUT;

static unsigned long asr_is_open;
static char asr_expect_close;

static unsigned int asr_type, asr_base, asr_length;
static unsigned int asr_read_addr, asr_write_addr;
static unsigned char asr_toggle_mask, asr_disable_mask;

static void asr_toggle(void)
{
	unsigned char reg = inb(asr_read_addr);

	outb(reg & ~asr_toggle_mask, asr_write_addr);
	reg = inb(asr_read_addr);

	outb(reg | asr_toggle_mask, asr_write_addr);
	reg = inb(asr_read_addr);

	outb(reg & ~asr_toggle_mask, asr_write_addr);
	reg = inb(asr_read_addr);
}

static void asr_enable(void)
{
	unsigned char reg;

	if (asr_type == ASMTYPE_TOPAZ) {
		/* asr_write_addr == asr_read_addr */
		reg = inb(asr_read_addr);
		outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
		     asr_read_addr);
	} else {
		/*
		 * First make sure the hardware timer is reset by toggling
		 * ASR hardware timer line.
		 */
		asr_toggle();

		reg = inb(asr_read_addr);
		outb(reg & ~asr_disable_mask, asr_write_addr);
	}
	reg = inb(asr_read_addr);
}

static void asr_disable(void)
{
	unsigned char reg = inb(asr_read_addr);

	if (asr_type == ASMTYPE_TOPAZ)
		/* asr_write_addr == asr_read_addr */
		outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
		     asr_read_addr);
	else {
		outb(reg | asr_toggle_mask, asr_write_addr);
		reg = inb(asr_read_addr);

		outb(reg | asr_disable_mask, asr_write_addr);
	}
	reg = inb(asr_read_addr);
}

static int __init asr_get_base_address(void)
{
	unsigned char low, high;
	const char *type = "";

	asr_length = 1;

	switch (asr_type) {
	case ASMTYPE_TOPAZ:
		/* SELECT SuperIO CHIP FOR QUERYING (WRITE 0x07 TO BOTH 0x2E and 0x2F) */
		outb(0x07, 0x2e);
		outb(0x07, 0x2f);

		/* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
		outb(0x60, 0x2e);
		high = inb(0x2f);

		/* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
		outb(0x61, 0x2e);
		low = inb(0x2f);

		asr_base = (high << 16) | low;
		asr_read_addr = asr_write_addr =
			asr_base + TOPAZ_ASR_REG_OFFSET;
		asr_length = 5;

		break;

	case ASMTYPE_JASPER:
		type = "Jaspers ";

		/* FIXME: need to use pci_config_lock here, but it's not exported */

/*		spin_lock_irqsave(&pci_config_lock, flags);*/

		/* Select the SuperIO chip in the PCI I/O port register */
		outl(0x8000f858, 0xcf8);

		/*
		 * Read the base address for the SuperIO chip.
		 * Only the lower 16 bits are valid, but the address is word
		 * aligned so the last bit must be masked off.
		 */
		asr_base = inl(0xcfc) & 0xfffe;

/*		spin_unlock_irqrestore(&pci_config_lock, flags);*/

		asr_read_addr = asr_write_addr =
			asr_base + JASPER_ASR_REG_OFFSET;
		asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
		asr_disable_mask = JASPER_ASR_DISABLE_MASK;
		asr_length = JASPER_ASR_REG_OFFSET + 1;

		break;

	case ASMTYPE_PEARL:
		type = "Pearls ";
		asr_base = PEARL_BASE;
		asr_read_addr = PEARL_READ;
		asr_write_addr = PEARL_WRITE;
		asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
		asr_disable_mask = PEARL_ASR_DISABLE_MASK;
		asr_length = 4;
		break;

	case ASMTYPE_JUNIPER:
		type = "Junipers ";
		asr_base = JUNIPER_BASE_ADDRESS;
		asr_read_addr = asr_write_addr = asr_base;
		asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
		asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
		break;

	case ASMTYPE_SPRUCE:
		type = "Spruce's ";
		asr_base = SPRUCE_BASE_ADDRESS;
		asr_read_addr = asr_write_addr = asr_base;
		asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
		asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
		break;
	}

	if (!request_region(asr_base, asr_length, "ibmasr")) {
		printk(KERN_ERR PFX "address %#x already in use\n",
			asr_base);
		return -EBUSY;
	}

	printk(KERN_INFO PFX "found %sASR @ addr %#x\n", type, asr_base);

	return 0;
}


static ssize_t asr_write(struct file *file, const char __user *buf,
			 size_t count, loff_t *ppos)
{
	if (count) {
		if (!nowayout) {
			size_t i;

			/* In case it was set long ago */
			asr_expect_close = 0;

			for (i = 0; i != count; i++) {
				char c;
				if (get_user(c, buf + i))
					return -EFAULT;
				if (c == 'V')
					asr_expect_close = 42;
			}
		}
		asr_toggle();
	}
	return count;
}

static int asr_ioctl(struct inode *inode, struct file *file,
		     unsigned int cmd, unsigned long arg)
{
	static const struct watchdog_info ident = {
		.options =	WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
				WDIOF_MAGICCLOSE,
		.identity =	"IBM ASR"
	};
	void __user *argp = (void __user *)arg;
	int __user *p = argp;
	int heartbeat;

	switch (cmd) {
		case WDIOC_GETSUPPORT:
			return copy_to_user(argp, &ident, sizeof(ident)) ?
				-EFAULT : 0;

		case WDIOC_GETSTATUS:
		case WDIOC_GETBOOTSTATUS:
			return put_user(0, p);

		case WDIOC_KEEPALIVE:
			asr_toggle();
			return 0;

		/*
		 * The hardware has a fixed timeout value, so WDIOC_SETTIMEOUT
		 * is a noop and WDIOC_GETTIMEOUT always returns 256.
		 */
		case WDIOC_SETTIMEOUT:
			if (get_user(heartbeat, p))
				return -EFAULT;
			/* Fall */

		case WDIOC_GETTIMEOUT:
			heartbeat = 256;
			return put_user(heartbeat, p);

		case WDIOC_SETOPTIONS: {
			int new_options, retval = -EINVAL;

			if (get_user(new_options, p))
				return -EFAULT;

			if (new_options & WDIOS_DISABLECARD) {
				asr_disable();
				retval = 0;
			}

			if (new_options & WDIOS_ENABLECARD) {
				asr_enable();
				asr_toggle();
				retval = 0;
			}

			return retval;
		}
	}

	return -ENOIOCTLCMD;
}

static int asr_open(struct inode *inode, struct file *file)
{
	if(test_and_set_bit(0, &asr_is_open))
		return -EBUSY;

	asr_toggle();
	asr_enable();

	return nonseekable_open(inode, file);
}

static int asr_release(struct inode *inode, struct file *file)
{
	if (asr_expect_close == 42)
		asr_disable();
	else {
		printk(KERN_CRIT PFX "unexpected close, not stopping watchdog!\n");
		asr_toggle();
	}
	clear_bit(0, &asr_is_open);
	asr_expect_close = 0;
	return 0;
}

static struct file_operations asr_fops = {
	.owner =	THIS_MODULE,
	.llseek	=	no_llseek,
	.write =	asr_write,
	.ioctl =	asr_ioctl,
	.open =		asr_open,
	.release =	asr_release,
};

static struct miscdevice asr_miscdev = {
	.minor =	WATCHDOG_MINOR,
	.name =		"watchdog",
	.fops =		&asr_fops,
};


struct ibmasr_id {
	const char *desc;
	int type;
};

static struct ibmasr_id __initdata ibmasr_id_table[] = {
	{ "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
	{ "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
	{ "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
	{ "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
	{ "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
	{ NULL }
};

static int __init ibmasr_init(void)
{
	struct ibmasr_id *id;
	int rc;

	for (id = ibmasr_id_table; id->desc; id++) {
		if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
			asr_type = id->type;
			break;
		}
	}

	if (!asr_type)
		return -ENODEV;

	rc = misc_register(&asr_miscdev);
	if (rc < 0) {
		printk(KERN_ERR PFX "failed to register misc device\n");
		return rc;
	}

	rc = asr_get_base_address();
	if (rc) {
		misc_deregister(&asr_miscdev);
		return rc;
	}

	return 0;
}

static void __exit ibmasr_exit(void)
{
	if (!nowayout)
		asr_disable();

	misc_deregister(&asr_miscdev);

	release_region(asr_base, asr_length);
}

module_init(ibmasr_init);
module_exit(ibmasr_exit);

module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");

MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
MODULE_AUTHOR("Andrey Panin");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Commit	Line	Data
d532134d AP	1	/*
	2	* IBM Automatic Server Restart driver.
	3	*
	4	* Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
	5	*
	6	* Based on driver written by Pete Reynolds.
	7	* Copyright (c) IBM Corporation, 1998-2004.
	8	*
	9	* This software may be used and distributed according to the terms
	10	* of the GNU Public License, incorporated herein by reference.
	11	*/
	12
	13	#include <linux/config.h>
	14	#include <linux/fs.h>
	15	#include <linux/kernel.h>
	16	#include <linux/slab.h>
	17	#include <linux/module.h>
	18	#include <linux/pci.h>
	19	#include <linux/timer.h>
	20	#include <linux/miscdevice.h>
	21	#include <linux/watchdog.h>
	22	#include <linux/dmi.h>
	23
	24	#include <asm/io.h>
	25	#include <asm/uaccess.h>
	26
	27
	28	enum {
	29	ASMTYPE_UNKNOWN,
	30	ASMTYPE_TOPAZ,
	31	ASMTYPE_JASPER,
	32	ASMTYPE_PEARL,
	33	ASMTYPE_JUNIPER,
	34	ASMTYPE_SPRUCE,
	35	};
	36
	37	#define PFX "ibmasr: "
	38
	39	#define TOPAZ_ASR_REG_OFFSET 4
	40	#define TOPAZ_ASR_TOGGLE 0x40
	41	#define TOPAZ_ASR_DISABLE 0x80
	42
	43	/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
	44	#define PEARL_BASE 0xe04
	45	#define PEARL_WRITE 0xe06
	46	#define PEARL_READ 0xe07
	47
	48	#define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
	49	#define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
	50
	51	/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
	52	#define JASPER_ASR_REG_OFFSET 0x38
	53
	54	#define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
	55	#define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
	56
	57	#define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
	58	#define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */
	59	#define JUNIPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
	60
	61	#define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */
	62	#define SPRUCE_ASR_DISABLE_MASK 0x01 /* bit 1: disable = 1 enable = 0 */
	63	#define SPRUCE_ASR_TOGGLE_MASK 0x02 /* bit 0: 0, then 1, then 0 */
	64
65
66	static int nowayout = WATCHDOG_NOWAYOUT;
67
68	static unsigned long asr_is_open;
69	static char asr_expect_close;
70
71	static unsigned int asr_type, asr_base, asr_length;
72	static unsigned int asr_read_addr, asr_write_addr;
73	static unsigned char asr_toggle_mask, asr_disable_mask;
74
75	static void asr_toggle(void)
76	{
77	unsigned char reg = inb(asr_read_addr);
78
79	outb(reg & ~asr_toggle_mask, asr_write_addr);
80	reg = inb(asr_read_addr);
81
82	outb(reg \| asr_toggle_mask, asr_write_addr);
83	reg = inb(asr_read_addr);
84
85	outb(reg & ~asr_toggle_mask, asr_write_addr);
86	reg = inb(asr_read_addr);
87	}
88
89	static void asr_enable(void)
90	{
91	unsigned char reg;
92
93	if (asr_type == ASMTYPE_TOPAZ) {
94	/* asr_write_addr == asr_read_addr */
95	reg = inb(asr_read_addr);
96	outb(reg & ~(TOPAZ_ASR_TOGGLE \| TOPAZ_ASR_DISABLE),
97	asr_read_addr);
98	} else {
99	/*
100	* First make sure the hardware timer is reset by toggling
101	* ASR hardware timer line.
102	*/
103	asr_toggle();
104
105	reg = inb(asr_read_addr);
106	outb(reg & ~asr_disable_mask, asr_write_addr);
107	}
108	reg = inb(asr_read_addr);
109	}
110
111	static void asr_disable(void)
112	{
113	unsigned char reg = inb(asr_read_addr);
114
115	if (asr_type == ASMTYPE_TOPAZ)
116	/* asr_write_addr == asr_read_addr */
117	outb(reg \| TOPAZ_ASR_TOGGLE \| TOPAZ_ASR_DISABLE,
118	asr_read_addr);
119	else {
120	outb(reg \| asr_toggle_mask, asr_write_addr);
121	reg = inb(asr_read_addr);
122
123	outb(reg \| asr_disable_mask, asr_write_addr);
124	}
125	reg = inb(asr_read_addr);
126	}
127
128	static int __init asr_get_base_address(void)
129	{
130	unsigned char low, high;
131	const char *type = "";
132
133	asr_length = 1;
134
135	switch (asr_type) {
136	case ASMTYPE_TOPAZ:
137	/* SELECT SuperIO CHIP FOR QUERYING (WRITE 0x07 TO BOTH 0x2E and 0x2F) */
138	outb(0x07, 0x2e);
139	outb(0x07, 0x2f);
140
141	/* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
142	outb(0x60, 0x2e);
143	high = inb(0x2f);
144
145	/* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
146	outb(0x61, 0x2e);
147	low = inb(0x2f);
148
149	asr_base = (high << 16) \| low;
150	asr_read_addr = asr_write_addr =
151	asr_base + TOPAZ_ASR_REG_OFFSET;
152	asr_length = 5;
153
154	break;
155
156	case ASMTYPE_JASPER:
157	type = "Jaspers ";
158
159	/* FIXME: need to use pci_config_lock here, but it's not exported */
160
161	/* spin_lock_irqsave(&pci_config_lock, flags);*/
162
163	/* Select the SuperIO chip in the PCI I/O port register */
164	outl(0x8000f858, 0xcf8);
165
166	/*
167	* Read the base address for the SuperIO chip.
168	* Only the lower 16 bits are valid, but the address is word
169	* aligned so the last bit must be masked off.
170	*/
171	asr_base = inl(0xcfc) & 0xfffe;
172
173	/* spin_unlock_irqrestore(&pci_config_lock, flags);*/
174
175	asr_read_addr = asr_write_addr =
176	asr_base + JASPER_ASR_REG_OFFSET;
177	asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
178	asr_disable_mask = JASPER_ASR_DISABLE_MASK;
179	asr_length = JASPER_ASR_REG_OFFSET + 1;
180
181	break;
182
183	case ASMTYPE_PEARL:
184	type = "Pearls ";
185	asr_base = PEARL_BASE;
186	asr_read_addr = PEARL_READ;
187	asr_write_addr = PEARL_WRITE;
188	asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
189	asr_disable_mask = PEARL_ASR_DISABLE_MASK;
190	asr_length = 4;
191	break;
192
193	case ASMTYPE_JUNIPER:
194	type = "Junipers ";
195	asr_base = JUNIPER_BASE_ADDRESS;
196	asr_read_addr = asr_write_addr = asr_base;
197	asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
198	asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
199	break;
200
201	case ASMTYPE_SPRUCE:
202	type = "Spruce's ";
203	asr_base = SPRUCE_BASE_ADDRESS;
204	asr_read_addr = asr_write_addr = asr_base;
205	asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
206	asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
207	break;
208	}
209
210	if (!request_region(asr_base, asr_length, "ibmasr")) {
211	printk(KERN_ERR PFX "address %#x already in use\n",
212	asr_base);
213	return -EBUSY;
214	}
215
216	printk(KERN_INFO PFX "found %sASR @ addr %#x\n", type, asr_base);
217
218	return 0;
219	}
220
221
222	static ssize_t asr_write(struct file file, const char __user buf,
223	size_t count, loff_t *ppos)
224	{
225	if (count) {
226	if (!nowayout) {
227	size_t i;
228
229	/* In case it was set long ago */
230	asr_expect_close = 0;
231
232	for (i = 0; i != count; i++) {
233	char c;
234	if (get_user(c, buf + i))
235	return -EFAULT;
236	if (c == 'V')
237	asr_expect_close = 42;
238	}
239	}
240	asr_toggle();
241	}
242	return count;
243	}
244
245	static int asr_ioctl(struct inode inode, struct file file,
246	unsigned int cmd, unsigned long arg)
247	{
248	static const struct watchdog_info ident = {
249	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \|
250	WDIOF_MAGICCLOSE,
251	.identity = "IBM ASR"
252	};
253	void __user argp = (void __user )arg;
254	int __user *p = argp;
255	int heartbeat;
256
257	switch (cmd) {
258	case WDIOC_GETSUPPORT:
259	return copy_to_user(argp, &ident, sizeof(ident)) ?
260	-EFAULT : 0;
261
262	case WDIOC_GETSTATUS:
263	case WDIOC_GETBOOTSTATUS:
264	return put_user(0, p);
265
266	case WDIOC_KEEPALIVE:
267	asr_toggle();
268	return 0;
269
cd7b8007 AM	270	/*
	271	* The hardware has a fixed timeout value, so WDIOC_SETTIMEOUT
	272	* is a noop and WDIOC_GETTIMEOUT always returns 256.
	273	*/
d532134d AP	274	case WDIOC_SETTIMEOUT:
	275	if (get_user(heartbeat, p))
	276	return -EFAULT;
	277	/* Fall */
	278
	279	case WDIOC_GETTIMEOUT:
	280	heartbeat = 256;
	281	return put_user(heartbeat, p);
	282
	283	case WDIOC_SETOPTIONS: {
	284	int new_options, retval = -EINVAL;
	285
	286	if (get_user(new_options, p))
	287	return -EFAULT;
	288
	289	if (new_options & WDIOS_DISABLECARD) {
	290	asr_disable();
	291	retval = 0;
	292	}
	293
	294	if (new_options & WDIOS_ENABLECARD) {
	295	asr_enable();
	296	asr_toggle();
	297	retval = 0;
	298	}
	299
	300	return retval;
	301	}
	302	}
	303
	304	return -ENOIOCTLCMD;
	305	}
	306
	307	static int asr_open(struct inode inode, struct file file)
	308	{
	309	if(test_and_set_bit(0, &asr_is_open))
	310	return -EBUSY;
	311
	312	asr_toggle();
	313	asr_enable();
	314
	315	return nonseekable_open(inode, file);
	316	}
	317
	318	static int asr_release(struct inode inode, struct file file)
	319	{
	320	if (asr_expect_close == 42)
	321	asr_disable();
	322	else {
	323	printk(KERN_CRIT PFX "unexpected close, not stopping watchdog!\n");
	324	asr_toggle();
	325	}
	326	clear_bit(0, &asr_is_open);
	327	asr_expect_close = 0;
	328	return 0;
	329	}
	330
	331	static struct file_operations asr_fops = {
	332	.owner = THIS_MODULE,
	333	.llseek = no_llseek,
	334	.write = asr_write,
	335	.ioctl = asr_ioctl,
	336	.open = asr_open,
	337	.release = asr_release,
338	};
339
340	static struct miscdevice asr_miscdev = {
341	.minor = WATCHDOG_MINOR,
342	.name = "watchdog",
343	.fops = &asr_fops,
344	};
345
346
347	struct ibmasr_id {
348	const char *desc;
349	int type;
350	};
351
352	static struct ibmasr_id __initdata ibmasr_id_table[] = {
353	{ "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
354	{ "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
355	{ "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
356	{ "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
357	{ "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
358	{ NULL }
359	};
360
361	static int __init ibmasr_init(void)
362	{
363	struct ibmasr_id *id;
364	int rc;
365
366	for (id = ibmasr_id_table; id->desc; id++) {
367	if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
368	asr_type = id->type;
369	break;
370	}
371	}
372
373	if (!asr_type)
374	return -ENODEV;
375
376	rc = misc_register(&asr_miscdev);
377	if (rc < 0) {
378	printk(KERN_ERR PFX "failed to register misc device\n");
379	return rc;
380	}
381
382	rc = asr_get_base_address();
383	if (rc) {
384	misc_deregister(&asr_miscdev);
385	return rc;
386	}
387
388	return 0;
389	}
390
391	static void __exit ibmasr_exit(void)
392	{
393	if (!nowayout)
394	asr_disable();
395
396	misc_deregister(&asr_miscdev);
397
398	release_region(asr_base, asr_length);
399	}
400
401	module_init(ibmasr_init);
402	module_exit(ibmasr_exit);
403
404	module_param(nowayout, int, 0);
405	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
406
407	MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
408	MODULE_AUTHOR("Andrey Panin");
409	MODULE_LICENSE("GPL");
410	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);