[mirror_ubuntu-artful-kernel.git] / drivers / char / watchdog / mv64x60_wdt.c

/*
 * mv64x60_wdt.c - MV64X60 (Marvell Discovery) watchdog userspace interface
 *
 * Author: James Chapman <jchapman@katalix.com>
 *
 * Platform-specific setup code should configure the dog to generate
 * interrupt or reset as required.  This code only enables/disables
 * and services the watchdog.
 *
 * Derived from mpc8xx_wdt.c, with the following copyright.
 * 
 * 2002 (c) Florian Schirmer <jolt@tuxbox.org> This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/fs.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>

#include <linux/mv643xx.h>
#include <asm/uaccess.h>
#include <asm/io.h>

#define MV64x60_WDT_WDC_OFFSET	0

/* MV64x60 WDC (config) register access definitions */
#define MV64x60_WDC_CTL1_MASK	(3 << 24)
#define MV64x60_WDC_CTL1(val)	((val & 3) << 24)
#define MV64x60_WDC_CTL2_MASK	(3 << 26)
#define MV64x60_WDC_CTL2(val)	((val & 3) << 26)

/* Flags bits */
#define MV64x60_WDOG_FLAG_OPENED	0
#define MV64x60_WDOG_FLAG_ENABLED	1

static unsigned long wdt_flags;
static int wdt_status;
static void __iomem *mv64x60_wdt_regs;
static int mv64x60_wdt_timeout;
static unsigned int bus_clk;

static void mv64x60_wdt_reg_write(u32 val)
{
	/* Allow write only to CTL1 / CTL2 fields, retaining values in
	 * other fields.
	 */
	u32 data = readl(mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
	data &= ~(MV64x60_WDC_CTL1_MASK | MV64x60_WDC_CTL2_MASK);
	data |= val;
	writel(data, mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
}

static void mv64x60_wdt_service(void)
{
	/* Write 01 followed by 10 to CTL2 */
	mv64x60_wdt_reg_write(MV64x60_WDC_CTL2(0x01));
	mv64x60_wdt_reg_write(MV64x60_WDC_CTL2(0x02));
}

static void mv64x60_wdt_handler_disable(void)
{
	if (test_and_clear_bit(MV64x60_WDOG_FLAG_ENABLED, &wdt_flags)) {
		/* Write 01 followed by 10 to CTL1 */
		mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x01));
		mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x02));
		printk(KERN_NOTICE "mv64x60_wdt: watchdog deactivated\n");
	}
}

static void mv64x60_wdt_handler_enable(void)
{
	if (!test_and_set_bit(MV64x60_WDOG_FLAG_ENABLED, &wdt_flags)) {
		/* Write 01 followed by 10 to CTL1 */
		mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x01));
		mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x02));
		printk(KERN_NOTICE "mv64x60_wdt: watchdog activated\n");
	}
}

static void mv64x60_wdt_set_timeout(int timeout)
{
	/* maximum bus cycle count is 0xFFFFFFFF */
	if (timeout > 0xFFFFFFFF / bus_clk)
		timeout = 0xFFFFFFFF / bus_clk;

	mv64x60_wdt_timeout = timeout;
	writel((timeout * bus_clk) >> 8,
	       mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
	mv64x60_wdt_service();
}

static int mv64x60_wdt_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(MV64x60_WDOG_FLAG_OPENED, &wdt_flags))
		return -EBUSY;

	mv64x60_wdt_service();
	mv64x60_wdt_handler_enable();

	return nonseekable_open(inode, file);
}

static int mv64x60_wdt_release(struct inode *inode, struct file *file)
{
	mv64x60_wdt_service();

#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
	mv64x60_wdt_handler_disable();
#endif

	clear_bit(MV64x60_WDOG_FLAG_OPENED, &wdt_flags);

	return 0;
}

static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data,
				 size_t len, loff_t * ppos)
{
	if (len)
		mv64x60_wdt_service();

	return len;
}

static int mv64x60_wdt_ioctl(struct inode *inode, struct file *file,
			     unsigned int cmd, unsigned long arg)
{
	int timeout;
	void __user *argp = (void __user *)arg;
	static struct watchdog_info info = {
		.options =	WDIOF_SETTIMEOUT	|
				WDIOF_KEEPALIVEPING,
		.firmware_version = 0,
		.identity = "MV64x60 watchdog",
	};

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		if (copy_to_user(argp, &info, sizeof(info)))
			return -EFAULT;
		break;

	case WDIOC_GETSTATUS:
	case WDIOC_GETBOOTSTATUS:
		if (put_user(wdt_status, (int __user *)argp))
			return -EFAULT;
		wdt_status &= ~WDIOF_KEEPALIVEPING;
		break;

	case WDIOC_GETTEMP:
		return -EOPNOTSUPP;

	case WDIOC_SETOPTIONS:
		return -EOPNOTSUPP;

	case WDIOC_KEEPALIVE:
		mv64x60_wdt_service();
		wdt_status |= WDIOF_KEEPALIVEPING;
		break;

	case WDIOC_SETTIMEOUT:
		if (get_user(timeout, (int __user *)argp))
			return -EFAULT;
		mv64x60_wdt_set_timeout(timeout);
		/* Fall through */

	case WDIOC_GETTIMEOUT:
		if (put_user(mv64x60_wdt_timeout, (int __user *)argp))
			return -EFAULT;
		break;

	default:
		return -ENOTTY;
	}

	return 0;
}

static const struct file_operations mv64x60_wdt_fops = {
	.owner = THIS_MODULE,
	.llseek = no_llseek,
	.write = mv64x60_wdt_write,
	.ioctl = mv64x60_wdt_ioctl,
	.open = mv64x60_wdt_open,
	.release = mv64x60_wdt_release,
};

static struct miscdevice mv64x60_wdt_miscdev = {
	.minor = WATCHDOG_MINOR,
	.name = "watchdog",
	.fops = &mv64x60_wdt_fops,
};

static int __devinit mv64x60_wdt_probe(struct platform_device *dev)
{
	struct mv64x60_wdt_pdata *pdata = dev->dev.platform_data;
	struct resource *r;
	int timeout = 10;

	bus_clk = 133;			/* in MHz */
	if (pdata) {
		timeout = pdata->timeout;
		bus_clk = pdata->bus_clk;
	}

	/* Since bus_clk is truncated MHz, actual frequency could be
	 * up to 1MHz higher.  Round up, since it's better to time out
	 * too late than too soon.
	 */
	bus_clk++;
	bus_clk *= 1000000;		/* convert to Hz */

	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!r)
		return -ENODEV;

	mv64x60_wdt_regs = ioremap(r->start, r->end - r->start + 1);
	if (mv64x60_wdt_regs == NULL)
		return -ENOMEM;

	mv64x60_wdt_set_timeout(timeout);

	return misc_register(&mv64x60_wdt_miscdev);
}

static int __devexit mv64x60_wdt_remove(struct platform_device *dev)
{
	misc_deregister(&mv64x60_wdt_miscdev);

	mv64x60_wdt_service();
	mv64x60_wdt_handler_disable();

	iounmap(mv64x60_wdt_regs);

	return 0;
}

static struct platform_driver mv64x60_wdt_driver = {
	.probe = mv64x60_wdt_probe,
	.remove = __devexit_p(mv64x60_wdt_remove),
	.driver = {
		.owner = THIS_MODULE,
		.name = MV64x60_WDT_NAME,
	},
};

static int __init mv64x60_wdt_init(void)
{
	printk(KERN_INFO "MV64x60 watchdog driver\n");

	return platform_driver_register(&mv64x60_wdt_driver);
}

static void __exit mv64x60_wdt_exit(void)
{
	platform_driver_unregister(&mv64x60_wdt_driver);
}

module_init(mv64x60_wdt_init);
module_exit(mv64x60_wdt_exit);

MODULE_AUTHOR("James Chapman <jchapman@katalix.com>");
MODULE_DESCRIPTION("MV64x60 watchdog driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Commit	Line	Data
3be10211 JC	1	/*
	2	* mv64x60_wdt.c - MV64X60 (Marvell Discovery) watchdog userspace interface
	3	*
	4	* Author: James Chapman <jchapman@katalix.com>
	5	*
	6	* Platform-specific setup code should configure the dog to generate
	7	* interrupt or reset as required. This code only enables/disables
	8	* and services the watchdog.
	9	*
	10	* Derived from mpc8xx_wdt.c, with the following copyright.
	11	*
	12	* 2002 (c) Florian Schirmer <jolt@tuxbox.org> This file is licensed under
	13	* the terms of the GNU General Public License version 2. This program
	14	* is licensed "as is" without any warranty of any kind, whether express
	15	* or implied.
	16	*/
	17
3be10211 JC	18	#include <linux/fs.h>
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/miscdevice.h>
	22	#include <linux/module.h>
	23	#include <linux/watchdog.h>
d052d1be RK	24	#include <linux/platform_device.h>
d052d1be RK	25
7e07a159	26	#include <linux/mv643xx.h>
3be10211 JC	27	#include <asm/uaccess.h>
	28	#include <asm/io.h>
	29
8a5cfa64 DF	30	#define MV64x60_WDT_WDC_OFFSET 0
8a5cfa64 DF	31
3be10211 JC	32	/* MV64x60 WDC (config) register access definitions */
	33	#define MV64x60_WDC_CTL1_MASK (3 << 24)
	34	#define MV64x60_WDC_CTL1(val) ((val & 3) << 24)
	35	#define MV64x60_WDC_CTL2_MASK (3 << 26)
	36	#define MV64x60_WDC_CTL2(val) ((val & 3) << 26)
	37
	38	/* Flags bits */
	39	#define MV64x60_WDOG_FLAG_OPENED 0
	40	#define MV64x60_WDOG_FLAG_ENABLED 1
	41
	42	static unsigned long wdt_flags;
	43	static int wdt_status;
8a5cfa64	44	static void __iomem *mv64x60_wdt_regs;
3be10211	45	static int mv64x60_wdt_timeout;
94796f90	46	static unsigned int bus_clk;
3be10211 JC	47
	48	static void mv64x60_wdt_reg_write(u32 val)
	49	{
	50	/* Allow write only to CTL1 / CTL2 fields, retaining values in
	51	* other fields.
	52	*/
8a5cfa64	53	u32 data = readl(mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
3be10211 JC	54	data &= ~(MV64x60_WDC_CTL1_MASK \| MV64x60_WDC_CTL2_MASK);
3be10211 JC	55	data \|= val;
8a5cfa64	56	writel(data, mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
3be10211 JC	57	}
	58
	59	static void mv64x60_wdt_service(void)
	60	{
	61	/* Write 01 followed by 10 to CTL2 */
	62	mv64x60_wdt_reg_write(MV64x60_WDC_CTL2(0x01));
	63	mv64x60_wdt_reg_write(MV64x60_WDC_CTL2(0x02));
	64	}
	65
	66	static void mv64x60_wdt_handler_disable(void)
	67	{
	68	if (test_and_clear_bit(MV64x60_WDOG_FLAG_ENABLED, &wdt_flags)) {
	69	/* Write 01 followed by 10 to CTL1 */
	70	mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x01));
	71	mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x02));
	72	printk(KERN_NOTICE "mv64x60_wdt: watchdog deactivated\n");
	73	}
	74	}
	75
	76	static void mv64x60_wdt_handler_enable(void)
	77	{
	78	if (!test_and_set_bit(MV64x60_WDOG_FLAG_ENABLED, &wdt_flags)) {
	79	/* Write 01 followed by 10 to CTL1 */
	80	mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x01));
	81	mv64x60_wdt_reg_write(MV64x60_WDC_CTL1(0x02));
	82	printk(KERN_NOTICE "mv64x60_wdt: watchdog activated\n");
	83	}
	84	}
	85
94796f90 DF	86	static void mv64x60_wdt_set_timeout(int timeout)
	87	{
	88	/* maximum bus cycle count is 0xFFFFFFFF */
	89	if (timeout > 0xFFFFFFFF / bus_clk)
	90	timeout = 0xFFFFFFFF / bus_clk;
	91
	92	mv64x60_wdt_timeout = timeout;
	93	writel((timeout * bus_clk) >> 8,
	94	mv64x60_wdt_regs + MV64x60_WDT_WDC_OFFSET);
	95	mv64x60_wdt_service();
	96	}
	97
3be10211 JC	98	static int mv64x60_wdt_open(struct inode inode, struct file file)
	99	{
	100	if (test_and_set_bit(MV64x60_WDOG_FLAG_OPENED, &wdt_flags))
	101	return -EBUSY;
	102
	103	mv64x60_wdt_service();
	104	mv64x60_wdt_handler_enable();
	105
861e5137	106	return nonseekable_open(inode, file);
3be10211 JC	107	}
	108
	109	static int mv64x60_wdt_release(struct inode inode, struct file file)
	110	{
	111	mv64x60_wdt_service();
	112
	113	#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
	114	mv64x60_wdt_handler_disable();
	115	#endif
	116
	117	clear_bit(MV64x60_WDOG_FLAG_OPENED, &wdt_flags);
	118
	119	return 0;
	120	}
	121
b2846dfa	122	static ssize_t mv64x60_wdt_write(struct file file, const char __user data,
3be10211 JC	123	size_t len, loff_t * ppos)
3be10211 JC	124	{
3be10211 JC	125	if (len)
	126	mv64x60_wdt_service();
	127
	128	return len;
	129	}
	130
	131	static int mv64x60_wdt_ioctl(struct inode inode, struct file file,
	132	unsigned int cmd, unsigned long arg)
	133	{
94796f90	134	int timeout;
b2846dfa	135	void __user argp = (void __user )arg;
3be10211	136	static struct watchdog_info info = {
94796f90 DF	137	.options = WDIOF_SETTIMEOUT \|
94796f90 DF	138	WDIOF_KEEPALIVEPING,
3be10211 JC	139	.firmware_version = 0,
	140	.identity = "MV64x60 watchdog",
	141	};
	142
	143	switch (cmd) {
	144	case WDIOC_GETSUPPORT:
b2846dfa	145	if (copy_to_user(argp, &info, sizeof(info)))
3be10211 JC	146	return -EFAULT;
	147	break;
	148
	149	case WDIOC_GETSTATUS:
	150	case WDIOC_GETBOOTSTATUS:
b2846dfa	151	if (put_user(wdt_status, (int __user *)argp))
3be10211 JC	152	return -EFAULT;
	153	wdt_status &= ~WDIOF_KEEPALIVEPING;
	154	break;
	155
	156	case WDIOC_GETTEMP:
	157	return -EOPNOTSUPP;
	158
	159	case WDIOC_SETOPTIONS:
	160	return -EOPNOTSUPP;
	161
	162	case WDIOC_KEEPALIVE:
	163	mv64x60_wdt_service();
	164	wdt_status \|= WDIOF_KEEPALIVEPING;
	165	break;
	166
	167	case WDIOC_SETTIMEOUT:
94796f90 DF	168	if (get_user(timeout, (int __user *)argp))
	169	return -EFAULT;
	170	mv64x60_wdt_set_timeout(timeout);
	171	/* Fall through */
3be10211 JC	172
3be10211 JC	173	case WDIOC_GETTIMEOUT:
264f0991	174	if (put_user(mv64x60_wdt_timeout, (int __user *)argp))
3be10211 JC	175	return -EFAULT;
	176	break;
	177
	178	default:
795b89d2	179	return -ENOTTY;
3be10211 JC	180	}
	181
	182	return 0;
	183	}
	184
62322d25	185	static const struct file_operations mv64x60_wdt_fops = {
3be10211 JC	186	.owner = THIS_MODULE,
	187	.llseek = no_llseek,
	188	.write = mv64x60_wdt_write,
	189	.ioctl = mv64x60_wdt_ioctl,
	190	.open = mv64x60_wdt_open,
	191	.release = mv64x60_wdt_release,
	192	};
	193
	194	static struct miscdevice mv64x60_wdt_miscdev = {
	195	.minor = WATCHDOG_MINOR,
	196	.name = "watchdog",
	197	.fops = &mv64x60_wdt_fops,
	198	};
	199
3ae5eaec	200	static int __devinit mv64x60_wdt_probe(struct platform_device *dev)
3be10211	201	{
3ae5eaec	202	struct mv64x60_wdt_pdata *pdata = dev->dev.platform_data;
8a5cfa64	203	struct resource *r;
94796f90	204	int timeout = 10;
3be10211	205
94796f90	206	bus_clk = 133; /* in MHz */
3be10211	207	if (pdata) {
94796f90	208	timeout = pdata->timeout;
3be10211 JC	209	bus_clk = pdata->bus_clk;
	210	}
	211
94796f90 DF	212	/* Since bus_clk is truncated MHz, actual frequency could be
	213	* up to 1MHz higher. Round up, since it's better to time out
	214	* too late than too soon.
	215	*/
	216	bus_clk++;
	217	bus_clk = 1000000; / convert to Hz */
	218
8a5cfa64 DF	219	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	220	if (!r)
	221	return -ENODEV;
	222
	223	mv64x60_wdt_regs = ioremap(r->start, r->end - r->start + 1);
	224	if (mv64x60_wdt_regs == NULL)
	225	return -ENOMEM;
3be10211	226
94796f90	227	mv64x60_wdt_set_timeout(timeout);
3be10211 JC	228
	229	return misc_register(&mv64x60_wdt_miscdev);
	230	}
	231
3ae5eaec	232	static int __devexit mv64x60_wdt_remove(struct platform_device *dev)
3be10211 JC	233	{
	234	misc_deregister(&mv64x60_wdt_miscdev);
	235
	236	mv64x60_wdt_service();
	237	mv64x60_wdt_handler_disable();
	238
8a5cfa64 DF	239	iounmap(mv64x60_wdt_regs);
8a5cfa64 DF	240
3be10211 JC	241	return 0;
	242	}
	243
3ae5eaec	244	static struct platform_driver mv64x60_wdt_driver = {
3be10211 JC	245	.probe = mv64x60_wdt_probe,
3be10211 JC	246	.remove = __devexit_p(mv64x60_wdt_remove),
3ae5eaec RK	247	.driver = {
	248	.owner = THIS_MODULE,
	249	.name = MV64x60_WDT_NAME,
	250	},
3be10211 JC	251	};
3be10211 JC	252
3be10211 JC	253	static int __init mv64x60_wdt_init(void)
3be10211 JC	254	{
3be10211 JC	255	printk(KERN_INFO "MV64x60 watchdog driver\n");
3be10211 JC	256
422db8d2	257	return platform_driver_register(&mv64x60_wdt_driver);
3be10211 JC	258	}
	259
	260	static void __exit mv64x60_wdt_exit(void)
	261	{
3ae5eaec	262	platform_driver_unregister(&mv64x60_wdt_driver);
3be10211 JC	263	}
	264
	265	module_init(mv64x60_wdt_init);
	266	module_exit(mv64x60_wdt_exit);
	267
	268	MODULE_AUTHOR("James Chapman <jchapman@katalix.com>");
	269	MODULE_DESCRIPTION("MV64x60 watchdog driver");
	270	MODULE_LICENSE("GPL");
	271	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);