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9325fa36 VW |
1 | /* |
2 | * drivers/char/watchdog/pnx4008_wdt.c | |
3 | * | |
4 | * Watchdog driver for PNX4008 board | |
5 | * | |
6 | * Authors: Dmitry Chigirev <source@mvista.com>, | |
7 | * Vitaly Wool <vitalywool@gmail.com> | |
8 | * Based on sa1100 driver, | |
9 | * Copyright (C) 2000 Oleg Drokin <green@crimea.edu> | |
10 | * | |
11 | * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under | |
12 | * the terms of the GNU General Public License version 2. This program | |
13 | * is licensed "as is" without any warranty of any kind, whether express | |
14 | * or implied. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/moduleparam.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/fs.h> | |
23 | #include <linux/miscdevice.h> | |
24 | #include <linux/watchdog.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/bitops.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
99d2853a | 31 | #include <linux/spinlock.h> |
9325fa36 VW |
32 | |
33 | #include <asm/hardware.h> | |
34 | #include <asm/uaccess.h> | |
35 | #include <asm/io.h> | |
36 | ||
37 | #define MODULE_NAME "PNX4008-WDT: " | |
38 | ||
39 | /* WatchDog Timer - Chapter 23 Page 207 */ | |
40 | ||
41 | #define DEFAULT_HEARTBEAT 19 | |
42 | #define MAX_HEARTBEAT 60 | |
43 | ||
44 | /* Watchdog timer register set definition */ | |
45 | #define WDTIM_INT(p) ((p) + 0x0) | |
46 | #define WDTIM_CTRL(p) ((p) + 0x4) | |
47 | #define WDTIM_COUNTER(p) ((p) + 0x8) | |
48 | #define WDTIM_MCTRL(p) ((p) + 0xC) | |
49 | #define WDTIM_MATCH0(p) ((p) + 0x10) | |
50 | #define WDTIM_EMR(p) ((p) + 0x14) | |
51 | #define WDTIM_PULSE(p) ((p) + 0x18) | |
52 | #define WDTIM_RES(p) ((p) + 0x1C) | |
53 | ||
54 | /* WDTIM_INT bit definitions */ | |
55 | #define MATCH_INT 1 | |
56 | ||
57 | /* WDTIM_CTRL bit definitions */ | |
58 | #define COUNT_ENAB 1 | |
59 | #define RESET_COUNT (1<<1) | |
60 | #define DEBUG_EN (1<<2) | |
61 | ||
62 | /* WDTIM_MCTRL bit definitions */ | |
63 | #define MR0_INT 1 | |
64 | #undef RESET_COUNT0 | |
65 | #define RESET_COUNT0 (1<<2) | |
66 | #define STOP_COUNT0 (1<<2) | |
67 | #define M_RES1 (1<<3) | |
68 | #define M_RES2 (1<<4) | |
69 | #define RESFRC1 (1<<5) | |
70 | #define RESFRC2 (1<<6) | |
71 | ||
72 | /* WDTIM_EMR bit definitions */ | |
73 | #define EXT_MATCH0 1 | |
74 | #define MATCH_OUTPUT_HIGH (2<<4) /*a MATCH_CTRL setting */ | |
75 | ||
76 | /* WDTIM_RES bit definitions */ | |
77 | #define WDOG_RESET 1 /* read only */ | |
78 | ||
79 | #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */ | |
80 | ||
28981727 | 81 | static int nowayout = WATCHDOG_NOWAYOUT; |
9325fa36 VW |
82 | static int heartbeat = DEFAULT_HEARTBEAT; |
83 | ||
99d2853a | 84 | static spinlock_t io_lock; |
9325fa36 VW |
85 | static unsigned long wdt_status; |
86 | #define WDT_IN_USE 0 | |
87 | #define WDT_OK_TO_CLOSE 1 | |
88 | #define WDT_REGION_INITED 2 | |
89 | #define WDT_DEVICE_INITED 3 | |
90 | ||
91 | static unsigned long boot_status; | |
92 | ||
93 | static struct resource *wdt_mem; | |
94 | static void __iomem *wdt_base; | |
95 | struct clk *wdt_clk; | |
96 | ||
97 | static void wdt_enable(void) | |
98 | { | |
99d2853a WVS |
99 | spin_lock(&io_lock); |
100 | ||
9325fa36 VW |
101 | if (wdt_clk) |
102 | clk_set_rate(wdt_clk, 1); | |
103 | ||
104 | /* stop counter, initiate counter reset */ | |
105 | __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); | |
106 | /*wait for reset to complete. 100% guarantee event */ | |
65a64ec3 VW |
107 | while (__raw_readl(WDTIM_COUNTER(wdt_base))) |
108 | cpu_relax(); | |
9325fa36 VW |
109 | /* internal and external reset, stop after that */ |
110 | __raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, | |
111 | WDTIM_MCTRL(wdt_base)); | |
112 | /* configure match output */ | |
113 | __raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); | |
114 | /* clear interrupt, just in case */ | |
115 | __raw_writel(MATCH_INT, WDTIM_INT(wdt_base)); | |
116 | /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ | |
117 | __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base)); | |
118 | __raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); | |
119 | /*enable counter, stop when debugger active */ | |
120 | __raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); | |
99d2853a WVS |
121 | |
122 | spin_unlock(&io_lock); | |
9325fa36 VW |
123 | } |
124 | ||
125 | static void wdt_disable(void) | |
126 | { | |
99d2853a WVS |
127 | spin_lock(&io_lock); |
128 | ||
9325fa36 VW |
129 | __raw_writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ |
130 | if (wdt_clk) | |
131 | clk_set_rate(wdt_clk, 0); | |
99d2853a WVS |
132 | |
133 | spin_unlock(&io_lock); | |
9325fa36 VW |
134 | } |
135 | ||
136 | static int pnx4008_wdt_open(struct inode *inode, struct file *file) | |
137 | { | |
138 | if (test_and_set_bit(WDT_IN_USE, &wdt_status)) | |
139 | return -EBUSY; | |
140 | ||
141 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | |
142 | ||
143 | wdt_enable(); | |
144 | ||
145 | return nonseekable_open(inode, file); | |
146 | } | |
147 | ||
148 | static ssize_t | |
149 | pnx4008_wdt_write(struct file *file, const char *data, size_t len, | |
150 | loff_t * ppos) | |
151 | { | |
152 | /* Can't seek (pwrite) on this device */ | |
153 | if (ppos != &file->f_pos) | |
154 | return -ESPIPE; | |
155 | ||
156 | if (len) { | |
157 | if (!nowayout) { | |
158 | size_t i; | |
159 | ||
160 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | |
161 | ||
162 | for (i = 0; i != len; i++) { | |
163 | char c; | |
164 | ||
165 | if (get_user(c, data + i)) | |
166 | return -EFAULT; | |
167 | if (c == 'V') | |
168 | set_bit(WDT_OK_TO_CLOSE, &wdt_status); | |
169 | } | |
170 | } | |
171 | wdt_enable(); | |
172 | } | |
173 | ||
174 | return len; | |
175 | } | |
176 | ||
177 | static struct watchdog_info ident = { | |
178 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | | |
179 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
180 | .identity = "PNX4008 Watchdog", | |
181 | }; | |
182 | ||
183 | static int | |
184 | pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | |
185 | unsigned long arg) | |
186 | { | |
187 | int ret = -ENOIOCTLCMD; | |
188 | int time; | |
189 | ||
190 | switch (cmd) { | |
191 | case WDIOC_GETSUPPORT: | |
192 | ret = copy_to_user((struct watchdog_info *)arg, &ident, | |
193 | sizeof(ident)) ? -EFAULT : 0; | |
194 | break; | |
195 | ||
196 | case WDIOC_GETSTATUS: | |
197 | ret = put_user(0, (int *)arg); | |
198 | break; | |
199 | ||
200 | case WDIOC_GETBOOTSTATUS: | |
201 | ret = put_user(boot_status, (int *)arg); | |
202 | break; | |
203 | ||
204 | case WDIOC_SETTIMEOUT: | |
205 | ret = get_user(time, (int *)arg); | |
206 | if (ret) | |
207 | break; | |
208 | ||
209 | if (time <= 0 || time > MAX_HEARTBEAT) { | |
210 | ret = -EINVAL; | |
211 | break; | |
212 | } | |
213 | ||
214 | heartbeat = time; | |
215 | wdt_enable(); | |
216 | /* Fall through */ | |
217 | ||
218 | case WDIOC_GETTIMEOUT: | |
219 | ret = put_user(heartbeat, (int *)arg); | |
220 | break; | |
221 | ||
222 | case WDIOC_KEEPALIVE: | |
223 | wdt_enable(); | |
224 | ret = 0; | |
225 | break; | |
226 | } | |
227 | return ret; | |
228 | } | |
229 | ||
230 | static int pnx4008_wdt_release(struct inode *inode, struct file *file) | |
231 | { | |
232 | if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status)) | |
233 | printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n"); | |
234 | ||
235 | wdt_disable(); | |
236 | clear_bit(WDT_IN_USE, &wdt_status); | |
237 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | static struct file_operations pnx4008_wdt_fops = { | |
243 | .owner = THIS_MODULE, | |
244 | .llseek = no_llseek, | |
245 | .write = pnx4008_wdt_write, | |
246 | .ioctl = pnx4008_wdt_ioctl, | |
247 | .open = pnx4008_wdt_open, | |
248 | .release = pnx4008_wdt_release, | |
249 | }; | |
250 | ||
251 | static struct miscdevice pnx4008_wdt_miscdev = { | |
252 | .minor = WATCHDOG_MINOR, | |
253 | .name = "watchdog", | |
254 | .fops = &pnx4008_wdt_fops, | |
255 | }; | |
256 | ||
257 | static int pnx4008_wdt_probe(struct platform_device *pdev) | |
258 | { | |
259 | int ret = 0, size; | |
260 | struct resource *res; | |
261 | ||
99d2853a WVS |
262 | spin_lock_init(&io_lock); |
263 | ||
9325fa36 VW |
264 | if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) |
265 | heartbeat = DEFAULT_HEARTBEAT; | |
266 | ||
267 | printk(KERN_INFO MODULE_NAME | |
268 | "PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat); | |
269 | ||
270 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
271 | if (res == NULL) { | |
272 | printk(KERN_INFO MODULE_NAME | |
273 | "failed to get memory region resouce\n"); | |
274 | return -ENOENT; | |
275 | } | |
276 | ||
277 | size = res->end - res->start + 1; | |
278 | wdt_mem = request_mem_region(res->start, size, pdev->name); | |
279 | ||
280 | if (wdt_mem == NULL) { | |
281 | printk(KERN_INFO MODULE_NAME "failed to get memory region\n"); | |
282 | return -ENOENT; | |
283 | } | |
284 | wdt_base = (void __iomem *)IO_ADDRESS(res->start); | |
285 | ||
286 | wdt_clk = clk_get(&pdev->dev, "wdt_ck"); | |
287 | if (!wdt_clk) { | |
288 | release_resource(wdt_mem); | |
289 | kfree(wdt_mem); | |
290 | goto out; | |
291 | } else | |
292 | clk_set_rate(wdt_clk, 1); | |
293 | ||
294 | ret = misc_register(&pnx4008_wdt_miscdev); | |
295 | if (ret < 0) { | |
296 | printk(KERN_ERR MODULE_NAME "cannot register misc device\n"); | |
297 | release_resource(wdt_mem); | |
298 | kfree(wdt_mem); | |
299 | clk_set_rate(wdt_clk, 0); | |
300 | } else { | |
301 | boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? | |
302 | WDIOF_CARDRESET : 0; | |
303 | wdt_disable(); /*disable for now */ | |
304 | set_bit(WDT_DEVICE_INITED, &wdt_status); | |
305 | } | |
306 | ||
307 | out: | |
308 | return ret; | |
309 | } | |
310 | ||
311 | static int pnx4008_wdt_remove(struct platform_device *pdev) | |
312 | { | |
f6764497 | 313 | misc_deregister(&pnx4008_wdt_miscdev); |
9325fa36 VW |
314 | if (wdt_clk) { |
315 | clk_set_rate(wdt_clk, 0); | |
316 | clk_put(wdt_clk); | |
317 | wdt_clk = NULL; | |
318 | } | |
f6764497 WVS |
319 | if (wdt_mem) { |
320 | release_resource(wdt_mem); | |
321 | kfree(wdt_mem); | |
322 | wdt_mem = NULL; | |
323 | } | |
9325fa36 VW |
324 | return 0; |
325 | } | |
326 | ||
327 | static struct platform_driver platform_wdt_driver = { | |
328 | .driver = { | |
329 | .name = "watchdog", | |
330 | }, | |
331 | .probe = pnx4008_wdt_probe, | |
332 | .remove = pnx4008_wdt_remove, | |
333 | }; | |
334 | ||
335 | static int __init pnx4008_wdt_init(void) | |
336 | { | |
337 | return platform_driver_register(&platform_wdt_driver); | |
338 | } | |
339 | ||
340 | static void __exit pnx4008_wdt_exit(void) | |
341 | { | |
342 | return platform_driver_unregister(&platform_wdt_driver); | |
343 | } | |
344 | ||
345 | module_init(pnx4008_wdt_init); | |
346 | module_exit(pnx4008_wdt_exit); | |
347 | ||
348 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
349 | MODULE_DESCRIPTION("PNX4008 Watchdog Driver"); | |
350 | ||
351 | module_param(heartbeat, int, 0); | |
352 | MODULE_PARM_DESC(heartbeat, | |
353 | "Watchdog heartbeat period in seconds from 1 to " | |
354 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
355 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
356 | ||
357 | module_param(nowayout, int, 0); | |
358 | MODULE_PARM_DESC(nowayout, | |
359 | "Set to 1 to keep watchdog running after device release"); | |
360 | ||
361 | MODULE_LICENSE("GPL"); | |
362 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |