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Commit | Line | Data |
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6d803ba7 JCPV |
1 | |
2 | config CLKDEV_LOOKUP | |
3 | bool | |
4 | select HAVE_CLK | |
aa3831cf | 5 | |
5c77f560 SG |
6 | config HAVE_CLK_PREPARE |
7 | bool | |
8 | ||
aa3831cf KP |
9 | config HAVE_MACH_CLKDEV |
10 | bool | |
b2476490 | 11 | |
8fb61e33 AB |
12 | config COMMON_CLK |
13 | bool | |
b2476490 | 14 | select HAVE_CLK_PREPARE |
01033be1 | 15 | select CLKDEV_LOOKUP |
b2476490 MT |
16 | ---help--- |
17 | The common clock framework is a single definition of struct | |
18 | clk, useful across many platforms, as well as an | |
19 | implementation of the clock API in include/linux/clk.h. | |
20 | Architectures utilizing the common struct clk should select | |
8fb61e33 | 21 | this option. |
b2476490 | 22 | |
8fb61e33 AB |
23 | menu "Common Clock Framework" |
24 | depends on COMMON_CLK | |
b2476490 | 25 | |
f05259a6 MB |
26 | config COMMON_CLK_WM831X |
27 | tristate "Clock driver for WM831x/2x PMICs" | |
28 | depends on MFD_WM831X | |
29 | ---help--- | |
30 | Supports the clocking subsystem of the WM831x/2x series of | |
31 | PMICs from Wolfson Microlectronics. | |
32 | ||
f9a6aa43 | 33 | config COMMON_CLK_VERSATILE |
672575e1 | 34 | bool "Clock driver for ARM Reference designs" |
c7f6e2d8 | 35 | depends on ARCH_INTEGRATOR || ARCH_REALVIEW || ARCH_VEXPRESS || ARM64 |
f9a6aa43 | 36 | ---help--- |
bcd6f569 PM |
37 | Supports clocking on ARM Reference designs: |
38 | - Integrator/AP and Integrator/CP | |
39 | - RealView PB1176, EB, PB11MP and PBX | |
40 | - Versatile Express | |
f9a6aa43 | 41 | |
73118e61 JL |
42 | config COMMON_CLK_MAX77686 |
43 | tristate "Clock driver for Maxim 77686 MFD" | |
44 | depends on MFD_MAX77686 | |
45 | ---help--- | |
46 | This driver supports Maxim 77686 crystal oscillator clock. | |
47 | ||
9abd5f05 SH |
48 | config COMMON_CLK_SI5351 |
49 | tristate "Clock driver for SiLabs 5351A/B/C" | |
50 | depends on I2C | |
51 | select REGMAP_I2C | |
52 | select RATIONAL | |
53 | ---help--- | |
54 | This driver supports Silicon Labs 5351A/B/C programmable clock | |
55 | generators. | |
56 | ||
1459c837 SB |
57 | config COMMON_CLK_SI570 |
58 | tristate "Clock driver for SiLabs 570 and compatible devices" | |
59 | depends on I2C | |
60 | depends on OF | |
61 | select REGMAP_I2C | |
62 | help | |
63 | ---help--- | |
64 | This driver supports Silicon Labs 570/571/598/599 programmable | |
65 | clock generators. | |
66 | ||
7cc560de YSB |
67 | config COMMON_CLK_S2MPS11 |
68 | tristate "Clock driver for S2MPS11 MFD" | |
69 | depends on MFD_SEC_CORE | |
70 | ---help--- | |
71 | This driver supports S2MPS11 crystal oscillator clock. | |
72 | ||
f9f8c043 PU |
73 | config CLK_TWL6040 |
74 | tristate "External McPDM functional clock from twl6040" | |
75 | depends on TWL6040_CORE | |
76 | ---help--- | |
77 | Enable the external functional clock support on OMAP4+ platforms for | |
78 | McPDM. McPDM module is using the external bit clock on the McPDM bus | |
79 | as functional clock. | |
80 | ||
0e646c52 LPC |
81 | config COMMON_CLK_AXI_CLKGEN |
82 | tristate "AXI clkgen driver" | |
83 | depends on ARCH_ZYNQ || MICROBLAZE | |
84 | help | |
85 | ---help--- | |
86 | Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx | |
87 | FPGAs. It is commonly used in Analog Devices' reference designs. | |
88 | ||
555eae97 TY |
89 | config CLK_PPC_CORENET |
90 | bool "Clock driver for PowerPC corenet platforms" | |
91 | depends on PPC_E500MC && OF | |
92 | ---help--- | |
93 | This adds the clock driver support for Freescale PowerPC corenet | |
94 | platforms using common clock framework. | |
95 | ||
308964ca LH |
96 | config COMMON_CLK_XGENE |
97 | bool "Clock driver for APM XGene SoC" | |
98 | default y | |
99 | depends on ARM64 | |
100 | ---help--- | |
101 | Sypport for the APM X-Gene SoC reference, PLL, and device clocks. | |
102 | ||
6cfc229d SS |
103 | config COMMON_CLK_KEYSTONE |
104 | tristate "Clock drivers for Keystone based SOCs" | |
105 | depends on ARCH_KEYSTONE && OF | |
106 | ---help--- | |
107 | Supports clock drivers for Keystone based SOCs. These SOCs have local | |
108 | a power sleep control module that gate the clock to the IPs and PLLs. | |
109 | ||
8fb61e33 | 110 | endmenu |
97fa4cf4 SH |
111 | |
112 | source "drivers/clk/mvebu/Kconfig" |