[mirror_ubuntu-jammy-kernel.git] / drivers / clk / at91 / at91sam9x5.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/slab.h>

#include <dt-bindings/clock/at91.h>

#include "pmc.h"

static const struct clk_master_characteristics mck_characteristics = {
	.output = { .min = 0, .max = 133333333 },
	.divisors = { 1, 2, 4, 3 },
	.have_div3_pres = 1,
};

static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };

static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };

static const struct clk_range plla_outputs[] = {
	{ .min = 745000000, .max = 800000000 },
	{ .min = 695000000, .max = 750000000 },
	{ .min = 645000000, .max = 700000000 },
	{ .min = 595000000, .max = 650000000 },
	{ .min = 545000000, .max = 600000000 },
	{ .min = 495000000, .max = 555000000 },
	{ .min = 445000000, .max = 500000000 },
	{ .min = 400000000, .max = 450000000 },
};

static const struct clk_pll_characteristics plla_characteristics = {
	.input = { .min = 2000000, .max = 32000000 },
	.num_output = ARRAY_SIZE(plla_outputs),
	.output = plla_outputs,
	.icpll = plla_icpll,
	.out = plla_out,
};

static const struct {
	char *n;
	char *p;
	u8 id;
} at91sam9x5_systemck[] = {
	{ .n = "ddrck", .p = "masterck", .id = 2 },
	{ .n = "smdck", .p = "smdclk",   .id = 4 },
	{ .n = "uhpck", .p = "usbck",    .id = 6 },
	{ .n = "udpck", .p = "usbck",    .id = 7 },
	{ .n = "pck0",  .p = "prog0",    .id = 8 },
	{ .n = "pck1",  .p = "prog1",    .id = 9 },
};

static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
	.offset = 0x10c,
	.cmd = BIT(12),
	.pid_mask = GENMASK(5, 0),
	.div_mask = GENMASK(17, 16),
};

struct pck {
	char *n;
	u8 id;
};

static const struct pck at91sam9x5_periphck[] = {
	{ .n = "pioAB_clk",  .id = 2, },
	{ .n = "pioCD_clk",  .id = 3, },
	{ .n = "smd_clk",    .id = 4, },
	{ .n = "usart0_clk", .id = 5, },
	{ .n = "usart1_clk", .id = 6, },
	{ .n = "usart2_clk", .id = 7, },
	{ .n = "twi0_clk",   .id = 9, },
	{ .n = "twi1_clk",   .id = 10, },
	{ .n = "twi2_clk",   .id = 11, },
	{ .n = "mci0_clk",   .id = 12, },
	{ .n = "spi0_clk",   .id = 13, },
	{ .n = "spi1_clk",   .id = 14, },
	{ .n = "uart0_clk",  .id = 15, },
	{ .n = "uart1_clk",  .id = 16, },
	{ .n = "tcb0_clk",   .id = 17, },
	{ .n = "pwm_clk",    .id = 18, },
	{ .n = "adc_clk",    .id = 19, },
	{ .n = "dma0_clk",   .id = 20, },
	{ .n = "dma1_clk",   .id = 21, },
	{ .n = "uhphs_clk",  .id = 22, },
	{ .n = "udphs_clk",  .id = 23, },
	{ .n = "mci1_clk",   .id = 26, },
	{ .n = "ssc0_clk",   .id = 28, },
};

static const struct pck at91sam9g15_periphck[] = {
	{ .n = "lcdc_clk", .id = 25, },
	{ /* sentinel */}
};

static const struct pck at91sam9g25_periphck[] = {
	{ .n = "usart3_clk", .id = 8, },
	{ .n = "macb0_clk", .id = 24, },
	{ .n = "isi_clk", .id = 25, },
	{ /* sentinel */}
};

static const struct pck at91sam9g35_periphck[] = {
	{ .n = "macb0_clk", .id = 24, },
	{ .n = "lcdc_clk", .id = 25, },
	{ /* sentinel */}
};

static const struct pck at91sam9x25_periphck[] = {
	{ .n = "usart3_clk", .id = 8, },
	{ .n = "macb0_clk", .id = 24, },
	{ .n = "macb1_clk", .id = 27, },
	{ .n = "can0_clk", .id = 29, },
	{ .n = "can1_clk", .id = 30, },
	{ /* sentinel */}
};

static const struct pck at91sam9x35_periphck[] = {
	{ .n = "macb0_clk", .id = 24, },
	{ .n = "lcdc_clk", .id = 25, },
	{ .n = "can0_clk", .id = 29, },
	{ .n = "can1_clk", .id = 30, },
	{ /* sentinel */}
};

static void __init at91sam9x5_pmc_setup(struct device_node *np,
					const struct pck *extra_pcks,
					bool has_lcdck)
{
	struct clk_range range = CLK_RANGE(0, 0);
	const char *slck_name, *mainxtal_name;
	struct pmc_data *at91sam9x5_pmc;
	const char *parent_names[6];
	struct regmap *regmap;
	struct clk_hw *hw;
	int i;
	bool bypass;

	i = of_property_match_string(np, "clock-names", "slow_clk");
	if (i < 0)
		return;

	slck_name = of_clk_get_parent_name(np, i);

	i = of_property_match_string(np, "clock-names", "main_xtal");
	if (i < 0)
		return;
	mainxtal_name = of_clk_get_parent_name(np, i);

	regmap = device_node_to_regmap(np);
	if (IS_ERR(regmap))
		return;

	at91sam9x5_pmc = pmc_data_allocate(PMC_PLLACK + 1,
					   nck(at91sam9x5_systemck), 31, 0, 2);
	if (!at91sam9x5_pmc)
		return;

	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
					   50000000);
	if (IS_ERR(hw))
		goto err_free;

	bypass = of_property_read_bool(np, "atmel,osc-bypass");

	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
					bypass);
	if (IS_ERR(hw))
		goto err_free;

	parent_names[0] = "main_rc_osc";
	parent_names[1] = "main_osc";
	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
	if (IS_ERR(hw))
		goto err_free;

	at91sam9x5_pmc->chws[PMC_MAIN] = hw;

	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
				   &at91rm9200_pll_layout, &plla_characteristics);
	if (IS_ERR(hw))
		goto err_free;

	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
	if (IS_ERR(hw))
		goto err_free;

	at91sam9x5_pmc->chws[PMC_PLLACK] = hw;

	hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
	if (IS_ERR(hw))
		goto err_free;

	at91sam9x5_pmc->chws[PMC_UTMI] = hw;

	parent_names[0] = slck_name;
	parent_names[1] = "mainck";
	parent_names[2] = "plladivck";
	parent_names[3] = "utmick";
	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
				      &at91sam9x5_master_layout,
				      &mck_characteristics);
	if (IS_ERR(hw))
		goto err_free;

	at91sam9x5_pmc->chws[PMC_MCK] = hw;

	parent_names[0] = "plladivck";
	parent_names[1] = "utmick";
	hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
	if (IS_ERR(hw))
		goto err_free;

	hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
	if (IS_ERR(hw))
		goto err_free;

	parent_names[0] = slck_name;
	parent_names[1] = "mainck";
	parent_names[2] = "plladivck";
	parent_names[3] = "utmick";
	parent_names[4] = "masterck";
	for (i = 0; i < 2; i++) {
		char name[6];

		snprintf(name, sizeof(name), "prog%d", i);

		hw = at91_clk_register_programmable(regmap, name,
						    parent_names, 5, i,
						    &at91sam9x5_programmable_layout,
						    NULL);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->pchws[i] = hw;
	}

	for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
		hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
					      at91sam9x5_systemck[i].p,
					      at91sam9x5_systemck[i].id);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
	}

	if (has_lcdck) {
		hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->shws[3] = hw;
	}

	for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
							 &at91sam9x5_pcr_layout,
							 at91sam9x5_periphck[i].n,
							 "masterck",
							 at91sam9x5_periphck[i].id,
							 &range, INT_MIN);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
	}

	for (i = 0; extra_pcks[i].id; i++) {
		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
							 &at91sam9x5_pcr_layout,
							 extra_pcks[i].n,
							 "masterck",
							 extra_pcks[i].id,
							 &range, INT_MIN);
		if (IS_ERR(hw))
			goto err_free;

		at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
	}

	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);

	return;

err_free:
	kfree(at91sam9x5_pmc);
}

static void __init at91sam9g15_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
}
CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
		      at91sam9g15_pmc_setup);

static void __init at91sam9g25_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
}
CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
		      at91sam9g25_pmc_setup);

static void __init at91sam9g35_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
}
CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
		      at91sam9g35_pmc_setup);

static void __init at91sam9x25_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
}
CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
		      at91sam9x25_pmc_setup);

static void __init at91sam9x35_pmc_setup(struct device_node *np)
{
	at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
}
CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
		      at91sam9x35_pmc_setup);
Commit	Line	Data
1eabdc2f AB	1	// SPDX-License-Identifier: GPL-2.0
	2	#include <linux/clk-provider.h>
	3	#include <linux/mfd/syscon.h>
	4	#include <linux/slab.h>
	5
	6	#include <dt-bindings/clock/at91.h>
	7
	8	#include "pmc.h"
	9
	10	static const struct clk_master_characteristics mck_characteristics = {
	11	.output = { .min = 0, .max = 133333333 },
	12	.divisors = { 1, 2, 4, 3 },
	13	.have_div3_pres = 1,
	14	};
	15
	16	static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
	17
	18	static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
	19
7b4c162e	20	static const struct clk_range plla_outputs[] = {
1eabdc2f AB	21	{ .min = 745000000, .max = 800000000 },
	22	{ .min = 695000000, .max = 750000000 },
	23	{ .min = 645000000, .max = 700000000 },
	24	{ .min = 595000000, .max = 650000000 },
	25	{ .min = 545000000, .max = 600000000 },
	26	{ .min = 495000000, .max = 555000000 },
	27	{ .min = 445000000, .max = 500000000 },
	28	{ .min = 400000000, .max = 450000000 },
	29	};
	30
	31	static const struct clk_pll_characteristics plla_characteristics = {
	32	.input = { .min = 2000000, .max = 32000000 },
	33	.num_output = ARRAY_SIZE(plla_outputs),
	34	.output = plla_outputs,
	35	.icpll = plla_icpll,
	36	.out = plla_out,
	37	};
	38
	39	static const struct {
	40	char *n;
	41	char *p;
	42	u8 id;
	43	} at91sam9x5_systemck[] = {
	44	{ .n = "ddrck", .p = "masterck", .id = 2 },
	45	{ .n = "smdck", .p = "smdclk", .id = 4 },
	46	{ .n = "uhpck", .p = "usbck", .id = 6 },
	47	{ .n = "udpck", .p = "usbck", .id = 7 },
	48	{ .n = "pck0", .p = "prog0", .id = 8 },
	49	{ .n = "pck1", .p = "prog1", .id = 9 },
	50	};
	51
cb4f4949 AB	52	static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
	53	.offset = 0x10c,
	54	.cmd = BIT(12),
	55	.pid_mask = GENMASK(5, 0),
	56	.div_mask = GENMASK(17, 16),
	57	};
	58
1eabdc2f AB	59	struct pck {
	60	char *n;
	61	u8 id;
	62	};
	63
	64	static const struct pck at91sam9x5_periphck[] = {
	65	{ .n = "pioAB_clk", .id = 2, },
	66	{ .n = "pioCD_clk", .id = 3, },
	67	{ .n = "smd_clk", .id = 4, },
	68	{ .n = "usart0_clk", .id = 5, },
	69	{ .n = "usart1_clk", .id = 6, },
	70	{ .n = "usart2_clk", .id = 7, },
	71	{ .n = "twi0_clk", .id = 9, },
	72	{ .n = "twi1_clk", .id = 10, },
	73	{ .n = "twi2_clk", .id = 11, },
	74	{ .n = "mci0_clk", .id = 12, },
	75	{ .n = "spi0_clk", .id = 13, },
	76	{ .n = "spi1_clk", .id = 14, },
	77	{ .n = "uart0_clk", .id = 15, },
	78	{ .n = "uart1_clk", .id = 16, },
	79	{ .n = "tcb0_clk", .id = 17, },
	80	{ .n = "pwm_clk", .id = 18, },
	81	{ .n = "adc_clk", .id = 19, },
	82	{ .n = "dma0_clk", .id = 20, },
	83	{ .n = "dma1_clk", .id = 21, },
	84	{ .n = "uhphs_clk", .id = 22, },
	85	{ .n = "udphs_clk", .id = 23, },
	86	{ .n = "mci1_clk", .id = 26, },
	87	{ .n = "ssc0_clk", .id = 28, },
	88	};
	89
	90	static const struct pck at91sam9g15_periphck[] = {
	91	{ .n = "lcdc_clk", .id = 25, },
	92	{ /* sentinel */}
	93	};
	94
	95	static const struct pck at91sam9g25_periphck[] = {
	96	{ .n = "usart3_clk", .id = 8, },
	97	{ .n = "macb0_clk", .id = 24, },
	98	{ .n = "isi_clk", .id = 25, },
	99	{ /* sentinel */}
	100	};
	101
	102	static const struct pck at91sam9g35_periphck[] = {
	103	{ .n = "macb0_clk", .id = 24, },
	104	{ .n = "lcdc_clk", .id = 25, },
	105	{ /* sentinel */}
	106	};
	107
	108	static const struct pck at91sam9x25_periphck[] = {
	109	{ .n = "usart3_clk", .id = 8, },
	110	{ .n = "macb0_clk", .id = 24, },
	111	{ .n = "macb1_clk", .id = 27, },
	112	{ .n = "can0_clk", .id = 29, },
	113	{ .n = "can1_clk", .id = 30, },
	114	{ /* sentinel */}
	115	};
	116
	117	static const struct pck at91sam9x35_periphck[] = {
	118	{ .n = "macb0_clk", .id = 24, },
	119	{ .n = "lcdc_clk", .id = 25, },
	120	{ .n = "can0_clk", .id = 29, },
	121	{ .n = "can1_clk", .id = 30, },
	122	{ /* sentinel */}
123	};
124
125	static void __init at91sam9x5_pmc_setup(struct device_node *np,
126	const struct pck *extra_pcks,
127	bool has_lcdck)
128	{
129	struct clk_range range = CLK_RANGE(0, 0);
130	const char slck_name, mainxtal_name;
131	struct pmc_data *at91sam9x5_pmc;
132	const char *parent_names[6];
133	struct regmap *regmap;
134	struct clk_hw *hw;
135	int i;
136	bool bypass;
137
138	i = of_property_match_string(np, "clock-names", "slow_clk");
139	if (i < 0)
140	return;
141
142	slck_name = of_clk_get_parent_name(np, i);
143
144	i = of_property_match_string(np, "clock-names", "main_xtal");
145	if (i < 0)
146	return;
147	mainxtal_name = of_clk_get_parent_name(np, i);
148
6956eb33	149	regmap = device_node_to_regmap(np);
1eabdc2f AB	150	if (IS_ERR(regmap))
	151	return;
	152
03a1ee1d	153	at91sam9x5_pmc = pmc_data_allocate(PMC_PLLACK + 1,
99767cd4	154	nck(at91sam9x5_systemck), 31, 0, 2);
1eabdc2f AB	155	if (!at91sam9x5_pmc)
	156	return;
	157
	158	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
	159	50000000);
	160	if (IS_ERR(hw))
	161	goto err_free;
	162
	163	bypass = of_property_read_bool(np, "atmel,osc-bypass");
	164
	165	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
	166	bypass);
	167	if (IS_ERR(hw))
	168	goto err_free;
	169
	170	parent_names[0] = "main_rc_osc";
	171	parent_names[1] = "main_osc";
	172	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
	173	if (IS_ERR(hw))
	174	goto err_free;
	175
	176	at91sam9x5_pmc->chws[PMC_MAIN] = hw;
	177
	178	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
	179	&at91rm9200_pll_layout, &plla_characteristics);
	180	if (IS_ERR(hw))
	181	goto err_free;
	182
	183	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
	184	if (IS_ERR(hw))
	185	goto err_free;
	186
03a1ee1d MM	187	at91sam9x5_pmc->chws[PMC_PLLACK] = hw;
03a1ee1d MM	188
1eabdc2f AB	189	hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
	190	if (IS_ERR(hw))
	191	goto err_free;
	192
	193	at91sam9x5_pmc->chws[PMC_UTMI] = hw;
	194
	195	parent_names[0] = slck_name;
	196	parent_names[1] = "mainck";
	197	parent_names[2] = "plladivck";
	198	parent_names[3] = "utmick";
	199	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
	200	&at91sam9x5_master_layout,
	201	&mck_characteristics);
	202	if (IS_ERR(hw))
	203	goto err_free;
	204
	205	at91sam9x5_pmc->chws[PMC_MCK] = hw;
	206
	207	parent_names[0] = "plladivck";
	208	parent_names[1] = "utmick";
	209	hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
	210	if (IS_ERR(hw))
	211	goto err_free;
	212
	213	hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
	214	if (IS_ERR(hw))
	215	goto err_free;
	216
	217	parent_names[0] = slck_name;
	218	parent_names[1] = "mainck";
	219	parent_names[2] = "plladivck";
	220	parent_names[3] = "utmick";
65a91e2e	221	parent_names[4] = "masterck";
1eabdc2f AB	222	for (i = 0; i < 2; i++) {
	223	char name[6];
	224
	225	snprintf(name, sizeof(name), "prog%d", i);
	226
	227	hw = at91_clk_register_programmable(regmap, name,
	228	parent_names, 5, i,
c57aaaa2 CB	229	&at91sam9x5_programmable_layout,
c57aaaa2 CB	230	NULL);
1eabdc2f AB	231	if (IS_ERR(hw))
1eabdc2f AB	232	goto err_free;
99767cd4 MM	233
99767cd4 MM	234	at91sam9x5_pmc->pchws[i] = hw;
1eabdc2f AB	235	}
	236
	237	for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
	238	hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
	239	at91sam9x5_systemck[i].p,
	240	at91sam9x5_systemck[i].id);
	241	if (IS_ERR(hw))
	242	goto err_free;
	243
	244	at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
	245	}
	246
	247	if (has_lcdck) {
	248	hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3);
	249	if (IS_ERR(hw))
	250	goto err_free;
	251
	252	at91sam9x5_pmc->shws[3] = hw;
	253	}
	254
	255	for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
	256	hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
cb4f4949	257	&at91sam9x5_pcr_layout,
1eabdc2f AB	258	at91sam9x5_periphck[i].n,
	259	"masterck",
	260	at91sam9x5_periphck[i].id,
b4c115c7	261	&range, INT_MIN);
1eabdc2f AB	262	if (IS_ERR(hw))
	263	goto err_free;
	264
	265	at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
	266	}
	267
	268	for (i = 0; extra_pcks[i].id; i++) {
	269	hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
cb4f4949	270	&at91sam9x5_pcr_layout,
1eabdc2f AB	271	extra_pcks[i].n,
	272	"masterck",
	273	extra_pcks[i].id,
b4c115c7	274	&range, INT_MIN);
1eabdc2f AB	275	if (IS_ERR(hw))
	276	goto err_free;
	277
	278	at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
	279	}
	280
	281	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
	282
	283	return;
	284
	285	err_free:
7425f246	286	kfree(at91sam9x5_pmc);
1eabdc2f AB	287	}
	288
	289	static void __init at91sam9g15_pmc_setup(struct device_node *np)
	290	{
	291	at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
	292	}
	293	CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
	294	at91sam9g15_pmc_setup);
	295
	296	static void __init at91sam9g25_pmc_setup(struct device_node *np)
	297	{
	298	at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
	299	}
	300	CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
	301	at91sam9g25_pmc_setup);
	302
	303	static void __init at91sam9g35_pmc_setup(struct device_node *np)
	304	{
	305	at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
	306	}
	307	CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
	308	at91sam9g35_pmc_setup);
	309
	310	static void __init at91sam9x25_pmc_setup(struct device_node *np)
	311	{
	312	at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
	313	}
	314	CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
	315	at91sam9x25_pmc_setup);
	316
	317	static void __init at91sam9x35_pmc_setup(struct device_node *np)
	318	{
	319	at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
	320	}
	321	CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
	322	at91sam9x35_pmc_setup);