[mirror_ubuntu-eoan-kernel.git] / drivers / clk / at91 / clk-pll.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/at91_pmc.h>
#include <linux/of.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include "pmc.h"

#define PLL_STATUS_MASK(id)	(1 << (1 + (id)))
#define PLL_REG(id)		(AT91_CKGR_PLLAR + ((id) * 4))
#define PLL_DIV_MASK		0xff
#define PLL_DIV_MAX		PLL_DIV_MASK
#define PLL_DIV(reg)		((reg) & PLL_DIV_MASK)
#define PLL_MUL(reg, layout)	(((reg) >> (layout)->mul_shift) & \
				 (layout)->mul_mask)
#define PLL_MUL_MIN		2
#define PLL_MUL_MASK(layout)	((layout)->mul_mask)
#define PLL_MUL_MAX(layout)	(PLL_MUL_MASK(layout) + 1)
#define PLL_ICPR_SHIFT(id)	((id) * 16)
#define PLL_ICPR_MASK(id)	(0xffff << PLL_ICPR_SHIFT(id))
#define PLL_MAX_COUNT		0x3f
#define PLL_COUNT_SHIFT		8
#define PLL_OUT_SHIFT		14
#define PLL_MAX_ID		1

#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)

struct clk_pll {
	struct clk_hw hw;
	struct regmap *regmap;
	u8 id;
	u8 div;
	u8 range;
	u16 mul;
	const struct clk_pll_layout *layout;
	const struct clk_pll_characteristics *characteristics;
};

static inline bool clk_pll_ready(struct regmap *regmap, int id)
{
	unsigned int status;

	regmap_read(regmap, AT91_PMC_SR, &status);

	return status & PLL_STATUS_MASK(id) ? 1 : 0;
}

static int clk_pll_prepare(struct clk_hw *hw)
{
	struct clk_pll *pll = to_clk_pll(hw);
	struct regmap *regmap = pll->regmap;
	const struct clk_pll_layout *layout = pll->layout;
	const struct clk_pll_characteristics *characteristics =
							pll->characteristics;
	u8 id = pll->id;
	u32 mask = PLL_STATUS_MASK(id);
	int offset = PLL_REG(id);
	u8 out = 0;
	unsigned int pllr;
	unsigned int status;
	u8 div;
	u16 mul;

	regmap_read(regmap, offset, &pllr);
	div = PLL_DIV(pllr);
	mul = PLL_MUL(pllr, layout);

	regmap_read(regmap, AT91_PMC_SR, &status);
	if ((status & mask) &&
	    (div == pll->div && mul == pll->mul))
		return 0;

	if (characteristics->out)
		out = characteristics->out[pll->range];

	if (characteristics->icpll)
		regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
			characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));

	regmap_update_bits(regmap, offset, layout->pllr_mask,
			pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
			(out << PLL_OUT_SHIFT) |
			((pll->mul & layout->mul_mask) << layout->mul_shift));

	while (!clk_pll_ready(regmap, pll->id))
		cpu_relax();

	return 0;
}

static int clk_pll_is_prepared(struct clk_hw *hw)
{
	struct clk_pll *pll = to_clk_pll(hw);

	return clk_pll_ready(pll->regmap, pll->id);
}

static void clk_pll_unprepare(struct clk_hw *hw)
{
	struct clk_pll *pll = to_clk_pll(hw);
	unsigned int mask = pll->layout->pllr_mask;

	regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
}

static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
					 unsigned long parent_rate)
{
	struct clk_pll *pll = to_clk_pll(hw);

	if (!pll->div || !pll->mul)
		return 0;

	return (parent_rate / pll->div) * (pll->mul + 1);
}

static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
				     unsigned long parent_rate,
				     u32 *div, u32 *mul,
				     u32 *index) {
	const struct clk_pll_layout *layout = pll->layout;
	const struct clk_pll_characteristics *characteristics =
							pll->characteristics;
	unsigned long bestremainder = ULONG_MAX;
	unsigned long maxdiv, mindiv, tmpdiv;
	long bestrate = -ERANGE;
	unsigned long bestdiv;
	unsigned long bestmul;
	int i = 0;

	/* Check if parent_rate is a valid input rate */
	if (parent_rate < characteristics->input.min)
		return -ERANGE;

	/*
	 * Calculate minimum divider based on the minimum multiplier, the
	 * parent_rate and the requested rate.
	 * Should always be 2 according to the input and output characteristics
	 * of the PLL blocks.
	 */
	mindiv = (parent_rate * PLL_MUL_MIN) / rate;
	if (!mindiv)
		mindiv = 1;

	if (parent_rate > characteristics->input.max) {
		tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
		if (tmpdiv > PLL_DIV_MAX)
			return -ERANGE;

		if (tmpdiv > mindiv)
			mindiv = tmpdiv;
	}

	/*
	 * Calculate the maximum divider which is limited by PLL register
	 * layout (limited by the MUL or DIV field size).
	 */
	maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
	if (maxdiv > PLL_DIV_MAX)
		maxdiv = PLL_DIV_MAX;

	/*
	 * Iterate over the acceptable divider values to find the best
	 * divider/multiplier pair (the one that generates the closest
	 * rate to the requested one).
	 */
	for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
		unsigned long remainder;
		unsigned long tmprate;
		unsigned long tmpmul;

		/*
		 * Calculate the multiplier associated with the current
		 * divider that provide the closest rate to the requested one.
		 */
		tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
		tmprate = (parent_rate / tmpdiv) * tmpmul;
		if (tmprate > rate)
			remainder = tmprate - rate;
		else
			remainder = rate - tmprate;

		/*
		 * Compare the remainder with the best remainder found until
		 * now and elect a new best multiplier/divider pair if the
		 * current remainder is smaller than the best one.
		 */
		if (remainder < bestremainder) {
			bestremainder = remainder;
			bestdiv = tmpdiv;
			bestmul = tmpmul;
			bestrate = tmprate;
		}

		/*
		 * We've found a perfect match!
		 * Stop searching now and use this multiplier/divider pair.
		 */
		if (!remainder)
			break;
	}

	/* We haven't found any multiplier/divider pair => return -ERANGE */
	if (bestrate < 0)
		return bestrate;

	/* Check if bestrate is a valid output rate  */
	for (i = 0; i < characteristics->num_output; i++) {
		if (bestrate >= characteristics->output[i].min &&
		    bestrate <= characteristics->output[i].max)
			break;
	}

	if (i >= characteristics->num_output)
		return -ERANGE;

	if (div)
		*div = bestdiv;
	if (mul)
		*mul = bestmul - 1;
	if (index)
		*index = i;

	return bestrate;
}

static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
					unsigned long *parent_rate)
{
	struct clk_pll *pll = to_clk_pll(hw);

	return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
					NULL, NULL, NULL);
}

static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
			    unsigned long parent_rate)
{
	struct clk_pll *pll = to_clk_pll(hw);
	long ret;
	u32 div;
	u32 mul;
	u32 index;

	ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
				       &div, &mul, &index);
	if (ret < 0)
		return ret;

	pll->range = index;
	pll->div = div;
	pll->mul = mul;

	return 0;
}

static const struct clk_ops pll_ops = {
	.prepare = clk_pll_prepare,
	.unprepare = clk_pll_unprepare,
	.is_prepared = clk_pll_is_prepared,
	.recalc_rate = clk_pll_recalc_rate,
	.round_rate = clk_pll_round_rate,
	.set_rate = clk_pll_set_rate,
};

struct clk_hw * __init
at91_clk_register_pll(struct regmap *regmap, const char *name,
		      const char *parent_name, u8 id,
		      const struct clk_pll_layout *layout,
		      const struct clk_pll_characteristics *characteristics)
{
	struct clk_pll *pll;
	struct clk_hw *hw;
	struct clk_init_data init;
	int offset = PLL_REG(id);
	unsigned int pllr;
	int ret;

	if (id > PLL_MAX_ID)
		return ERR_PTR(-EINVAL);

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (!pll)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &pll_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = CLK_SET_RATE_GATE;

	pll->id = id;
	pll->hw.init = &init;
	pll->layout = layout;
	pll->characteristics = characteristics;
	pll->regmap = regmap;
	regmap_read(regmap, offset, &pllr);
	pll->div = PLL_DIV(pllr);
	pll->mul = PLL_MUL(pllr, layout);

	hw = &pll->hw;
	ret = clk_hw_register(NULL, &pll->hw);
	if (ret) {
		kfree(pll);
		hw = ERR_PTR(ret);
	}

	return hw;
}


const struct clk_pll_layout at91rm9200_pll_layout = {
	.pllr_mask = 0x7FFFFFF,
	.mul_shift = 16,
	.mul_mask = 0x7FF,
};

const struct clk_pll_layout at91sam9g45_pll_layout = {
	.pllr_mask = 0xFFFFFF,
	.mul_shift = 16,
	.mul_mask = 0xFF,
};

const struct clk_pll_layout at91sam9g20_pllb_layout = {
	.pllr_mask = 0x3FFFFF,
	.mul_shift = 16,
	.mul_mask = 0x3F,
};

const struct clk_pll_layout sama5d3_pll_layout = {
	.pllr_mask = 0x1FFFFFF,
	.mul_shift = 18,
	.mul_mask = 0x7F,
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
1a748d2b BB	2	/*
1a748d2b BB	3	* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
1a748d2b BB	4	*/
	5
	6	#include <linux/clk-provider.h>
	7	#include <linux/clkdev.h>
	8	#include <linux/clk/at91_pmc.h>
	9	#include <linux/of.h>
1bdf0232 BB	10	#include <linux/mfd/syscon.h>
1bdf0232 BB	11	#include <linux/regmap.h>
1a748d2b BB	12
	13	#include "pmc.h"
	14
	15	#define PLL_STATUS_MASK(id) (1 << (1 + (id)))
	16	#define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
	17	#define PLL_DIV_MASK 0xff
	18	#define PLL_DIV_MAX PLL_DIV_MASK
	19	#define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
	20	#define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
	21	(layout)->mul_mask)
3ef9dd2b BB	22	#define PLL_MUL_MIN 2
	23	#define PLL_MUL_MASK(layout) ((layout)->mul_mask)
	24	#define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
1a748d2b BB	25	#define PLL_ICPR_SHIFT(id) ((id) * 16)
1a748d2b BB	26	#define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
078a3eb5	27	#define PLL_MAX_COUNT 0x3f
1a748d2b BB	28	#define PLL_COUNT_SHIFT 8
	29	#define PLL_OUT_SHIFT 14
	30	#define PLL_MAX_ID 1
	31
1a748d2b BB	32	#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
	33
	34	struct clk_pll {
	35	struct clk_hw hw;
1bdf0232	36	struct regmap *regmap;
1a748d2b BB	37	u8 id;
	38	u8 div;
	39	u8 range;
	40	u16 mul;
	41	const struct clk_pll_layout *layout;
	42	const struct clk_pll_characteristics *characteristics;
	43	};
	44
1bdf0232 BB	45	static inline bool clk_pll_ready(struct regmap *regmap, int id)
	46	{
	47	unsigned int status;
	48
	49	regmap_read(regmap, AT91_PMC_SR, &status);
	50
	51	return status & PLL_STATUS_MASK(id) ? 1 : 0;
	52	}
	53
1a748d2b BB	54	static int clk_pll_prepare(struct clk_hw *hw)
	55	{
	56	struct clk_pll *pll = to_clk_pll(hw);
1bdf0232	57	struct regmap *regmap = pll->regmap;
1a748d2b	58	const struct clk_pll_layout *layout = pll->layout;
e442d234 BB	59	const struct clk_pll_characteristics *characteristics =
e442d234 BB	60	pll->characteristics;
1a748d2b BB	61	u8 id = pll->id;
	62	u32 mask = PLL_STATUS_MASK(id);
	63	int offset = PLL_REG(id);
	64	u8 out = 0;
1bdf0232 BB	65	unsigned int pllr;
1bdf0232 BB	66	unsigned int status;
1a748d2b BB	67	u8 div;
	68	u16 mul;
	69
1bdf0232	70	regmap_read(regmap, offset, &pllr);
1a748d2b BB	71	div = PLL_DIV(pllr);
	72	mul = PLL_MUL(pllr, layout);
	73
1bdf0232 BB	74	regmap_read(regmap, AT91_PMC_SR, &status);
1bdf0232 BB	75	if ((status & mask) &&
1a748d2b BB	76	(div == pll->div && mul == pll->mul))
	77	return 0;
	78
	79	if (characteristics->out)
	80	out = characteristics->out[pll->range];
1a748d2b	81
1bdf0232 BB	82	if (characteristics->icpll)
	83	regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
	84	characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));
1a748d2b	85
1bdf0232 BB	86	regmap_update_bits(regmap, offset, layout->pllr_mask,
	87	pll->div \| (PLL_MAX_COUNT << PLL_COUNT_SHIFT) \|
	88	(out << PLL_OUT_SHIFT) \|
	89	((pll->mul & layout->mul_mask) << layout->mul_shift));
	90
99a81706 AB	91	while (!clk_pll_ready(regmap, pll->id))
99a81706 AB	92	cpu_relax();
1a748d2b BB	93
	94	return 0;
	95	}
	96
	97	static int clk_pll_is_prepared(struct clk_hw *hw)
	98	{
	99	struct clk_pll *pll = to_clk_pll(hw);
1a748d2b	100
1bdf0232	101	return clk_pll_ready(pll->regmap, pll->id);
1a748d2b BB	102	}
	103
	104	static void clk_pll_unprepare(struct clk_hw *hw)
	105	{
	106	struct clk_pll *pll = to_clk_pll(hw);
1bdf0232	107	unsigned int mask = pll->layout->pllr_mask;
1a748d2b	108
1bdf0232	109	regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
1a748d2b BB	110	}
	111
	112	static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
	113	unsigned long parent_rate)
	114	{
	115	struct clk_pll *pll = to_clk_pll(hw);
1a748d2b	116
0f5cb0e6 RW	117	if (!pll->div \|\| !pll->mul)
	118	return 0;
	119
a982e45d	120	return (parent_rate / pll->div) * (pll->mul + 1);
1a748d2b BB	121	}
	122
	123	static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
	124	unsigned long parent_rate,
	125	u32 div, u32 mul,
	126	u32 *index) {
1a748d2b BB	127	const struct clk_pll_layout *layout = pll->layout;
	128	const struct clk_pll_characteristics *characteristics =
	129	pll->characteristics;
3ef9dd2b BB	130	unsigned long bestremainder = ULONG_MAX;
	131	unsigned long maxdiv, mindiv, tmpdiv;
	132	long bestrate = -ERANGE;
	133	unsigned long bestdiv;
	134	unsigned long bestmul;
	135	int i = 0;
1a748d2b	136
3ef9dd2b	137	/* Check if parent_rate is a valid input rate */
6c7b03e1	138	if (parent_rate < characteristics->input.min)
1a748d2b BB	139	return -ERANGE;
1a748d2b BB	140
3ef9dd2b BB	141	/*
	142	* Calculate minimum divider based on the minimum multiplier, the
	143	* parent_rate and the requested rate.
	144	* Should always be 2 according to the input and output characteristics
	145	* of the PLL blocks.
	146	*/
	147	mindiv = (parent_rate * PLL_MUL_MIN) / rate;
	148	if (!mindiv)
	149	mindiv = 1;
	150
6c7b03e1 BB	151	if (parent_rate > characteristics->input.max) {
	152	tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
	153	if (tmpdiv > PLL_DIV_MAX)
	154	return -ERANGE;
	155
	156	if (tmpdiv > mindiv)
	157	mindiv = tmpdiv;
	158	}
	159
3ef9dd2b BB	160	/*
	161	* Calculate the maximum divider which is limited by PLL register
	162	* layout (limited by the MUL or DIV field size).
	163	*/
	164	maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
	165	if (maxdiv > PLL_DIV_MAX)
	166	maxdiv = PLL_DIV_MAX;
	167
	168	/*
	169	* Iterate over the acceptable divider values to find the best
	170	* divider/multiplier pair (the one that generates the closest
	171	* rate to the requested one).
	172	*/
	173	for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
	174	unsigned long remainder;
	175	unsigned long tmprate;
	176	unsigned long tmpmul;
	177
	178	/*
	179	* Calculate the multiplier associated with the current
	180	* divider that provide the closest rate to the requested one.
	181	*/
	182	tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
	183	tmprate = (parent_rate / tmpdiv) * tmpmul;
	184	if (tmprate > rate)
	185	remainder = tmprate - rate;
	186	else
	187	remainder = rate - tmprate;
	188
	189	/*
	190	* Compare the remainder with the best remainder found until
	191	* now and elect a new best multiplier/divider pair if the
	192	* current remainder is smaller than the best one.
	193	*/
1a748d2b BB	194	if (remainder < bestremainder) {
1a748d2b BB	195	bestremainder = remainder;
1a748d2b	196	bestdiv = tmpdiv;
3ef9dd2b BB	197	bestmul = tmpmul;
3ef9dd2b BB	198	bestrate = tmprate;
1a748d2b BB	199	}
1a748d2b BB	200
3ef9dd2b BB	201	/*
	202	* We've found a perfect match!
	203	* Stop searching now and use this multiplier/divider pair.
	204	*/
1a748d2b BB	205	if (!remainder)
	206	break;
	207	}
	208
3ef9dd2b BB	209	/* We haven't found any multiplier/divider pair => return -ERANGE */
	210	if (bestrate < 0)
	211	return bestrate;
	212
	213	/* Check if bestrate is a valid output rate */
	214	for (i = 0; i < characteristics->num_output; i++) {
	215	if (bestrate >= characteristics->output[i].min &&
	216	bestrate <= characteristics->output[i].max)
	217	break;
	218	}
	219
	220	if (i >= characteristics->num_output)
	221	return -ERANGE;
1a748d2b BB	222
	223	if (div)
	224	*div = bestdiv;
	225	if (mul)
3ef9dd2b	226	*mul = bestmul - 1;
1a748d2b BB	227	if (index)
	228	*index = i;
	229
3ef9dd2b	230	return bestrate;
1a748d2b BB	231	}
	232
	233	static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
	234	unsigned long *parent_rate)
	235	{
	236	struct clk_pll *pll = to_clk_pll(hw);
	237
	238	return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
	239	NULL, NULL, NULL);
	240	}
	241
	242	static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
	243	unsigned long parent_rate)
	244	{
	245	struct clk_pll *pll = to_clk_pll(hw);
1a748d2b BB	246	long ret;
	247	u32 div;
	248	u32 mul;
	249	u32 index;
1a748d2b BB	250
	251	ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
	252	&div, &mul, &index);
	253	if (ret < 0)
	254	return ret;
	255
	256	pll->range = index;
	257	pll->div = div;
	258	pll->mul = mul;
	259
	260	return 0;
	261	}
	262
	263	static const struct clk_ops pll_ops = {
	264	.prepare = clk_pll_prepare,
	265	.unprepare = clk_pll_unprepare,
	266	.is_prepared = clk_pll_is_prepared,
	267	.recalc_rate = clk_pll_recalc_rate,
	268	.round_rate = clk_pll_round_rate,
	269	.set_rate = clk_pll_set_rate,
	270	};
	271
b2e39dc0	272	struct clk_hw * __init
99a81706	273	at91_clk_register_pll(struct regmap regmap, const char name,
1a748d2b BB	274	const char *parent_name, u8 id,
	275	const struct clk_pll_layout *layout,
	276	const struct clk_pll_characteristics *characteristics)
	277	{
	278	struct clk_pll *pll;
f5644f10	279	struct clk_hw *hw;
1a748d2b	280	struct clk_init_data init;
1a748d2b	281	int offset = PLL_REG(id);
1bdf0232	282	unsigned int pllr;
f5644f10	283	int ret;
1a748d2b BB	284
	285	if (id > PLL_MAX_ID)
	286	return ERR_PTR(-EINVAL);
	287
	288	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	289	if (!pll)
	290	return ERR_PTR(-ENOMEM);
	291
	292	init.name = name;
	293	init.ops = &pll_ops;
	294	init.parent_names = &parent_name;
	295	init.num_parents = 1;
	296	init.flags = CLK_SET_RATE_GATE;
	297
	298	pll->id = id;
	299	pll->hw.init = &init;
	300	pll->layout = layout;
	301	pll->characteristics = characteristics;
1bdf0232	302	pll->regmap = regmap;
1bdf0232 BB	303	regmap_read(regmap, offset, &pllr);
	304	pll->div = PLL_DIV(pllr);
	305	pll->mul = PLL_MUL(pllr, layout);
1a748d2b	306
f5644f10 SB	307	hw = &pll->hw;
	308	ret = clk_hw_register(NULL, &pll->hw);
	309	if (ret) {
1a748d2b	310	kfree(pll);
f5644f10	311	hw = ERR_PTR(ret);
c76a024e	312	}
1a748d2b	313
f5644f10	314	return hw;
1a748d2b BB	315	}
	316
	317
b2e39dc0	318	const struct clk_pll_layout at91rm9200_pll_layout = {
1a748d2b BB	319	.pllr_mask = 0x7FFFFFF,
	320	.mul_shift = 16,
	321	.mul_mask = 0x7FF,
	322	};
	323
b2e39dc0	324	const struct clk_pll_layout at91sam9g45_pll_layout = {
1a748d2b BB	325	.pllr_mask = 0xFFFFFF,
	326	.mul_shift = 16,
	327	.mul_mask = 0xFF,
	328	};
	329
b2e39dc0	330	const struct clk_pll_layout at91sam9g20_pllb_layout = {
1a748d2b BB	331	.pllr_mask = 0x3FFFFF,
	332	.mul_shift = 16,
	333	.mul_mask = 0x3F,
	334	};
	335
b2e39dc0	336	const struct clk_pll_layout sama5d3_pll_layout = {
1a748d2b BB	337	.pllr_mask = 0x1FFFFFF,
	338	.mul_shift = 18,
	339	.mul_mask = 0x7F,
	340	};