[mirror_ubuntu-jammy-kernel.git] / drivers / clk / at91 / pmc.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * drivers/clk/at91/pmc.h
 *
 *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 */

#ifndef __PMC_H_
#define __PMC_H_

#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>

extern spinlock_t pmc_pcr_lock;

struct pmc_data {
	unsigned int ncore;
	struct clk_hw **chws;
	unsigned int nsystem;
	struct clk_hw **shws;
	unsigned int nperiph;
	struct clk_hw **phws;
	unsigned int ngck;
	struct clk_hw **ghws;
	unsigned int npck;
	struct clk_hw **pchws;

	struct clk_hw *hwtable[];
};

struct clk_range {
	unsigned long min;
	unsigned long max;
};

#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}

struct clk_master_layout {
	u32 offset;
	u32 mask;
	u8 pres_shift;
};

extern const struct clk_master_layout at91rm9200_master_layout;
extern const struct clk_master_layout at91sam9x5_master_layout;

struct clk_master_characteristics {
	struct clk_range output;
	u32 divisors[4];
	u8 have_div3_pres;
};

struct clk_pll_layout {
	u32 pllr_mask;
	u32 mul_mask;
	u32 frac_mask;
	u32 div_mask;
	u32 endiv_mask;
	u8 mul_shift;
	u8 frac_shift;
	u8 div_shift;
	u8 endiv_shift;
};

extern const struct clk_pll_layout at91rm9200_pll_layout;
extern const struct clk_pll_layout at91sam9g45_pll_layout;
extern const struct clk_pll_layout at91sam9g20_pllb_layout;
extern const struct clk_pll_layout sama5d3_pll_layout;

struct clk_pll_characteristics {
	struct clk_range input;
	int num_output;
	const struct clk_range *output;
	u16 *icpll;
	u8 *out;
	u8 upll : 1;
};

struct clk_programmable_layout {
	u8 pres_mask;
	u8 pres_shift;
	u8 css_mask;
	u8 have_slck_mck;
	u8 is_pres_direct;
};

extern const struct clk_programmable_layout at91rm9200_programmable_layout;
extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
extern const struct clk_programmable_layout at91sam9x5_programmable_layout;

struct clk_pcr_layout {
	u32 offset;
	u32 cmd;
	u32 div_mask;
	u32 gckcss_mask;
	u32 pid_mask;
};

#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))

#define ndck(a, s) (a[s - 1].id + 1)
#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
				   unsigned int nperiph, unsigned int ngck,
				   unsigned int npck);

int of_at91_get_clk_range(struct device_node *np, const char *propname,
			  struct clk_range *range);

struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);

struct clk_hw * __init
at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
				 const char *parent_name);

struct clk_hw * __init
at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
				const char *parent_name);

struct clk_hw * __init
at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
				const char *parent_name);

struct clk_hw * __init
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
			    const struct clk_pcr_layout *layout,
			    const char *name, const char **parent_names,
			    u32 *mux_table, u8 num_parents, u8 id,
			    const struct clk_range *range, int chg_pid);

struct clk_hw * __init
at91_clk_register_h32mx(struct regmap *regmap, const char *name,
			const char *parent_name);

struct clk_hw * __init
at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
			  const char * const *parent_names,
			  unsigned int num_parents, u8 bus_id);

struct clk_hw * __init
at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
			      u32 frequency, u32 accuracy);
struct clk_hw * __init
at91_clk_register_main_osc(struct regmap *regmap, const char *name,
			   const char *parent_name, bool bypass);
struct clk_hw * __init
at91_clk_register_rm9200_main(struct regmap *regmap,
			      const char *name,
			      const char *parent_name);
struct clk_hw * __init
at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
			      const char **parent_names, int num_parents);

struct clk_hw * __init
at91_clk_register_master(struct regmap *regmap, const char *name,
			 int num_parents, const char **parent_names,
			 const struct clk_master_layout *layout,
			 const struct clk_master_characteristics *characteristics);

struct clk_hw * __init
at91_clk_sama7g5_register_master(struct regmap *regmap,
				 const char *name, int num_parents,
				 const char **parent_names, u32 *mux_table,
				 spinlock_t *lock, u8 id, bool critical,
				 int chg_pid);

struct clk_hw * __init
at91_clk_register_peripheral(struct regmap *regmap, const char *name,
			     const char *parent_name, u32 id);
struct clk_hw * __init
at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
				    const struct clk_pcr_layout *layout,
				    const char *name, const char *parent_name,
				    u32 id, const struct clk_range *range,
				    int chg_pid);

struct clk_hw * __init
at91_clk_register_pll(struct regmap *regmap, const char *name,
		      const char *parent_name, u8 id,
		      const struct clk_pll_layout *layout,
		      const struct clk_pll_characteristics *characteristics);
struct clk_hw * __init
at91_clk_register_plldiv(struct regmap *regmap, const char *name,
			 const char *parent_name);

struct clk_hw * __init
sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
			     const char *name, const char *parent_name, u8 id,
			     const struct clk_pll_characteristics *characteristics,
			     const struct clk_pll_layout *layout, bool critical);

struct clk_hw * __init
sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
			      const char *name, const char *parent_name,
			      struct clk_hw *parent_hw, u8 id,
			      const struct clk_pll_characteristics *characteristics,
			      const struct clk_pll_layout *layout, bool critical);

struct clk_hw * __init
at91_clk_register_programmable(struct regmap *regmap, const char *name,
			       const char **parent_names, u8 num_parents, u8 id,
			       const struct clk_programmable_layout *layout,
			       u32 *mux_table);

struct clk_hw * __init
at91_clk_register_sam9260_slow(struct regmap *regmap,
			       const char *name,
			       const char **parent_names,
			       int num_parents);

struct clk_hw * __init
at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
			    const char **parent_names, u8 num_parents);

struct clk_hw * __init
at91_clk_register_system(struct regmap *regmap, const char *name,
			 const char *parent_name, u8 id);

struct clk_hw * __init
at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
			    const char **parent_names, u8 num_parents);
struct clk_hw * __init
at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
			     const char *parent_name);
struct clk_hw * __init
sam9x60_clk_register_usb(struct regmap *regmap, const char *name,
			 const char **parent_names, u8 num_parents);
struct clk_hw * __init
at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
			    const char *parent_name, const u32 *divisors);

struct clk_hw * __init
at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
		       const char *name, const char *parent_name);

struct clk_hw * __init
at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
			       const char *parent_name);

#ifdef CONFIG_PM
void pmc_register_id(u8 id);
void pmc_register_pck(u8 pck);
#else
static inline void pmc_register_id(u8 id) {}
static inline void pmc_register_pck(u8 pck) {}
#endif

#endif /* __PMC_H_ */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
0ad6125b BB	2	/*
	3	* drivers/clk/at91/pmc.h
	4	*
	5	* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
0ad6125b BB	6	*/
	7
	8	#ifndef __PMC_H_
	9	#define __PMC_H_
	10
	11	#include <linux/io.h>
	12	#include <linux/irqdomain.h>
863a81c3	13	#include <linux/regmap.h>
0ad6125b BB	14	#include <linux/spinlock.h>
0ad6125b BB	15
1bdf0232 BB	16	extern spinlock_t pmc_pcr_lock;
1bdf0232 BB	17
b00cd8e4 AB	18	struct pmc_data {
	19	unsigned int ncore;
	20	struct clk_hw **chws;
	21	unsigned int nsystem;
	22	struct clk_hw **shws;
	23	unsigned int nperiph;
	24	struct clk_hw **phws;
	25	unsigned int ngck;
	26	struct clk_hw **ghws;
99767cd4 MM	27	unsigned int npck;
99767cd4 MM	28	struct clk_hw **pchws;
7425f246 MM	29
7425f246 MM	30	struct clk_hw *hwtable[];
b00cd8e4 AB	31	};
b00cd8e4 AB	32
0ad6125b BB	33	struct clk_range {
	34	unsigned long min;
	35	unsigned long max;
	36	};
	37
	38	#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
	39
b2e39dc0	40	struct clk_master_layout {
e5be5370	41	u32 offset;
b2e39dc0 AB	42	u32 mask;
	43	u8 pres_shift;
	44	};
	45
	46	extern const struct clk_master_layout at91rm9200_master_layout;
	47	extern const struct clk_master_layout at91sam9x5_master_layout;
	48
	49	struct clk_master_characteristics {
	50	struct clk_range output;
	51	u32 divisors[4];
	52	u8 have_div3_pres;
	53	};
	54
	55	struct clk_pll_layout {
	56	u32 pllr_mask;
43b1bb4a CB	57	u32 mul_mask;
	58	u32 frac_mask;
	59	u32 div_mask;
	60	u32 endiv_mask;
b2e39dc0	61	u8 mul_shift;
43b1bb4a CB	62	u8 frac_shift;
	63	u8 div_shift;
	64	u8 endiv_shift;
b2e39dc0 AB	65	};
	66
	67	extern const struct clk_pll_layout at91rm9200_pll_layout;
	68	extern const struct clk_pll_layout at91sam9g45_pll_layout;
	69	extern const struct clk_pll_layout at91sam9g20_pllb_layout;
	70	extern const struct clk_pll_layout sama5d3_pll_layout;
	71
	72	struct clk_pll_characteristics {
	73	struct clk_range input;
	74	int num_output;
7b4c162e	75	const struct clk_range *output;
b2e39dc0 AB	76	u16 *icpll;
b2e39dc0 AB	77	u8 *out;
a436c2a4	78	u8 upll : 1;
b2e39dc0 AB	79	};
	80
	81	struct clk_programmable_layout {
45b06682	82	u8 pres_mask;
b2e39dc0 AB	83	u8 pres_shift;
	84	u8 css_mask;
	85	u8 have_slck_mck;
45b06682	86	u8 is_pres_direct;
b2e39dc0 AB	87	};
	88
	89	extern const struct clk_programmable_layout at91rm9200_programmable_layout;
	90	extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
	91	extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
	92
cb4f4949 AB	93	struct clk_pcr_layout {
	94	u32 offset;
	95	u32 cmd;
	96	u32 div_mask;
	97	u32 gckcss_mask;
	98	u32 pid_mask;
	99	};
	100
	101	#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
	102	#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
	103
b00cd8e4 AB	104	#define ndck(a, s) (a[s - 1].id + 1)
	105	#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
	106	struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
99767cd4 MM	107	unsigned int nperiph, unsigned int ngck,
99767cd4 MM	108	unsigned int npck);
b00cd8e4	109
0ad6125b BB	110	int of_at91_get_clk_range(struct device_node np, const char propname,
	111	struct clk_range *range);
	112
b2e39dc0 AB	113	struct clk_hw of_clk_hw_pmc_get(struct of_phandle_args clkspec, void *data);
	114
	115	struct clk_hw * __init
	116	at91_clk_register_audio_pll_frac(struct regmap regmap, const char name,
	117	const char *parent_name);
	118
	119	struct clk_hw * __init
	120	at91_clk_register_audio_pll_pad(struct regmap regmap, const char name,
	121	const char *parent_name);
	122
	123	struct clk_hw * __init
	124	at91_clk_register_audio_pll_pmc(struct regmap regmap, const char name,
	125	const char *parent_name);
	126
	127	struct clk_hw * __init
	128	at91_clk_register_generated(struct regmap regmap, spinlock_t lock,
e4cfb823	129	const struct clk_pcr_layout *layout,
b2e39dc0	130	const char name, const char *parent_names,
22a1dfe9	131	u32 *mux_table, u8 num_parents, u8 id,
64c9247b	132	const struct clk_range *range, int chg_pid);
b2e39dc0 AB	133
	134	struct clk_hw * __init
	135	at91_clk_register_h32mx(struct regmap regmap, const char name,
	136	const char *parent_name);
	137
	138	struct clk_hw * __init
	139	at91_clk_i2s_mux_register(struct regmap regmap, const char name,
	140	const char * const *parent_names,
	141	unsigned int num_parents, u8 bus_id);
	142
	143	struct clk_hw * __init
	144	at91_clk_register_main_rc_osc(struct regmap regmap, const char name,
	145	u32 frequency, u32 accuracy);
	146	struct clk_hw * __init
	147	at91_clk_register_main_osc(struct regmap regmap, const char name,
	148	const char *parent_name, bool bypass);
	149	struct clk_hw * __init
	150	at91_clk_register_rm9200_main(struct regmap *regmap,
	151	const char *name,
	152	const char *parent_name);
	153	struct clk_hw * __init
	154	at91_clk_register_sam9x5_main(struct regmap regmap, const char name,
	155	const char **parent_names, int num_parents);
	156
	157	struct clk_hw * __init
	158	at91_clk_register_master(struct regmap regmap, const char name,
	159	int num_parents, const char **parent_names,
	160	const struct clk_master_layout *layout,
	161	const struct clk_master_characteristics *characteristics);
	162
75c88143 CB	163	struct clk_hw * __init
	164	at91_clk_sama7g5_register_master(struct regmap *regmap,
	165	const char *name, int num_parents,
	166	const char *parent_names, u32 mux_table,
	167	spinlock_t *lock, u8 id, bool critical,
	168	int chg_pid);
	169
b2e39dc0 AB	170	struct clk_hw * __init
	171	at91_clk_register_peripheral(struct regmap regmap, const char name,
	172	const char *parent_name, u32 id);
	173	struct clk_hw * __init
	174	at91_clk_register_sam9x5_peripheral(struct regmap regmap, spinlock_t lock,
cb4f4949	175	const struct clk_pcr_layout *layout,
b2e39dc0	176	const char name, const char parent_name,
b4c115c7 CB	177	u32 id, const struct clk_range *range,
b4c115c7 CB	178	int chg_pid);
b2e39dc0 AB	179
	180	struct clk_hw * __init
	181	at91_clk_register_pll(struct regmap regmap, const char name,
	182	const char *parent_name, u8 id,
	183	const struct clk_pll_layout *layout,
	184	const struct clk_pll_characteristics *characteristics);
	185	struct clk_hw * __init
	186	at91_clk_register_plldiv(struct regmap regmap, const char name,
	187	const char *parent_name);
	188
a436c2a4	189	struct clk_hw * __init
43b1bb4a CB	190	sam9x60_clk_register_div_pll(struct regmap regmap, spinlock_t lock,
	191	const char name, const char parent_name, u8 id,
	192	const struct clk_pll_characteristics *characteristics,
	193	const struct clk_pll_layout *layout, bool critical);
	194
	195	struct clk_hw * __init
	196	sam9x60_clk_register_frac_pll(struct regmap regmap, spinlock_t lock,
	197	const char name, const char parent_name,
	198	struct clk_hw *parent_hw, u8 id,
	199	const struct clk_pll_characteristics *characteristics,
	200	const struct clk_pll_layout *layout, bool critical);
a436c2a4	201
b2e39dc0 AB	202	struct clk_hw * __init
	203	at91_clk_register_programmable(struct regmap regmap, const char name,
	204	const char **parent_names, u8 num_parents, u8 id,
c57aaaa2 CB	205	const struct clk_programmable_layout *layout,
c57aaaa2 CB	206	u32 *mux_table);
b2e39dc0 AB	207
	208	struct clk_hw * __init
	209	at91_clk_register_sam9260_slow(struct regmap *regmap,
	210	const char *name,
	211	const char **parent_names,
	212	int num_parents);
	213
	214	struct clk_hw * __init
	215	at91sam9x5_clk_register_smd(struct regmap regmap, const char name,
	216	const char **parent_names, u8 num_parents);
	217
	218	struct clk_hw * __init
	219	at91_clk_register_system(struct regmap regmap, const char name,
	220	const char *parent_name, u8 id);
	221
	222	struct clk_hw * __init
	223	at91sam9x5_clk_register_usb(struct regmap regmap, const char name,
	224	const char **parent_names, u8 num_parents);
	225	struct clk_hw * __init
	226	at91sam9n12_clk_register_usb(struct regmap regmap, const char name,
	227	const char *parent_name);
	228	struct clk_hw * __init
2423eeae AB	229	sam9x60_clk_register_usb(struct regmap regmap, const char name,
	230	const char **parent_names, u8 num_parents);
	231	struct clk_hw * __init
b2e39dc0 AB	232	at91rm9200_clk_register_usb(struct regmap regmap, const char name,
	233	const char parent_name, const u32 divisors);
	234
	235	struct clk_hw * __init
	236	at91_clk_register_utmi(struct regmap regmap_pmc, struct regmap regmap_sfr,
	237	const char name, const char parent_name);
	238
ef396df9 CB	239	struct clk_hw * __init
	240	at91_clk_sama7g5_register_utmi(struct regmap regmap, const char name,
	241	const char *parent_name);
	242
b3b02eac AB	243	#ifdef CONFIG_PM
b3b02eac AB	244	void pmc_register_id(u8 id);
13967bea	245	void pmc_register_pck(u8 pck);
b3b02eac AB	246	#else
b3b02eac AB	247	static inline void pmc_register_id(u8 id) {}
13967bea	248	static inline void pmc_register_pck(u8 pck) {}
b3b02eac AB	249	#endif
b3b02eac AB	250
0ad6125b	251	#endif /* __PMC_H_ */