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75fabc3f | 1 | /* |
41691b88 | 2 | * Copyright (C) 2010,2015 Broadcom |
75fabc3f SA |
3 | * Copyright (C) 2012 Stephen Warren |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
75fabc3f SA |
15 | */ |
16 | ||
41691b88 EA |
17 | /** |
18 | * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) | |
19 | * | |
20 | * The clock tree on the 2835 has several levels. There's a root | |
21 | * oscillator running at 19.2Mhz. After the oscillator there are 5 | |
22 | * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", | |
23 | * and "HDMI displays". Those 5 PLLs each can divide their output to | |
24 | * produce up to 4 channels. Finally, there is the level of clocks to | |
25 | * be consumed by other hardware components (like "H264" or "HDMI | |
26 | * state machine"), which divide off of some subset of the PLL | |
27 | * channels. | |
28 | * | |
29 | * All of the clocks in the tree are exposed in the DT, because the DT | |
30 | * may want to make assignments of the final layer of clocks to the | |
31 | * PLL channels, and some components of the hardware will actually | |
32 | * skip layers of the tree (for example, the pixel clock comes | |
33 | * directly from the PLLH PIX channel without using a CM_*CTL clock | |
34 | * generator). | |
35 | */ | |
36 | ||
75fabc3f SA |
37 | #include <linux/clk-provider.h> |
38 | #include <linux/clkdev.h> | |
9e400c5c | 39 | #include <linux/clk.h> |
75fabc3f | 40 | #include <linux/clk/bcm2835.h> |
96bf9c69 | 41 | #include <linux/debugfs.h> |
41691b88 | 42 | #include <linux/module.h> |
526d239c | 43 | #include <linux/of.h> |
41691b88 EA |
44 | #include <linux/platform_device.h> |
45 | #include <linux/slab.h> | |
46 | #include <dt-bindings/clock/bcm2835.h> | |
47 | ||
48 | #define CM_PASSWORD 0x5a000000 | |
49 | ||
50 | #define CM_GNRICCTL 0x000 | |
51 | #define CM_GNRICDIV 0x004 | |
52 | # define CM_DIV_FRAC_BITS 12 | |
959ca92a | 53 | # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) |
41691b88 EA |
54 | |
55 | #define CM_VPUCTL 0x008 | |
56 | #define CM_VPUDIV 0x00c | |
57 | #define CM_SYSCTL 0x010 | |
58 | #define CM_SYSDIV 0x014 | |
59 | #define CM_PERIACTL 0x018 | |
60 | #define CM_PERIADIV 0x01c | |
61 | #define CM_PERIICTL 0x020 | |
62 | #define CM_PERIIDIV 0x024 | |
63 | #define CM_H264CTL 0x028 | |
64 | #define CM_H264DIV 0x02c | |
65 | #define CM_ISPCTL 0x030 | |
66 | #define CM_ISPDIV 0x034 | |
67 | #define CM_V3DCTL 0x038 | |
68 | #define CM_V3DDIV 0x03c | |
69 | #define CM_CAM0CTL 0x040 | |
70 | #define CM_CAM0DIV 0x044 | |
71 | #define CM_CAM1CTL 0x048 | |
72 | #define CM_CAM1DIV 0x04c | |
73 | #define CM_CCP2CTL 0x050 | |
74 | #define CM_CCP2DIV 0x054 | |
75 | #define CM_DSI0ECTL 0x058 | |
76 | #define CM_DSI0EDIV 0x05c | |
77 | #define CM_DSI0PCTL 0x060 | |
78 | #define CM_DSI0PDIV 0x064 | |
79 | #define CM_DPICTL 0x068 | |
80 | #define CM_DPIDIV 0x06c | |
81 | #define CM_GP0CTL 0x070 | |
82 | #define CM_GP0DIV 0x074 | |
83 | #define CM_GP1CTL 0x078 | |
84 | #define CM_GP1DIV 0x07c | |
85 | #define CM_GP2CTL 0x080 | |
86 | #define CM_GP2DIV 0x084 | |
87 | #define CM_HSMCTL 0x088 | |
88 | #define CM_HSMDIV 0x08c | |
89 | #define CM_OTPCTL 0x090 | |
90 | #define CM_OTPDIV 0x094 | |
2103a215 MS |
91 | #define CM_PCMCTL 0x098 |
92 | #define CM_PCMDIV 0x09c | |
41691b88 EA |
93 | #define CM_PWMCTL 0x0a0 |
94 | #define CM_PWMDIV 0x0a4 | |
2103a215 MS |
95 | #define CM_SLIMCTL 0x0a8 |
96 | #define CM_SLIMDIV 0x0ac | |
41691b88 EA |
97 | #define CM_SMICTL 0x0b0 |
98 | #define CM_SMIDIV 0x0b4 | |
2103a215 MS |
99 | /* no definition for 0x0b8 and 0x0bc */ |
100 | #define CM_TCNTCTL 0x0c0 | |
101 | #define CM_TCNTDIV 0x0c4 | |
102 | #define CM_TECCTL 0x0c8 | |
103 | #define CM_TECDIV 0x0cc | |
104 | #define CM_TD0CTL 0x0d0 | |
105 | #define CM_TD0DIV 0x0d4 | |
106 | #define CM_TD1CTL 0x0d8 | |
107 | #define CM_TD1DIV 0x0dc | |
41691b88 EA |
108 | #define CM_TSENSCTL 0x0e0 |
109 | #define CM_TSENSDIV 0x0e4 | |
110 | #define CM_TIMERCTL 0x0e8 | |
111 | #define CM_TIMERDIV 0x0ec | |
112 | #define CM_UARTCTL 0x0f0 | |
113 | #define CM_UARTDIV 0x0f4 | |
114 | #define CM_VECCTL 0x0f8 | |
115 | #define CM_VECDIV 0x0fc | |
116 | #define CM_PULSECTL 0x190 | |
117 | #define CM_PULSEDIV 0x194 | |
118 | #define CM_SDCCTL 0x1a8 | |
119 | #define CM_SDCDIV 0x1ac | |
120 | #define CM_ARMCTL 0x1b0 | |
d3d6f15f MS |
121 | #define CM_AVEOCTL 0x1b8 |
122 | #define CM_AVEODIV 0x1bc | |
41691b88 EA |
123 | #define CM_EMMCCTL 0x1c0 |
124 | #define CM_EMMCDIV 0x1c4 | |
125 | ||
126 | /* General bits for the CM_*CTL regs */ | |
127 | # define CM_ENABLE BIT(4) | |
128 | # define CM_KILL BIT(5) | |
129 | # define CM_GATE_BIT 6 | |
130 | # define CM_GATE BIT(CM_GATE_BIT) | |
131 | # define CM_BUSY BIT(7) | |
132 | # define CM_BUSYD BIT(8) | |
959ca92a | 133 | # define CM_FRAC BIT(9) |
41691b88 EA |
134 | # define CM_SRC_SHIFT 0 |
135 | # define CM_SRC_BITS 4 | |
136 | # define CM_SRC_MASK 0xf | |
137 | # define CM_SRC_GND 0 | |
138 | # define CM_SRC_OSC 1 | |
139 | # define CM_SRC_TESTDEBUG0 2 | |
140 | # define CM_SRC_TESTDEBUG1 3 | |
141 | # define CM_SRC_PLLA_CORE 4 | |
142 | # define CM_SRC_PLLA_PER 4 | |
143 | # define CM_SRC_PLLC_CORE0 5 | |
144 | # define CM_SRC_PLLC_PER 5 | |
145 | # define CM_SRC_PLLC_CORE1 8 | |
146 | # define CM_SRC_PLLD_CORE 6 | |
147 | # define CM_SRC_PLLD_PER 6 | |
148 | # define CM_SRC_PLLH_AUX 7 | |
149 | # define CM_SRC_PLLC_CORE1 8 | |
150 | # define CM_SRC_PLLC_CORE2 9 | |
151 | ||
152 | #define CM_OSCCOUNT 0x100 | |
153 | ||
154 | #define CM_PLLA 0x104 | |
155 | # define CM_PLL_ANARST BIT(8) | |
156 | # define CM_PLLA_HOLDPER BIT(7) | |
157 | # define CM_PLLA_LOADPER BIT(6) | |
158 | # define CM_PLLA_HOLDCORE BIT(5) | |
159 | # define CM_PLLA_LOADCORE BIT(4) | |
160 | # define CM_PLLA_HOLDCCP2 BIT(3) | |
161 | # define CM_PLLA_LOADCCP2 BIT(2) | |
162 | # define CM_PLLA_HOLDDSI0 BIT(1) | |
163 | # define CM_PLLA_LOADDSI0 BIT(0) | |
164 | ||
165 | #define CM_PLLC 0x108 | |
166 | # define CM_PLLC_HOLDPER BIT(7) | |
167 | # define CM_PLLC_LOADPER BIT(6) | |
168 | # define CM_PLLC_HOLDCORE2 BIT(5) | |
169 | # define CM_PLLC_LOADCORE2 BIT(4) | |
170 | # define CM_PLLC_HOLDCORE1 BIT(3) | |
171 | # define CM_PLLC_LOADCORE1 BIT(2) | |
172 | # define CM_PLLC_HOLDCORE0 BIT(1) | |
173 | # define CM_PLLC_LOADCORE0 BIT(0) | |
174 | ||
175 | #define CM_PLLD 0x10c | |
176 | # define CM_PLLD_HOLDPER BIT(7) | |
177 | # define CM_PLLD_LOADPER BIT(6) | |
178 | # define CM_PLLD_HOLDCORE BIT(5) | |
179 | # define CM_PLLD_LOADCORE BIT(4) | |
180 | # define CM_PLLD_HOLDDSI1 BIT(3) | |
181 | # define CM_PLLD_LOADDSI1 BIT(2) | |
182 | # define CM_PLLD_HOLDDSI0 BIT(1) | |
183 | # define CM_PLLD_LOADDSI0 BIT(0) | |
184 | ||
185 | #define CM_PLLH 0x110 | |
186 | # define CM_PLLH_LOADRCAL BIT(2) | |
187 | # define CM_PLLH_LOADAUX BIT(1) | |
188 | # define CM_PLLH_LOADPIX BIT(0) | |
189 | ||
190 | #define CM_LOCK 0x114 | |
191 | # define CM_LOCK_FLOCKH BIT(12) | |
192 | # define CM_LOCK_FLOCKD BIT(11) | |
193 | # define CM_LOCK_FLOCKC BIT(10) | |
194 | # define CM_LOCK_FLOCKB BIT(9) | |
195 | # define CM_LOCK_FLOCKA BIT(8) | |
196 | ||
197 | #define CM_EVENT 0x118 | |
198 | #define CM_DSI1ECTL 0x158 | |
199 | #define CM_DSI1EDIV 0x15c | |
200 | #define CM_DSI1PCTL 0x160 | |
201 | #define CM_DSI1PDIV 0x164 | |
202 | #define CM_DFTCTL 0x168 | |
203 | #define CM_DFTDIV 0x16c | |
204 | ||
205 | #define CM_PLLB 0x170 | |
206 | # define CM_PLLB_HOLDARM BIT(1) | |
207 | # define CM_PLLB_LOADARM BIT(0) | |
208 | ||
209 | #define A2W_PLLA_CTRL 0x1100 | |
210 | #define A2W_PLLC_CTRL 0x1120 | |
211 | #define A2W_PLLD_CTRL 0x1140 | |
212 | #define A2W_PLLH_CTRL 0x1160 | |
213 | #define A2W_PLLB_CTRL 0x11e0 | |
214 | # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) | |
215 | # define A2W_PLL_CTRL_PWRDN BIT(16) | |
216 | # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 | |
217 | # define A2W_PLL_CTRL_PDIV_SHIFT 12 | |
218 | # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff | |
219 | # define A2W_PLL_CTRL_NDIV_SHIFT 0 | |
220 | ||
221 | #define A2W_PLLA_ANA0 0x1010 | |
222 | #define A2W_PLLC_ANA0 0x1030 | |
223 | #define A2W_PLLD_ANA0 0x1050 | |
224 | #define A2W_PLLH_ANA0 0x1070 | |
225 | #define A2W_PLLB_ANA0 0x10f0 | |
226 | ||
227 | #define A2W_PLL_KA_SHIFT 7 | |
228 | #define A2W_PLL_KA_MASK GENMASK(9, 7) | |
229 | #define A2W_PLL_KI_SHIFT 19 | |
230 | #define A2W_PLL_KI_MASK GENMASK(21, 19) | |
231 | #define A2W_PLL_KP_SHIFT 15 | |
232 | #define A2W_PLL_KP_MASK GENMASK(18, 15) | |
233 | ||
234 | #define A2W_PLLH_KA_SHIFT 19 | |
235 | #define A2W_PLLH_KA_MASK GENMASK(21, 19) | |
236 | #define A2W_PLLH_KI_LOW_SHIFT 22 | |
237 | #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) | |
238 | #define A2W_PLLH_KI_HIGH_SHIFT 0 | |
239 | #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) | |
240 | #define A2W_PLLH_KP_SHIFT 1 | |
241 | #define A2W_PLLH_KP_MASK GENMASK(4, 1) | |
242 | ||
243 | #define A2W_XOSC_CTRL 0x1190 | |
244 | # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) | |
245 | # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) | |
246 | # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) | |
247 | # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) | |
248 | # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) | |
249 | # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) | |
250 | # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) | |
251 | # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) | |
252 | ||
253 | #define A2W_PLLA_FRAC 0x1200 | |
254 | #define A2W_PLLC_FRAC 0x1220 | |
255 | #define A2W_PLLD_FRAC 0x1240 | |
256 | #define A2W_PLLH_FRAC 0x1260 | |
257 | #define A2W_PLLB_FRAC 0x12e0 | |
258 | # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) | |
259 | # define A2W_PLL_FRAC_BITS 20 | |
260 | ||
261 | #define A2W_PLL_CHANNEL_DISABLE BIT(8) | |
262 | #define A2W_PLL_DIV_BITS 8 | |
263 | #define A2W_PLL_DIV_SHIFT 0 | |
264 | ||
265 | #define A2W_PLLA_DSI0 0x1300 | |
266 | #define A2W_PLLA_CORE 0x1400 | |
267 | #define A2W_PLLA_PER 0x1500 | |
268 | #define A2W_PLLA_CCP2 0x1600 | |
269 | ||
270 | #define A2W_PLLC_CORE2 0x1320 | |
271 | #define A2W_PLLC_CORE1 0x1420 | |
272 | #define A2W_PLLC_PER 0x1520 | |
273 | #define A2W_PLLC_CORE0 0x1620 | |
274 | ||
275 | #define A2W_PLLD_DSI0 0x1340 | |
276 | #define A2W_PLLD_CORE 0x1440 | |
277 | #define A2W_PLLD_PER 0x1540 | |
278 | #define A2W_PLLD_DSI1 0x1640 | |
279 | ||
280 | #define A2W_PLLH_AUX 0x1360 | |
281 | #define A2W_PLLH_RCAL 0x1460 | |
282 | #define A2W_PLLH_PIX 0x1560 | |
283 | #define A2W_PLLH_STS 0x1660 | |
284 | ||
285 | #define A2W_PLLH_CTRLR 0x1960 | |
286 | #define A2W_PLLH_FRACR 0x1a60 | |
287 | #define A2W_PLLH_AUXR 0x1b60 | |
288 | #define A2W_PLLH_RCALR 0x1c60 | |
289 | #define A2W_PLLH_PIXR 0x1d60 | |
290 | #define A2W_PLLH_STSR 0x1e60 | |
291 | ||
292 | #define A2W_PLLB_ARM 0x13e0 | |
293 | #define A2W_PLLB_SP0 0x14e0 | |
294 | #define A2W_PLLB_SP1 0x15e0 | |
295 | #define A2W_PLLB_SP2 0x16e0 | |
296 | ||
297 | #define LOCK_TIMEOUT_NS 100000000 | |
298 | #define BCM2835_MAX_FB_RATE 1750000000u | |
299 | ||
300 | struct bcm2835_cprman { | |
301 | struct device *dev; | |
302 | void __iomem *regs; | |
6e1e60da | 303 | spinlock_t regs_lock; /* spinlock for all clocks */ |
41691b88 EA |
304 | const char *osc_name; |
305 | ||
b19f009d SB |
306 | /* Must be last */ |
307 | struct clk_hw_onecell_data onecell; | |
41691b88 EA |
308 | }; |
309 | ||
310 | static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) | |
311 | { | |
312 | writel(CM_PASSWORD | val, cprman->regs + reg); | |
313 | } | |
314 | ||
315 | static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) | |
316 | { | |
317 | return readl(cprman->regs + reg); | |
318 | } | |
526d239c | 319 | |
96bf9c69 MS |
320 | static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, |
321 | struct debugfs_reg32 *regs, size_t nregs, | |
322 | struct dentry *dentry) | |
323 | { | |
324 | struct dentry *regdump; | |
325 | struct debugfs_regset32 *regset; | |
326 | ||
327 | regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); | |
328 | if (!regset) | |
329 | return -ENOMEM; | |
330 | ||
331 | regset->regs = regs; | |
332 | regset->nregs = nregs; | |
333 | regset->base = cprman->regs + base; | |
334 | ||
335 | regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry, | |
336 | regset); | |
337 | ||
338 | return regdump ? 0 : -ENOMEM; | |
339 | } | |
340 | ||
75fabc3f SA |
341 | /* |
342 | * These are fixed clocks. They're probably not all root clocks and it may | |
343 | * be possible to turn them on and off but until this is mapped out better | |
344 | * it's the only way they can be used. | |
345 | */ | |
346 | void __init bcm2835_init_clocks(void) | |
347 | { | |
b19f009d | 348 | struct clk_hw *hw; |
75fabc3f SA |
349 | int ret; |
350 | ||
b19f009d SB |
351 | hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); |
352 | if (IS_ERR(hw)) | |
75fabc3f SA |
353 | pr_err("apb_pclk not registered\n"); |
354 | ||
b19f009d SB |
355 | hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); |
356 | if (IS_ERR(hw)) | |
75fabc3f | 357 | pr_err("uart0_pclk not registered\n"); |
b19f009d | 358 | ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart"); |
75fabc3f SA |
359 | if (ret) |
360 | pr_err("uart0_pclk alias not registered\n"); | |
361 | ||
b19f009d SB |
362 | hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); |
363 | if (IS_ERR(hw)) | |
75fabc3f | 364 | pr_err("uart1_pclk not registered\n"); |
b19f009d | 365 | ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart"); |
75fabc3f | 366 | if (ret) |
686ea585 | 367 | pr_err("uart1_pclk alias not registered\n"); |
75fabc3f | 368 | } |
41691b88 EA |
369 | |
370 | struct bcm2835_pll_data { | |
371 | const char *name; | |
372 | u32 cm_ctrl_reg; | |
373 | u32 a2w_ctrl_reg; | |
374 | u32 frac_reg; | |
375 | u32 ana_reg_base; | |
376 | u32 reference_enable_mask; | |
377 | /* Bit in CM_LOCK to indicate when the PLL has locked. */ | |
378 | u32 lock_mask; | |
379 | ||
380 | const struct bcm2835_pll_ana_bits *ana; | |
381 | ||
382 | unsigned long min_rate; | |
383 | unsigned long max_rate; | |
384 | /* | |
385 | * Highest rate for the VCO before we have to use the | |
386 | * pre-divide-by-2. | |
387 | */ | |
388 | unsigned long max_fb_rate; | |
389 | }; | |
390 | ||
391 | struct bcm2835_pll_ana_bits { | |
392 | u32 mask0; | |
393 | u32 set0; | |
394 | u32 mask1; | |
395 | u32 set1; | |
396 | u32 mask3; | |
397 | u32 set3; | |
398 | u32 fb_prediv_mask; | |
399 | }; | |
400 | ||
401 | static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { | |
402 | .mask0 = 0, | |
403 | .set0 = 0, | |
286259ef | 404 | .mask1 = (u32)~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK), |
41691b88 | 405 | .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), |
286259ef | 406 | .mask3 = (u32)~A2W_PLL_KA_MASK, |
41691b88 EA |
407 | .set3 = (2 << A2W_PLL_KA_SHIFT), |
408 | .fb_prediv_mask = BIT(14), | |
409 | }; | |
410 | ||
411 | static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { | |
286259ef | 412 | .mask0 = (u32)~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK), |
41691b88 | 413 | .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), |
286259ef | 414 | .mask1 = (u32)~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK), |
41691b88 EA |
415 | .set1 = (6 << A2W_PLLH_KP_SHIFT), |
416 | .mask3 = 0, | |
417 | .set3 = 0, | |
418 | .fb_prediv_mask = BIT(11), | |
419 | }; | |
420 | ||
41691b88 EA |
421 | struct bcm2835_pll_divider_data { |
422 | const char *name; | |
3b15afef MS |
423 | const char *source_pll; |
424 | ||
41691b88 EA |
425 | u32 cm_reg; |
426 | u32 a2w_reg; | |
427 | ||
428 | u32 load_mask; | |
429 | u32 hold_mask; | |
430 | u32 fixed_divider; | |
431 | }; | |
432 | ||
41691b88 EA |
433 | struct bcm2835_clock_data { |
434 | const char *name; | |
435 | ||
436 | const char *const *parents; | |
437 | int num_mux_parents; | |
438 | ||
439 | u32 ctl_reg; | |
440 | u32 div_reg; | |
441 | ||
442 | /* Number of integer bits in the divider */ | |
443 | u32 int_bits; | |
444 | /* Number of fractional bits in the divider */ | |
445 | u32 frac_bits; | |
446 | ||
e69fdcca EA |
447 | u32 flags; |
448 | ||
41691b88 | 449 | bool is_vpu_clock; |
959ca92a | 450 | bool is_mash_clock; |
41691b88 EA |
451 | }; |
452 | ||
56eb3a2e MS |
453 | struct bcm2835_gate_data { |
454 | const char *name; | |
455 | const char *parent; | |
456 | ||
457 | u32 ctl_reg; | |
458 | }; | |
459 | ||
41691b88 EA |
460 | struct bcm2835_pll { |
461 | struct clk_hw hw; | |
462 | struct bcm2835_cprman *cprman; | |
463 | const struct bcm2835_pll_data *data; | |
464 | }; | |
465 | ||
466 | static int bcm2835_pll_is_on(struct clk_hw *hw) | |
467 | { | |
468 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
469 | struct bcm2835_cprman *cprman = pll->cprman; | |
470 | const struct bcm2835_pll_data *data = pll->data; | |
471 | ||
472 | return cprman_read(cprman, data->a2w_ctrl_reg) & | |
473 | A2W_PLL_CTRL_PRST_DISABLE; | |
474 | } | |
475 | ||
476 | static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, | |
477 | unsigned long parent_rate, | |
478 | u32 *ndiv, u32 *fdiv) | |
479 | { | |
480 | u64 div; | |
481 | ||
482 | div = (u64)rate << A2W_PLL_FRAC_BITS; | |
483 | do_div(div, parent_rate); | |
484 | ||
485 | *ndiv = div >> A2W_PLL_FRAC_BITS; | |
486 | *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); | |
487 | } | |
488 | ||
489 | static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, | |
490 | u32 ndiv, u32 fdiv, u32 pdiv) | |
491 | { | |
492 | u64 rate; | |
493 | ||
494 | if (pdiv == 0) | |
495 | return 0; | |
496 | ||
497 | rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); | |
498 | do_div(rate, pdiv); | |
499 | return rate >> A2W_PLL_FRAC_BITS; | |
500 | } | |
501 | ||
502 | static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
503 | unsigned long *parent_rate) | |
504 | { | |
c4e634ce EA |
505 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); |
506 | const struct bcm2835_pll_data *data = pll->data; | |
41691b88 EA |
507 | u32 ndiv, fdiv; |
508 | ||
c4e634ce EA |
509 | rate = clamp(rate, data->min_rate, data->max_rate); |
510 | ||
41691b88 EA |
511 | bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); |
512 | ||
513 | return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); | |
514 | } | |
515 | ||
516 | static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, | |
517 | unsigned long parent_rate) | |
518 | { | |
519 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
520 | struct bcm2835_cprman *cprman = pll->cprman; | |
521 | const struct bcm2835_pll_data *data = pll->data; | |
522 | u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); | |
523 | u32 ndiv, pdiv, fdiv; | |
524 | bool using_prediv; | |
525 | ||
526 | if (parent_rate == 0) | |
527 | return 0; | |
528 | ||
529 | fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; | |
530 | ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; | |
531 | pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; | |
532 | using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & | |
533 | data->ana->fb_prediv_mask; | |
534 | ||
535 | if (using_prediv) | |
536 | ndiv *= 2; | |
537 | ||
538 | return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); | |
539 | } | |
540 | ||
541 | static void bcm2835_pll_off(struct clk_hw *hw) | |
542 | { | |
543 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
544 | struct bcm2835_cprman *cprman = pll->cprman; | |
545 | const struct bcm2835_pll_data *data = pll->data; | |
546 | ||
6727f086 MS |
547 | spin_lock(&cprman->regs_lock); |
548 | cprman_write(cprman, data->cm_ctrl_reg, | |
549 | cprman_read(cprman, data->cm_ctrl_reg) | | |
550 | CM_PLL_ANARST); | |
551 | cprman_write(cprman, data->a2w_ctrl_reg, | |
552 | cprman_read(cprman, data->a2w_ctrl_reg) | | |
553 | A2W_PLL_CTRL_PWRDN); | |
554 | spin_unlock(&cprman->regs_lock); | |
41691b88 EA |
555 | } |
556 | ||
557 | static int bcm2835_pll_on(struct clk_hw *hw) | |
558 | { | |
559 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
560 | struct bcm2835_cprman *cprman = pll->cprman; | |
561 | const struct bcm2835_pll_data *data = pll->data; | |
562 | ktime_t timeout; | |
563 | ||
e708b383 EA |
564 | cprman_write(cprman, data->a2w_ctrl_reg, |
565 | cprman_read(cprman, data->a2w_ctrl_reg) & | |
566 | ~A2W_PLL_CTRL_PWRDN); | |
567 | ||
41691b88 EA |
568 | /* Take the PLL out of reset. */ |
569 | cprman_write(cprman, data->cm_ctrl_reg, | |
570 | cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); | |
571 | ||
572 | /* Wait for the PLL to lock. */ | |
573 | timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
574 | while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { | |
575 | if (ktime_after(ktime_get(), timeout)) { | |
576 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
577 | clk_hw_get_name(hw)); | |
578 | return -ETIMEDOUT; | |
579 | } | |
580 | ||
581 | cpu_relax(); | |
582 | } | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | static void | |
588 | bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) | |
589 | { | |
590 | int i; | |
591 | ||
592 | /* | |
593 | * ANA register setup is done as a series of writes to | |
594 | * ANA3-ANA0, in that order. This lets us write all 4 | |
595 | * registers as a single cycle of the serdes interface (taking | |
596 | * 100 xosc clocks), whereas if we were to update ana0, 1, and | |
597 | * 3 individually through their partial-write registers, each | |
598 | * would be their own serdes cycle. | |
599 | */ | |
600 | for (i = 3; i >= 0; i--) | |
601 | cprman_write(cprman, ana_reg_base + i * 4, ana[i]); | |
602 | } | |
603 | ||
604 | static int bcm2835_pll_set_rate(struct clk_hw *hw, | |
605 | unsigned long rate, unsigned long parent_rate) | |
606 | { | |
607 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
608 | struct bcm2835_cprman *cprman = pll->cprman; | |
609 | const struct bcm2835_pll_data *data = pll->data; | |
610 | bool was_using_prediv, use_fb_prediv, do_ana_setup_first; | |
611 | u32 ndiv, fdiv, a2w_ctl; | |
612 | u32 ana[4]; | |
613 | int i; | |
614 | ||
41691b88 EA |
615 | if (rate > data->max_fb_rate) { |
616 | use_fb_prediv = true; | |
617 | rate /= 2; | |
618 | } else { | |
619 | use_fb_prediv = false; | |
620 | } | |
621 | ||
622 | bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); | |
623 | ||
624 | for (i = 3; i >= 0; i--) | |
625 | ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); | |
626 | ||
627 | was_using_prediv = ana[1] & data->ana->fb_prediv_mask; | |
628 | ||
629 | ana[0] &= ~data->ana->mask0; | |
630 | ana[0] |= data->ana->set0; | |
631 | ana[1] &= ~data->ana->mask1; | |
632 | ana[1] |= data->ana->set1; | |
633 | ana[3] &= ~data->ana->mask3; | |
634 | ana[3] |= data->ana->set3; | |
635 | ||
636 | if (was_using_prediv && !use_fb_prediv) { | |
637 | ana[1] &= ~data->ana->fb_prediv_mask; | |
638 | do_ana_setup_first = true; | |
639 | } else if (!was_using_prediv && use_fb_prediv) { | |
640 | ana[1] |= data->ana->fb_prediv_mask; | |
641 | do_ana_setup_first = false; | |
642 | } else { | |
643 | do_ana_setup_first = true; | |
644 | } | |
645 | ||
646 | /* Unmask the reference clock from the oscillator. */ | |
647 | cprman_write(cprman, A2W_XOSC_CTRL, | |
648 | cprman_read(cprman, A2W_XOSC_CTRL) | | |
649 | data->reference_enable_mask); | |
650 | ||
651 | if (do_ana_setup_first) | |
652 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
653 | ||
654 | /* Set the PLL multiplier from the oscillator. */ | |
655 | cprman_write(cprman, data->frac_reg, fdiv); | |
656 | ||
657 | a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); | |
658 | a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; | |
659 | a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; | |
660 | a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; | |
661 | a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; | |
662 | cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); | |
663 | ||
664 | if (!do_ana_setup_first) | |
665 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
96bf9c69 MS |
670 | static int bcm2835_pll_debug_init(struct clk_hw *hw, |
671 | struct dentry *dentry) | |
672 | { | |
673 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
674 | struct bcm2835_cprman *cprman = pll->cprman; | |
675 | const struct bcm2835_pll_data *data = pll->data; | |
676 | struct debugfs_reg32 *regs; | |
677 | ||
678 | regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); | |
679 | if (!regs) | |
680 | return -ENOMEM; | |
681 | ||
682 | regs[0].name = "cm_ctrl"; | |
683 | regs[0].offset = data->cm_ctrl_reg; | |
684 | regs[1].name = "a2w_ctrl"; | |
685 | regs[1].offset = data->a2w_ctrl_reg; | |
686 | regs[2].name = "frac"; | |
687 | regs[2].offset = data->frac_reg; | |
688 | regs[3].name = "ana0"; | |
689 | regs[3].offset = data->ana_reg_base + 0 * 4; | |
690 | regs[4].name = "ana1"; | |
691 | regs[4].offset = data->ana_reg_base + 1 * 4; | |
692 | regs[5].name = "ana2"; | |
693 | regs[5].offset = data->ana_reg_base + 2 * 4; | |
694 | regs[6].name = "ana3"; | |
695 | regs[6].offset = data->ana_reg_base + 3 * 4; | |
696 | ||
697 | return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); | |
698 | } | |
699 | ||
41691b88 EA |
700 | static const struct clk_ops bcm2835_pll_clk_ops = { |
701 | .is_prepared = bcm2835_pll_is_on, | |
702 | .prepare = bcm2835_pll_on, | |
703 | .unprepare = bcm2835_pll_off, | |
704 | .recalc_rate = bcm2835_pll_get_rate, | |
705 | .set_rate = bcm2835_pll_set_rate, | |
706 | .round_rate = bcm2835_pll_round_rate, | |
96bf9c69 | 707 | .debug_init = bcm2835_pll_debug_init, |
41691b88 EA |
708 | }; |
709 | ||
710 | struct bcm2835_pll_divider { | |
711 | struct clk_divider div; | |
712 | struct bcm2835_cprman *cprman; | |
713 | const struct bcm2835_pll_divider_data *data; | |
714 | }; | |
715 | ||
716 | static struct bcm2835_pll_divider * | |
717 | bcm2835_pll_divider_from_hw(struct clk_hw *hw) | |
718 | { | |
719 | return container_of(hw, struct bcm2835_pll_divider, div.hw); | |
720 | } | |
721 | ||
722 | static int bcm2835_pll_divider_is_on(struct clk_hw *hw) | |
723 | { | |
724 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
725 | struct bcm2835_cprman *cprman = divider->cprman; | |
726 | const struct bcm2835_pll_divider_data *data = divider->data; | |
727 | ||
728 | return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); | |
729 | } | |
730 | ||
731 | static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, | |
732 | unsigned long rate, | |
733 | unsigned long *parent_rate) | |
734 | { | |
735 | return clk_divider_ops.round_rate(hw, rate, parent_rate); | |
736 | } | |
737 | ||
738 | static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, | |
739 | unsigned long parent_rate) | |
740 | { | |
79c1e2fc | 741 | return clk_divider_ops.recalc_rate(hw, parent_rate); |
41691b88 EA |
742 | } |
743 | ||
744 | static void bcm2835_pll_divider_off(struct clk_hw *hw) | |
745 | { | |
746 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
747 | struct bcm2835_cprman *cprman = divider->cprman; | |
748 | const struct bcm2835_pll_divider_data *data = divider->data; | |
749 | ||
ec36a5c6 | 750 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
751 | cprman_write(cprman, data->cm_reg, |
752 | (cprman_read(cprman, data->cm_reg) & | |
753 | ~data->load_mask) | data->hold_mask); | |
68af4fa8 BB |
754 | cprman_write(cprman, data->a2w_reg, |
755 | cprman_read(cprman, data->a2w_reg) | | |
756 | A2W_PLL_CHANNEL_DISABLE); | |
ec36a5c6 | 757 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
758 | } |
759 | ||
760 | static int bcm2835_pll_divider_on(struct clk_hw *hw) | |
761 | { | |
762 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
763 | struct bcm2835_cprman *cprman = divider->cprman; | |
764 | const struct bcm2835_pll_divider_data *data = divider->data; | |
765 | ||
ec36a5c6 | 766 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
767 | cprman_write(cprman, data->a2w_reg, |
768 | cprman_read(cprman, data->a2w_reg) & | |
769 | ~A2W_PLL_CHANNEL_DISABLE); | |
770 | ||
771 | cprman_write(cprman, data->cm_reg, | |
772 | cprman_read(cprman, data->cm_reg) & ~data->hold_mask); | |
ec36a5c6 | 773 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
774 | |
775 | return 0; | |
776 | } | |
777 | ||
778 | static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, | |
779 | unsigned long rate, | |
780 | unsigned long parent_rate) | |
781 | { | |
782 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
783 | struct bcm2835_cprman *cprman = divider->cprman; | |
784 | const struct bcm2835_pll_divider_data *data = divider->data; | |
773b3966 | 785 | u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; |
41691b88 | 786 | |
773b3966 EA |
787 | div = DIV_ROUND_UP_ULL(parent_rate, rate); |
788 | ||
789 | div = min(div, max_div); | |
790 | if (div == max_div) | |
791 | div = 0; | |
41691b88 | 792 | |
773b3966 | 793 | cprman_write(cprman, data->a2w_reg, div); |
41691b88 EA |
794 | cm = cprman_read(cprman, data->cm_reg); |
795 | cprman_write(cprman, data->cm_reg, cm | data->load_mask); | |
796 | cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
96bf9c69 MS |
801 | static int bcm2835_pll_divider_debug_init(struct clk_hw *hw, |
802 | struct dentry *dentry) | |
803 | { | |
804 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
805 | struct bcm2835_cprman *cprman = divider->cprman; | |
806 | const struct bcm2835_pll_divider_data *data = divider->data; | |
807 | struct debugfs_reg32 *regs; | |
808 | ||
809 | regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); | |
810 | if (!regs) | |
811 | return -ENOMEM; | |
812 | ||
813 | regs[0].name = "cm"; | |
814 | regs[0].offset = data->cm_reg; | |
815 | regs[1].name = "a2w"; | |
816 | regs[1].offset = data->a2w_reg; | |
817 | ||
818 | return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); | |
819 | } | |
820 | ||
41691b88 EA |
821 | static const struct clk_ops bcm2835_pll_divider_clk_ops = { |
822 | .is_prepared = bcm2835_pll_divider_is_on, | |
823 | .prepare = bcm2835_pll_divider_on, | |
824 | .unprepare = bcm2835_pll_divider_off, | |
825 | .recalc_rate = bcm2835_pll_divider_get_rate, | |
826 | .set_rate = bcm2835_pll_divider_set_rate, | |
827 | .round_rate = bcm2835_pll_divider_round_rate, | |
96bf9c69 | 828 | .debug_init = bcm2835_pll_divider_debug_init, |
41691b88 EA |
829 | }; |
830 | ||
831 | /* | |
832 | * The CM dividers do fixed-point division, so we can't use the | |
833 | * generic integer divider code like the PLL dividers do (and we can't | |
834 | * fake it by having some fixed shifts preceding it in the clock tree, | |
835 | * because we'd run out of bits in a 32-bit unsigned long). | |
836 | */ | |
837 | struct bcm2835_clock { | |
838 | struct clk_hw hw; | |
839 | struct bcm2835_cprman *cprman; | |
840 | const struct bcm2835_clock_data *data; | |
841 | }; | |
842 | ||
843 | static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) | |
844 | { | |
845 | return container_of(hw, struct bcm2835_clock, hw); | |
846 | } | |
847 | ||
848 | static int bcm2835_clock_is_on(struct clk_hw *hw) | |
849 | { | |
850 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
851 | struct bcm2835_cprman *cprman = clock->cprman; | |
852 | const struct bcm2835_clock_data *data = clock->data; | |
853 | ||
854 | return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; | |
855 | } | |
856 | ||
857 | static u32 bcm2835_clock_choose_div(struct clk_hw *hw, | |
858 | unsigned long rate, | |
9c95b32c RP |
859 | unsigned long parent_rate, |
860 | bool round_up) | |
41691b88 EA |
861 | { |
862 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
863 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c RP |
864 | u32 unused_frac_mask = |
865 | GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; | |
41691b88 | 866 | u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; |
9c95b32c | 867 | u64 rem; |
959ca92a | 868 | u32 div, mindiv, maxdiv; |
41691b88 | 869 | |
9c95b32c | 870 | rem = do_div(temp, rate); |
41691b88 EA |
871 | div = temp; |
872 | ||
9c95b32c RP |
873 | /* Round up and mask off the unused bits */ |
874 | if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) | |
875 | div += unused_frac_mask + 1; | |
876 | div &= ~unused_frac_mask; | |
41691b88 | 877 | |
959ca92a MS |
878 | /* different clamping limits apply for a mash clock */ |
879 | if (data->is_mash_clock) { | |
880 | /* clamp to min divider of 2 */ | |
881 | mindiv = 2 << CM_DIV_FRAC_BITS; | |
882 | /* clamp to the highest possible integer divider */ | |
883 | maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; | |
884 | } else { | |
885 | /* clamp to min divider of 1 */ | |
886 | mindiv = 1 << CM_DIV_FRAC_BITS; | |
887 | /* clamp to the highest possible fractional divider */ | |
888 | maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, | |
889 | CM_DIV_FRAC_BITS - data->frac_bits); | |
890 | } | |
891 | ||
892 | /* apply the clamping limits */ | |
893 | div = max_t(u32, div, mindiv); | |
894 | div = min_t(u32, div, maxdiv); | |
41691b88 EA |
895 | |
896 | return div; | |
897 | } | |
898 | ||
899 | static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, | |
900 | unsigned long parent_rate, | |
901 | u32 div) | |
902 | { | |
903 | const struct bcm2835_clock_data *data = clock->data; | |
904 | u64 temp; | |
905 | ||
906 | /* | |
907 | * The divisor is a 12.12 fixed point field, but only some of | |
908 | * the bits are populated in any given clock. | |
909 | */ | |
910 | div >>= CM_DIV_FRAC_BITS - data->frac_bits; | |
911 | div &= (1 << (data->int_bits + data->frac_bits)) - 1; | |
912 | ||
913 | if (div == 0) | |
914 | return 0; | |
915 | ||
916 | temp = (u64)parent_rate << data->frac_bits; | |
917 | ||
918 | do_div(temp, div); | |
919 | ||
920 | return temp; | |
921 | } | |
922 | ||
41691b88 EA |
923 | static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, |
924 | unsigned long parent_rate) | |
925 | { | |
926 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
927 | struct bcm2835_cprman *cprman = clock->cprman; | |
928 | const struct bcm2835_clock_data *data = clock->data; | |
929 | u32 div = cprman_read(cprman, data->div_reg); | |
930 | ||
931 | return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); | |
932 | } | |
933 | ||
934 | static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) | |
935 | { | |
936 | struct bcm2835_cprman *cprman = clock->cprman; | |
937 | const struct bcm2835_clock_data *data = clock->data; | |
938 | ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
939 | ||
940 | while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { | |
941 | if (ktime_after(ktime_get(), timeout)) { | |
942 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
943 | clk_hw_get_name(&clock->hw)); | |
944 | return; | |
945 | } | |
946 | cpu_relax(); | |
947 | } | |
948 | } | |
949 | ||
950 | static void bcm2835_clock_off(struct clk_hw *hw) | |
951 | { | |
952 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
953 | struct bcm2835_cprman *cprman = clock->cprman; | |
954 | const struct bcm2835_clock_data *data = clock->data; | |
955 | ||
956 | spin_lock(&cprman->regs_lock); | |
957 | cprman_write(cprman, data->ctl_reg, | |
958 | cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); | |
959 | spin_unlock(&cprman->regs_lock); | |
960 | ||
961 | /* BUSY will remain high until the divider completes its cycle. */ | |
962 | bcm2835_clock_wait_busy(clock); | |
963 | } | |
964 | ||
965 | static int bcm2835_clock_on(struct clk_hw *hw) | |
966 | { | |
967 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
968 | struct bcm2835_cprman *cprman = clock->cprman; | |
969 | const struct bcm2835_clock_data *data = clock->data; | |
970 | ||
971 | spin_lock(&cprman->regs_lock); | |
972 | cprman_write(cprman, data->ctl_reg, | |
973 | cprman_read(cprman, data->ctl_reg) | | |
974 | CM_ENABLE | | |
975 | CM_GATE); | |
976 | spin_unlock(&cprman->regs_lock); | |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
981 | static int bcm2835_clock_set_rate(struct clk_hw *hw, | |
982 | unsigned long rate, unsigned long parent_rate) | |
983 | { | |
984 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
985 | struct bcm2835_cprman *cprman = clock->cprman; | |
986 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c | 987 | u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); |
959ca92a MS |
988 | u32 ctl; |
989 | ||
990 | spin_lock(&cprman->regs_lock); | |
991 | ||
992 | /* | |
993 | * Setting up frac support | |
994 | * | |
995 | * In principle it is recommended to stop/start the clock first, | |
996 | * but as we set CLK_SET_RATE_GATE during registration of the | |
997 | * clock this requirement should be take care of by the | |
998 | * clk-framework. | |
999 | */ | |
1000 | ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; | |
1001 | ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; | |
1002 | cprman_write(cprman, data->ctl_reg, ctl); | |
41691b88 EA |
1003 | |
1004 | cprman_write(cprman, data->div_reg, div); | |
1005 | ||
959ca92a MS |
1006 | spin_unlock(&cprman->regs_lock); |
1007 | ||
41691b88 EA |
1008 | return 0; |
1009 | } | |
1010 | ||
67615c58 EA |
1011 | static bool |
1012 | bcm2835_clk_is_pllc(struct clk_hw *hw) | |
1013 | { | |
1014 | if (!hw) | |
1015 | return false; | |
1016 | ||
1017 | return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; | |
1018 | } | |
1019 | ||
6d18b8ad | 1020 | static int bcm2835_clock_determine_rate(struct clk_hw *hw, |
6e1e60da | 1021 | struct clk_rate_request *req) |
6d18b8ad RP |
1022 | { |
1023 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1024 | struct clk_hw *parent, *best_parent = NULL; | |
67615c58 | 1025 | bool current_parent_is_pllc; |
6d18b8ad RP |
1026 | unsigned long rate, best_rate = 0; |
1027 | unsigned long prate, best_prate = 0; | |
1028 | size_t i; | |
1029 | u32 div; | |
1030 | ||
67615c58 EA |
1031 | current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); |
1032 | ||
6d18b8ad RP |
1033 | /* |
1034 | * Select parent clock that results in the closest but lower rate | |
1035 | */ | |
1036 | for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { | |
1037 | parent = clk_hw_get_parent_by_index(hw, i); | |
1038 | if (!parent) | |
1039 | continue; | |
67615c58 EA |
1040 | |
1041 | /* | |
1042 | * Don't choose a PLLC-derived clock as our parent | |
1043 | * unless it had been manually set that way. PLLC's | |
1044 | * frequency gets adjusted by the firmware due to | |
1045 | * over-temp or under-voltage conditions, without | |
1046 | * prior notification to our clock consumer. | |
1047 | */ | |
1048 | if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) | |
1049 | continue; | |
1050 | ||
6d18b8ad RP |
1051 | prate = clk_hw_get_rate(parent); |
1052 | div = bcm2835_clock_choose_div(hw, req->rate, prate, true); | |
1053 | rate = bcm2835_clock_rate_from_divisor(clock, prate, div); | |
1054 | if (rate > best_rate && rate <= req->rate) { | |
1055 | best_parent = parent; | |
1056 | best_prate = prate; | |
1057 | best_rate = rate; | |
1058 | } | |
1059 | } | |
1060 | ||
1061 | if (!best_parent) | |
1062 | return -EINVAL; | |
1063 | ||
1064 | req->best_parent_hw = best_parent; | |
1065 | req->best_parent_rate = best_prate; | |
1066 | ||
1067 | req->rate = best_rate; | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) | |
1073 | { | |
1074 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1075 | struct bcm2835_cprman *cprman = clock->cprman; | |
1076 | const struct bcm2835_clock_data *data = clock->data; | |
1077 | u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; | |
1078 | ||
1079 | cprman_write(cprman, data->ctl_reg, src); | |
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | static u8 bcm2835_clock_get_parent(struct clk_hw *hw) | |
1084 | { | |
1085 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1086 | struct bcm2835_cprman *cprman = clock->cprman; | |
1087 | const struct bcm2835_clock_data *data = clock->data; | |
1088 | u32 src = cprman_read(cprman, data->ctl_reg); | |
1089 | ||
1090 | return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; | |
1091 | } | |
1092 | ||
96bf9c69 MS |
1093 | static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { |
1094 | { | |
1095 | .name = "ctl", | |
1096 | .offset = 0, | |
1097 | }, | |
1098 | { | |
1099 | .name = "div", | |
1100 | .offset = 4, | |
1101 | }, | |
1102 | }; | |
1103 | ||
1104 | static int bcm2835_clock_debug_init(struct clk_hw *hw, | |
1105 | struct dentry *dentry) | |
1106 | { | |
1107 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1108 | struct bcm2835_cprman *cprman = clock->cprman; | |
1109 | const struct bcm2835_clock_data *data = clock->data; | |
1110 | ||
1111 | return bcm2835_debugfs_regset( | |
1112 | cprman, data->ctl_reg, | |
1113 | bcm2835_debugfs_clock_reg32, | |
1114 | ARRAY_SIZE(bcm2835_debugfs_clock_reg32), | |
1115 | dentry); | |
1116 | } | |
1117 | ||
41691b88 EA |
1118 | static const struct clk_ops bcm2835_clock_clk_ops = { |
1119 | .is_prepared = bcm2835_clock_is_on, | |
1120 | .prepare = bcm2835_clock_on, | |
1121 | .unprepare = bcm2835_clock_off, | |
1122 | .recalc_rate = bcm2835_clock_get_rate, | |
1123 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1124 | .determine_rate = bcm2835_clock_determine_rate, |
1125 | .set_parent = bcm2835_clock_set_parent, | |
1126 | .get_parent = bcm2835_clock_get_parent, | |
96bf9c69 | 1127 | .debug_init = bcm2835_clock_debug_init, |
41691b88 EA |
1128 | }; |
1129 | ||
1130 | static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) | |
1131 | { | |
1132 | return true; | |
1133 | } | |
1134 | ||
1135 | /* | |
1136 | * The VPU clock can never be disabled (it doesn't have an ENABLE | |
1137 | * bit), so it gets its own set of clock ops. | |
1138 | */ | |
1139 | static const struct clk_ops bcm2835_vpu_clock_clk_ops = { | |
1140 | .is_prepared = bcm2835_vpu_clock_is_on, | |
1141 | .recalc_rate = bcm2835_clock_get_rate, | |
1142 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1143 | .determine_rate = bcm2835_clock_determine_rate, |
1144 | .set_parent = bcm2835_clock_set_parent, | |
1145 | .get_parent = bcm2835_clock_get_parent, | |
96bf9c69 | 1146 | .debug_init = bcm2835_clock_debug_init, |
41691b88 EA |
1147 | }; |
1148 | ||
b19f009d SB |
1149 | static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, |
1150 | const struct bcm2835_pll_data *data) | |
41691b88 EA |
1151 | { |
1152 | struct bcm2835_pll *pll; | |
1153 | struct clk_init_data init; | |
b19f009d | 1154 | int ret; |
41691b88 EA |
1155 | |
1156 | memset(&init, 0, sizeof(init)); | |
1157 | ||
1158 | /* All of the PLLs derive from the external oscillator. */ | |
1159 | init.parent_names = &cprman->osc_name; | |
1160 | init.num_parents = 1; | |
1161 | init.name = data->name; | |
1162 | init.ops = &bcm2835_pll_clk_ops; | |
1163 | init.flags = CLK_IGNORE_UNUSED; | |
1164 | ||
1165 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
1166 | if (!pll) | |
1167 | return NULL; | |
1168 | ||
1169 | pll->cprman = cprman; | |
1170 | pll->data = data; | |
1171 | pll->hw.init = &init; | |
1172 | ||
b19f009d SB |
1173 | ret = devm_clk_hw_register(cprman->dev, &pll->hw); |
1174 | if (ret) | |
1175 | return NULL; | |
1176 | return &pll->hw; | |
41691b88 EA |
1177 | } |
1178 | ||
b19f009d | 1179 | static struct clk_hw * |
41691b88 EA |
1180 | bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, |
1181 | const struct bcm2835_pll_divider_data *data) | |
1182 | { | |
1183 | struct bcm2835_pll_divider *divider; | |
1184 | struct clk_init_data init; | |
41691b88 | 1185 | const char *divider_name; |
b19f009d | 1186 | int ret; |
41691b88 EA |
1187 | |
1188 | if (data->fixed_divider != 1) { | |
1189 | divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, | |
1190 | "%s_prediv", data->name); | |
1191 | if (!divider_name) | |
1192 | return NULL; | |
1193 | } else { | |
1194 | divider_name = data->name; | |
1195 | } | |
1196 | ||
1197 | memset(&init, 0, sizeof(init)); | |
1198 | ||
3b15afef | 1199 | init.parent_names = &data->source_pll; |
41691b88 EA |
1200 | init.num_parents = 1; |
1201 | init.name = divider_name; | |
1202 | init.ops = &bcm2835_pll_divider_clk_ops; | |
1203 | init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; | |
1204 | ||
1205 | divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); | |
1206 | if (!divider) | |
1207 | return NULL; | |
1208 | ||
1209 | divider->div.reg = cprman->regs + data->a2w_reg; | |
1210 | divider->div.shift = A2W_PLL_DIV_SHIFT; | |
1211 | divider->div.width = A2W_PLL_DIV_BITS; | |
79c1e2fc | 1212 | divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; |
41691b88 EA |
1213 | divider->div.lock = &cprman->regs_lock; |
1214 | divider->div.hw.init = &init; | |
1215 | divider->div.table = NULL; | |
1216 | ||
1217 | divider->cprman = cprman; | |
1218 | divider->data = data; | |
1219 | ||
b19f009d SB |
1220 | ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); |
1221 | if (ret) | |
1222 | return ERR_PTR(ret); | |
41691b88 EA |
1223 | |
1224 | /* | |
1225 | * PLLH's channels have a fixed divide by 10 afterwards, which | |
1226 | * is what our consumers are actually using. | |
1227 | */ | |
1228 | if (data->fixed_divider != 1) { | |
b19f009d SB |
1229 | return clk_hw_register_fixed_factor(cprman->dev, data->name, |
1230 | divider_name, | |
1231 | CLK_SET_RATE_PARENT, | |
1232 | 1, | |
1233 | data->fixed_divider); | |
41691b88 EA |
1234 | } |
1235 | ||
b19f009d | 1236 | return ÷r->div.hw; |
41691b88 EA |
1237 | } |
1238 | ||
b19f009d | 1239 | static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, |
41691b88 EA |
1240 | const struct bcm2835_clock_data *data) |
1241 | { | |
1242 | struct bcm2835_clock *clock; | |
1243 | struct clk_init_data init; | |
6d18b8ad RP |
1244 | const char *parents[1 << CM_SRC_BITS]; |
1245 | size_t i; | |
b19f009d | 1246 | int ret; |
41691b88 EA |
1247 | |
1248 | /* | |
6d18b8ad RP |
1249 | * Replace our "xosc" references with the oscillator's |
1250 | * actual name. | |
41691b88 | 1251 | */ |
6d18b8ad RP |
1252 | for (i = 0; i < data->num_mux_parents; i++) { |
1253 | if (strcmp(data->parents[i], "xosc") == 0) | |
1254 | parents[i] = cprman->osc_name; | |
1255 | else | |
1256 | parents[i] = data->parents[i]; | |
41691b88 EA |
1257 | } |
1258 | ||
1259 | memset(&init, 0, sizeof(init)); | |
6d18b8ad RP |
1260 | init.parent_names = parents; |
1261 | init.num_parents = data->num_mux_parents; | |
41691b88 | 1262 | init.name = data->name; |
e69fdcca | 1263 | init.flags = data->flags | CLK_IGNORE_UNUSED; |
41691b88 EA |
1264 | |
1265 | if (data->is_vpu_clock) { | |
1266 | init.ops = &bcm2835_vpu_clock_clk_ops; | |
1267 | } else { | |
1268 | init.ops = &bcm2835_clock_clk_ops; | |
1269 | init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; | |
eddcbe83 EA |
1270 | |
1271 | /* If the clock wasn't actually enabled at boot, it's not | |
1272 | * critical. | |
1273 | */ | |
1274 | if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE)) | |
1275 | init.flags &= ~CLK_IS_CRITICAL; | |
41691b88 EA |
1276 | } |
1277 | ||
1278 | clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); | |
1279 | if (!clock) | |
1280 | return NULL; | |
1281 | ||
1282 | clock->cprman = cprman; | |
1283 | clock->data = data; | |
1284 | clock->hw.init = &init; | |
1285 | ||
b19f009d SB |
1286 | ret = devm_clk_hw_register(cprman->dev, &clock->hw); |
1287 | if (ret) | |
1288 | return ERR_PTR(ret); | |
1289 | return &clock->hw; | |
41691b88 EA |
1290 | } |
1291 | ||
56eb3a2e MS |
1292 | static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman, |
1293 | const struct bcm2835_gate_data *data) | |
1294 | { | |
1295 | return clk_register_gate(cprman->dev, data->name, data->parent, | |
1296 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, | |
1297 | cprman->regs + data->ctl_reg, | |
1298 | CM_GATE_BIT, 0, &cprman->regs_lock); | |
1299 | } | |
1300 | ||
b19f009d SB |
1301 | typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, |
1302 | const void *data); | |
56eb3a2e MS |
1303 | struct bcm2835_clk_desc { |
1304 | bcm2835_clk_register clk_register; | |
1305 | const void *data; | |
1306 | }; | |
1307 | ||
3b15afef MS |
1308 | /* assignment helper macros for different clock types */ |
1309 | #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ | |
1310 | .data = __VA_ARGS__ } | |
1311 | #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ | |
1312 | &(struct bcm2835_pll_data) \ | |
1313 | {__VA_ARGS__}) | |
1314 | #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ | |
1315 | &(struct bcm2835_pll_divider_data) \ | |
1316 | {__VA_ARGS__}) | |
1317 | #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ | |
1318 | &(struct bcm2835_clock_data) \ | |
1319 | {__VA_ARGS__}) | |
1320 | #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ | |
1321 | &(struct bcm2835_gate_data) \ | |
1322 | {__VA_ARGS__}) | |
1323 | ||
1324 | /* parent mux arrays plus helper macros */ | |
1325 | ||
1326 | /* main oscillator parent mux */ | |
1327 | static const char *const bcm2835_clock_osc_parents[] = { | |
1328 | "gnd", | |
1329 | "xosc", | |
1330 | "testdebug0", | |
1331 | "testdebug1" | |
1332 | }; | |
1333 | ||
1334 | #define REGISTER_OSC_CLK(...) REGISTER_CLK( \ | |
1335 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ | |
1336 | .parents = bcm2835_clock_osc_parents, \ | |
1337 | __VA_ARGS__) | |
1338 | ||
1339 | /* main peripherial parent mux */ | |
1340 | static const char *const bcm2835_clock_per_parents[] = { | |
1341 | "gnd", | |
1342 | "xosc", | |
1343 | "testdebug0", | |
1344 | "testdebug1", | |
1345 | "plla_per", | |
1346 | "pllc_per", | |
1347 | "plld_per", | |
1348 | "pllh_aux", | |
1349 | }; | |
1350 | ||
1351 | #define REGISTER_PER_CLK(...) REGISTER_CLK( \ | |
1352 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ | |
1353 | .parents = bcm2835_clock_per_parents, \ | |
1354 | __VA_ARGS__) | |
56eb3a2e | 1355 | |
3b15afef MS |
1356 | /* main vpu parent mux */ |
1357 | static const char *const bcm2835_clock_vpu_parents[] = { | |
1358 | "gnd", | |
1359 | "xosc", | |
1360 | "testdebug0", | |
1361 | "testdebug1", | |
1362 | "plla_core", | |
1363 | "pllc_core0", | |
1364 | "plld_core", | |
1365 | "pllh_aux", | |
1366 | "pllc_core1", | |
1367 | "pllc_core2", | |
1368 | }; | |
1369 | ||
1370 | #define REGISTER_VPU_CLK(...) REGISTER_CLK( \ | |
1371 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ | |
1372 | .parents = bcm2835_clock_vpu_parents, \ | |
1373 | __VA_ARGS__) | |
1374 | ||
1375 | /* | |
1376 | * the real definition of all the pll, pll_dividers and clocks | |
1377 | * these make use of the above REGISTER_* macros | |
1378 | */ | |
56eb3a2e | 1379 | static const struct bcm2835_clk_desc clk_desc_array[] = { |
3b15afef MS |
1380 | /* the PLL + PLL dividers */ |
1381 | ||
1382 | /* | |
1383 | * PLLA is the auxiliary PLL, used to drive the CCP2 | |
1384 | * (Compact Camera Port 2) transmitter clock. | |
1385 | * | |
1386 | * It is in the PX LDO power domain, which is on when the | |
1387 | * AUDIO domain is on. | |
1388 | */ | |
1389 | [BCM2835_PLLA] = REGISTER_PLL( | |
1390 | .name = "plla", | |
1391 | .cm_ctrl_reg = CM_PLLA, | |
1392 | .a2w_ctrl_reg = A2W_PLLA_CTRL, | |
1393 | .frac_reg = A2W_PLLA_FRAC, | |
1394 | .ana_reg_base = A2W_PLLA_ANA0, | |
1395 | .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, | |
1396 | .lock_mask = CM_LOCK_FLOCKA, | |
1397 | ||
1398 | .ana = &bcm2835_ana_default, | |
1399 | ||
1400 | .min_rate = 600000000u, | |
1401 | .max_rate = 2400000000u, | |
1402 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1403 | [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( | |
1404 | .name = "plla_core", | |
1405 | .source_pll = "plla", | |
1406 | .cm_reg = CM_PLLA, | |
1407 | .a2w_reg = A2W_PLLA_CORE, | |
1408 | .load_mask = CM_PLLA_LOADCORE, | |
1409 | .hold_mask = CM_PLLA_HOLDCORE, | |
1410 | .fixed_divider = 1), | |
1411 | [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( | |
1412 | .name = "plla_per", | |
1413 | .source_pll = "plla", | |
1414 | .cm_reg = CM_PLLA, | |
1415 | .a2w_reg = A2W_PLLA_PER, | |
1416 | .load_mask = CM_PLLA_LOADPER, | |
1417 | .hold_mask = CM_PLLA_HOLDPER, | |
1418 | .fixed_divider = 1), | |
72843695 MS |
1419 | [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( |
1420 | .name = "plla_dsi0", | |
1421 | .source_pll = "plla", | |
1422 | .cm_reg = CM_PLLA, | |
1423 | .a2w_reg = A2W_PLLA_DSI0, | |
1424 | .load_mask = CM_PLLA_LOADDSI0, | |
1425 | .hold_mask = CM_PLLA_HOLDDSI0, | |
1426 | .fixed_divider = 1), | |
1427 | [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( | |
1428 | .name = "plla_ccp2", | |
1429 | .source_pll = "plla", | |
1430 | .cm_reg = CM_PLLA, | |
1431 | .a2w_reg = A2W_PLLA_CCP2, | |
1432 | .load_mask = CM_PLLA_LOADCCP2, | |
1433 | .hold_mask = CM_PLLA_HOLDCCP2, | |
1434 | .fixed_divider = 1), | |
3b15afef MS |
1435 | |
1436 | /* PLLB is used for the ARM's clock. */ | |
1437 | [BCM2835_PLLB] = REGISTER_PLL( | |
1438 | .name = "pllb", | |
1439 | .cm_ctrl_reg = CM_PLLB, | |
1440 | .a2w_ctrl_reg = A2W_PLLB_CTRL, | |
1441 | .frac_reg = A2W_PLLB_FRAC, | |
1442 | .ana_reg_base = A2W_PLLB_ANA0, | |
1443 | .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, | |
1444 | .lock_mask = CM_LOCK_FLOCKB, | |
1445 | ||
1446 | .ana = &bcm2835_ana_default, | |
1447 | ||
1448 | .min_rate = 600000000u, | |
1449 | .max_rate = 3000000000u, | |
1450 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1451 | [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( | |
1452 | .name = "pllb_arm", | |
1453 | .source_pll = "pllb", | |
1454 | .cm_reg = CM_PLLB, | |
1455 | .a2w_reg = A2W_PLLB_ARM, | |
1456 | .load_mask = CM_PLLB_LOADARM, | |
1457 | .hold_mask = CM_PLLB_HOLDARM, | |
1458 | .fixed_divider = 1), | |
1459 | ||
1460 | /* | |
1461 | * PLLC is the core PLL, used to drive the core VPU clock. | |
1462 | * | |
1463 | * It is in the PX LDO power domain, which is on when the | |
1464 | * AUDIO domain is on. | |
1465 | */ | |
1466 | [BCM2835_PLLC] = REGISTER_PLL( | |
1467 | .name = "pllc", | |
1468 | .cm_ctrl_reg = CM_PLLC, | |
1469 | .a2w_ctrl_reg = A2W_PLLC_CTRL, | |
1470 | .frac_reg = A2W_PLLC_FRAC, | |
1471 | .ana_reg_base = A2W_PLLC_ANA0, | |
1472 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
1473 | .lock_mask = CM_LOCK_FLOCKC, | |
1474 | ||
1475 | .ana = &bcm2835_ana_default, | |
1476 | ||
1477 | .min_rate = 600000000u, | |
1478 | .max_rate = 3000000000u, | |
1479 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1480 | [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( | |
1481 | .name = "pllc_core0", | |
1482 | .source_pll = "pllc", | |
1483 | .cm_reg = CM_PLLC, | |
1484 | .a2w_reg = A2W_PLLC_CORE0, | |
1485 | .load_mask = CM_PLLC_LOADCORE0, | |
1486 | .hold_mask = CM_PLLC_HOLDCORE0, | |
1487 | .fixed_divider = 1), | |
1488 | [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( | |
1489 | .name = "pllc_core1", | |
1490 | .source_pll = "pllc", | |
1491 | .cm_reg = CM_PLLC, | |
1492 | .a2w_reg = A2W_PLLC_CORE1, | |
1493 | .load_mask = CM_PLLC_LOADCORE1, | |
1494 | .hold_mask = CM_PLLC_HOLDCORE1, | |
1495 | .fixed_divider = 1), | |
1496 | [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( | |
1497 | .name = "pllc_core2", | |
1498 | .source_pll = "pllc", | |
1499 | .cm_reg = CM_PLLC, | |
1500 | .a2w_reg = A2W_PLLC_CORE2, | |
1501 | .load_mask = CM_PLLC_LOADCORE2, | |
1502 | .hold_mask = CM_PLLC_HOLDCORE2, | |
1503 | .fixed_divider = 1), | |
1504 | [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( | |
1505 | .name = "pllc_per", | |
1506 | .source_pll = "pllc", | |
1507 | .cm_reg = CM_PLLC, | |
1508 | .a2w_reg = A2W_PLLC_PER, | |
1509 | .load_mask = CM_PLLC_LOADPER, | |
1510 | .hold_mask = CM_PLLC_HOLDPER, | |
1511 | .fixed_divider = 1), | |
1512 | ||
1513 | /* | |
1514 | * PLLD is the display PLL, used to drive DSI display panels. | |
1515 | * | |
1516 | * It is in the PX LDO power domain, which is on when the | |
1517 | * AUDIO domain is on. | |
1518 | */ | |
1519 | [BCM2835_PLLD] = REGISTER_PLL( | |
1520 | .name = "plld", | |
1521 | .cm_ctrl_reg = CM_PLLD, | |
1522 | .a2w_ctrl_reg = A2W_PLLD_CTRL, | |
1523 | .frac_reg = A2W_PLLD_FRAC, | |
1524 | .ana_reg_base = A2W_PLLD_ANA0, | |
1525 | .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, | |
1526 | .lock_mask = CM_LOCK_FLOCKD, | |
1527 | ||
1528 | .ana = &bcm2835_ana_default, | |
1529 | ||
1530 | .min_rate = 600000000u, | |
1531 | .max_rate = 2400000000u, | |
1532 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1533 | [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( | |
1534 | .name = "plld_core", | |
1535 | .source_pll = "plld", | |
1536 | .cm_reg = CM_PLLD, | |
1537 | .a2w_reg = A2W_PLLD_CORE, | |
1538 | .load_mask = CM_PLLD_LOADCORE, | |
1539 | .hold_mask = CM_PLLD_HOLDCORE, | |
1540 | .fixed_divider = 1), | |
1541 | [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( | |
1542 | .name = "plld_per", | |
1543 | .source_pll = "plld", | |
1544 | .cm_reg = CM_PLLD, | |
1545 | .a2w_reg = A2W_PLLD_PER, | |
1546 | .load_mask = CM_PLLD_LOADPER, | |
1547 | .hold_mask = CM_PLLD_HOLDPER, | |
1548 | .fixed_divider = 1), | |
72843695 MS |
1549 | [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( |
1550 | .name = "plld_dsi0", | |
1551 | .source_pll = "plld", | |
1552 | .cm_reg = CM_PLLD, | |
1553 | .a2w_reg = A2W_PLLD_DSI0, | |
1554 | .load_mask = CM_PLLD_LOADDSI0, | |
1555 | .hold_mask = CM_PLLD_HOLDDSI0, | |
1556 | .fixed_divider = 1), | |
1557 | [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( | |
1558 | .name = "plld_dsi1", | |
1559 | .source_pll = "plld", | |
1560 | .cm_reg = CM_PLLD, | |
1561 | .a2w_reg = A2W_PLLD_DSI1, | |
1562 | .load_mask = CM_PLLD_LOADDSI1, | |
1563 | .hold_mask = CM_PLLD_HOLDDSI1, | |
1564 | .fixed_divider = 1), | |
3b15afef MS |
1565 | |
1566 | /* | |
1567 | * PLLH is used to supply the pixel clock or the AUX clock for the | |
1568 | * TV encoder. | |
1569 | * | |
1570 | * It is in the HDMI power domain. | |
1571 | */ | |
1572 | [BCM2835_PLLH] = REGISTER_PLL( | |
1573 | "pllh", | |
1574 | .cm_ctrl_reg = CM_PLLH, | |
1575 | .a2w_ctrl_reg = A2W_PLLH_CTRL, | |
1576 | .frac_reg = A2W_PLLH_FRAC, | |
1577 | .ana_reg_base = A2W_PLLH_ANA0, | |
1578 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
1579 | .lock_mask = CM_LOCK_FLOCKH, | |
1580 | ||
1581 | .ana = &bcm2835_ana_pllh, | |
1582 | ||
1583 | .min_rate = 600000000u, | |
1584 | .max_rate = 3000000000u, | |
1585 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1586 | [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( | |
1587 | .name = "pllh_rcal", | |
1588 | .source_pll = "pllh", | |
1589 | .cm_reg = CM_PLLH, | |
1590 | .a2w_reg = A2W_PLLH_RCAL, | |
1591 | .load_mask = CM_PLLH_LOADRCAL, | |
1592 | .hold_mask = 0, | |
1593 | .fixed_divider = 10), | |
1594 | [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( | |
1595 | .name = "pllh_aux", | |
1596 | .source_pll = "pllh", | |
1597 | .cm_reg = CM_PLLH, | |
1598 | .a2w_reg = A2W_PLLH_AUX, | |
1599 | .load_mask = CM_PLLH_LOADAUX, | |
1600 | .hold_mask = 0, | |
f2a46926 | 1601 | .fixed_divider = 1), |
3b15afef MS |
1602 | [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( |
1603 | .name = "pllh_pix", | |
1604 | .source_pll = "pllh", | |
1605 | .cm_reg = CM_PLLH, | |
1606 | .a2w_reg = A2W_PLLH_PIX, | |
1607 | .load_mask = CM_PLLH_LOADPIX, | |
1608 | .hold_mask = 0, | |
1609 | .fixed_divider = 10), | |
1610 | ||
56eb3a2e | 1611 | /* the clocks */ |
3b15afef MS |
1612 | |
1613 | /* clocks with oscillator parent mux */ | |
1614 | ||
1615 | /* One Time Programmable Memory clock. Maximum 10Mhz. */ | |
1616 | [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( | |
1617 | .name = "otp", | |
1618 | .ctl_reg = CM_OTPCTL, | |
1619 | .div_reg = CM_OTPDIV, | |
1620 | .int_bits = 4, | |
1621 | .frac_bits = 0), | |
1622 | /* | |
1623 | * Used for a 1Mhz clock for the system clocksource, and also used | |
1624 | * bythe watchdog timer and the camera pulse generator. | |
1625 | */ | |
1626 | [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( | |
1627 | .name = "timer", | |
1628 | .ctl_reg = CM_TIMERCTL, | |
1629 | .div_reg = CM_TIMERDIV, | |
1630 | .int_bits = 6, | |
1631 | .frac_bits = 12), | |
1632 | /* | |
1633 | * Clock for the temperature sensor. | |
1634 | * Generally run at 2Mhz, max 5Mhz. | |
1635 | */ | |
1636 | [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( | |
1637 | .name = "tsens", | |
1638 | .ctl_reg = CM_TSENSCTL, | |
1639 | .div_reg = CM_TSENSDIV, | |
1640 | .int_bits = 5, | |
1641 | .frac_bits = 0), | |
d3d6f15f MS |
1642 | [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( |
1643 | .name = "tec", | |
1644 | .ctl_reg = CM_TECCTL, | |
1645 | .div_reg = CM_TECDIV, | |
1646 | .int_bits = 6, | |
1647 | .frac_bits = 0), | |
3b15afef MS |
1648 | |
1649 | /* clocks with vpu parent mux */ | |
1650 | [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( | |
1651 | .name = "h264", | |
1652 | .ctl_reg = CM_H264CTL, | |
1653 | .div_reg = CM_H264DIV, | |
1654 | .int_bits = 4, | |
1655 | .frac_bits = 8), | |
1656 | [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( | |
1657 | .name = "isp", | |
1658 | .ctl_reg = CM_ISPCTL, | |
1659 | .div_reg = CM_ISPDIV, | |
1660 | .int_bits = 4, | |
1661 | .frac_bits = 8), | |
d3d6f15f | 1662 | |
3b15afef MS |
1663 | /* |
1664 | * Secondary SDRAM clock. Used for low-voltage modes when the PLL | |
1665 | * in the SDRAM controller can't be used. | |
1666 | */ | |
1667 | [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( | |
1668 | .name = "sdram", | |
1669 | .ctl_reg = CM_SDCCTL, | |
1670 | .div_reg = CM_SDCDIV, | |
1671 | .int_bits = 6, | |
1672 | .frac_bits = 0), | |
1673 | [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( | |
1674 | .name = "v3d", | |
1675 | .ctl_reg = CM_V3DCTL, | |
1676 | .div_reg = CM_V3DDIV, | |
1677 | .int_bits = 4, | |
1678 | .frac_bits = 8), | |
1679 | /* | |
1680 | * VPU clock. This doesn't have an enable bit, since it drives | |
1681 | * the bus for everything else, and is special so it doesn't need | |
1682 | * to be gated for rate changes. It is also known as "clk_audio" | |
1683 | * in various hardware documentation. | |
1684 | */ | |
1685 | [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( | |
1686 | .name = "vpu", | |
1687 | .ctl_reg = CM_VPUCTL, | |
1688 | .div_reg = CM_VPUDIV, | |
1689 | .int_bits = 12, | |
1690 | .frac_bits = 8, | |
e69fdcca | 1691 | .flags = CLK_IS_CRITICAL, |
3b15afef MS |
1692 | .is_vpu_clock = true), |
1693 | ||
1694 | /* clocks with per parent mux */ | |
d3d6f15f MS |
1695 | [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( |
1696 | .name = "aveo", | |
1697 | .ctl_reg = CM_AVEOCTL, | |
1698 | .div_reg = CM_AVEODIV, | |
1699 | .int_bits = 4, | |
1700 | .frac_bits = 0), | |
1701 | [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( | |
1702 | .name = "cam0", | |
1703 | .ctl_reg = CM_CAM0CTL, | |
1704 | .div_reg = CM_CAM0DIV, | |
1705 | .int_bits = 4, | |
1706 | .frac_bits = 8), | |
1707 | [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( | |
1708 | .name = "cam1", | |
1709 | .ctl_reg = CM_CAM1CTL, | |
1710 | .div_reg = CM_CAM1DIV, | |
1711 | .int_bits = 4, | |
1712 | .frac_bits = 8), | |
1713 | [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( | |
1714 | .name = "dft", | |
1715 | .ctl_reg = CM_DFTCTL, | |
1716 | .div_reg = CM_DFTDIV, | |
1717 | .int_bits = 5, | |
1718 | .frac_bits = 0), | |
1719 | [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( | |
1720 | .name = "dpi", | |
1721 | .ctl_reg = CM_DPICTL, | |
1722 | .div_reg = CM_DPIDIV, | |
1723 | .int_bits = 4, | |
1724 | .frac_bits = 8), | |
3b15afef MS |
1725 | |
1726 | /* Arasan EMMC clock */ | |
1727 | [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( | |
1728 | .name = "emmc", | |
1729 | .ctl_reg = CM_EMMCCTL, | |
1730 | .div_reg = CM_EMMCDIV, | |
1731 | .int_bits = 4, | |
1732 | .frac_bits = 8), | |
d3d6f15f MS |
1733 | |
1734 | /* General purpose (GPIO) clocks */ | |
1735 | [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( | |
1736 | .name = "gp0", | |
1737 | .ctl_reg = CM_GP0CTL, | |
1738 | .div_reg = CM_GP0DIV, | |
1739 | .int_bits = 12, | |
1740 | .frac_bits = 12, | |
1741 | .is_mash_clock = true), | |
1742 | [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( | |
1743 | .name = "gp1", | |
1744 | .ctl_reg = CM_GP1CTL, | |
1745 | .div_reg = CM_GP1DIV, | |
1746 | .int_bits = 12, | |
1747 | .frac_bits = 12, | |
eddcbe83 | 1748 | .flags = CLK_IS_CRITICAL, |
d3d6f15f MS |
1749 | .is_mash_clock = true), |
1750 | [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( | |
1751 | .name = "gp2", | |
1752 | .ctl_reg = CM_GP2CTL, | |
1753 | .div_reg = CM_GP2DIV, | |
1754 | .int_bits = 12, | |
eddcbe83 EA |
1755 | .frac_bits = 12, |
1756 | .flags = CLK_IS_CRITICAL), | |
d3d6f15f | 1757 | |
3b15afef MS |
1758 | /* HDMI state machine */ |
1759 | [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( | |
1760 | .name = "hsm", | |
1761 | .ctl_reg = CM_HSMCTL, | |
1762 | .div_reg = CM_HSMDIV, | |
1763 | .int_bits = 4, | |
1764 | .frac_bits = 8), | |
33b68960 MS |
1765 | [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK( |
1766 | .name = "pcm", | |
1767 | .ctl_reg = CM_PCMCTL, | |
1768 | .div_reg = CM_PCMDIV, | |
1769 | .int_bits = 12, | |
1770 | .frac_bits = 12, | |
1771 | .is_mash_clock = true), | |
3b15afef MS |
1772 | [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( |
1773 | .name = "pwm", | |
1774 | .ctl_reg = CM_PWMCTL, | |
1775 | .div_reg = CM_PWMDIV, | |
1776 | .int_bits = 12, | |
1777 | .frac_bits = 12, | |
1778 | .is_mash_clock = true), | |
d3d6f15f MS |
1779 | [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( |
1780 | .name = "slim", | |
1781 | .ctl_reg = CM_SLIMCTL, | |
1782 | .div_reg = CM_SLIMDIV, | |
1783 | .int_bits = 12, | |
1784 | .frac_bits = 12, | |
1785 | .is_mash_clock = true), | |
1786 | [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( | |
1787 | .name = "smi", | |
1788 | .ctl_reg = CM_SMICTL, | |
1789 | .div_reg = CM_SMIDIV, | |
1790 | .int_bits = 4, | |
1791 | .frac_bits = 8), | |
3b15afef MS |
1792 | [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( |
1793 | .name = "uart", | |
1794 | .ctl_reg = CM_UARTCTL, | |
1795 | .div_reg = CM_UARTDIV, | |
1796 | .int_bits = 10, | |
1797 | .frac_bits = 12), | |
d3d6f15f | 1798 | |
3b15afef MS |
1799 | /* TV encoder clock. Only operating frequency is 108Mhz. */ |
1800 | [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( | |
1801 | .name = "vec", | |
1802 | .ctl_reg = CM_VECCTL, | |
1803 | .div_reg = CM_VECDIV, | |
1804 | .int_bits = 4, | |
1805 | .frac_bits = 0), | |
1806 | ||
d3d6f15f MS |
1807 | /* dsi clocks */ |
1808 | [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( | |
1809 | .name = "dsi0e", | |
1810 | .ctl_reg = CM_DSI0ECTL, | |
1811 | .div_reg = CM_DSI0EDIV, | |
1812 | .int_bits = 4, | |
1813 | .frac_bits = 8), | |
1814 | [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( | |
1815 | .name = "dsi1e", | |
1816 | .ctl_reg = CM_DSI1ECTL, | |
1817 | .div_reg = CM_DSI1EDIV, | |
1818 | .int_bits = 4, | |
1819 | .frac_bits = 8), | |
1820 | ||
56eb3a2e | 1821 | /* the gates */ |
3b15afef MS |
1822 | |
1823 | /* | |
1824 | * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if | |
1825 | * you have the debug bit set in the power manager, which we | |
1826 | * don't bother exposing) are individual gates off of the | |
1827 | * non-stop vpu clock. | |
1828 | */ | |
56eb3a2e | 1829 | [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( |
3b15afef MS |
1830 | .name = "peri_image", |
1831 | .parent = "vpu", | |
1832 | .ctl_reg = CM_PERIICTL), | |
56eb3a2e MS |
1833 | }; |
1834 | ||
9e400c5c EA |
1835 | /* |
1836 | * Permanently take a reference on the parent of the SDRAM clock. | |
1837 | * | |
1838 | * While the SDRAM is being driven by its dedicated PLL most of the | |
1839 | * time, there is a little loop running in the firmware that | |
1840 | * periodically switches the SDRAM to using our CM clock to do PVT | |
1841 | * recalibration, with the assumption that the previously configured | |
1842 | * SDRAM parent is still enabled and running. | |
1843 | */ | |
1844 | static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) | |
1845 | { | |
1846 | struct clk *parent = clk_get_parent(sdc); | |
1847 | ||
1848 | if (IS_ERR(parent)) | |
1849 | return PTR_ERR(parent); | |
1850 | ||
1851 | return clk_prepare_enable(parent); | |
1852 | } | |
1853 | ||
41691b88 EA |
1854 | static int bcm2835_clk_probe(struct platform_device *pdev) |
1855 | { | |
1856 | struct device *dev = &pdev->dev; | |
b19f009d | 1857 | struct clk_hw **hws; |
41691b88 EA |
1858 | struct bcm2835_cprman *cprman; |
1859 | struct resource *res; | |
56eb3a2e MS |
1860 | const struct bcm2835_clk_desc *desc; |
1861 | const size_t asize = ARRAY_SIZE(clk_desc_array); | |
1862 | size_t i; | |
9e400c5c | 1863 | int ret; |
41691b88 | 1864 | |
b19f009d SB |
1865 | cprman = devm_kzalloc(dev, sizeof(*cprman) + |
1866 | sizeof(*cprman->onecell.hws) * asize, | |
56eb3a2e | 1867 | GFP_KERNEL); |
41691b88 EA |
1868 | if (!cprman) |
1869 | return -ENOMEM; | |
1870 | ||
1871 | spin_lock_init(&cprman->regs_lock); | |
1872 | cprman->dev = dev; | |
1873 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1874 | cprman->regs = devm_ioremap_resource(dev, res); | |
1875 | if (IS_ERR(cprman->regs)) | |
1876 | return PTR_ERR(cprman->regs); | |
1877 | ||
1878 | cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0); | |
1879 | if (!cprman->osc_name) | |
1880 | return -ENODEV; | |
1881 | ||
1882 | platform_set_drvdata(pdev, cprman); | |
1883 | ||
b19f009d SB |
1884 | cprman->onecell.num = asize; |
1885 | hws = cprman->onecell.hws; | |
41691b88 | 1886 | |
56eb3a2e MS |
1887 | for (i = 0; i < asize; i++) { |
1888 | desc = &clk_desc_array[i]; | |
1889 | if (desc->clk_register && desc->data) | |
b19f009d | 1890 | hws[i] = desc->clk_register(cprman, desc->data); |
56eb3a2e | 1891 | } |
cfbab8fb | 1892 | |
b19f009d | 1893 | ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); |
9e400c5c EA |
1894 | if (ret) |
1895 | return ret; | |
1896 | ||
b19f009d SB |
1897 | return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, |
1898 | &cprman->onecell); | |
41691b88 EA |
1899 | } |
1900 | ||
1901 | static const struct of_device_id bcm2835_clk_of_match[] = { | |
1902 | { .compatible = "brcm,bcm2835-cprman", }, | |
1903 | {} | |
1904 | }; | |
1905 | MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); | |
1906 | ||
1907 | static struct platform_driver bcm2835_clk_driver = { | |
1908 | .driver = { | |
1909 | .name = "bcm2835-clk", | |
1910 | .of_match_table = bcm2835_clk_of_match, | |
1911 | }, | |
1912 | .probe = bcm2835_clk_probe, | |
1913 | }; | |
1914 | ||
1915 | builtin_platform_driver(bcm2835_clk_driver); | |
1916 | ||
1917 | MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); | |
1918 | MODULE_DESCRIPTION("BCM2835 clock driver"); | |
1919 | MODULE_LICENSE("GPL v2"); |