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75fabc3f | 1 | /* |
41691b88 | 2 | * Copyright (C) 2010,2015 Broadcom |
75fabc3f SA |
3 | * Copyright (C) 2012 Stephen Warren |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
75fabc3f SA |
15 | */ |
16 | ||
41691b88 EA |
17 | /** |
18 | * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) | |
19 | * | |
20 | * The clock tree on the 2835 has several levels. There's a root | |
21 | * oscillator running at 19.2Mhz. After the oscillator there are 5 | |
22 | * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", | |
23 | * and "HDMI displays". Those 5 PLLs each can divide their output to | |
24 | * produce up to 4 channels. Finally, there is the level of clocks to | |
25 | * be consumed by other hardware components (like "H264" or "HDMI | |
26 | * state machine"), which divide off of some subset of the PLL | |
27 | * channels. | |
28 | * | |
29 | * All of the clocks in the tree are exposed in the DT, because the DT | |
30 | * may want to make assignments of the final layer of clocks to the | |
31 | * PLL channels, and some components of the hardware will actually | |
32 | * skip layers of the tree (for example, the pixel clock comes | |
33 | * directly from the PLLH PIX channel without using a CM_*CTL clock | |
34 | * generator). | |
35 | */ | |
36 | ||
75fabc3f SA |
37 | #include <linux/clk-provider.h> |
38 | #include <linux/clkdev.h> | |
39 | #include <linux/clk/bcm2835.h> | |
41691b88 | 40 | #include <linux/module.h> |
526d239c | 41 | #include <linux/of.h> |
41691b88 EA |
42 | #include <linux/platform_device.h> |
43 | #include <linux/slab.h> | |
44 | #include <dt-bindings/clock/bcm2835.h> | |
45 | ||
46 | #define CM_PASSWORD 0x5a000000 | |
47 | ||
48 | #define CM_GNRICCTL 0x000 | |
49 | #define CM_GNRICDIV 0x004 | |
50 | # define CM_DIV_FRAC_BITS 12 | |
959ca92a | 51 | # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) |
41691b88 EA |
52 | |
53 | #define CM_VPUCTL 0x008 | |
54 | #define CM_VPUDIV 0x00c | |
55 | #define CM_SYSCTL 0x010 | |
56 | #define CM_SYSDIV 0x014 | |
57 | #define CM_PERIACTL 0x018 | |
58 | #define CM_PERIADIV 0x01c | |
59 | #define CM_PERIICTL 0x020 | |
60 | #define CM_PERIIDIV 0x024 | |
61 | #define CM_H264CTL 0x028 | |
62 | #define CM_H264DIV 0x02c | |
63 | #define CM_ISPCTL 0x030 | |
64 | #define CM_ISPDIV 0x034 | |
65 | #define CM_V3DCTL 0x038 | |
66 | #define CM_V3DDIV 0x03c | |
67 | #define CM_CAM0CTL 0x040 | |
68 | #define CM_CAM0DIV 0x044 | |
69 | #define CM_CAM1CTL 0x048 | |
70 | #define CM_CAM1DIV 0x04c | |
71 | #define CM_CCP2CTL 0x050 | |
72 | #define CM_CCP2DIV 0x054 | |
73 | #define CM_DSI0ECTL 0x058 | |
74 | #define CM_DSI0EDIV 0x05c | |
75 | #define CM_DSI0PCTL 0x060 | |
76 | #define CM_DSI0PDIV 0x064 | |
77 | #define CM_DPICTL 0x068 | |
78 | #define CM_DPIDIV 0x06c | |
79 | #define CM_GP0CTL 0x070 | |
80 | #define CM_GP0DIV 0x074 | |
81 | #define CM_GP1CTL 0x078 | |
82 | #define CM_GP1DIV 0x07c | |
83 | #define CM_GP2CTL 0x080 | |
84 | #define CM_GP2DIV 0x084 | |
85 | #define CM_HSMCTL 0x088 | |
86 | #define CM_HSMDIV 0x08c | |
87 | #define CM_OTPCTL 0x090 | |
88 | #define CM_OTPDIV 0x094 | |
2103a215 MS |
89 | #define CM_PCMCTL 0x098 |
90 | #define CM_PCMDIV 0x09c | |
41691b88 EA |
91 | #define CM_PWMCTL 0x0a0 |
92 | #define CM_PWMDIV 0x0a4 | |
2103a215 MS |
93 | #define CM_SLIMCTL 0x0a8 |
94 | #define CM_SLIMDIV 0x0ac | |
41691b88 EA |
95 | #define CM_SMICTL 0x0b0 |
96 | #define CM_SMIDIV 0x0b4 | |
2103a215 MS |
97 | /* no definition for 0x0b8 and 0x0bc */ |
98 | #define CM_TCNTCTL 0x0c0 | |
99 | #define CM_TCNTDIV 0x0c4 | |
100 | #define CM_TECCTL 0x0c8 | |
101 | #define CM_TECDIV 0x0cc | |
102 | #define CM_TD0CTL 0x0d0 | |
103 | #define CM_TD0DIV 0x0d4 | |
104 | #define CM_TD1CTL 0x0d8 | |
105 | #define CM_TD1DIV 0x0dc | |
41691b88 EA |
106 | #define CM_TSENSCTL 0x0e0 |
107 | #define CM_TSENSDIV 0x0e4 | |
108 | #define CM_TIMERCTL 0x0e8 | |
109 | #define CM_TIMERDIV 0x0ec | |
110 | #define CM_UARTCTL 0x0f0 | |
111 | #define CM_UARTDIV 0x0f4 | |
112 | #define CM_VECCTL 0x0f8 | |
113 | #define CM_VECDIV 0x0fc | |
114 | #define CM_PULSECTL 0x190 | |
115 | #define CM_PULSEDIV 0x194 | |
116 | #define CM_SDCCTL 0x1a8 | |
117 | #define CM_SDCDIV 0x1ac | |
118 | #define CM_ARMCTL 0x1b0 | |
119 | #define CM_EMMCCTL 0x1c0 | |
120 | #define CM_EMMCDIV 0x1c4 | |
121 | ||
122 | /* General bits for the CM_*CTL regs */ | |
123 | # define CM_ENABLE BIT(4) | |
124 | # define CM_KILL BIT(5) | |
125 | # define CM_GATE_BIT 6 | |
126 | # define CM_GATE BIT(CM_GATE_BIT) | |
127 | # define CM_BUSY BIT(7) | |
128 | # define CM_BUSYD BIT(8) | |
959ca92a | 129 | # define CM_FRAC BIT(9) |
41691b88 EA |
130 | # define CM_SRC_SHIFT 0 |
131 | # define CM_SRC_BITS 4 | |
132 | # define CM_SRC_MASK 0xf | |
133 | # define CM_SRC_GND 0 | |
134 | # define CM_SRC_OSC 1 | |
135 | # define CM_SRC_TESTDEBUG0 2 | |
136 | # define CM_SRC_TESTDEBUG1 3 | |
137 | # define CM_SRC_PLLA_CORE 4 | |
138 | # define CM_SRC_PLLA_PER 4 | |
139 | # define CM_SRC_PLLC_CORE0 5 | |
140 | # define CM_SRC_PLLC_PER 5 | |
141 | # define CM_SRC_PLLC_CORE1 8 | |
142 | # define CM_SRC_PLLD_CORE 6 | |
143 | # define CM_SRC_PLLD_PER 6 | |
144 | # define CM_SRC_PLLH_AUX 7 | |
145 | # define CM_SRC_PLLC_CORE1 8 | |
146 | # define CM_SRC_PLLC_CORE2 9 | |
147 | ||
148 | #define CM_OSCCOUNT 0x100 | |
149 | ||
150 | #define CM_PLLA 0x104 | |
151 | # define CM_PLL_ANARST BIT(8) | |
152 | # define CM_PLLA_HOLDPER BIT(7) | |
153 | # define CM_PLLA_LOADPER BIT(6) | |
154 | # define CM_PLLA_HOLDCORE BIT(5) | |
155 | # define CM_PLLA_LOADCORE BIT(4) | |
156 | # define CM_PLLA_HOLDCCP2 BIT(3) | |
157 | # define CM_PLLA_LOADCCP2 BIT(2) | |
158 | # define CM_PLLA_HOLDDSI0 BIT(1) | |
159 | # define CM_PLLA_LOADDSI0 BIT(0) | |
160 | ||
161 | #define CM_PLLC 0x108 | |
162 | # define CM_PLLC_HOLDPER BIT(7) | |
163 | # define CM_PLLC_LOADPER BIT(6) | |
164 | # define CM_PLLC_HOLDCORE2 BIT(5) | |
165 | # define CM_PLLC_LOADCORE2 BIT(4) | |
166 | # define CM_PLLC_HOLDCORE1 BIT(3) | |
167 | # define CM_PLLC_LOADCORE1 BIT(2) | |
168 | # define CM_PLLC_HOLDCORE0 BIT(1) | |
169 | # define CM_PLLC_LOADCORE0 BIT(0) | |
170 | ||
171 | #define CM_PLLD 0x10c | |
172 | # define CM_PLLD_HOLDPER BIT(7) | |
173 | # define CM_PLLD_LOADPER BIT(6) | |
174 | # define CM_PLLD_HOLDCORE BIT(5) | |
175 | # define CM_PLLD_LOADCORE BIT(4) | |
176 | # define CM_PLLD_HOLDDSI1 BIT(3) | |
177 | # define CM_PLLD_LOADDSI1 BIT(2) | |
178 | # define CM_PLLD_HOLDDSI0 BIT(1) | |
179 | # define CM_PLLD_LOADDSI0 BIT(0) | |
180 | ||
181 | #define CM_PLLH 0x110 | |
182 | # define CM_PLLH_LOADRCAL BIT(2) | |
183 | # define CM_PLLH_LOADAUX BIT(1) | |
184 | # define CM_PLLH_LOADPIX BIT(0) | |
185 | ||
186 | #define CM_LOCK 0x114 | |
187 | # define CM_LOCK_FLOCKH BIT(12) | |
188 | # define CM_LOCK_FLOCKD BIT(11) | |
189 | # define CM_LOCK_FLOCKC BIT(10) | |
190 | # define CM_LOCK_FLOCKB BIT(9) | |
191 | # define CM_LOCK_FLOCKA BIT(8) | |
192 | ||
193 | #define CM_EVENT 0x118 | |
194 | #define CM_DSI1ECTL 0x158 | |
195 | #define CM_DSI1EDIV 0x15c | |
196 | #define CM_DSI1PCTL 0x160 | |
197 | #define CM_DSI1PDIV 0x164 | |
198 | #define CM_DFTCTL 0x168 | |
199 | #define CM_DFTDIV 0x16c | |
200 | ||
201 | #define CM_PLLB 0x170 | |
202 | # define CM_PLLB_HOLDARM BIT(1) | |
203 | # define CM_PLLB_LOADARM BIT(0) | |
204 | ||
205 | #define A2W_PLLA_CTRL 0x1100 | |
206 | #define A2W_PLLC_CTRL 0x1120 | |
207 | #define A2W_PLLD_CTRL 0x1140 | |
208 | #define A2W_PLLH_CTRL 0x1160 | |
209 | #define A2W_PLLB_CTRL 0x11e0 | |
210 | # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) | |
211 | # define A2W_PLL_CTRL_PWRDN BIT(16) | |
212 | # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 | |
213 | # define A2W_PLL_CTRL_PDIV_SHIFT 12 | |
214 | # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff | |
215 | # define A2W_PLL_CTRL_NDIV_SHIFT 0 | |
216 | ||
217 | #define A2W_PLLA_ANA0 0x1010 | |
218 | #define A2W_PLLC_ANA0 0x1030 | |
219 | #define A2W_PLLD_ANA0 0x1050 | |
220 | #define A2W_PLLH_ANA0 0x1070 | |
221 | #define A2W_PLLB_ANA0 0x10f0 | |
222 | ||
223 | #define A2W_PLL_KA_SHIFT 7 | |
224 | #define A2W_PLL_KA_MASK GENMASK(9, 7) | |
225 | #define A2W_PLL_KI_SHIFT 19 | |
226 | #define A2W_PLL_KI_MASK GENMASK(21, 19) | |
227 | #define A2W_PLL_KP_SHIFT 15 | |
228 | #define A2W_PLL_KP_MASK GENMASK(18, 15) | |
229 | ||
230 | #define A2W_PLLH_KA_SHIFT 19 | |
231 | #define A2W_PLLH_KA_MASK GENMASK(21, 19) | |
232 | #define A2W_PLLH_KI_LOW_SHIFT 22 | |
233 | #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) | |
234 | #define A2W_PLLH_KI_HIGH_SHIFT 0 | |
235 | #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) | |
236 | #define A2W_PLLH_KP_SHIFT 1 | |
237 | #define A2W_PLLH_KP_MASK GENMASK(4, 1) | |
238 | ||
239 | #define A2W_XOSC_CTRL 0x1190 | |
240 | # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) | |
241 | # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) | |
242 | # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) | |
243 | # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) | |
244 | # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) | |
245 | # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) | |
246 | # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) | |
247 | # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) | |
248 | ||
249 | #define A2W_PLLA_FRAC 0x1200 | |
250 | #define A2W_PLLC_FRAC 0x1220 | |
251 | #define A2W_PLLD_FRAC 0x1240 | |
252 | #define A2W_PLLH_FRAC 0x1260 | |
253 | #define A2W_PLLB_FRAC 0x12e0 | |
254 | # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) | |
255 | # define A2W_PLL_FRAC_BITS 20 | |
256 | ||
257 | #define A2W_PLL_CHANNEL_DISABLE BIT(8) | |
258 | #define A2W_PLL_DIV_BITS 8 | |
259 | #define A2W_PLL_DIV_SHIFT 0 | |
260 | ||
261 | #define A2W_PLLA_DSI0 0x1300 | |
262 | #define A2W_PLLA_CORE 0x1400 | |
263 | #define A2W_PLLA_PER 0x1500 | |
264 | #define A2W_PLLA_CCP2 0x1600 | |
265 | ||
266 | #define A2W_PLLC_CORE2 0x1320 | |
267 | #define A2W_PLLC_CORE1 0x1420 | |
268 | #define A2W_PLLC_PER 0x1520 | |
269 | #define A2W_PLLC_CORE0 0x1620 | |
270 | ||
271 | #define A2W_PLLD_DSI0 0x1340 | |
272 | #define A2W_PLLD_CORE 0x1440 | |
273 | #define A2W_PLLD_PER 0x1540 | |
274 | #define A2W_PLLD_DSI1 0x1640 | |
275 | ||
276 | #define A2W_PLLH_AUX 0x1360 | |
277 | #define A2W_PLLH_RCAL 0x1460 | |
278 | #define A2W_PLLH_PIX 0x1560 | |
279 | #define A2W_PLLH_STS 0x1660 | |
280 | ||
281 | #define A2W_PLLH_CTRLR 0x1960 | |
282 | #define A2W_PLLH_FRACR 0x1a60 | |
283 | #define A2W_PLLH_AUXR 0x1b60 | |
284 | #define A2W_PLLH_RCALR 0x1c60 | |
285 | #define A2W_PLLH_PIXR 0x1d60 | |
286 | #define A2W_PLLH_STSR 0x1e60 | |
287 | ||
288 | #define A2W_PLLB_ARM 0x13e0 | |
289 | #define A2W_PLLB_SP0 0x14e0 | |
290 | #define A2W_PLLB_SP1 0x15e0 | |
291 | #define A2W_PLLB_SP2 0x16e0 | |
292 | ||
293 | #define LOCK_TIMEOUT_NS 100000000 | |
294 | #define BCM2835_MAX_FB_RATE 1750000000u | |
295 | ||
296 | struct bcm2835_cprman { | |
297 | struct device *dev; | |
298 | void __iomem *regs; | |
6e1e60da | 299 | spinlock_t regs_lock; /* spinlock for all clocks */ |
41691b88 EA |
300 | const char *osc_name; |
301 | ||
302 | struct clk_onecell_data onecell; | |
303 | struct clk *clks[BCM2835_CLOCK_COUNT]; | |
304 | }; | |
305 | ||
306 | static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) | |
307 | { | |
308 | writel(CM_PASSWORD | val, cprman->regs + reg); | |
309 | } | |
310 | ||
311 | static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) | |
312 | { | |
313 | return readl(cprman->regs + reg); | |
314 | } | |
526d239c | 315 | |
75fabc3f SA |
316 | /* |
317 | * These are fixed clocks. They're probably not all root clocks and it may | |
318 | * be possible to turn them on and off but until this is mapped out better | |
319 | * it's the only way they can be used. | |
320 | */ | |
321 | void __init bcm2835_init_clocks(void) | |
322 | { | |
323 | struct clk *clk; | |
324 | int ret; | |
325 | ||
bd41aa67 | 326 | clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); |
0de9f23a | 327 | if (IS_ERR(clk)) |
75fabc3f SA |
328 | pr_err("apb_pclk not registered\n"); |
329 | ||
bd41aa67 | 330 | clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); |
0de9f23a | 331 | if (IS_ERR(clk)) |
75fabc3f SA |
332 | pr_err("uart0_pclk not registered\n"); |
333 | ret = clk_register_clkdev(clk, NULL, "20201000.uart"); | |
334 | if (ret) | |
335 | pr_err("uart0_pclk alias not registered\n"); | |
336 | ||
bd41aa67 | 337 | clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); |
0de9f23a | 338 | if (IS_ERR(clk)) |
75fabc3f SA |
339 | pr_err("uart1_pclk not registered\n"); |
340 | ret = clk_register_clkdev(clk, NULL, "20215000.uart"); | |
341 | if (ret) | |
686ea585 | 342 | pr_err("uart1_pclk alias not registered\n"); |
75fabc3f | 343 | } |
41691b88 EA |
344 | |
345 | struct bcm2835_pll_data { | |
346 | const char *name; | |
347 | u32 cm_ctrl_reg; | |
348 | u32 a2w_ctrl_reg; | |
349 | u32 frac_reg; | |
350 | u32 ana_reg_base; | |
351 | u32 reference_enable_mask; | |
352 | /* Bit in CM_LOCK to indicate when the PLL has locked. */ | |
353 | u32 lock_mask; | |
354 | ||
355 | const struct bcm2835_pll_ana_bits *ana; | |
356 | ||
357 | unsigned long min_rate; | |
358 | unsigned long max_rate; | |
359 | /* | |
360 | * Highest rate for the VCO before we have to use the | |
361 | * pre-divide-by-2. | |
362 | */ | |
363 | unsigned long max_fb_rate; | |
364 | }; | |
365 | ||
366 | struct bcm2835_pll_ana_bits { | |
367 | u32 mask0; | |
368 | u32 set0; | |
369 | u32 mask1; | |
370 | u32 set1; | |
371 | u32 mask3; | |
372 | u32 set3; | |
373 | u32 fb_prediv_mask; | |
374 | }; | |
375 | ||
376 | static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { | |
377 | .mask0 = 0, | |
378 | .set0 = 0, | |
379 | .mask1 = ~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK), | |
380 | .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), | |
381 | .mask3 = ~A2W_PLL_KA_MASK, | |
382 | .set3 = (2 << A2W_PLL_KA_SHIFT), | |
383 | .fb_prediv_mask = BIT(14), | |
384 | }; | |
385 | ||
386 | static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { | |
387 | .mask0 = ~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK), | |
388 | .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), | |
389 | .mask1 = ~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK), | |
390 | .set1 = (6 << A2W_PLLH_KP_SHIFT), | |
391 | .mask3 = 0, | |
392 | .set3 = 0, | |
393 | .fb_prediv_mask = BIT(11), | |
394 | }; | |
395 | ||
396 | /* | |
397 | * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera | |
398 | * Port 2) transmitter clock. | |
399 | * | |
400 | * It is in the PX LDO power domain, which is on when the AUDIO domain | |
401 | * is on. | |
402 | */ | |
403 | static const struct bcm2835_pll_data bcm2835_plla_data = { | |
404 | .name = "plla", | |
405 | .cm_ctrl_reg = CM_PLLA, | |
406 | .a2w_ctrl_reg = A2W_PLLA_CTRL, | |
407 | .frac_reg = A2W_PLLA_FRAC, | |
408 | .ana_reg_base = A2W_PLLA_ANA0, | |
409 | .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, | |
410 | .lock_mask = CM_LOCK_FLOCKA, | |
411 | ||
412 | .ana = &bcm2835_ana_default, | |
413 | ||
414 | .min_rate = 600000000u, | |
415 | .max_rate = 2400000000u, | |
416 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
417 | }; | |
418 | ||
419 | /* PLLB is used for the ARM's clock. */ | |
420 | static const struct bcm2835_pll_data bcm2835_pllb_data = { | |
421 | .name = "pllb", | |
422 | .cm_ctrl_reg = CM_PLLB, | |
423 | .a2w_ctrl_reg = A2W_PLLB_CTRL, | |
424 | .frac_reg = A2W_PLLB_FRAC, | |
425 | .ana_reg_base = A2W_PLLB_ANA0, | |
426 | .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, | |
427 | .lock_mask = CM_LOCK_FLOCKB, | |
428 | ||
429 | .ana = &bcm2835_ana_default, | |
430 | ||
431 | .min_rate = 600000000u, | |
432 | .max_rate = 3000000000u, | |
433 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
434 | }; | |
435 | ||
436 | /* | |
437 | * PLLC is the core PLL, used to drive the core VPU clock. | |
438 | * | |
439 | * It is in the PX LDO power domain, which is on when the AUDIO domain | |
440 | * is on. | |
441 | */ | |
442 | static const struct bcm2835_pll_data bcm2835_pllc_data = { | |
443 | .name = "pllc", | |
444 | .cm_ctrl_reg = CM_PLLC, | |
445 | .a2w_ctrl_reg = A2W_PLLC_CTRL, | |
446 | .frac_reg = A2W_PLLC_FRAC, | |
447 | .ana_reg_base = A2W_PLLC_ANA0, | |
448 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
449 | .lock_mask = CM_LOCK_FLOCKC, | |
450 | ||
451 | .ana = &bcm2835_ana_default, | |
452 | ||
453 | .min_rate = 600000000u, | |
454 | .max_rate = 3000000000u, | |
455 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
456 | }; | |
457 | ||
458 | /* | |
459 | * PLLD is the display PLL, used to drive DSI display panels. | |
460 | * | |
461 | * It is in the PX LDO power domain, which is on when the AUDIO domain | |
462 | * is on. | |
463 | */ | |
464 | static const struct bcm2835_pll_data bcm2835_plld_data = { | |
465 | .name = "plld", | |
466 | .cm_ctrl_reg = CM_PLLD, | |
467 | .a2w_ctrl_reg = A2W_PLLD_CTRL, | |
468 | .frac_reg = A2W_PLLD_FRAC, | |
469 | .ana_reg_base = A2W_PLLD_ANA0, | |
470 | .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, | |
471 | .lock_mask = CM_LOCK_FLOCKD, | |
472 | ||
473 | .ana = &bcm2835_ana_default, | |
474 | ||
475 | .min_rate = 600000000u, | |
476 | .max_rate = 2400000000u, | |
477 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
478 | }; | |
479 | ||
480 | /* | |
481 | * PLLH is used to supply the pixel clock or the AUX clock for the TV | |
482 | * encoder. | |
483 | * | |
484 | * It is in the HDMI power domain. | |
485 | */ | |
486 | static const struct bcm2835_pll_data bcm2835_pllh_data = { | |
487 | "pllh", | |
488 | .cm_ctrl_reg = CM_PLLH, | |
489 | .a2w_ctrl_reg = A2W_PLLH_CTRL, | |
490 | .frac_reg = A2W_PLLH_FRAC, | |
491 | .ana_reg_base = A2W_PLLH_ANA0, | |
492 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
493 | .lock_mask = CM_LOCK_FLOCKH, | |
494 | ||
495 | .ana = &bcm2835_ana_pllh, | |
496 | ||
497 | .min_rate = 600000000u, | |
498 | .max_rate = 3000000000u, | |
499 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
500 | }; | |
501 | ||
502 | struct bcm2835_pll_divider_data { | |
503 | const char *name; | |
504 | const struct bcm2835_pll_data *source_pll; | |
505 | u32 cm_reg; | |
506 | u32 a2w_reg; | |
507 | ||
508 | u32 load_mask; | |
509 | u32 hold_mask; | |
510 | u32 fixed_divider; | |
511 | }; | |
512 | ||
513 | static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = { | |
514 | .name = "plla_core", | |
515 | .source_pll = &bcm2835_plla_data, | |
516 | .cm_reg = CM_PLLA, | |
517 | .a2w_reg = A2W_PLLA_CORE, | |
518 | .load_mask = CM_PLLA_LOADCORE, | |
519 | .hold_mask = CM_PLLA_HOLDCORE, | |
520 | .fixed_divider = 1, | |
521 | }; | |
522 | ||
523 | static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = { | |
524 | .name = "plla_per", | |
525 | .source_pll = &bcm2835_plla_data, | |
526 | .cm_reg = CM_PLLA, | |
527 | .a2w_reg = A2W_PLLA_PER, | |
528 | .load_mask = CM_PLLA_LOADPER, | |
529 | .hold_mask = CM_PLLA_HOLDPER, | |
530 | .fixed_divider = 1, | |
531 | }; | |
532 | ||
533 | static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = { | |
534 | .name = "pllb_arm", | |
535 | .source_pll = &bcm2835_pllb_data, | |
536 | .cm_reg = CM_PLLB, | |
537 | .a2w_reg = A2W_PLLB_ARM, | |
538 | .load_mask = CM_PLLB_LOADARM, | |
539 | .hold_mask = CM_PLLB_HOLDARM, | |
540 | .fixed_divider = 1, | |
541 | }; | |
542 | ||
543 | static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = { | |
544 | .name = "pllc_core0", | |
545 | .source_pll = &bcm2835_pllc_data, | |
546 | .cm_reg = CM_PLLC, | |
547 | .a2w_reg = A2W_PLLC_CORE0, | |
548 | .load_mask = CM_PLLC_LOADCORE0, | |
549 | .hold_mask = CM_PLLC_HOLDCORE0, | |
550 | .fixed_divider = 1, | |
551 | }; | |
552 | ||
553 | static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = { | |
554 | .name = "pllc_core1", .source_pll = &bcm2835_pllc_data, | |
555 | .cm_reg = CM_PLLC, A2W_PLLC_CORE1, | |
556 | .load_mask = CM_PLLC_LOADCORE1, | |
557 | .hold_mask = CM_PLLC_HOLDCORE1, | |
558 | .fixed_divider = 1, | |
559 | }; | |
560 | ||
561 | static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = { | |
562 | .name = "pllc_core2", | |
563 | .source_pll = &bcm2835_pllc_data, | |
564 | .cm_reg = CM_PLLC, | |
565 | .a2w_reg = A2W_PLLC_CORE2, | |
566 | .load_mask = CM_PLLC_LOADCORE2, | |
567 | .hold_mask = CM_PLLC_HOLDCORE2, | |
568 | .fixed_divider = 1, | |
569 | }; | |
570 | ||
571 | static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = { | |
572 | .name = "pllc_per", | |
573 | .source_pll = &bcm2835_pllc_data, | |
574 | .cm_reg = CM_PLLC, | |
575 | .a2w_reg = A2W_PLLC_PER, | |
576 | .load_mask = CM_PLLC_LOADPER, | |
577 | .hold_mask = CM_PLLC_HOLDPER, | |
578 | .fixed_divider = 1, | |
579 | }; | |
580 | ||
581 | static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = { | |
582 | .name = "plld_core", | |
583 | .source_pll = &bcm2835_plld_data, | |
584 | .cm_reg = CM_PLLD, | |
585 | .a2w_reg = A2W_PLLD_CORE, | |
586 | .load_mask = CM_PLLD_LOADCORE, | |
587 | .hold_mask = CM_PLLD_HOLDCORE, | |
588 | .fixed_divider = 1, | |
589 | }; | |
590 | ||
591 | static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = { | |
592 | .name = "plld_per", | |
593 | .source_pll = &bcm2835_plld_data, | |
594 | .cm_reg = CM_PLLD, | |
595 | .a2w_reg = A2W_PLLD_PER, | |
596 | .load_mask = CM_PLLD_LOADPER, | |
597 | .hold_mask = CM_PLLD_HOLDPER, | |
598 | .fixed_divider = 1, | |
599 | }; | |
600 | ||
601 | static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = { | |
602 | .name = "pllh_rcal", | |
603 | .source_pll = &bcm2835_pllh_data, | |
604 | .cm_reg = CM_PLLH, | |
605 | .a2w_reg = A2W_PLLH_RCAL, | |
606 | .load_mask = CM_PLLH_LOADRCAL, | |
607 | .hold_mask = 0, | |
608 | .fixed_divider = 10, | |
609 | }; | |
610 | ||
611 | static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = { | |
612 | .name = "pllh_aux", | |
613 | .source_pll = &bcm2835_pllh_data, | |
614 | .cm_reg = CM_PLLH, | |
615 | .a2w_reg = A2W_PLLH_AUX, | |
616 | .load_mask = CM_PLLH_LOADAUX, | |
617 | .hold_mask = 0, | |
618 | .fixed_divider = 10, | |
619 | }; | |
620 | ||
621 | static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = { | |
622 | .name = "pllh_pix", | |
623 | .source_pll = &bcm2835_pllh_data, | |
624 | .cm_reg = CM_PLLH, | |
625 | .a2w_reg = A2W_PLLH_PIX, | |
626 | .load_mask = CM_PLLH_LOADPIX, | |
627 | .hold_mask = 0, | |
628 | .fixed_divider = 10, | |
629 | }; | |
630 | ||
631 | struct bcm2835_clock_data { | |
632 | const char *name; | |
633 | ||
634 | const char *const *parents; | |
635 | int num_mux_parents; | |
636 | ||
637 | u32 ctl_reg; | |
638 | u32 div_reg; | |
639 | ||
640 | /* Number of integer bits in the divider */ | |
641 | u32 int_bits; | |
642 | /* Number of fractional bits in the divider */ | |
643 | u32 frac_bits; | |
644 | ||
645 | bool is_vpu_clock; | |
959ca92a | 646 | bool is_mash_clock; |
41691b88 EA |
647 | }; |
648 | ||
649 | static const char *const bcm2835_clock_per_parents[] = { | |
650 | "gnd", | |
651 | "xosc", | |
652 | "testdebug0", | |
653 | "testdebug1", | |
654 | "plla_per", | |
655 | "pllc_per", | |
656 | "plld_per", | |
657 | "pllh_aux", | |
658 | }; | |
659 | ||
660 | static const char *const bcm2835_clock_vpu_parents[] = { | |
661 | "gnd", | |
662 | "xosc", | |
663 | "testdebug0", | |
664 | "testdebug1", | |
665 | "plla_core", | |
666 | "pllc_core0", | |
667 | "plld_core", | |
668 | "pllh_aux", | |
669 | "pllc_core1", | |
670 | "pllc_core2", | |
671 | }; | |
672 | ||
673 | static const char *const bcm2835_clock_osc_parents[] = { | |
674 | "gnd", | |
675 | "xosc", | |
676 | "testdebug0", | |
677 | "testdebug1" | |
678 | }; | |
679 | ||
680 | /* | |
681 | * Used for a 1Mhz clock for the system clocksource, and also used by | |
682 | * the watchdog timer and the camera pulse generator. | |
683 | */ | |
684 | static const struct bcm2835_clock_data bcm2835_clock_timer_data = { | |
685 | .name = "timer", | |
686 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), | |
687 | .parents = bcm2835_clock_osc_parents, | |
688 | .ctl_reg = CM_TIMERCTL, | |
689 | .div_reg = CM_TIMERDIV, | |
690 | .int_bits = 6, | |
691 | .frac_bits = 12, | |
692 | }; | |
693 | ||
694 | /* One Time Programmable Memory clock. Maximum 10Mhz. */ | |
695 | static const struct bcm2835_clock_data bcm2835_clock_otp_data = { | |
696 | .name = "otp", | |
697 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), | |
698 | .parents = bcm2835_clock_osc_parents, | |
699 | .ctl_reg = CM_OTPCTL, | |
700 | .div_reg = CM_OTPDIV, | |
701 | .int_bits = 4, | |
702 | .frac_bits = 0, | |
703 | }; | |
704 | ||
705 | /* | |
706 | * VPU clock. This doesn't have an enable bit, since it drives the | |
707 | * bus for everything else, and is special so it doesn't need to be | |
708 | * gated for rate changes. It is also known as "clk_audio" in various | |
709 | * hardware documentation. | |
710 | */ | |
711 | static const struct bcm2835_clock_data bcm2835_clock_vpu_data = { | |
712 | .name = "vpu", | |
713 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
714 | .parents = bcm2835_clock_vpu_parents, | |
715 | .ctl_reg = CM_VPUCTL, | |
716 | .div_reg = CM_VPUDIV, | |
717 | .int_bits = 12, | |
718 | .frac_bits = 8, | |
719 | .is_vpu_clock = true, | |
720 | }; | |
721 | ||
722 | static const struct bcm2835_clock_data bcm2835_clock_v3d_data = { | |
723 | .name = "v3d", | |
724 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
725 | .parents = bcm2835_clock_vpu_parents, | |
726 | .ctl_reg = CM_V3DCTL, | |
727 | .div_reg = CM_V3DDIV, | |
728 | .int_bits = 4, | |
729 | .frac_bits = 8, | |
730 | }; | |
731 | ||
732 | static const struct bcm2835_clock_data bcm2835_clock_isp_data = { | |
733 | .name = "isp", | |
734 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
735 | .parents = bcm2835_clock_vpu_parents, | |
736 | .ctl_reg = CM_ISPCTL, | |
737 | .div_reg = CM_ISPDIV, | |
738 | .int_bits = 4, | |
739 | .frac_bits = 8, | |
740 | }; | |
741 | ||
742 | static const struct bcm2835_clock_data bcm2835_clock_h264_data = { | |
743 | .name = "h264", | |
744 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
745 | .parents = bcm2835_clock_vpu_parents, | |
746 | .ctl_reg = CM_H264CTL, | |
747 | .div_reg = CM_H264DIV, | |
748 | .int_bits = 4, | |
749 | .frac_bits = 8, | |
750 | }; | |
751 | ||
752 | /* TV encoder clock. Only operating frequency is 108Mhz. */ | |
753 | static const struct bcm2835_clock_data bcm2835_clock_vec_data = { | |
754 | .name = "vec", | |
755 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
756 | .parents = bcm2835_clock_per_parents, | |
757 | .ctl_reg = CM_VECCTL, | |
758 | .div_reg = CM_VECDIV, | |
759 | .int_bits = 4, | |
760 | .frac_bits = 0, | |
761 | }; | |
762 | ||
763 | static const struct bcm2835_clock_data bcm2835_clock_uart_data = { | |
764 | .name = "uart", | |
765 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
766 | .parents = bcm2835_clock_per_parents, | |
767 | .ctl_reg = CM_UARTCTL, | |
768 | .div_reg = CM_UARTDIV, | |
769 | .int_bits = 10, | |
770 | .frac_bits = 12, | |
771 | }; | |
772 | ||
773 | /* HDMI state machine */ | |
774 | static const struct bcm2835_clock_data bcm2835_clock_hsm_data = { | |
775 | .name = "hsm", | |
776 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
777 | .parents = bcm2835_clock_per_parents, | |
778 | .ctl_reg = CM_HSMCTL, | |
779 | .div_reg = CM_HSMDIV, | |
780 | .int_bits = 4, | |
781 | .frac_bits = 8, | |
782 | }; | |
783 | ||
784 | /* | |
785 | * Secondary SDRAM clock. Used for low-voltage modes when the PLL in | |
786 | * the SDRAM controller can't be used. | |
787 | */ | |
788 | static const struct bcm2835_clock_data bcm2835_clock_sdram_data = { | |
789 | .name = "sdram", | |
790 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
791 | .parents = bcm2835_clock_vpu_parents, | |
792 | .ctl_reg = CM_SDCCTL, | |
793 | .div_reg = CM_SDCDIV, | |
794 | .int_bits = 6, | |
795 | .frac_bits = 0, | |
796 | }; | |
797 | ||
798 | /* Clock for the temperature sensor. Generally run at 2Mhz, max 5Mhz. */ | |
799 | static const struct bcm2835_clock_data bcm2835_clock_tsens_data = { | |
800 | .name = "tsens", | |
801 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), | |
802 | .parents = bcm2835_clock_osc_parents, | |
803 | .ctl_reg = CM_TSENSCTL, | |
804 | .div_reg = CM_TSENSDIV, | |
805 | .int_bits = 5, | |
806 | .frac_bits = 0, | |
807 | }; | |
808 | ||
809 | /* Arasan EMMC clock */ | |
810 | static const struct bcm2835_clock_data bcm2835_clock_emmc_data = { | |
811 | .name = "emmc", | |
812 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
813 | .parents = bcm2835_clock_per_parents, | |
814 | .ctl_reg = CM_EMMCCTL, | |
815 | .div_reg = CM_EMMCDIV, | |
816 | .int_bits = 4, | |
817 | .frac_bits = 8, | |
818 | }; | |
819 | ||
cfbab8fb RP |
820 | static const struct bcm2835_clock_data bcm2835_clock_pwm_data = { |
821 | .name = "pwm", | |
822 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
823 | .parents = bcm2835_clock_per_parents, | |
824 | .ctl_reg = CM_PWMCTL, | |
825 | .div_reg = CM_PWMDIV, | |
826 | .int_bits = 12, | |
827 | .frac_bits = 12, | |
959ca92a | 828 | .is_mash_clock = true, |
cfbab8fb RP |
829 | }; |
830 | ||
41691b88 EA |
831 | struct bcm2835_pll { |
832 | struct clk_hw hw; | |
833 | struct bcm2835_cprman *cprman; | |
834 | const struct bcm2835_pll_data *data; | |
835 | }; | |
836 | ||
837 | static int bcm2835_pll_is_on(struct clk_hw *hw) | |
838 | { | |
839 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
840 | struct bcm2835_cprman *cprman = pll->cprman; | |
841 | const struct bcm2835_pll_data *data = pll->data; | |
842 | ||
843 | return cprman_read(cprman, data->a2w_ctrl_reg) & | |
844 | A2W_PLL_CTRL_PRST_DISABLE; | |
845 | } | |
846 | ||
847 | static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, | |
848 | unsigned long parent_rate, | |
849 | u32 *ndiv, u32 *fdiv) | |
850 | { | |
851 | u64 div; | |
852 | ||
853 | div = (u64)rate << A2W_PLL_FRAC_BITS; | |
854 | do_div(div, parent_rate); | |
855 | ||
856 | *ndiv = div >> A2W_PLL_FRAC_BITS; | |
857 | *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); | |
858 | } | |
859 | ||
860 | static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, | |
861 | u32 ndiv, u32 fdiv, u32 pdiv) | |
862 | { | |
863 | u64 rate; | |
864 | ||
865 | if (pdiv == 0) | |
866 | return 0; | |
867 | ||
868 | rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); | |
869 | do_div(rate, pdiv); | |
870 | return rate >> A2W_PLL_FRAC_BITS; | |
871 | } | |
872 | ||
873 | static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
874 | unsigned long *parent_rate) | |
875 | { | |
876 | u32 ndiv, fdiv; | |
877 | ||
878 | bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); | |
879 | ||
880 | return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); | |
881 | } | |
882 | ||
883 | static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, | |
884 | unsigned long parent_rate) | |
885 | { | |
886 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
887 | struct bcm2835_cprman *cprman = pll->cprman; | |
888 | const struct bcm2835_pll_data *data = pll->data; | |
889 | u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); | |
890 | u32 ndiv, pdiv, fdiv; | |
891 | bool using_prediv; | |
892 | ||
893 | if (parent_rate == 0) | |
894 | return 0; | |
895 | ||
896 | fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; | |
897 | ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; | |
898 | pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; | |
899 | using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & | |
900 | data->ana->fb_prediv_mask; | |
901 | ||
902 | if (using_prediv) | |
903 | ndiv *= 2; | |
904 | ||
905 | return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); | |
906 | } | |
907 | ||
908 | static void bcm2835_pll_off(struct clk_hw *hw) | |
909 | { | |
910 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
911 | struct bcm2835_cprman *cprman = pll->cprman; | |
912 | const struct bcm2835_pll_data *data = pll->data; | |
913 | ||
6727f086 MS |
914 | spin_lock(&cprman->regs_lock); |
915 | cprman_write(cprman, data->cm_ctrl_reg, | |
916 | cprman_read(cprman, data->cm_ctrl_reg) | | |
917 | CM_PLL_ANARST); | |
918 | cprman_write(cprman, data->a2w_ctrl_reg, | |
919 | cprman_read(cprman, data->a2w_ctrl_reg) | | |
920 | A2W_PLL_CTRL_PWRDN); | |
921 | spin_unlock(&cprman->regs_lock); | |
41691b88 EA |
922 | } |
923 | ||
924 | static int bcm2835_pll_on(struct clk_hw *hw) | |
925 | { | |
926 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
927 | struct bcm2835_cprman *cprman = pll->cprman; | |
928 | const struct bcm2835_pll_data *data = pll->data; | |
929 | ktime_t timeout; | |
930 | ||
931 | /* Take the PLL out of reset. */ | |
932 | cprman_write(cprman, data->cm_ctrl_reg, | |
933 | cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); | |
934 | ||
935 | /* Wait for the PLL to lock. */ | |
936 | timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
937 | while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { | |
938 | if (ktime_after(ktime_get(), timeout)) { | |
939 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
940 | clk_hw_get_name(hw)); | |
941 | return -ETIMEDOUT; | |
942 | } | |
943 | ||
944 | cpu_relax(); | |
945 | } | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
950 | static void | |
951 | bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) | |
952 | { | |
953 | int i; | |
954 | ||
955 | /* | |
956 | * ANA register setup is done as a series of writes to | |
957 | * ANA3-ANA0, in that order. This lets us write all 4 | |
958 | * registers as a single cycle of the serdes interface (taking | |
959 | * 100 xosc clocks), whereas if we were to update ana0, 1, and | |
960 | * 3 individually through their partial-write registers, each | |
961 | * would be their own serdes cycle. | |
962 | */ | |
963 | for (i = 3; i >= 0; i--) | |
964 | cprman_write(cprman, ana_reg_base + i * 4, ana[i]); | |
965 | } | |
966 | ||
967 | static int bcm2835_pll_set_rate(struct clk_hw *hw, | |
968 | unsigned long rate, unsigned long parent_rate) | |
969 | { | |
970 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
971 | struct bcm2835_cprman *cprman = pll->cprman; | |
972 | const struct bcm2835_pll_data *data = pll->data; | |
973 | bool was_using_prediv, use_fb_prediv, do_ana_setup_first; | |
974 | u32 ndiv, fdiv, a2w_ctl; | |
975 | u32 ana[4]; | |
976 | int i; | |
977 | ||
978 | if (rate < data->min_rate || rate > data->max_rate) { | |
979 | dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n", | |
980 | clk_hw_get_name(hw), rate, | |
981 | data->min_rate, data->max_rate); | |
982 | return -EINVAL; | |
983 | } | |
984 | ||
985 | if (rate > data->max_fb_rate) { | |
986 | use_fb_prediv = true; | |
987 | rate /= 2; | |
988 | } else { | |
989 | use_fb_prediv = false; | |
990 | } | |
991 | ||
992 | bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); | |
993 | ||
994 | for (i = 3; i >= 0; i--) | |
995 | ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); | |
996 | ||
997 | was_using_prediv = ana[1] & data->ana->fb_prediv_mask; | |
998 | ||
999 | ana[0] &= ~data->ana->mask0; | |
1000 | ana[0] |= data->ana->set0; | |
1001 | ana[1] &= ~data->ana->mask1; | |
1002 | ana[1] |= data->ana->set1; | |
1003 | ana[3] &= ~data->ana->mask3; | |
1004 | ana[3] |= data->ana->set3; | |
1005 | ||
1006 | if (was_using_prediv && !use_fb_prediv) { | |
1007 | ana[1] &= ~data->ana->fb_prediv_mask; | |
1008 | do_ana_setup_first = true; | |
1009 | } else if (!was_using_prediv && use_fb_prediv) { | |
1010 | ana[1] |= data->ana->fb_prediv_mask; | |
1011 | do_ana_setup_first = false; | |
1012 | } else { | |
1013 | do_ana_setup_first = true; | |
1014 | } | |
1015 | ||
1016 | /* Unmask the reference clock from the oscillator. */ | |
1017 | cprman_write(cprman, A2W_XOSC_CTRL, | |
1018 | cprman_read(cprman, A2W_XOSC_CTRL) | | |
1019 | data->reference_enable_mask); | |
1020 | ||
1021 | if (do_ana_setup_first) | |
1022 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
1023 | ||
1024 | /* Set the PLL multiplier from the oscillator. */ | |
1025 | cprman_write(cprman, data->frac_reg, fdiv); | |
1026 | ||
1027 | a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); | |
1028 | a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; | |
1029 | a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; | |
1030 | a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; | |
1031 | a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; | |
1032 | cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); | |
1033 | ||
1034 | if (!do_ana_setup_first) | |
1035 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static const struct clk_ops bcm2835_pll_clk_ops = { | |
1041 | .is_prepared = bcm2835_pll_is_on, | |
1042 | .prepare = bcm2835_pll_on, | |
1043 | .unprepare = bcm2835_pll_off, | |
1044 | .recalc_rate = bcm2835_pll_get_rate, | |
1045 | .set_rate = bcm2835_pll_set_rate, | |
1046 | .round_rate = bcm2835_pll_round_rate, | |
1047 | }; | |
1048 | ||
1049 | struct bcm2835_pll_divider { | |
1050 | struct clk_divider div; | |
1051 | struct bcm2835_cprman *cprman; | |
1052 | const struct bcm2835_pll_divider_data *data; | |
1053 | }; | |
1054 | ||
1055 | static struct bcm2835_pll_divider * | |
1056 | bcm2835_pll_divider_from_hw(struct clk_hw *hw) | |
1057 | { | |
1058 | return container_of(hw, struct bcm2835_pll_divider, div.hw); | |
1059 | } | |
1060 | ||
1061 | static int bcm2835_pll_divider_is_on(struct clk_hw *hw) | |
1062 | { | |
1063 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1064 | struct bcm2835_cprman *cprman = divider->cprman; | |
1065 | const struct bcm2835_pll_divider_data *data = divider->data; | |
1066 | ||
1067 | return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); | |
1068 | } | |
1069 | ||
1070 | static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, | |
1071 | unsigned long rate, | |
1072 | unsigned long *parent_rate) | |
1073 | { | |
1074 | return clk_divider_ops.round_rate(hw, rate, parent_rate); | |
1075 | } | |
1076 | ||
1077 | static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, | |
1078 | unsigned long parent_rate) | |
1079 | { | |
79c1e2fc | 1080 | return clk_divider_ops.recalc_rate(hw, parent_rate); |
41691b88 EA |
1081 | } |
1082 | ||
1083 | static void bcm2835_pll_divider_off(struct clk_hw *hw) | |
1084 | { | |
1085 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1086 | struct bcm2835_cprman *cprman = divider->cprman; | |
1087 | const struct bcm2835_pll_divider_data *data = divider->data; | |
1088 | ||
ec36a5c6 | 1089 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
1090 | cprman_write(cprman, data->cm_reg, |
1091 | (cprman_read(cprman, data->cm_reg) & | |
1092 | ~data->load_mask) | data->hold_mask); | |
1093 | cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE); | |
ec36a5c6 | 1094 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
1095 | } |
1096 | ||
1097 | static int bcm2835_pll_divider_on(struct clk_hw *hw) | |
1098 | { | |
1099 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1100 | struct bcm2835_cprman *cprman = divider->cprman; | |
1101 | const struct bcm2835_pll_divider_data *data = divider->data; | |
1102 | ||
ec36a5c6 | 1103 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
1104 | cprman_write(cprman, data->a2w_reg, |
1105 | cprman_read(cprman, data->a2w_reg) & | |
1106 | ~A2W_PLL_CHANNEL_DISABLE); | |
1107 | ||
1108 | cprman_write(cprman, data->cm_reg, | |
1109 | cprman_read(cprman, data->cm_reg) & ~data->hold_mask); | |
ec36a5c6 | 1110 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, | |
1116 | unsigned long rate, | |
1117 | unsigned long parent_rate) | |
1118 | { | |
1119 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1120 | struct bcm2835_cprman *cprman = divider->cprman; | |
1121 | const struct bcm2835_pll_divider_data *data = divider->data; | |
773b3966 | 1122 | u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; |
41691b88 | 1123 | |
773b3966 EA |
1124 | div = DIV_ROUND_UP_ULL(parent_rate, rate); |
1125 | ||
1126 | div = min(div, max_div); | |
1127 | if (div == max_div) | |
1128 | div = 0; | |
41691b88 | 1129 | |
773b3966 | 1130 | cprman_write(cprman, data->a2w_reg, div); |
41691b88 EA |
1131 | cm = cprman_read(cprman, data->cm_reg); |
1132 | cprman_write(cprman, data->cm_reg, cm | data->load_mask); | |
1133 | cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); | |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | static const struct clk_ops bcm2835_pll_divider_clk_ops = { | |
1139 | .is_prepared = bcm2835_pll_divider_is_on, | |
1140 | .prepare = bcm2835_pll_divider_on, | |
1141 | .unprepare = bcm2835_pll_divider_off, | |
1142 | .recalc_rate = bcm2835_pll_divider_get_rate, | |
1143 | .set_rate = bcm2835_pll_divider_set_rate, | |
1144 | .round_rate = bcm2835_pll_divider_round_rate, | |
1145 | }; | |
1146 | ||
1147 | /* | |
1148 | * The CM dividers do fixed-point division, so we can't use the | |
1149 | * generic integer divider code like the PLL dividers do (and we can't | |
1150 | * fake it by having some fixed shifts preceding it in the clock tree, | |
1151 | * because we'd run out of bits in a 32-bit unsigned long). | |
1152 | */ | |
1153 | struct bcm2835_clock { | |
1154 | struct clk_hw hw; | |
1155 | struct bcm2835_cprman *cprman; | |
1156 | const struct bcm2835_clock_data *data; | |
1157 | }; | |
1158 | ||
1159 | static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) | |
1160 | { | |
1161 | return container_of(hw, struct bcm2835_clock, hw); | |
1162 | } | |
1163 | ||
1164 | static int bcm2835_clock_is_on(struct clk_hw *hw) | |
1165 | { | |
1166 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1167 | struct bcm2835_cprman *cprman = clock->cprman; | |
1168 | const struct bcm2835_clock_data *data = clock->data; | |
1169 | ||
1170 | return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; | |
1171 | } | |
1172 | ||
1173 | static u32 bcm2835_clock_choose_div(struct clk_hw *hw, | |
1174 | unsigned long rate, | |
9c95b32c RP |
1175 | unsigned long parent_rate, |
1176 | bool round_up) | |
41691b88 EA |
1177 | { |
1178 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1179 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c RP |
1180 | u32 unused_frac_mask = |
1181 | GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; | |
41691b88 | 1182 | u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; |
9c95b32c | 1183 | u64 rem; |
959ca92a | 1184 | u32 div, mindiv, maxdiv; |
41691b88 | 1185 | |
9c95b32c | 1186 | rem = do_div(temp, rate); |
41691b88 EA |
1187 | div = temp; |
1188 | ||
9c95b32c RP |
1189 | /* Round up and mask off the unused bits */ |
1190 | if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) | |
1191 | div += unused_frac_mask + 1; | |
1192 | div &= ~unused_frac_mask; | |
41691b88 | 1193 | |
959ca92a MS |
1194 | /* different clamping limits apply for a mash clock */ |
1195 | if (data->is_mash_clock) { | |
1196 | /* clamp to min divider of 2 */ | |
1197 | mindiv = 2 << CM_DIV_FRAC_BITS; | |
1198 | /* clamp to the highest possible integer divider */ | |
1199 | maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; | |
1200 | } else { | |
1201 | /* clamp to min divider of 1 */ | |
1202 | mindiv = 1 << CM_DIV_FRAC_BITS; | |
1203 | /* clamp to the highest possible fractional divider */ | |
1204 | maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, | |
1205 | CM_DIV_FRAC_BITS - data->frac_bits); | |
1206 | } | |
1207 | ||
1208 | /* apply the clamping limits */ | |
1209 | div = max_t(u32, div, mindiv); | |
1210 | div = min_t(u32, div, maxdiv); | |
41691b88 EA |
1211 | |
1212 | return div; | |
1213 | } | |
1214 | ||
1215 | static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, | |
1216 | unsigned long parent_rate, | |
1217 | u32 div) | |
1218 | { | |
1219 | const struct bcm2835_clock_data *data = clock->data; | |
1220 | u64 temp; | |
1221 | ||
1222 | /* | |
1223 | * The divisor is a 12.12 fixed point field, but only some of | |
1224 | * the bits are populated in any given clock. | |
1225 | */ | |
1226 | div >>= CM_DIV_FRAC_BITS - data->frac_bits; | |
1227 | div &= (1 << (data->int_bits + data->frac_bits)) - 1; | |
1228 | ||
1229 | if (div == 0) | |
1230 | return 0; | |
1231 | ||
1232 | temp = (u64)parent_rate << data->frac_bits; | |
1233 | ||
1234 | do_div(temp, div); | |
1235 | ||
1236 | return temp; | |
1237 | } | |
1238 | ||
41691b88 EA |
1239 | static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, |
1240 | unsigned long parent_rate) | |
1241 | { | |
1242 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1243 | struct bcm2835_cprman *cprman = clock->cprman; | |
1244 | const struct bcm2835_clock_data *data = clock->data; | |
1245 | u32 div = cprman_read(cprman, data->div_reg); | |
1246 | ||
1247 | return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); | |
1248 | } | |
1249 | ||
1250 | static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) | |
1251 | { | |
1252 | struct bcm2835_cprman *cprman = clock->cprman; | |
1253 | const struct bcm2835_clock_data *data = clock->data; | |
1254 | ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
1255 | ||
1256 | while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { | |
1257 | if (ktime_after(ktime_get(), timeout)) { | |
1258 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
1259 | clk_hw_get_name(&clock->hw)); | |
1260 | return; | |
1261 | } | |
1262 | cpu_relax(); | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | static void bcm2835_clock_off(struct clk_hw *hw) | |
1267 | { | |
1268 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1269 | struct bcm2835_cprman *cprman = clock->cprman; | |
1270 | const struct bcm2835_clock_data *data = clock->data; | |
1271 | ||
1272 | spin_lock(&cprman->regs_lock); | |
1273 | cprman_write(cprman, data->ctl_reg, | |
1274 | cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); | |
1275 | spin_unlock(&cprman->regs_lock); | |
1276 | ||
1277 | /* BUSY will remain high until the divider completes its cycle. */ | |
1278 | bcm2835_clock_wait_busy(clock); | |
1279 | } | |
1280 | ||
1281 | static int bcm2835_clock_on(struct clk_hw *hw) | |
1282 | { | |
1283 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1284 | struct bcm2835_cprman *cprman = clock->cprman; | |
1285 | const struct bcm2835_clock_data *data = clock->data; | |
1286 | ||
1287 | spin_lock(&cprman->regs_lock); | |
1288 | cprman_write(cprman, data->ctl_reg, | |
1289 | cprman_read(cprman, data->ctl_reg) | | |
1290 | CM_ENABLE | | |
1291 | CM_GATE); | |
1292 | spin_unlock(&cprman->regs_lock); | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static int bcm2835_clock_set_rate(struct clk_hw *hw, | |
1298 | unsigned long rate, unsigned long parent_rate) | |
1299 | { | |
1300 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1301 | struct bcm2835_cprman *cprman = clock->cprman; | |
1302 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c | 1303 | u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); |
959ca92a MS |
1304 | u32 ctl; |
1305 | ||
1306 | spin_lock(&cprman->regs_lock); | |
1307 | ||
1308 | /* | |
1309 | * Setting up frac support | |
1310 | * | |
1311 | * In principle it is recommended to stop/start the clock first, | |
1312 | * but as we set CLK_SET_RATE_GATE during registration of the | |
1313 | * clock this requirement should be take care of by the | |
1314 | * clk-framework. | |
1315 | */ | |
1316 | ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; | |
1317 | ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; | |
1318 | cprman_write(cprman, data->ctl_reg, ctl); | |
41691b88 EA |
1319 | |
1320 | cprman_write(cprman, data->div_reg, div); | |
1321 | ||
959ca92a MS |
1322 | spin_unlock(&cprman->regs_lock); |
1323 | ||
41691b88 EA |
1324 | return 0; |
1325 | } | |
1326 | ||
6d18b8ad | 1327 | static int bcm2835_clock_determine_rate(struct clk_hw *hw, |
6e1e60da | 1328 | struct clk_rate_request *req) |
6d18b8ad RP |
1329 | { |
1330 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1331 | struct clk_hw *parent, *best_parent = NULL; | |
1332 | unsigned long rate, best_rate = 0; | |
1333 | unsigned long prate, best_prate = 0; | |
1334 | size_t i; | |
1335 | u32 div; | |
1336 | ||
1337 | /* | |
1338 | * Select parent clock that results in the closest but lower rate | |
1339 | */ | |
1340 | for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { | |
1341 | parent = clk_hw_get_parent_by_index(hw, i); | |
1342 | if (!parent) | |
1343 | continue; | |
1344 | prate = clk_hw_get_rate(parent); | |
1345 | div = bcm2835_clock_choose_div(hw, req->rate, prate, true); | |
1346 | rate = bcm2835_clock_rate_from_divisor(clock, prate, div); | |
1347 | if (rate > best_rate && rate <= req->rate) { | |
1348 | best_parent = parent; | |
1349 | best_prate = prate; | |
1350 | best_rate = rate; | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | if (!best_parent) | |
1355 | return -EINVAL; | |
1356 | ||
1357 | req->best_parent_hw = best_parent; | |
1358 | req->best_parent_rate = best_prate; | |
1359 | ||
1360 | req->rate = best_rate; | |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) | |
1366 | { | |
1367 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1368 | struct bcm2835_cprman *cprman = clock->cprman; | |
1369 | const struct bcm2835_clock_data *data = clock->data; | |
1370 | u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; | |
1371 | ||
1372 | cprman_write(cprman, data->ctl_reg, src); | |
1373 | return 0; | |
1374 | } | |
1375 | ||
1376 | static u8 bcm2835_clock_get_parent(struct clk_hw *hw) | |
1377 | { | |
1378 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1379 | struct bcm2835_cprman *cprman = clock->cprman; | |
1380 | const struct bcm2835_clock_data *data = clock->data; | |
1381 | u32 src = cprman_read(cprman, data->ctl_reg); | |
1382 | ||
1383 | return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; | |
1384 | } | |
1385 | ||
41691b88 EA |
1386 | static const struct clk_ops bcm2835_clock_clk_ops = { |
1387 | .is_prepared = bcm2835_clock_is_on, | |
1388 | .prepare = bcm2835_clock_on, | |
1389 | .unprepare = bcm2835_clock_off, | |
1390 | .recalc_rate = bcm2835_clock_get_rate, | |
1391 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1392 | .determine_rate = bcm2835_clock_determine_rate, |
1393 | .set_parent = bcm2835_clock_set_parent, | |
1394 | .get_parent = bcm2835_clock_get_parent, | |
41691b88 EA |
1395 | }; |
1396 | ||
1397 | static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) | |
1398 | { | |
1399 | return true; | |
1400 | } | |
1401 | ||
1402 | /* | |
1403 | * The VPU clock can never be disabled (it doesn't have an ENABLE | |
1404 | * bit), so it gets its own set of clock ops. | |
1405 | */ | |
1406 | static const struct clk_ops bcm2835_vpu_clock_clk_ops = { | |
1407 | .is_prepared = bcm2835_vpu_clock_is_on, | |
1408 | .recalc_rate = bcm2835_clock_get_rate, | |
1409 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1410 | .determine_rate = bcm2835_clock_determine_rate, |
1411 | .set_parent = bcm2835_clock_set_parent, | |
1412 | .get_parent = bcm2835_clock_get_parent, | |
41691b88 EA |
1413 | }; |
1414 | ||
1415 | static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman, | |
1416 | const struct bcm2835_pll_data *data) | |
1417 | { | |
1418 | struct bcm2835_pll *pll; | |
1419 | struct clk_init_data init; | |
1420 | ||
1421 | memset(&init, 0, sizeof(init)); | |
1422 | ||
1423 | /* All of the PLLs derive from the external oscillator. */ | |
1424 | init.parent_names = &cprman->osc_name; | |
1425 | init.num_parents = 1; | |
1426 | init.name = data->name; | |
1427 | init.ops = &bcm2835_pll_clk_ops; | |
1428 | init.flags = CLK_IGNORE_UNUSED; | |
1429 | ||
1430 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
1431 | if (!pll) | |
1432 | return NULL; | |
1433 | ||
1434 | pll->cprman = cprman; | |
1435 | pll->data = data; | |
1436 | pll->hw.init = &init; | |
1437 | ||
1438 | return devm_clk_register(cprman->dev, &pll->hw); | |
1439 | } | |
1440 | ||
1441 | static struct clk * | |
1442 | bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, | |
1443 | const struct bcm2835_pll_divider_data *data) | |
1444 | { | |
1445 | struct bcm2835_pll_divider *divider; | |
1446 | struct clk_init_data init; | |
1447 | struct clk *clk; | |
1448 | const char *divider_name; | |
1449 | ||
1450 | if (data->fixed_divider != 1) { | |
1451 | divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, | |
1452 | "%s_prediv", data->name); | |
1453 | if (!divider_name) | |
1454 | return NULL; | |
1455 | } else { | |
1456 | divider_name = data->name; | |
1457 | } | |
1458 | ||
1459 | memset(&init, 0, sizeof(init)); | |
1460 | ||
1461 | init.parent_names = &data->source_pll->name; | |
1462 | init.num_parents = 1; | |
1463 | init.name = divider_name; | |
1464 | init.ops = &bcm2835_pll_divider_clk_ops; | |
1465 | init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; | |
1466 | ||
1467 | divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); | |
1468 | if (!divider) | |
1469 | return NULL; | |
1470 | ||
1471 | divider->div.reg = cprman->regs + data->a2w_reg; | |
1472 | divider->div.shift = A2W_PLL_DIV_SHIFT; | |
1473 | divider->div.width = A2W_PLL_DIV_BITS; | |
79c1e2fc | 1474 | divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; |
41691b88 EA |
1475 | divider->div.lock = &cprman->regs_lock; |
1476 | divider->div.hw.init = &init; | |
1477 | divider->div.table = NULL; | |
1478 | ||
1479 | divider->cprman = cprman; | |
1480 | divider->data = data; | |
1481 | ||
1482 | clk = devm_clk_register(cprman->dev, ÷r->div.hw); | |
1483 | if (IS_ERR(clk)) | |
1484 | return clk; | |
1485 | ||
1486 | /* | |
1487 | * PLLH's channels have a fixed divide by 10 afterwards, which | |
1488 | * is what our consumers are actually using. | |
1489 | */ | |
1490 | if (data->fixed_divider != 1) { | |
1491 | return clk_register_fixed_factor(cprman->dev, data->name, | |
1492 | divider_name, | |
1493 | CLK_SET_RATE_PARENT, | |
1494 | 1, | |
1495 | data->fixed_divider); | |
1496 | } | |
1497 | ||
1498 | return clk; | |
1499 | } | |
1500 | ||
1501 | static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman, | |
1502 | const struct bcm2835_clock_data *data) | |
1503 | { | |
1504 | struct bcm2835_clock *clock; | |
1505 | struct clk_init_data init; | |
6d18b8ad RP |
1506 | const char *parents[1 << CM_SRC_BITS]; |
1507 | size_t i; | |
41691b88 EA |
1508 | |
1509 | /* | |
6d18b8ad RP |
1510 | * Replace our "xosc" references with the oscillator's |
1511 | * actual name. | |
41691b88 | 1512 | */ |
6d18b8ad RP |
1513 | for (i = 0; i < data->num_mux_parents; i++) { |
1514 | if (strcmp(data->parents[i], "xosc") == 0) | |
1515 | parents[i] = cprman->osc_name; | |
1516 | else | |
1517 | parents[i] = data->parents[i]; | |
41691b88 EA |
1518 | } |
1519 | ||
1520 | memset(&init, 0, sizeof(init)); | |
6d18b8ad RP |
1521 | init.parent_names = parents; |
1522 | init.num_parents = data->num_mux_parents; | |
41691b88 EA |
1523 | init.name = data->name; |
1524 | init.flags = CLK_IGNORE_UNUSED; | |
1525 | ||
1526 | if (data->is_vpu_clock) { | |
1527 | init.ops = &bcm2835_vpu_clock_clk_ops; | |
1528 | } else { | |
1529 | init.ops = &bcm2835_clock_clk_ops; | |
1530 | init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; | |
1531 | } | |
1532 | ||
1533 | clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); | |
1534 | if (!clock) | |
1535 | return NULL; | |
1536 | ||
1537 | clock->cprman = cprman; | |
1538 | clock->data = data; | |
1539 | clock->hw.init = &init; | |
1540 | ||
1541 | return devm_clk_register(cprman->dev, &clock->hw); | |
1542 | } | |
1543 | ||
1544 | static int bcm2835_clk_probe(struct platform_device *pdev) | |
1545 | { | |
1546 | struct device *dev = &pdev->dev; | |
1547 | struct clk **clks; | |
1548 | struct bcm2835_cprman *cprman; | |
1549 | struct resource *res; | |
1550 | ||
1551 | cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL); | |
1552 | if (!cprman) | |
1553 | return -ENOMEM; | |
1554 | ||
1555 | spin_lock_init(&cprman->regs_lock); | |
1556 | cprman->dev = dev; | |
1557 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1558 | cprman->regs = devm_ioremap_resource(dev, res); | |
1559 | if (IS_ERR(cprman->regs)) | |
1560 | return PTR_ERR(cprman->regs); | |
1561 | ||
1562 | cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0); | |
1563 | if (!cprman->osc_name) | |
1564 | return -ENODEV; | |
1565 | ||
1566 | platform_set_drvdata(pdev, cprman); | |
1567 | ||
1568 | cprman->onecell.clk_num = BCM2835_CLOCK_COUNT; | |
1569 | cprman->onecell.clks = cprman->clks; | |
1570 | clks = cprman->clks; | |
1571 | ||
1572 | clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data); | |
1573 | clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data); | |
1574 | clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data); | |
1575 | clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data); | |
1576 | clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data); | |
1577 | ||
1578 | clks[BCM2835_PLLA_CORE] = | |
1579 | bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data); | |
1580 | clks[BCM2835_PLLA_PER] = | |
1581 | bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data); | |
1582 | clks[BCM2835_PLLC_CORE0] = | |
1583 | bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data); | |
1584 | clks[BCM2835_PLLC_CORE1] = | |
1585 | bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data); | |
1586 | clks[BCM2835_PLLC_CORE2] = | |
1587 | bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data); | |
1588 | clks[BCM2835_PLLC_PER] = | |
1589 | bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data); | |
1590 | clks[BCM2835_PLLD_CORE] = | |
1591 | bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data); | |
1592 | clks[BCM2835_PLLD_PER] = | |
1593 | bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data); | |
1594 | clks[BCM2835_PLLH_RCAL] = | |
1595 | bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data); | |
1596 | clks[BCM2835_PLLH_AUX] = | |
1597 | bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data); | |
1598 | clks[BCM2835_PLLH_PIX] = | |
1599 | bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data); | |
1600 | ||
1601 | clks[BCM2835_CLOCK_TIMER] = | |
1602 | bcm2835_register_clock(cprman, &bcm2835_clock_timer_data); | |
1603 | clks[BCM2835_CLOCK_OTP] = | |
1604 | bcm2835_register_clock(cprman, &bcm2835_clock_otp_data); | |
1605 | clks[BCM2835_CLOCK_TSENS] = | |
1606 | bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data); | |
1607 | clks[BCM2835_CLOCK_VPU] = | |
1608 | bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data); | |
1609 | clks[BCM2835_CLOCK_V3D] = | |
1610 | bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data); | |
1611 | clks[BCM2835_CLOCK_ISP] = | |
1612 | bcm2835_register_clock(cprman, &bcm2835_clock_isp_data); | |
1613 | clks[BCM2835_CLOCK_H264] = | |
1614 | bcm2835_register_clock(cprman, &bcm2835_clock_h264_data); | |
1615 | clks[BCM2835_CLOCK_V3D] = | |
1616 | bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data); | |
1617 | clks[BCM2835_CLOCK_SDRAM] = | |
1618 | bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data); | |
1619 | clks[BCM2835_CLOCK_UART] = | |
1620 | bcm2835_register_clock(cprman, &bcm2835_clock_uart_data); | |
1621 | clks[BCM2835_CLOCK_VEC] = | |
1622 | bcm2835_register_clock(cprman, &bcm2835_clock_vec_data); | |
1623 | clks[BCM2835_CLOCK_HSM] = | |
1624 | bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data); | |
1625 | clks[BCM2835_CLOCK_EMMC] = | |
1626 | bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data); | |
1627 | ||
1628 | /* | |
1629 | * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if | |
1630 | * you have the debug bit set in the power manager, which we | |
1631 | * don't bother exposing) are individual gates off of the | |
1632 | * non-stop vpu clock. | |
1633 | */ | |
1634 | clks[BCM2835_CLOCK_PERI_IMAGE] = | |
1635 | clk_register_gate(dev, "peri_image", "vpu", | |
1636 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, | |
1637 | cprman->regs + CM_PERIICTL, CM_GATE_BIT, | |
1638 | 0, &cprman->regs_lock); | |
1639 | ||
cfbab8fb RP |
1640 | clks[BCM2835_CLOCK_PWM] = |
1641 | bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data); | |
1642 | ||
41691b88 EA |
1643 | return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, |
1644 | &cprman->onecell); | |
1645 | } | |
1646 | ||
1647 | static const struct of_device_id bcm2835_clk_of_match[] = { | |
1648 | { .compatible = "brcm,bcm2835-cprman", }, | |
1649 | {} | |
1650 | }; | |
1651 | MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); | |
1652 | ||
1653 | static struct platform_driver bcm2835_clk_driver = { | |
1654 | .driver = { | |
1655 | .name = "bcm2835-clk", | |
1656 | .of_match_table = bcm2835_clk_of_match, | |
1657 | }, | |
1658 | .probe = bcm2835_clk_probe, | |
1659 | }; | |
1660 | ||
1661 | builtin_platform_driver(bcm2835_clk_driver); | |
1662 | ||
1663 | MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); | |
1664 | MODULE_DESCRIPTION("BCM2835 clock driver"); | |
1665 | MODULE_LICENSE("GPL v2"); |