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75fabc3f | 1 | /* |
41691b88 | 2 | * Copyright (C) 2010,2015 Broadcom |
75fabc3f SA |
3 | * Copyright (C) 2012 Stephen Warren |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
75fabc3f SA |
15 | */ |
16 | ||
41691b88 EA |
17 | /** |
18 | * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) | |
19 | * | |
20 | * The clock tree on the 2835 has several levels. There's a root | |
21 | * oscillator running at 19.2Mhz. After the oscillator there are 5 | |
22 | * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", | |
23 | * and "HDMI displays". Those 5 PLLs each can divide their output to | |
24 | * produce up to 4 channels. Finally, there is the level of clocks to | |
25 | * be consumed by other hardware components (like "H264" or "HDMI | |
26 | * state machine"), which divide off of some subset of the PLL | |
27 | * channels. | |
28 | * | |
29 | * All of the clocks in the tree are exposed in the DT, because the DT | |
30 | * may want to make assignments of the final layer of clocks to the | |
31 | * PLL channels, and some components of the hardware will actually | |
32 | * skip layers of the tree (for example, the pixel clock comes | |
33 | * directly from the PLLH PIX channel without using a CM_*CTL clock | |
34 | * generator). | |
35 | */ | |
36 | ||
75fabc3f SA |
37 | #include <linux/clk-provider.h> |
38 | #include <linux/clkdev.h> | |
9e400c5c | 39 | #include <linux/clk.h> |
75fabc3f | 40 | #include <linux/clk/bcm2835.h> |
96bf9c69 | 41 | #include <linux/debugfs.h> |
41691b88 | 42 | #include <linux/module.h> |
526d239c | 43 | #include <linux/of.h> |
41691b88 EA |
44 | #include <linux/platform_device.h> |
45 | #include <linux/slab.h> | |
46 | #include <dt-bindings/clock/bcm2835.h> | |
47 | ||
48 | #define CM_PASSWORD 0x5a000000 | |
49 | ||
50 | #define CM_GNRICCTL 0x000 | |
51 | #define CM_GNRICDIV 0x004 | |
52 | # define CM_DIV_FRAC_BITS 12 | |
959ca92a | 53 | # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) |
41691b88 EA |
54 | |
55 | #define CM_VPUCTL 0x008 | |
56 | #define CM_VPUDIV 0x00c | |
57 | #define CM_SYSCTL 0x010 | |
58 | #define CM_SYSDIV 0x014 | |
59 | #define CM_PERIACTL 0x018 | |
60 | #define CM_PERIADIV 0x01c | |
61 | #define CM_PERIICTL 0x020 | |
62 | #define CM_PERIIDIV 0x024 | |
63 | #define CM_H264CTL 0x028 | |
64 | #define CM_H264DIV 0x02c | |
65 | #define CM_ISPCTL 0x030 | |
66 | #define CM_ISPDIV 0x034 | |
67 | #define CM_V3DCTL 0x038 | |
68 | #define CM_V3DDIV 0x03c | |
69 | #define CM_CAM0CTL 0x040 | |
70 | #define CM_CAM0DIV 0x044 | |
71 | #define CM_CAM1CTL 0x048 | |
72 | #define CM_CAM1DIV 0x04c | |
73 | #define CM_CCP2CTL 0x050 | |
74 | #define CM_CCP2DIV 0x054 | |
75 | #define CM_DSI0ECTL 0x058 | |
76 | #define CM_DSI0EDIV 0x05c | |
77 | #define CM_DSI0PCTL 0x060 | |
78 | #define CM_DSI0PDIV 0x064 | |
79 | #define CM_DPICTL 0x068 | |
80 | #define CM_DPIDIV 0x06c | |
81 | #define CM_GP0CTL 0x070 | |
82 | #define CM_GP0DIV 0x074 | |
83 | #define CM_GP1CTL 0x078 | |
84 | #define CM_GP1DIV 0x07c | |
85 | #define CM_GP2CTL 0x080 | |
86 | #define CM_GP2DIV 0x084 | |
87 | #define CM_HSMCTL 0x088 | |
88 | #define CM_HSMDIV 0x08c | |
89 | #define CM_OTPCTL 0x090 | |
90 | #define CM_OTPDIV 0x094 | |
2103a215 MS |
91 | #define CM_PCMCTL 0x098 |
92 | #define CM_PCMDIV 0x09c | |
41691b88 EA |
93 | #define CM_PWMCTL 0x0a0 |
94 | #define CM_PWMDIV 0x0a4 | |
2103a215 MS |
95 | #define CM_SLIMCTL 0x0a8 |
96 | #define CM_SLIMDIV 0x0ac | |
41691b88 EA |
97 | #define CM_SMICTL 0x0b0 |
98 | #define CM_SMIDIV 0x0b4 | |
2103a215 MS |
99 | /* no definition for 0x0b8 and 0x0bc */ |
100 | #define CM_TCNTCTL 0x0c0 | |
101 | #define CM_TCNTDIV 0x0c4 | |
102 | #define CM_TECCTL 0x0c8 | |
103 | #define CM_TECDIV 0x0cc | |
104 | #define CM_TD0CTL 0x0d0 | |
105 | #define CM_TD0DIV 0x0d4 | |
106 | #define CM_TD1CTL 0x0d8 | |
107 | #define CM_TD1DIV 0x0dc | |
41691b88 EA |
108 | #define CM_TSENSCTL 0x0e0 |
109 | #define CM_TSENSDIV 0x0e4 | |
110 | #define CM_TIMERCTL 0x0e8 | |
111 | #define CM_TIMERDIV 0x0ec | |
112 | #define CM_UARTCTL 0x0f0 | |
113 | #define CM_UARTDIV 0x0f4 | |
114 | #define CM_VECCTL 0x0f8 | |
115 | #define CM_VECDIV 0x0fc | |
116 | #define CM_PULSECTL 0x190 | |
117 | #define CM_PULSEDIV 0x194 | |
118 | #define CM_SDCCTL 0x1a8 | |
119 | #define CM_SDCDIV 0x1ac | |
120 | #define CM_ARMCTL 0x1b0 | |
d3d6f15f MS |
121 | #define CM_AVEOCTL 0x1b8 |
122 | #define CM_AVEODIV 0x1bc | |
41691b88 EA |
123 | #define CM_EMMCCTL 0x1c0 |
124 | #define CM_EMMCDIV 0x1c4 | |
125 | ||
126 | /* General bits for the CM_*CTL regs */ | |
127 | # define CM_ENABLE BIT(4) | |
128 | # define CM_KILL BIT(5) | |
129 | # define CM_GATE_BIT 6 | |
130 | # define CM_GATE BIT(CM_GATE_BIT) | |
131 | # define CM_BUSY BIT(7) | |
132 | # define CM_BUSYD BIT(8) | |
959ca92a | 133 | # define CM_FRAC BIT(9) |
41691b88 EA |
134 | # define CM_SRC_SHIFT 0 |
135 | # define CM_SRC_BITS 4 | |
136 | # define CM_SRC_MASK 0xf | |
137 | # define CM_SRC_GND 0 | |
138 | # define CM_SRC_OSC 1 | |
139 | # define CM_SRC_TESTDEBUG0 2 | |
140 | # define CM_SRC_TESTDEBUG1 3 | |
141 | # define CM_SRC_PLLA_CORE 4 | |
142 | # define CM_SRC_PLLA_PER 4 | |
143 | # define CM_SRC_PLLC_CORE0 5 | |
144 | # define CM_SRC_PLLC_PER 5 | |
145 | # define CM_SRC_PLLC_CORE1 8 | |
146 | # define CM_SRC_PLLD_CORE 6 | |
147 | # define CM_SRC_PLLD_PER 6 | |
148 | # define CM_SRC_PLLH_AUX 7 | |
149 | # define CM_SRC_PLLC_CORE1 8 | |
150 | # define CM_SRC_PLLC_CORE2 9 | |
151 | ||
152 | #define CM_OSCCOUNT 0x100 | |
153 | ||
154 | #define CM_PLLA 0x104 | |
155 | # define CM_PLL_ANARST BIT(8) | |
156 | # define CM_PLLA_HOLDPER BIT(7) | |
157 | # define CM_PLLA_LOADPER BIT(6) | |
158 | # define CM_PLLA_HOLDCORE BIT(5) | |
159 | # define CM_PLLA_LOADCORE BIT(4) | |
160 | # define CM_PLLA_HOLDCCP2 BIT(3) | |
161 | # define CM_PLLA_LOADCCP2 BIT(2) | |
162 | # define CM_PLLA_HOLDDSI0 BIT(1) | |
163 | # define CM_PLLA_LOADDSI0 BIT(0) | |
164 | ||
165 | #define CM_PLLC 0x108 | |
166 | # define CM_PLLC_HOLDPER BIT(7) | |
167 | # define CM_PLLC_LOADPER BIT(6) | |
168 | # define CM_PLLC_HOLDCORE2 BIT(5) | |
169 | # define CM_PLLC_LOADCORE2 BIT(4) | |
170 | # define CM_PLLC_HOLDCORE1 BIT(3) | |
171 | # define CM_PLLC_LOADCORE1 BIT(2) | |
172 | # define CM_PLLC_HOLDCORE0 BIT(1) | |
173 | # define CM_PLLC_LOADCORE0 BIT(0) | |
174 | ||
175 | #define CM_PLLD 0x10c | |
176 | # define CM_PLLD_HOLDPER BIT(7) | |
177 | # define CM_PLLD_LOADPER BIT(6) | |
178 | # define CM_PLLD_HOLDCORE BIT(5) | |
179 | # define CM_PLLD_LOADCORE BIT(4) | |
180 | # define CM_PLLD_HOLDDSI1 BIT(3) | |
181 | # define CM_PLLD_LOADDSI1 BIT(2) | |
182 | # define CM_PLLD_HOLDDSI0 BIT(1) | |
183 | # define CM_PLLD_LOADDSI0 BIT(0) | |
184 | ||
185 | #define CM_PLLH 0x110 | |
186 | # define CM_PLLH_LOADRCAL BIT(2) | |
187 | # define CM_PLLH_LOADAUX BIT(1) | |
188 | # define CM_PLLH_LOADPIX BIT(0) | |
189 | ||
190 | #define CM_LOCK 0x114 | |
191 | # define CM_LOCK_FLOCKH BIT(12) | |
192 | # define CM_LOCK_FLOCKD BIT(11) | |
193 | # define CM_LOCK_FLOCKC BIT(10) | |
194 | # define CM_LOCK_FLOCKB BIT(9) | |
195 | # define CM_LOCK_FLOCKA BIT(8) | |
196 | ||
197 | #define CM_EVENT 0x118 | |
198 | #define CM_DSI1ECTL 0x158 | |
199 | #define CM_DSI1EDIV 0x15c | |
200 | #define CM_DSI1PCTL 0x160 | |
201 | #define CM_DSI1PDIV 0x164 | |
202 | #define CM_DFTCTL 0x168 | |
203 | #define CM_DFTDIV 0x16c | |
204 | ||
205 | #define CM_PLLB 0x170 | |
206 | # define CM_PLLB_HOLDARM BIT(1) | |
207 | # define CM_PLLB_LOADARM BIT(0) | |
208 | ||
209 | #define A2W_PLLA_CTRL 0x1100 | |
210 | #define A2W_PLLC_CTRL 0x1120 | |
211 | #define A2W_PLLD_CTRL 0x1140 | |
212 | #define A2W_PLLH_CTRL 0x1160 | |
213 | #define A2W_PLLB_CTRL 0x11e0 | |
214 | # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) | |
215 | # define A2W_PLL_CTRL_PWRDN BIT(16) | |
216 | # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 | |
217 | # define A2W_PLL_CTRL_PDIV_SHIFT 12 | |
218 | # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff | |
219 | # define A2W_PLL_CTRL_NDIV_SHIFT 0 | |
220 | ||
221 | #define A2W_PLLA_ANA0 0x1010 | |
222 | #define A2W_PLLC_ANA0 0x1030 | |
223 | #define A2W_PLLD_ANA0 0x1050 | |
224 | #define A2W_PLLH_ANA0 0x1070 | |
225 | #define A2W_PLLB_ANA0 0x10f0 | |
226 | ||
227 | #define A2W_PLL_KA_SHIFT 7 | |
228 | #define A2W_PLL_KA_MASK GENMASK(9, 7) | |
229 | #define A2W_PLL_KI_SHIFT 19 | |
230 | #define A2W_PLL_KI_MASK GENMASK(21, 19) | |
231 | #define A2W_PLL_KP_SHIFT 15 | |
232 | #define A2W_PLL_KP_MASK GENMASK(18, 15) | |
233 | ||
234 | #define A2W_PLLH_KA_SHIFT 19 | |
235 | #define A2W_PLLH_KA_MASK GENMASK(21, 19) | |
236 | #define A2W_PLLH_KI_LOW_SHIFT 22 | |
237 | #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) | |
238 | #define A2W_PLLH_KI_HIGH_SHIFT 0 | |
239 | #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) | |
240 | #define A2W_PLLH_KP_SHIFT 1 | |
241 | #define A2W_PLLH_KP_MASK GENMASK(4, 1) | |
242 | ||
243 | #define A2W_XOSC_CTRL 0x1190 | |
244 | # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) | |
245 | # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) | |
246 | # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) | |
247 | # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) | |
248 | # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) | |
249 | # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) | |
250 | # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) | |
251 | # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) | |
252 | ||
253 | #define A2W_PLLA_FRAC 0x1200 | |
254 | #define A2W_PLLC_FRAC 0x1220 | |
255 | #define A2W_PLLD_FRAC 0x1240 | |
256 | #define A2W_PLLH_FRAC 0x1260 | |
257 | #define A2W_PLLB_FRAC 0x12e0 | |
258 | # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) | |
259 | # define A2W_PLL_FRAC_BITS 20 | |
260 | ||
261 | #define A2W_PLL_CHANNEL_DISABLE BIT(8) | |
262 | #define A2W_PLL_DIV_BITS 8 | |
263 | #define A2W_PLL_DIV_SHIFT 0 | |
264 | ||
265 | #define A2W_PLLA_DSI0 0x1300 | |
266 | #define A2W_PLLA_CORE 0x1400 | |
267 | #define A2W_PLLA_PER 0x1500 | |
268 | #define A2W_PLLA_CCP2 0x1600 | |
269 | ||
270 | #define A2W_PLLC_CORE2 0x1320 | |
271 | #define A2W_PLLC_CORE1 0x1420 | |
272 | #define A2W_PLLC_PER 0x1520 | |
273 | #define A2W_PLLC_CORE0 0x1620 | |
274 | ||
275 | #define A2W_PLLD_DSI0 0x1340 | |
276 | #define A2W_PLLD_CORE 0x1440 | |
277 | #define A2W_PLLD_PER 0x1540 | |
278 | #define A2W_PLLD_DSI1 0x1640 | |
279 | ||
280 | #define A2W_PLLH_AUX 0x1360 | |
281 | #define A2W_PLLH_RCAL 0x1460 | |
282 | #define A2W_PLLH_PIX 0x1560 | |
283 | #define A2W_PLLH_STS 0x1660 | |
284 | ||
285 | #define A2W_PLLH_CTRLR 0x1960 | |
286 | #define A2W_PLLH_FRACR 0x1a60 | |
287 | #define A2W_PLLH_AUXR 0x1b60 | |
288 | #define A2W_PLLH_RCALR 0x1c60 | |
289 | #define A2W_PLLH_PIXR 0x1d60 | |
290 | #define A2W_PLLH_STSR 0x1e60 | |
291 | ||
292 | #define A2W_PLLB_ARM 0x13e0 | |
293 | #define A2W_PLLB_SP0 0x14e0 | |
294 | #define A2W_PLLB_SP1 0x15e0 | |
295 | #define A2W_PLLB_SP2 0x16e0 | |
296 | ||
297 | #define LOCK_TIMEOUT_NS 100000000 | |
298 | #define BCM2835_MAX_FB_RATE 1750000000u | |
299 | ||
8a39e9fa EA |
300 | /* |
301 | * Names of clocks used within the driver that need to be replaced | |
302 | * with an external parent's name. This array is in the order that | |
303 | * the clocks node in the DT references external clocks. | |
304 | */ | |
305 | static const char *const cprman_parent_names[] = { | |
306 | "xosc", | |
307 | "dsi0_byte", | |
308 | "dsi0_ddr2", | |
309 | "dsi0_ddr", | |
310 | "dsi1_byte", | |
311 | "dsi1_ddr2", | |
312 | "dsi1_ddr", | |
313 | }; | |
314 | ||
41691b88 EA |
315 | struct bcm2835_cprman { |
316 | struct device *dev; | |
317 | void __iomem *regs; | |
6e1e60da | 318 | spinlock_t regs_lock; /* spinlock for all clocks */ |
8a39e9fa EA |
319 | |
320 | /* | |
321 | * Real names of cprman clock parents looked up through | |
322 | * of_clk_get_parent_name(), which will be used in the | |
323 | * parent_names[] arrays for clock registration. | |
324 | */ | |
325 | const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)]; | |
41691b88 | 326 | |
b19f009d SB |
327 | /* Must be last */ |
328 | struct clk_hw_onecell_data onecell; | |
41691b88 EA |
329 | }; |
330 | ||
331 | static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) | |
332 | { | |
333 | writel(CM_PASSWORD | val, cprman->regs + reg); | |
334 | } | |
335 | ||
336 | static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) | |
337 | { | |
338 | return readl(cprman->regs + reg); | |
339 | } | |
526d239c | 340 | |
96bf9c69 MS |
341 | static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, |
342 | struct debugfs_reg32 *regs, size_t nregs, | |
343 | struct dentry *dentry) | |
344 | { | |
345 | struct dentry *regdump; | |
346 | struct debugfs_regset32 *regset; | |
347 | ||
348 | regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); | |
349 | if (!regset) | |
350 | return -ENOMEM; | |
351 | ||
352 | regset->regs = regs; | |
353 | regset->nregs = nregs; | |
354 | regset->base = cprman->regs + base; | |
355 | ||
356 | regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry, | |
357 | regset); | |
358 | ||
359 | return regdump ? 0 : -ENOMEM; | |
360 | } | |
361 | ||
75fabc3f SA |
362 | /* |
363 | * These are fixed clocks. They're probably not all root clocks and it may | |
364 | * be possible to turn them on and off but until this is mapped out better | |
365 | * it's the only way they can be used. | |
366 | */ | |
367 | void __init bcm2835_init_clocks(void) | |
368 | { | |
b19f009d | 369 | struct clk_hw *hw; |
75fabc3f SA |
370 | int ret; |
371 | ||
b19f009d SB |
372 | hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); |
373 | if (IS_ERR(hw)) | |
75fabc3f SA |
374 | pr_err("apb_pclk not registered\n"); |
375 | ||
b19f009d SB |
376 | hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); |
377 | if (IS_ERR(hw)) | |
75fabc3f | 378 | pr_err("uart0_pclk not registered\n"); |
b19f009d | 379 | ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart"); |
75fabc3f SA |
380 | if (ret) |
381 | pr_err("uart0_pclk alias not registered\n"); | |
382 | ||
b19f009d SB |
383 | hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); |
384 | if (IS_ERR(hw)) | |
75fabc3f | 385 | pr_err("uart1_pclk not registered\n"); |
b19f009d | 386 | ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart"); |
75fabc3f | 387 | if (ret) |
686ea585 | 388 | pr_err("uart1_pclk alias not registered\n"); |
75fabc3f | 389 | } |
41691b88 EA |
390 | |
391 | struct bcm2835_pll_data { | |
392 | const char *name; | |
393 | u32 cm_ctrl_reg; | |
394 | u32 a2w_ctrl_reg; | |
395 | u32 frac_reg; | |
396 | u32 ana_reg_base; | |
397 | u32 reference_enable_mask; | |
398 | /* Bit in CM_LOCK to indicate when the PLL has locked. */ | |
399 | u32 lock_mask; | |
400 | ||
401 | const struct bcm2835_pll_ana_bits *ana; | |
402 | ||
403 | unsigned long min_rate; | |
404 | unsigned long max_rate; | |
405 | /* | |
406 | * Highest rate for the VCO before we have to use the | |
407 | * pre-divide-by-2. | |
408 | */ | |
409 | unsigned long max_fb_rate; | |
410 | }; | |
411 | ||
412 | struct bcm2835_pll_ana_bits { | |
413 | u32 mask0; | |
414 | u32 set0; | |
415 | u32 mask1; | |
416 | u32 set1; | |
417 | u32 mask3; | |
418 | u32 set3; | |
419 | u32 fb_prediv_mask; | |
420 | }; | |
421 | ||
422 | static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { | |
423 | .mask0 = 0, | |
424 | .set0 = 0, | |
286259ef | 425 | .mask1 = (u32)~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK), |
41691b88 | 426 | .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), |
286259ef | 427 | .mask3 = (u32)~A2W_PLL_KA_MASK, |
41691b88 EA |
428 | .set3 = (2 << A2W_PLL_KA_SHIFT), |
429 | .fb_prediv_mask = BIT(14), | |
430 | }; | |
431 | ||
432 | static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { | |
286259ef | 433 | .mask0 = (u32)~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK), |
41691b88 | 434 | .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), |
286259ef | 435 | .mask1 = (u32)~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK), |
41691b88 EA |
436 | .set1 = (6 << A2W_PLLH_KP_SHIFT), |
437 | .mask3 = 0, | |
438 | .set3 = 0, | |
439 | .fb_prediv_mask = BIT(11), | |
440 | }; | |
441 | ||
41691b88 EA |
442 | struct bcm2835_pll_divider_data { |
443 | const char *name; | |
3b15afef MS |
444 | const char *source_pll; |
445 | ||
41691b88 EA |
446 | u32 cm_reg; |
447 | u32 a2w_reg; | |
448 | ||
449 | u32 load_mask; | |
450 | u32 hold_mask; | |
451 | u32 fixed_divider; | |
55486091 | 452 | u32 flags; |
41691b88 EA |
453 | }; |
454 | ||
41691b88 EA |
455 | struct bcm2835_clock_data { |
456 | const char *name; | |
457 | ||
458 | const char *const *parents; | |
459 | int num_mux_parents; | |
460 | ||
155e8b3b BB |
461 | /* Bitmap encoding which parents accept rate change propagation. */ |
462 | unsigned int set_rate_parent; | |
463 | ||
41691b88 EA |
464 | u32 ctl_reg; |
465 | u32 div_reg; | |
466 | ||
467 | /* Number of integer bits in the divider */ | |
468 | u32 int_bits; | |
469 | /* Number of fractional bits in the divider */ | |
470 | u32 frac_bits; | |
471 | ||
e69fdcca EA |
472 | u32 flags; |
473 | ||
41691b88 | 474 | bool is_vpu_clock; |
959ca92a | 475 | bool is_mash_clock; |
41691b88 EA |
476 | }; |
477 | ||
56eb3a2e MS |
478 | struct bcm2835_gate_data { |
479 | const char *name; | |
480 | const char *parent; | |
481 | ||
482 | u32 ctl_reg; | |
483 | }; | |
484 | ||
41691b88 EA |
485 | struct bcm2835_pll { |
486 | struct clk_hw hw; | |
487 | struct bcm2835_cprman *cprman; | |
488 | const struct bcm2835_pll_data *data; | |
489 | }; | |
490 | ||
491 | static int bcm2835_pll_is_on(struct clk_hw *hw) | |
492 | { | |
493 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
494 | struct bcm2835_cprman *cprman = pll->cprman; | |
495 | const struct bcm2835_pll_data *data = pll->data; | |
496 | ||
497 | return cprman_read(cprman, data->a2w_ctrl_reg) & | |
498 | A2W_PLL_CTRL_PRST_DISABLE; | |
499 | } | |
500 | ||
501 | static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, | |
502 | unsigned long parent_rate, | |
503 | u32 *ndiv, u32 *fdiv) | |
504 | { | |
505 | u64 div; | |
506 | ||
507 | div = (u64)rate << A2W_PLL_FRAC_BITS; | |
508 | do_div(div, parent_rate); | |
509 | ||
510 | *ndiv = div >> A2W_PLL_FRAC_BITS; | |
511 | *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); | |
512 | } | |
513 | ||
514 | static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, | |
515 | u32 ndiv, u32 fdiv, u32 pdiv) | |
516 | { | |
517 | u64 rate; | |
518 | ||
519 | if (pdiv == 0) | |
520 | return 0; | |
521 | ||
522 | rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); | |
523 | do_div(rate, pdiv); | |
524 | return rate >> A2W_PLL_FRAC_BITS; | |
525 | } | |
526 | ||
527 | static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
528 | unsigned long *parent_rate) | |
529 | { | |
c4e634ce EA |
530 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); |
531 | const struct bcm2835_pll_data *data = pll->data; | |
41691b88 EA |
532 | u32 ndiv, fdiv; |
533 | ||
c4e634ce EA |
534 | rate = clamp(rate, data->min_rate, data->max_rate); |
535 | ||
41691b88 EA |
536 | bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); |
537 | ||
538 | return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); | |
539 | } | |
540 | ||
541 | static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, | |
542 | unsigned long parent_rate) | |
543 | { | |
544 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
545 | struct bcm2835_cprman *cprman = pll->cprman; | |
546 | const struct bcm2835_pll_data *data = pll->data; | |
547 | u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); | |
548 | u32 ndiv, pdiv, fdiv; | |
549 | bool using_prediv; | |
550 | ||
551 | if (parent_rate == 0) | |
552 | return 0; | |
553 | ||
554 | fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; | |
555 | ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; | |
556 | pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; | |
557 | using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & | |
558 | data->ana->fb_prediv_mask; | |
559 | ||
560 | if (using_prediv) | |
561 | ndiv *= 2; | |
562 | ||
563 | return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); | |
564 | } | |
565 | ||
566 | static void bcm2835_pll_off(struct clk_hw *hw) | |
567 | { | |
568 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
569 | struct bcm2835_cprman *cprman = pll->cprman; | |
570 | const struct bcm2835_pll_data *data = pll->data; | |
571 | ||
6727f086 MS |
572 | spin_lock(&cprman->regs_lock); |
573 | cprman_write(cprman, data->cm_ctrl_reg, | |
574 | cprman_read(cprman, data->cm_ctrl_reg) | | |
575 | CM_PLL_ANARST); | |
576 | cprman_write(cprman, data->a2w_ctrl_reg, | |
577 | cprman_read(cprman, data->a2w_ctrl_reg) | | |
578 | A2W_PLL_CTRL_PWRDN); | |
579 | spin_unlock(&cprman->regs_lock); | |
41691b88 EA |
580 | } |
581 | ||
582 | static int bcm2835_pll_on(struct clk_hw *hw) | |
583 | { | |
584 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
585 | struct bcm2835_cprman *cprman = pll->cprman; | |
586 | const struct bcm2835_pll_data *data = pll->data; | |
587 | ktime_t timeout; | |
588 | ||
e708b383 EA |
589 | cprman_write(cprman, data->a2w_ctrl_reg, |
590 | cprman_read(cprman, data->a2w_ctrl_reg) & | |
591 | ~A2W_PLL_CTRL_PWRDN); | |
592 | ||
41691b88 EA |
593 | /* Take the PLL out of reset. */ |
594 | cprman_write(cprman, data->cm_ctrl_reg, | |
595 | cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); | |
596 | ||
597 | /* Wait for the PLL to lock. */ | |
598 | timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
599 | while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { | |
600 | if (ktime_after(ktime_get(), timeout)) { | |
601 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
602 | clk_hw_get_name(hw)); | |
603 | return -ETIMEDOUT; | |
604 | } | |
605 | ||
606 | cpu_relax(); | |
607 | } | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
612 | static void | |
613 | bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) | |
614 | { | |
615 | int i; | |
616 | ||
617 | /* | |
618 | * ANA register setup is done as a series of writes to | |
619 | * ANA3-ANA0, in that order. This lets us write all 4 | |
620 | * registers as a single cycle of the serdes interface (taking | |
621 | * 100 xosc clocks), whereas if we were to update ana0, 1, and | |
622 | * 3 individually through their partial-write registers, each | |
623 | * would be their own serdes cycle. | |
624 | */ | |
625 | for (i = 3; i >= 0; i--) | |
626 | cprman_write(cprman, ana_reg_base + i * 4, ana[i]); | |
627 | } | |
628 | ||
629 | static int bcm2835_pll_set_rate(struct clk_hw *hw, | |
630 | unsigned long rate, unsigned long parent_rate) | |
631 | { | |
632 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
633 | struct bcm2835_cprman *cprman = pll->cprman; | |
634 | const struct bcm2835_pll_data *data = pll->data; | |
635 | bool was_using_prediv, use_fb_prediv, do_ana_setup_first; | |
636 | u32 ndiv, fdiv, a2w_ctl; | |
637 | u32 ana[4]; | |
638 | int i; | |
639 | ||
41691b88 EA |
640 | if (rate > data->max_fb_rate) { |
641 | use_fb_prediv = true; | |
642 | rate /= 2; | |
643 | } else { | |
644 | use_fb_prediv = false; | |
645 | } | |
646 | ||
647 | bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); | |
648 | ||
649 | for (i = 3; i >= 0; i--) | |
650 | ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); | |
651 | ||
652 | was_using_prediv = ana[1] & data->ana->fb_prediv_mask; | |
653 | ||
654 | ana[0] &= ~data->ana->mask0; | |
655 | ana[0] |= data->ana->set0; | |
656 | ana[1] &= ~data->ana->mask1; | |
657 | ana[1] |= data->ana->set1; | |
658 | ana[3] &= ~data->ana->mask3; | |
659 | ana[3] |= data->ana->set3; | |
660 | ||
661 | if (was_using_prediv && !use_fb_prediv) { | |
662 | ana[1] &= ~data->ana->fb_prediv_mask; | |
663 | do_ana_setup_first = true; | |
664 | } else if (!was_using_prediv && use_fb_prediv) { | |
665 | ana[1] |= data->ana->fb_prediv_mask; | |
666 | do_ana_setup_first = false; | |
667 | } else { | |
668 | do_ana_setup_first = true; | |
669 | } | |
670 | ||
671 | /* Unmask the reference clock from the oscillator. */ | |
672 | cprman_write(cprman, A2W_XOSC_CTRL, | |
673 | cprman_read(cprman, A2W_XOSC_CTRL) | | |
674 | data->reference_enable_mask); | |
675 | ||
676 | if (do_ana_setup_first) | |
677 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
678 | ||
679 | /* Set the PLL multiplier from the oscillator. */ | |
680 | cprman_write(cprman, data->frac_reg, fdiv); | |
681 | ||
682 | a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); | |
683 | a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; | |
684 | a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; | |
685 | a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; | |
686 | a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; | |
687 | cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); | |
688 | ||
689 | if (!do_ana_setup_first) | |
690 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
96bf9c69 MS |
695 | static int bcm2835_pll_debug_init(struct clk_hw *hw, |
696 | struct dentry *dentry) | |
697 | { | |
698 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
699 | struct bcm2835_cprman *cprman = pll->cprman; | |
700 | const struct bcm2835_pll_data *data = pll->data; | |
701 | struct debugfs_reg32 *regs; | |
702 | ||
703 | regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); | |
704 | if (!regs) | |
705 | return -ENOMEM; | |
706 | ||
707 | regs[0].name = "cm_ctrl"; | |
708 | regs[0].offset = data->cm_ctrl_reg; | |
709 | regs[1].name = "a2w_ctrl"; | |
710 | regs[1].offset = data->a2w_ctrl_reg; | |
711 | regs[2].name = "frac"; | |
712 | regs[2].offset = data->frac_reg; | |
713 | regs[3].name = "ana0"; | |
714 | regs[3].offset = data->ana_reg_base + 0 * 4; | |
715 | regs[4].name = "ana1"; | |
716 | regs[4].offset = data->ana_reg_base + 1 * 4; | |
717 | regs[5].name = "ana2"; | |
718 | regs[5].offset = data->ana_reg_base + 2 * 4; | |
719 | regs[6].name = "ana3"; | |
720 | regs[6].offset = data->ana_reg_base + 3 * 4; | |
721 | ||
722 | return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); | |
723 | } | |
724 | ||
41691b88 EA |
725 | static const struct clk_ops bcm2835_pll_clk_ops = { |
726 | .is_prepared = bcm2835_pll_is_on, | |
727 | .prepare = bcm2835_pll_on, | |
728 | .unprepare = bcm2835_pll_off, | |
729 | .recalc_rate = bcm2835_pll_get_rate, | |
730 | .set_rate = bcm2835_pll_set_rate, | |
731 | .round_rate = bcm2835_pll_round_rate, | |
96bf9c69 | 732 | .debug_init = bcm2835_pll_debug_init, |
41691b88 EA |
733 | }; |
734 | ||
735 | struct bcm2835_pll_divider { | |
736 | struct clk_divider div; | |
737 | struct bcm2835_cprman *cprman; | |
738 | const struct bcm2835_pll_divider_data *data; | |
739 | }; | |
740 | ||
741 | static struct bcm2835_pll_divider * | |
742 | bcm2835_pll_divider_from_hw(struct clk_hw *hw) | |
743 | { | |
744 | return container_of(hw, struct bcm2835_pll_divider, div.hw); | |
745 | } | |
746 | ||
747 | static int bcm2835_pll_divider_is_on(struct clk_hw *hw) | |
748 | { | |
749 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
750 | struct bcm2835_cprman *cprman = divider->cprman; | |
751 | const struct bcm2835_pll_divider_data *data = divider->data; | |
752 | ||
753 | return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); | |
754 | } | |
755 | ||
756 | static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, | |
757 | unsigned long rate, | |
758 | unsigned long *parent_rate) | |
759 | { | |
760 | return clk_divider_ops.round_rate(hw, rate, parent_rate); | |
761 | } | |
762 | ||
763 | static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, | |
764 | unsigned long parent_rate) | |
765 | { | |
79c1e2fc | 766 | return clk_divider_ops.recalc_rate(hw, parent_rate); |
41691b88 EA |
767 | } |
768 | ||
769 | static void bcm2835_pll_divider_off(struct clk_hw *hw) | |
770 | { | |
771 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
772 | struct bcm2835_cprman *cprman = divider->cprman; | |
773 | const struct bcm2835_pll_divider_data *data = divider->data; | |
774 | ||
ec36a5c6 | 775 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
776 | cprman_write(cprman, data->cm_reg, |
777 | (cprman_read(cprman, data->cm_reg) & | |
778 | ~data->load_mask) | data->hold_mask); | |
68af4fa8 BB |
779 | cprman_write(cprman, data->a2w_reg, |
780 | cprman_read(cprman, data->a2w_reg) | | |
781 | A2W_PLL_CHANNEL_DISABLE); | |
ec36a5c6 | 782 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
783 | } |
784 | ||
785 | static int bcm2835_pll_divider_on(struct clk_hw *hw) | |
786 | { | |
787 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
788 | struct bcm2835_cprman *cprman = divider->cprman; | |
789 | const struct bcm2835_pll_divider_data *data = divider->data; | |
790 | ||
ec36a5c6 | 791 | spin_lock(&cprman->regs_lock); |
41691b88 EA |
792 | cprman_write(cprman, data->a2w_reg, |
793 | cprman_read(cprman, data->a2w_reg) & | |
794 | ~A2W_PLL_CHANNEL_DISABLE); | |
795 | ||
796 | cprman_write(cprman, data->cm_reg, | |
797 | cprman_read(cprman, data->cm_reg) & ~data->hold_mask); | |
ec36a5c6 | 798 | spin_unlock(&cprman->regs_lock); |
41691b88 EA |
799 | |
800 | return 0; | |
801 | } | |
802 | ||
803 | static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, | |
804 | unsigned long rate, | |
805 | unsigned long parent_rate) | |
806 | { | |
807 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
808 | struct bcm2835_cprman *cprman = divider->cprman; | |
809 | const struct bcm2835_pll_divider_data *data = divider->data; | |
773b3966 | 810 | u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; |
41691b88 | 811 | |
773b3966 EA |
812 | div = DIV_ROUND_UP_ULL(parent_rate, rate); |
813 | ||
814 | div = min(div, max_div); | |
815 | if (div == max_div) | |
816 | div = 0; | |
41691b88 | 817 | |
773b3966 | 818 | cprman_write(cprman, data->a2w_reg, div); |
41691b88 EA |
819 | cm = cprman_read(cprman, data->cm_reg); |
820 | cprman_write(cprman, data->cm_reg, cm | data->load_mask); | |
821 | cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
96bf9c69 MS |
826 | static int bcm2835_pll_divider_debug_init(struct clk_hw *hw, |
827 | struct dentry *dentry) | |
828 | { | |
829 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
830 | struct bcm2835_cprman *cprman = divider->cprman; | |
831 | const struct bcm2835_pll_divider_data *data = divider->data; | |
832 | struct debugfs_reg32 *regs; | |
833 | ||
834 | regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); | |
835 | if (!regs) | |
836 | return -ENOMEM; | |
837 | ||
838 | regs[0].name = "cm"; | |
839 | regs[0].offset = data->cm_reg; | |
840 | regs[1].name = "a2w"; | |
841 | regs[1].offset = data->a2w_reg; | |
842 | ||
843 | return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); | |
844 | } | |
845 | ||
41691b88 EA |
846 | static const struct clk_ops bcm2835_pll_divider_clk_ops = { |
847 | .is_prepared = bcm2835_pll_divider_is_on, | |
848 | .prepare = bcm2835_pll_divider_on, | |
849 | .unprepare = bcm2835_pll_divider_off, | |
850 | .recalc_rate = bcm2835_pll_divider_get_rate, | |
851 | .set_rate = bcm2835_pll_divider_set_rate, | |
852 | .round_rate = bcm2835_pll_divider_round_rate, | |
96bf9c69 | 853 | .debug_init = bcm2835_pll_divider_debug_init, |
41691b88 EA |
854 | }; |
855 | ||
856 | /* | |
857 | * The CM dividers do fixed-point division, so we can't use the | |
858 | * generic integer divider code like the PLL dividers do (and we can't | |
859 | * fake it by having some fixed shifts preceding it in the clock tree, | |
860 | * because we'd run out of bits in a 32-bit unsigned long). | |
861 | */ | |
862 | struct bcm2835_clock { | |
863 | struct clk_hw hw; | |
864 | struct bcm2835_cprman *cprman; | |
865 | const struct bcm2835_clock_data *data; | |
866 | }; | |
867 | ||
868 | static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) | |
869 | { | |
870 | return container_of(hw, struct bcm2835_clock, hw); | |
871 | } | |
872 | ||
873 | static int bcm2835_clock_is_on(struct clk_hw *hw) | |
874 | { | |
875 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
876 | struct bcm2835_cprman *cprman = clock->cprman; | |
877 | const struct bcm2835_clock_data *data = clock->data; | |
878 | ||
879 | return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; | |
880 | } | |
881 | ||
882 | static u32 bcm2835_clock_choose_div(struct clk_hw *hw, | |
883 | unsigned long rate, | |
9c95b32c RP |
884 | unsigned long parent_rate, |
885 | bool round_up) | |
41691b88 EA |
886 | { |
887 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
888 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c RP |
889 | u32 unused_frac_mask = |
890 | GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; | |
41691b88 | 891 | u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; |
9c95b32c | 892 | u64 rem; |
959ca92a | 893 | u32 div, mindiv, maxdiv; |
41691b88 | 894 | |
9c95b32c | 895 | rem = do_div(temp, rate); |
41691b88 EA |
896 | div = temp; |
897 | ||
9c95b32c RP |
898 | /* Round up and mask off the unused bits */ |
899 | if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) | |
900 | div += unused_frac_mask + 1; | |
901 | div &= ~unused_frac_mask; | |
41691b88 | 902 | |
959ca92a MS |
903 | /* different clamping limits apply for a mash clock */ |
904 | if (data->is_mash_clock) { | |
905 | /* clamp to min divider of 2 */ | |
906 | mindiv = 2 << CM_DIV_FRAC_BITS; | |
907 | /* clamp to the highest possible integer divider */ | |
908 | maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; | |
909 | } else { | |
910 | /* clamp to min divider of 1 */ | |
911 | mindiv = 1 << CM_DIV_FRAC_BITS; | |
912 | /* clamp to the highest possible fractional divider */ | |
913 | maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, | |
914 | CM_DIV_FRAC_BITS - data->frac_bits); | |
915 | } | |
916 | ||
917 | /* apply the clamping limits */ | |
918 | div = max_t(u32, div, mindiv); | |
919 | div = min_t(u32, div, maxdiv); | |
41691b88 EA |
920 | |
921 | return div; | |
922 | } | |
923 | ||
924 | static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, | |
925 | unsigned long parent_rate, | |
926 | u32 div) | |
927 | { | |
928 | const struct bcm2835_clock_data *data = clock->data; | |
929 | u64 temp; | |
930 | ||
8a39e9fa EA |
931 | if (data->int_bits == 0 && data->frac_bits == 0) |
932 | return parent_rate; | |
933 | ||
41691b88 EA |
934 | /* |
935 | * The divisor is a 12.12 fixed point field, but only some of | |
936 | * the bits are populated in any given clock. | |
937 | */ | |
938 | div >>= CM_DIV_FRAC_BITS - data->frac_bits; | |
939 | div &= (1 << (data->int_bits + data->frac_bits)) - 1; | |
940 | ||
941 | if (div == 0) | |
942 | return 0; | |
943 | ||
944 | temp = (u64)parent_rate << data->frac_bits; | |
945 | ||
946 | do_div(temp, div); | |
947 | ||
948 | return temp; | |
949 | } | |
950 | ||
41691b88 EA |
951 | static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, |
952 | unsigned long parent_rate) | |
953 | { | |
954 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
955 | struct bcm2835_cprman *cprman = clock->cprman; | |
956 | const struct bcm2835_clock_data *data = clock->data; | |
8a39e9fa EA |
957 | u32 div; |
958 | ||
959 | if (data->int_bits == 0 && data->frac_bits == 0) | |
960 | return parent_rate; | |
961 | ||
962 | div = cprman_read(cprman, data->div_reg); | |
41691b88 EA |
963 | |
964 | return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); | |
965 | } | |
966 | ||
967 | static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) | |
968 | { | |
969 | struct bcm2835_cprman *cprman = clock->cprman; | |
970 | const struct bcm2835_clock_data *data = clock->data; | |
971 | ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
972 | ||
973 | while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { | |
974 | if (ktime_after(ktime_get(), timeout)) { | |
975 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
976 | clk_hw_get_name(&clock->hw)); | |
977 | return; | |
978 | } | |
979 | cpu_relax(); | |
980 | } | |
981 | } | |
982 | ||
983 | static void bcm2835_clock_off(struct clk_hw *hw) | |
984 | { | |
985 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
986 | struct bcm2835_cprman *cprman = clock->cprman; | |
987 | const struct bcm2835_clock_data *data = clock->data; | |
988 | ||
989 | spin_lock(&cprman->regs_lock); | |
990 | cprman_write(cprman, data->ctl_reg, | |
991 | cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); | |
992 | spin_unlock(&cprman->regs_lock); | |
993 | ||
994 | /* BUSY will remain high until the divider completes its cycle. */ | |
995 | bcm2835_clock_wait_busy(clock); | |
996 | } | |
997 | ||
998 | static int bcm2835_clock_on(struct clk_hw *hw) | |
999 | { | |
1000 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1001 | struct bcm2835_cprman *cprman = clock->cprman; | |
1002 | const struct bcm2835_clock_data *data = clock->data; | |
1003 | ||
1004 | spin_lock(&cprman->regs_lock); | |
1005 | cprman_write(cprman, data->ctl_reg, | |
1006 | cprman_read(cprman, data->ctl_reg) | | |
1007 | CM_ENABLE | | |
1008 | CM_GATE); | |
1009 | spin_unlock(&cprman->regs_lock); | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | static int bcm2835_clock_set_rate(struct clk_hw *hw, | |
1015 | unsigned long rate, unsigned long parent_rate) | |
1016 | { | |
1017 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1018 | struct bcm2835_cprman *cprman = clock->cprman; | |
1019 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c | 1020 | u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); |
959ca92a MS |
1021 | u32 ctl; |
1022 | ||
1023 | spin_lock(&cprman->regs_lock); | |
1024 | ||
1025 | /* | |
1026 | * Setting up frac support | |
1027 | * | |
1028 | * In principle it is recommended to stop/start the clock first, | |
1029 | * but as we set CLK_SET_RATE_GATE during registration of the | |
1030 | * clock this requirement should be take care of by the | |
1031 | * clk-framework. | |
1032 | */ | |
1033 | ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; | |
1034 | ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; | |
1035 | cprman_write(cprman, data->ctl_reg, ctl); | |
41691b88 EA |
1036 | |
1037 | cprman_write(cprman, data->div_reg, div); | |
1038 | ||
959ca92a MS |
1039 | spin_unlock(&cprman->regs_lock); |
1040 | ||
41691b88 EA |
1041 | return 0; |
1042 | } | |
1043 | ||
67615c58 EA |
1044 | static bool |
1045 | bcm2835_clk_is_pllc(struct clk_hw *hw) | |
1046 | { | |
1047 | if (!hw) | |
1048 | return false; | |
1049 | ||
1050 | return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; | |
1051 | } | |
1052 | ||
155e8b3b BB |
1053 | static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, |
1054 | int parent_idx, | |
1055 | unsigned long rate, | |
1056 | u32 *div, | |
1057 | unsigned long *prate) | |
1058 | { | |
1059 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1060 | struct bcm2835_cprman *cprman = clock->cprman; | |
1061 | const struct bcm2835_clock_data *data = clock->data; | |
2aab7a20 | 1062 | unsigned long best_rate = 0; |
155e8b3b BB |
1063 | u32 curdiv, mindiv, maxdiv; |
1064 | struct clk_hw *parent; | |
1065 | ||
1066 | parent = clk_hw_get_parent_by_index(hw, parent_idx); | |
1067 | ||
1068 | if (!(BIT(parent_idx) & data->set_rate_parent)) { | |
1069 | *prate = clk_hw_get_rate(parent); | |
1070 | *div = bcm2835_clock_choose_div(hw, rate, *prate, true); | |
1071 | ||
1072 | return bcm2835_clock_rate_from_divisor(clock, *prate, | |
1073 | *div); | |
1074 | } | |
1075 | ||
1076 | if (data->frac_bits) | |
1077 | dev_warn(cprman->dev, | |
1078 | "frac bits are not used when propagating rate change"); | |
1079 | ||
1080 | /* clamp to min divider of 2 if we're dealing with a mash clock */ | |
1081 | mindiv = data->is_mash_clock ? 2 : 1; | |
1082 | maxdiv = BIT(data->int_bits) - 1; | |
1083 | ||
1084 | /* TODO: Be smart, and only test a subset of the available divisors. */ | |
1085 | for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) { | |
1086 | unsigned long tmp_rate; | |
1087 | ||
1088 | tmp_rate = clk_hw_round_rate(parent, rate * curdiv); | |
1089 | tmp_rate /= curdiv; | |
1090 | if (curdiv == mindiv || | |
1091 | (tmp_rate > best_rate && tmp_rate <= rate)) | |
1092 | best_rate = tmp_rate; | |
1093 | ||
1094 | if (best_rate == rate) | |
1095 | break; | |
1096 | } | |
1097 | ||
1098 | *div = curdiv << CM_DIV_FRAC_BITS; | |
1099 | *prate = curdiv * best_rate; | |
1100 | ||
1101 | return best_rate; | |
1102 | } | |
1103 | ||
6d18b8ad | 1104 | static int bcm2835_clock_determine_rate(struct clk_hw *hw, |
6e1e60da | 1105 | struct clk_rate_request *req) |
6d18b8ad | 1106 | { |
6d18b8ad | 1107 | struct clk_hw *parent, *best_parent = NULL; |
67615c58 | 1108 | bool current_parent_is_pllc; |
6d18b8ad RP |
1109 | unsigned long rate, best_rate = 0; |
1110 | unsigned long prate, best_prate = 0; | |
1111 | size_t i; | |
1112 | u32 div; | |
1113 | ||
67615c58 EA |
1114 | current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); |
1115 | ||
6d18b8ad RP |
1116 | /* |
1117 | * Select parent clock that results in the closest but lower rate | |
1118 | */ | |
1119 | for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { | |
1120 | parent = clk_hw_get_parent_by_index(hw, i); | |
1121 | if (!parent) | |
1122 | continue; | |
67615c58 EA |
1123 | |
1124 | /* | |
1125 | * Don't choose a PLLC-derived clock as our parent | |
1126 | * unless it had been manually set that way. PLLC's | |
1127 | * frequency gets adjusted by the firmware due to | |
1128 | * over-temp or under-voltage conditions, without | |
1129 | * prior notification to our clock consumer. | |
1130 | */ | |
1131 | if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) | |
1132 | continue; | |
1133 | ||
155e8b3b BB |
1134 | rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, |
1135 | &div, &prate); | |
6d18b8ad RP |
1136 | if (rate > best_rate && rate <= req->rate) { |
1137 | best_parent = parent; | |
1138 | best_prate = prate; | |
1139 | best_rate = rate; | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | if (!best_parent) | |
1144 | return -EINVAL; | |
1145 | ||
1146 | req->best_parent_hw = best_parent; | |
1147 | req->best_parent_rate = best_prate; | |
1148 | ||
1149 | req->rate = best_rate; | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) | |
1155 | { | |
1156 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1157 | struct bcm2835_cprman *cprman = clock->cprman; | |
1158 | const struct bcm2835_clock_data *data = clock->data; | |
1159 | u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; | |
1160 | ||
1161 | cprman_write(cprman, data->ctl_reg, src); | |
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static u8 bcm2835_clock_get_parent(struct clk_hw *hw) | |
1166 | { | |
1167 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1168 | struct bcm2835_cprman *cprman = clock->cprman; | |
1169 | const struct bcm2835_clock_data *data = clock->data; | |
1170 | u32 src = cprman_read(cprman, data->ctl_reg); | |
1171 | ||
1172 | return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; | |
1173 | } | |
1174 | ||
96bf9c69 MS |
1175 | static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { |
1176 | { | |
1177 | .name = "ctl", | |
1178 | .offset = 0, | |
1179 | }, | |
1180 | { | |
1181 | .name = "div", | |
1182 | .offset = 4, | |
1183 | }, | |
1184 | }; | |
1185 | ||
1186 | static int bcm2835_clock_debug_init(struct clk_hw *hw, | |
1187 | struct dentry *dentry) | |
1188 | { | |
1189 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1190 | struct bcm2835_cprman *cprman = clock->cprman; | |
1191 | const struct bcm2835_clock_data *data = clock->data; | |
1192 | ||
1193 | return bcm2835_debugfs_regset( | |
1194 | cprman, data->ctl_reg, | |
1195 | bcm2835_debugfs_clock_reg32, | |
1196 | ARRAY_SIZE(bcm2835_debugfs_clock_reg32), | |
1197 | dentry); | |
1198 | } | |
1199 | ||
41691b88 EA |
1200 | static const struct clk_ops bcm2835_clock_clk_ops = { |
1201 | .is_prepared = bcm2835_clock_is_on, | |
1202 | .prepare = bcm2835_clock_on, | |
1203 | .unprepare = bcm2835_clock_off, | |
1204 | .recalc_rate = bcm2835_clock_get_rate, | |
1205 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1206 | .determine_rate = bcm2835_clock_determine_rate, |
1207 | .set_parent = bcm2835_clock_set_parent, | |
1208 | .get_parent = bcm2835_clock_get_parent, | |
96bf9c69 | 1209 | .debug_init = bcm2835_clock_debug_init, |
41691b88 EA |
1210 | }; |
1211 | ||
1212 | static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) | |
1213 | { | |
1214 | return true; | |
1215 | } | |
1216 | ||
1217 | /* | |
1218 | * The VPU clock can never be disabled (it doesn't have an ENABLE | |
1219 | * bit), so it gets its own set of clock ops. | |
1220 | */ | |
1221 | static const struct clk_ops bcm2835_vpu_clock_clk_ops = { | |
1222 | .is_prepared = bcm2835_vpu_clock_is_on, | |
1223 | .recalc_rate = bcm2835_clock_get_rate, | |
1224 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1225 | .determine_rate = bcm2835_clock_determine_rate, |
1226 | .set_parent = bcm2835_clock_set_parent, | |
1227 | .get_parent = bcm2835_clock_get_parent, | |
96bf9c69 | 1228 | .debug_init = bcm2835_clock_debug_init, |
41691b88 EA |
1229 | }; |
1230 | ||
b19f009d SB |
1231 | static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, |
1232 | const struct bcm2835_pll_data *data) | |
41691b88 EA |
1233 | { |
1234 | struct bcm2835_pll *pll; | |
1235 | struct clk_init_data init; | |
b19f009d | 1236 | int ret; |
41691b88 EA |
1237 | |
1238 | memset(&init, 0, sizeof(init)); | |
1239 | ||
1240 | /* All of the PLLs derive from the external oscillator. */ | |
8a39e9fa | 1241 | init.parent_names = &cprman->real_parent_names[0]; |
41691b88 EA |
1242 | init.num_parents = 1; |
1243 | init.name = data->name; | |
1244 | init.ops = &bcm2835_pll_clk_ops; | |
1245 | init.flags = CLK_IGNORE_UNUSED; | |
1246 | ||
1247 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
1248 | if (!pll) | |
1249 | return NULL; | |
1250 | ||
1251 | pll->cprman = cprman; | |
1252 | pll->data = data; | |
1253 | pll->hw.init = &init; | |
1254 | ||
b19f009d SB |
1255 | ret = devm_clk_hw_register(cprman->dev, &pll->hw); |
1256 | if (ret) | |
1257 | return NULL; | |
1258 | return &pll->hw; | |
41691b88 EA |
1259 | } |
1260 | ||
b19f009d | 1261 | static struct clk_hw * |
41691b88 EA |
1262 | bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, |
1263 | const struct bcm2835_pll_divider_data *data) | |
1264 | { | |
1265 | struct bcm2835_pll_divider *divider; | |
1266 | struct clk_init_data init; | |
41691b88 | 1267 | const char *divider_name; |
b19f009d | 1268 | int ret; |
41691b88 EA |
1269 | |
1270 | if (data->fixed_divider != 1) { | |
1271 | divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, | |
1272 | "%s_prediv", data->name); | |
1273 | if (!divider_name) | |
1274 | return NULL; | |
1275 | } else { | |
1276 | divider_name = data->name; | |
1277 | } | |
1278 | ||
1279 | memset(&init, 0, sizeof(init)); | |
1280 | ||
3b15afef | 1281 | init.parent_names = &data->source_pll; |
41691b88 EA |
1282 | init.num_parents = 1; |
1283 | init.name = divider_name; | |
1284 | init.ops = &bcm2835_pll_divider_clk_ops; | |
55486091 | 1285 | init.flags = data->flags | CLK_IGNORE_UNUSED; |
41691b88 EA |
1286 | |
1287 | divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); | |
1288 | if (!divider) | |
1289 | return NULL; | |
1290 | ||
1291 | divider->div.reg = cprman->regs + data->a2w_reg; | |
1292 | divider->div.shift = A2W_PLL_DIV_SHIFT; | |
1293 | divider->div.width = A2W_PLL_DIV_BITS; | |
79c1e2fc | 1294 | divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; |
41691b88 EA |
1295 | divider->div.lock = &cprman->regs_lock; |
1296 | divider->div.hw.init = &init; | |
1297 | divider->div.table = NULL; | |
1298 | ||
1299 | divider->cprman = cprman; | |
1300 | divider->data = data; | |
1301 | ||
b19f009d SB |
1302 | ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); |
1303 | if (ret) | |
1304 | return ERR_PTR(ret); | |
41691b88 EA |
1305 | |
1306 | /* | |
1307 | * PLLH's channels have a fixed divide by 10 afterwards, which | |
1308 | * is what our consumers are actually using. | |
1309 | */ | |
1310 | if (data->fixed_divider != 1) { | |
b19f009d SB |
1311 | return clk_hw_register_fixed_factor(cprman->dev, data->name, |
1312 | divider_name, | |
1313 | CLK_SET_RATE_PARENT, | |
1314 | 1, | |
1315 | data->fixed_divider); | |
41691b88 EA |
1316 | } |
1317 | ||
b19f009d | 1318 | return ÷r->div.hw; |
41691b88 EA |
1319 | } |
1320 | ||
b19f009d | 1321 | static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, |
41691b88 EA |
1322 | const struct bcm2835_clock_data *data) |
1323 | { | |
1324 | struct bcm2835_clock *clock; | |
1325 | struct clk_init_data init; | |
6d18b8ad | 1326 | const char *parents[1 << CM_SRC_BITS]; |
8a39e9fa | 1327 | size_t i, j; |
b19f009d | 1328 | int ret; |
41691b88 EA |
1329 | |
1330 | /* | |
8a39e9fa EA |
1331 | * Replace our strings referencing parent clocks with the |
1332 | * actual clock-output-name of the parent. | |
41691b88 | 1333 | */ |
6d18b8ad | 1334 | for (i = 0; i < data->num_mux_parents; i++) { |
8a39e9fa EA |
1335 | parents[i] = data->parents[i]; |
1336 | ||
1337 | for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) { | |
1338 | if (strcmp(parents[i], cprman_parent_names[j]) == 0) { | |
1339 | parents[i] = cprman->real_parent_names[j]; | |
1340 | break; | |
1341 | } | |
1342 | } | |
41691b88 EA |
1343 | } |
1344 | ||
1345 | memset(&init, 0, sizeof(init)); | |
6d18b8ad RP |
1346 | init.parent_names = parents; |
1347 | init.num_parents = data->num_mux_parents; | |
41691b88 | 1348 | init.name = data->name; |
e69fdcca | 1349 | init.flags = data->flags | CLK_IGNORE_UNUSED; |
41691b88 | 1350 | |
155e8b3b BB |
1351 | /* |
1352 | * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate | |
1353 | * rate changes on at least of the parents. | |
1354 | */ | |
1355 | if (data->set_rate_parent) | |
1356 | init.flags |= CLK_SET_RATE_PARENT; | |
1357 | ||
41691b88 EA |
1358 | if (data->is_vpu_clock) { |
1359 | init.ops = &bcm2835_vpu_clock_clk_ops; | |
1360 | } else { | |
1361 | init.ops = &bcm2835_clock_clk_ops; | |
1362 | init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; | |
eddcbe83 EA |
1363 | |
1364 | /* If the clock wasn't actually enabled at boot, it's not | |
1365 | * critical. | |
1366 | */ | |
1367 | if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE)) | |
1368 | init.flags &= ~CLK_IS_CRITICAL; | |
41691b88 EA |
1369 | } |
1370 | ||
1371 | clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); | |
1372 | if (!clock) | |
1373 | return NULL; | |
1374 | ||
1375 | clock->cprman = cprman; | |
1376 | clock->data = data; | |
1377 | clock->hw.init = &init; | |
1378 | ||
b19f009d SB |
1379 | ret = devm_clk_hw_register(cprman->dev, &clock->hw); |
1380 | if (ret) | |
1381 | return ERR_PTR(ret); | |
1382 | return &clock->hw; | |
41691b88 EA |
1383 | } |
1384 | ||
56eb3a2e MS |
1385 | static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman, |
1386 | const struct bcm2835_gate_data *data) | |
1387 | { | |
1388 | return clk_register_gate(cprman->dev, data->name, data->parent, | |
1389 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, | |
1390 | cprman->regs + data->ctl_reg, | |
1391 | CM_GATE_BIT, 0, &cprman->regs_lock); | |
1392 | } | |
1393 | ||
b19f009d SB |
1394 | typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, |
1395 | const void *data); | |
56eb3a2e MS |
1396 | struct bcm2835_clk_desc { |
1397 | bcm2835_clk_register clk_register; | |
1398 | const void *data; | |
1399 | }; | |
1400 | ||
3b15afef MS |
1401 | /* assignment helper macros for different clock types */ |
1402 | #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ | |
1403 | .data = __VA_ARGS__ } | |
1404 | #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ | |
1405 | &(struct bcm2835_pll_data) \ | |
1406 | {__VA_ARGS__}) | |
1407 | #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ | |
1408 | &(struct bcm2835_pll_divider_data) \ | |
1409 | {__VA_ARGS__}) | |
1410 | #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ | |
1411 | &(struct bcm2835_clock_data) \ | |
1412 | {__VA_ARGS__}) | |
1413 | #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ | |
1414 | &(struct bcm2835_gate_data) \ | |
1415 | {__VA_ARGS__}) | |
1416 | ||
1417 | /* parent mux arrays plus helper macros */ | |
1418 | ||
1419 | /* main oscillator parent mux */ | |
1420 | static const char *const bcm2835_clock_osc_parents[] = { | |
1421 | "gnd", | |
1422 | "xosc", | |
1423 | "testdebug0", | |
1424 | "testdebug1" | |
1425 | }; | |
1426 | ||
1427 | #define REGISTER_OSC_CLK(...) REGISTER_CLK( \ | |
1428 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ | |
1429 | .parents = bcm2835_clock_osc_parents, \ | |
1430 | __VA_ARGS__) | |
1431 | ||
1432 | /* main peripherial parent mux */ | |
1433 | static const char *const bcm2835_clock_per_parents[] = { | |
1434 | "gnd", | |
1435 | "xosc", | |
1436 | "testdebug0", | |
1437 | "testdebug1", | |
1438 | "plla_per", | |
1439 | "pllc_per", | |
1440 | "plld_per", | |
1441 | "pllh_aux", | |
1442 | }; | |
1443 | ||
1444 | #define REGISTER_PER_CLK(...) REGISTER_CLK( \ | |
1445 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ | |
1446 | .parents = bcm2835_clock_per_parents, \ | |
1447 | __VA_ARGS__) | |
56eb3a2e | 1448 | |
3b15afef MS |
1449 | /* main vpu parent mux */ |
1450 | static const char *const bcm2835_clock_vpu_parents[] = { | |
1451 | "gnd", | |
1452 | "xosc", | |
1453 | "testdebug0", | |
1454 | "testdebug1", | |
1455 | "plla_core", | |
1456 | "pllc_core0", | |
1457 | "plld_core", | |
1458 | "pllh_aux", | |
1459 | "pllc_core1", | |
1460 | "pllc_core2", | |
1461 | }; | |
1462 | ||
1463 | #define REGISTER_VPU_CLK(...) REGISTER_CLK( \ | |
1464 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ | |
1465 | .parents = bcm2835_clock_vpu_parents, \ | |
1466 | __VA_ARGS__) | |
1467 | ||
8a39e9fa EA |
1468 | /* |
1469 | * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI | |
1470 | * analog PHY. The _inv variants are generated internally to cprman, | |
1471 | * but we don't use them so they aren't hooked up. | |
1472 | */ | |
1473 | static const char *const bcm2835_clock_dsi0_parents[] = { | |
1474 | "gnd", | |
1475 | "xosc", | |
1476 | "testdebug0", | |
1477 | "testdebug1", | |
1478 | "dsi0_ddr", | |
1479 | "dsi0_ddr_inv", | |
1480 | "dsi0_ddr2", | |
1481 | "dsi0_ddr2_inv", | |
1482 | "dsi0_byte", | |
1483 | "dsi0_byte_inv", | |
1484 | }; | |
1485 | ||
1486 | static const char *const bcm2835_clock_dsi1_parents[] = { | |
1487 | "gnd", | |
1488 | "xosc", | |
1489 | "testdebug0", | |
1490 | "testdebug1", | |
1491 | "dsi1_ddr", | |
1492 | "dsi1_ddr_inv", | |
1493 | "dsi1_ddr2", | |
1494 | "dsi1_ddr2_inv", | |
1495 | "dsi1_byte", | |
1496 | "dsi1_byte_inv", | |
1497 | }; | |
1498 | ||
1499 | #define REGISTER_DSI0_CLK(...) REGISTER_CLK( \ | |
1500 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ | |
1501 | .parents = bcm2835_clock_dsi0_parents, \ | |
1502 | __VA_ARGS__) | |
1503 | ||
1504 | #define REGISTER_DSI1_CLK(...) REGISTER_CLK( \ | |
1505 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ | |
1506 | .parents = bcm2835_clock_dsi1_parents, \ | |
1507 | __VA_ARGS__) | |
1508 | ||
3b15afef MS |
1509 | /* |
1510 | * the real definition of all the pll, pll_dividers and clocks | |
1511 | * these make use of the above REGISTER_* macros | |
1512 | */ | |
56eb3a2e | 1513 | static const struct bcm2835_clk_desc clk_desc_array[] = { |
3b15afef MS |
1514 | /* the PLL + PLL dividers */ |
1515 | ||
1516 | /* | |
1517 | * PLLA is the auxiliary PLL, used to drive the CCP2 | |
1518 | * (Compact Camera Port 2) transmitter clock. | |
1519 | * | |
1520 | * It is in the PX LDO power domain, which is on when the | |
1521 | * AUDIO domain is on. | |
1522 | */ | |
1523 | [BCM2835_PLLA] = REGISTER_PLL( | |
1524 | .name = "plla", | |
1525 | .cm_ctrl_reg = CM_PLLA, | |
1526 | .a2w_ctrl_reg = A2W_PLLA_CTRL, | |
1527 | .frac_reg = A2W_PLLA_FRAC, | |
1528 | .ana_reg_base = A2W_PLLA_ANA0, | |
1529 | .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, | |
1530 | .lock_mask = CM_LOCK_FLOCKA, | |
1531 | ||
1532 | .ana = &bcm2835_ana_default, | |
1533 | ||
1534 | .min_rate = 600000000u, | |
1535 | .max_rate = 2400000000u, | |
1536 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1537 | [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( | |
1538 | .name = "plla_core", | |
1539 | .source_pll = "plla", | |
1540 | .cm_reg = CM_PLLA, | |
1541 | .a2w_reg = A2W_PLLA_CORE, | |
1542 | .load_mask = CM_PLLA_LOADCORE, | |
1543 | .hold_mask = CM_PLLA_HOLDCORE, | |
55486091 EA |
1544 | .fixed_divider = 1, |
1545 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1546 | [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( |
1547 | .name = "plla_per", | |
1548 | .source_pll = "plla", | |
1549 | .cm_reg = CM_PLLA, | |
1550 | .a2w_reg = A2W_PLLA_PER, | |
1551 | .load_mask = CM_PLLA_LOADPER, | |
1552 | .hold_mask = CM_PLLA_HOLDPER, | |
55486091 EA |
1553 | .fixed_divider = 1, |
1554 | .flags = CLK_SET_RATE_PARENT), | |
72843695 MS |
1555 | [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( |
1556 | .name = "plla_dsi0", | |
1557 | .source_pll = "plla", | |
1558 | .cm_reg = CM_PLLA, | |
1559 | .a2w_reg = A2W_PLLA_DSI0, | |
1560 | .load_mask = CM_PLLA_LOADDSI0, | |
1561 | .hold_mask = CM_PLLA_HOLDDSI0, | |
1562 | .fixed_divider = 1), | |
1563 | [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( | |
1564 | .name = "plla_ccp2", | |
1565 | .source_pll = "plla", | |
1566 | .cm_reg = CM_PLLA, | |
1567 | .a2w_reg = A2W_PLLA_CCP2, | |
1568 | .load_mask = CM_PLLA_LOADCCP2, | |
1569 | .hold_mask = CM_PLLA_HOLDCCP2, | |
55486091 EA |
1570 | .fixed_divider = 1, |
1571 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1572 | |
1573 | /* PLLB is used for the ARM's clock. */ | |
1574 | [BCM2835_PLLB] = REGISTER_PLL( | |
1575 | .name = "pllb", | |
1576 | .cm_ctrl_reg = CM_PLLB, | |
1577 | .a2w_ctrl_reg = A2W_PLLB_CTRL, | |
1578 | .frac_reg = A2W_PLLB_FRAC, | |
1579 | .ana_reg_base = A2W_PLLB_ANA0, | |
1580 | .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, | |
1581 | .lock_mask = CM_LOCK_FLOCKB, | |
1582 | ||
1583 | .ana = &bcm2835_ana_default, | |
1584 | ||
1585 | .min_rate = 600000000u, | |
1586 | .max_rate = 3000000000u, | |
1587 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1588 | [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( | |
1589 | .name = "pllb_arm", | |
1590 | .source_pll = "pllb", | |
1591 | .cm_reg = CM_PLLB, | |
1592 | .a2w_reg = A2W_PLLB_ARM, | |
1593 | .load_mask = CM_PLLB_LOADARM, | |
1594 | .hold_mask = CM_PLLB_HOLDARM, | |
55486091 EA |
1595 | .fixed_divider = 1, |
1596 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1597 | |
1598 | /* | |
1599 | * PLLC is the core PLL, used to drive the core VPU clock. | |
1600 | * | |
1601 | * It is in the PX LDO power domain, which is on when the | |
1602 | * AUDIO domain is on. | |
1603 | */ | |
1604 | [BCM2835_PLLC] = REGISTER_PLL( | |
1605 | .name = "pllc", | |
1606 | .cm_ctrl_reg = CM_PLLC, | |
1607 | .a2w_ctrl_reg = A2W_PLLC_CTRL, | |
1608 | .frac_reg = A2W_PLLC_FRAC, | |
1609 | .ana_reg_base = A2W_PLLC_ANA0, | |
1610 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
1611 | .lock_mask = CM_LOCK_FLOCKC, | |
1612 | ||
1613 | .ana = &bcm2835_ana_default, | |
1614 | ||
1615 | .min_rate = 600000000u, | |
1616 | .max_rate = 3000000000u, | |
1617 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1618 | [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( | |
1619 | .name = "pllc_core0", | |
1620 | .source_pll = "pllc", | |
1621 | .cm_reg = CM_PLLC, | |
1622 | .a2w_reg = A2W_PLLC_CORE0, | |
1623 | .load_mask = CM_PLLC_LOADCORE0, | |
1624 | .hold_mask = CM_PLLC_HOLDCORE0, | |
55486091 EA |
1625 | .fixed_divider = 1, |
1626 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1627 | [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( |
1628 | .name = "pllc_core1", | |
1629 | .source_pll = "pllc", | |
1630 | .cm_reg = CM_PLLC, | |
1631 | .a2w_reg = A2W_PLLC_CORE1, | |
1632 | .load_mask = CM_PLLC_LOADCORE1, | |
1633 | .hold_mask = CM_PLLC_HOLDCORE1, | |
55486091 EA |
1634 | .fixed_divider = 1, |
1635 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1636 | [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( |
1637 | .name = "pllc_core2", | |
1638 | .source_pll = "pllc", | |
1639 | .cm_reg = CM_PLLC, | |
1640 | .a2w_reg = A2W_PLLC_CORE2, | |
1641 | .load_mask = CM_PLLC_LOADCORE2, | |
1642 | .hold_mask = CM_PLLC_HOLDCORE2, | |
55486091 EA |
1643 | .fixed_divider = 1, |
1644 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1645 | [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( |
1646 | .name = "pllc_per", | |
1647 | .source_pll = "pllc", | |
1648 | .cm_reg = CM_PLLC, | |
1649 | .a2w_reg = A2W_PLLC_PER, | |
1650 | .load_mask = CM_PLLC_LOADPER, | |
1651 | .hold_mask = CM_PLLC_HOLDPER, | |
55486091 EA |
1652 | .fixed_divider = 1, |
1653 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1654 | |
1655 | /* | |
1656 | * PLLD is the display PLL, used to drive DSI display panels. | |
1657 | * | |
1658 | * It is in the PX LDO power domain, which is on when the | |
1659 | * AUDIO domain is on. | |
1660 | */ | |
1661 | [BCM2835_PLLD] = REGISTER_PLL( | |
1662 | .name = "plld", | |
1663 | .cm_ctrl_reg = CM_PLLD, | |
1664 | .a2w_ctrl_reg = A2W_PLLD_CTRL, | |
1665 | .frac_reg = A2W_PLLD_FRAC, | |
1666 | .ana_reg_base = A2W_PLLD_ANA0, | |
1667 | .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, | |
1668 | .lock_mask = CM_LOCK_FLOCKD, | |
1669 | ||
1670 | .ana = &bcm2835_ana_default, | |
1671 | ||
1672 | .min_rate = 600000000u, | |
1673 | .max_rate = 2400000000u, | |
1674 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1675 | [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( | |
1676 | .name = "plld_core", | |
1677 | .source_pll = "plld", | |
1678 | .cm_reg = CM_PLLD, | |
1679 | .a2w_reg = A2W_PLLD_CORE, | |
1680 | .load_mask = CM_PLLD_LOADCORE, | |
1681 | .hold_mask = CM_PLLD_HOLDCORE, | |
55486091 EA |
1682 | .fixed_divider = 1, |
1683 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1684 | [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( |
1685 | .name = "plld_per", | |
1686 | .source_pll = "plld", | |
1687 | .cm_reg = CM_PLLD, | |
1688 | .a2w_reg = A2W_PLLD_PER, | |
1689 | .load_mask = CM_PLLD_LOADPER, | |
1690 | .hold_mask = CM_PLLD_HOLDPER, | |
55486091 EA |
1691 | .fixed_divider = 1, |
1692 | .flags = CLK_SET_RATE_PARENT), | |
72843695 MS |
1693 | [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( |
1694 | .name = "plld_dsi0", | |
1695 | .source_pll = "plld", | |
1696 | .cm_reg = CM_PLLD, | |
1697 | .a2w_reg = A2W_PLLD_DSI0, | |
1698 | .load_mask = CM_PLLD_LOADDSI0, | |
1699 | .hold_mask = CM_PLLD_HOLDDSI0, | |
1700 | .fixed_divider = 1), | |
1701 | [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( | |
1702 | .name = "plld_dsi1", | |
1703 | .source_pll = "plld", | |
1704 | .cm_reg = CM_PLLD, | |
1705 | .a2w_reg = A2W_PLLD_DSI1, | |
1706 | .load_mask = CM_PLLD_LOADDSI1, | |
1707 | .hold_mask = CM_PLLD_HOLDDSI1, | |
1708 | .fixed_divider = 1), | |
3b15afef MS |
1709 | |
1710 | /* | |
1711 | * PLLH is used to supply the pixel clock or the AUX clock for the | |
1712 | * TV encoder. | |
1713 | * | |
1714 | * It is in the HDMI power domain. | |
1715 | */ | |
1716 | [BCM2835_PLLH] = REGISTER_PLL( | |
1717 | "pllh", | |
1718 | .cm_ctrl_reg = CM_PLLH, | |
1719 | .a2w_ctrl_reg = A2W_PLLH_CTRL, | |
1720 | .frac_reg = A2W_PLLH_FRAC, | |
1721 | .ana_reg_base = A2W_PLLH_ANA0, | |
1722 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
1723 | .lock_mask = CM_LOCK_FLOCKH, | |
1724 | ||
1725 | .ana = &bcm2835_ana_pllh, | |
1726 | ||
1727 | .min_rate = 600000000u, | |
1728 | .max_rate = 3000000000u, | |
1729 | .max_fb_rate = BCM2835_MAX_FB_RATE), | |
1730 | [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( | |
1731 | .name = "pllh_rcal", | |
1732 | .source_pll = "pllh", | |
1733 | .cm_reg = CM_PLLH, | |
1734 | .a2w_reg = A2W_PLLH_RCAL, | |
1735 | .load_mask = CM_PLLH_LOADRCAL, | |
1736 | .hold_mask = 0, | |
55486091 EA |
1737 | .fixed_divider = 10, |
1738 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1739 | [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( |
1740 | .name = "pllh_aux", | |
1741 | .source_pll = "pllh", | |
1742 | .cm_reg = CM_PLLH, | |
1743 | .a2w_reg = A2W_PLLH_AUX, | |
1744 | .load_mask = CM_PLLH_LOADAUX, | |
1745 | .hold_mask = 0, | |
55486091 EA |
1746 | .fixed_divider = 1, |
1747 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef MS |
1748 | [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( |
1749 | .name = "pllh_pix", | |
1750 | .source_pll = "pllh", | |
1751 | .cm_reg = CM_PLLH, | |
1752 | .a2w_reg = A2W_PLLH_PIX, | |
1753 | .load_mask = CM_PLLH_LOADPIX, | |
1754 | .hold_mask = 0, | |
55486091 EA |
1755 | .fixed_divider = 10, |
1756 | .flags = CLK_SET_RATE_PARENT), | |
3b15afef | 1757 | |
56eb3a2e | 1758 | /* the clocks */ |
3b15afef MS |
1759 | |
1760 | /* clocks with oscillator parent mux */ | |
1761 | ||
1762 | /* One Time Programmable Memory clock. Maximum 10Mhz. */ | |
1763 | [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( | |
1764 | .name = "otp", | |
1765 | .ctl_reg = CM_OTPCTL, | |
1766 | .div_reg = CM_OTPDIV, | |
1767 | .int_bits = 4, | |
1768 | .frac_bits = 0), | |
1769 | /* | |
1770 | * Used for a 1Mhz clock for the system clocksource, and also used | |
1771 | * bythe watchdog timer and the camera pulse generator. | |
1772 | */ | |
1773 | [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( | |
1774 | .name = "timer", | |
1775 | .ctl_reg = CM_TIMERCTL, | |
1776 | .div_reg = CM_TIMERDIV, | |
1777 | .int_bits = 6, | |
1778 | .frac_bits = 12), | |
1779 | /* | |
1780 | * Clock for the temperature sensor. | |
1781 | * Generally run at 2Mhz, max 5Mhz. | |
1782 | */ | |
1783 | [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( | |
1784 | .name = "tsens", | |
1785 | .ctl_reg = CM_TSENSCTL, | |
1786 | .div_reg = CM_TSENSDIV, | |
1787 | .int_bits = 5, | |
1788 | .frac_bits = 0), | |
d3d6f15f MS |
1789 | [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( |
1790 | .name = "tec", | |
1791 | .ctl_reg = CM_TECCTL, | |
1792 | .div_reg = CM_TECDIV, | |
1793 | .int_bits = 6, | |
1794 | .frac_bits = 0), | |
3b15afef MS |
1795 | |
1796 | /* clocks with vpu parent mux */ | |
1797 | [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( | |
1798 | .name = "h264", | |
1799 | .ctl_reg = CM_H264CTL, | |
1800 | .div_reg = CM_H264DIV, | |
1801 | .int_bits = 4, | |
1802 | .frac_bits = 8), | |
1803 | [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( | |
1804 | .name = "isp", | |
1805 | .ctl_reg = CM_ISPCTL, | |
1806 | .div_reg = CM_ISPDIV, | |
1807 | .int_bits = 4, | |
1808 | .frac_bits = 8), | |
d3d6f15f | 1809 | |
3b15afef MS |
1810 | /* |
1811 | * Secondary SDRAM clock. Used for low-voltage modes when the PLL | |
1812 | * in the SDRAM controller can't be used. | |
1813 | */ | |
1814 | [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( | |
1815 | .name = "sdram", | |
1816 | .ctl_reg = CM_SDCCTL, | |
1817 | .div_reg = CM_SDCDIV, | |
1818 | .int_bits = 6, | |
1819 | .frac_bits = 0), | |
1820 | [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( | |
1821 | .name = "v3d", | |
1822 | .ctl_reg = CM_V3DCTL, | |
1823 | .div_reg = CM_V3DDIV, | |
1824 | .int_bits = 4, | |
1825 | .frac_bits = 8), | |
1826 | /* | |
1827 | * VPU clock. This doesn't have an enable bit, since it drives | |
1828 | * the bus for everything else, and is special so it doesn't need | |
1829 | * to be gated for rate changes. It is also known as "clk_audio" | |
1830 | * in various hardware documentation. | |
1831 | */ | |
1832 | [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( | |
1833 | .name = "vpu", | |
1834 | .ctl_reg = CM_VPUCTL, | |
1835 | .div_reg = CM_VPUDIV, | |
1836 | .int_bits = 12, | |
1837 | .frac_bits = 8, | |
e69fdcca | 1838 | .flags = CLK_IS_CRITICAL, |
3b15afef MS |
1839 | .is_vpu_clock = true), |
1840 | ||
1841 | /* clocks with per parent mux */ | |
d3d6f15f MS |
1842 | [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( |
1843 | .name = "aveo", | |
1844 | .ctl_reg = CM_AVEOCTL, | |
1845 | .div_reg = CM_AVEODIV, | |
1846 | .int_bits = 4, | |
1847 | .frac_bits = 0), | |
1848 | [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( | |
1849 | .name = "cam0", | |
1850 | .ctl_reg = CM_CAM0CTL, | |
1851 | .div_reg = CM_CAM0DIV, | |
1852 | .int_bits = 4, | |
1853 | .frac_bits = 8), | |
1854 | [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( | |
1855 | .name = "cam1", | |
1856 | .ctl_reg = CM_CAM1CTL, | |
1857 | .div_reg = CM_CAM1DIV, | |
1858 | .int_bits = 4, | |
1859 | .frac_bits = 8), | |
1860 | [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( | |
1861 | .name = "dft", | |
1862 | .ctl_reg = CM_DFTCTL, | |
1863 | .div_reg = CM_DFTDIV, | |
1864 | .int_bits = 5, | |
1865 | .frac_bits = 0), | |
1866 | [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( | |
1867 | .name = "dpi", | |
1868 | .ctl_reg = CM_DPICTL, | |
1869 | .div_reg = CM_DPIDIV, | |
1870 | .int_bits = 4, | |
1871 | .frac_bits = 8), | |
3b15afef MS |
1872 | |
1873 | /* Arasan EMMC clock */ | |
1874 | [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( | |
1875 | .name = "emmc", | |
1876 | .ctl_reg = CM_EMMCCTL, | |
1877 | .div_reg = CM_EMMCDIV, | |
1878 | .int_bits = 4, | |
1879 | .frac_bits = 8), | |
d3d6f15f MS |
1880 | |
1881 | /* General purpose (GPIO) clocks */ | |
1882 | [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( | |
1883 | .name = "gp0", | |
1884 | .ctl_reg = CM_GP0CTL, | |
1885 | .div_reg = CM_GP0DIV, | |
1886 | .int_bits = 12, | |
1887 | .frac_bits = 12, | |
1888 | .is_mash_clock = true), | |
1889 | [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( | |
1890 | .name = "gp1", | |
1891 | .ctl_reg = CM_GP1CTL, | |
1892 | .div_reg = CM_GP1DIV, | |
1893 | .int_bits = 12, | |
1894 | .frac_bits = 12, | |
eddcbe83 | 1895 | .flags = CLK_IS_CRITICAL, |
d3d6f15f MS |
1896 | .is_mash_clock = true), |
1897 | [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( | |
1898 | .name = "gp2", | |
1899 | .ctl_reg = CM_GP2CTL, | |
1900 | .div_reg = CM_GP2DIV, | |
1901 | .int_bits = 12, | |
eddcbe83 EA |
1902 | .frac_bits = 12, |
1903 | .flags = CLK_IS_CRITICAL), | |
d3d6f15f | 1904 | |
3b15afef MS |
1905 | /* HDMI state machine */ |
1906 | [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( | |
1907 | .name = "hsm", | |
1908 | .ctl_reg = CM_HSMCTL, | |
1909 | .div_reg = CM_HSMDIV, | |
1910 | .int_bits = 4, | |
1911 | .frac_bits = 8), | |
33b68960 MS |
1912 | [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK( |
1913 | .name = "pcm", | |
1914 | .ctl_reg = CM_PCMCTL, | |
1915 | .div_reg = CM_PCMDIV, | |
1916 | .int_bits = 12, | |
1917 | .frac_bits = 12, | |
1918 | .is_mash_clock = true), | |
3b15afef MS |
1919 | [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( |
1920 | .name = "pwm", | |
1921 | .ctl_reg = CM_PWMCTL, | |
1922 | .div_reg = CM_PWMDIV, | |
1923 | .int_bits = 12, | |
1924 | .frac_bits = 12, | |
1925 | .is_mash_clock = true), | |
d3d6f15f MS |
1926 | [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( |
1927 | .name = "slim", | |
1928 | .ctl_reg = CM_SLIMCTL, | |
1929 | .div_reg = CM_SLIMDIV, | |
1930 | .int_bits = 12, | |
1931 | .frac_bits = 12, | |
1932 | .is_mash_clock = true), | |
1933 | [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( | |
1934 | .name = "smi", | |
1935 | .ctl_reg = CM_SMICTL, | |
1936 | .div_reg = CM_SMIDIV, | |
1937 | .int_bits = 4, | |
1938 | .frac_bits = 8), | |
3b15afef MS |
1939 | [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( |
1940 | .name = "uart", | |
1941 | .ctl_reg = CM_UARTCTL, | |
1942 | .div_reg = CM_UARTDIV, | |
1943 | .int_bits = 10, | |
1944 | .frac_bits = 12), | |
d3d6f15f | 1945 | |
3b15afef MS |
1946 | /* TV encoder clock. Only operating frequency is 108Mhz. */ |
1947 | [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( | |
1948 | .name = "vec", | |
1949 | .ctl_reg = CM_VECCTL, | |
1950 | .div_reg = CM_VECDIV, | |
1951 | .int_bits = 4, | |
d86d46af BB |
1952 | .frac_bits = 0, |
1953 | /* | |
1954 | * Allow rate change propagation only on PLLH_AUX which is | |
1955 | * assigned index 7 in the parent array. | |
1956 | */ | |
1957 | .set_rate_parent = BIT(7)), | |
3b15afef | 1958 | |
d3d6f15f MS |
1959 | /* dsi clocks */ |
1960 | [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( | |
1961 | .name = "dsi0e", | |
1962 | .ctl_reg = CM_DSI0ECTL, | |
1963 | .div_reg = CM_DSI0EDIV, | |
1964 | .int_bits = 4, | |
1965 | .frac_bits = 8), | |
1966 | [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( | |
1967 | .name = "dsi1e", | |
1968 | .ctl_reg = CM_DSI1ECTL, | |
1969 | .div_reg = CM_DSI1EDIV, | |
1970 | .int_bits = 4, | |
1971 | .frac_bits = 8), | |
8a39e9fa EA |
1972 | [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( |
1973 | .name = "dsi0p", | |
1974 | .ctl_reg = CM_DSI0PCTL, | |
1975 | .div_reg = CM_DSI0PDIV, | |
1976 | .int_bits = 0, | |
1977 | .frac_bits = 0), | |
1978 | [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( | |
1979 | .name = "dsi1p", | |
1980 | .ctl_reg = CM_DSI1PCTL, | |
1981 | .div_reg = CM_DSI1PDIV, | |
1982 | .int_bits = 0, | |
1983 | .frac_bits = 0), | |
d3d6f15f | 1984 | |
56eb3a2e | 1985 | /* the gates */ |
3b15afef MS |
1986 | |
1987 | /* | |
1988 | * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if | |
1989 | * you have the debug bit set in the power manager, which we | |
1990 | * don't bother exposing) are individual gates off of the | |
1991 | * non-stop vpu clock. | |
1992 | */ | |
56eb3a2e | 1993 | [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( |
3b15afef MS |
1994 | .name = "peri_image", |
1995 | .parent = "vpu", | |
1996 | .ctl_reg = CM_PERIICTL), | |
56eb3a2e MS |
1997 | }; |
1998 | ||
9e400c5c EA |
1999 | /* |
2000 | * Permanently take a reference on the parent of the SDRAM clock. | |
2001 | * | |
2002 | * While the SDRAM is being driven by its dedicated PLL most of the | |
2003 | * time, there is a little loop running in the firmware that | |
2004 | * periodically switches the SDRAM to using our CM clock to do PVT | |
2005 | * recalibration, with the assumption that the previously configured | |
2006 | * SDRAM parent is still enabled and running. | |
2007 | */ | |
2008 | static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) | |
2009 | { | |
2010 | struct clk *parent = clk_get_parent(sdc); | |
2011 | ||
2012 | if (IS_ERR(parent)) | |
2013 | return PTR_ERR(parent); | |
2014 | ||
2015 | return clk_prepare_enable(parent); | |
2016 | } | |
2017 | ||
41691b88 EA |
2018 | static int bcm2835_clk_probe(struct platform_device *pdev) |
2019 | { | |
2020 | struct device *dev = &pdev->dev; | |
b19f009d | 2021 | struct clk_hw **hws; |
41691b88 EA |
2022 | struct bcm2835_cprman *cprman; |
2023 | struct resource *res; | |
56eb3a2e MS |
2024 | const struct bcm2835_clk_desc *desc; |
2025 | const size_t asize = ARRAY_SIZE(clk_desc_array); | |
2026 | size_t i; | |
9e400c5c | 2027 | int ret; |
41691b88 | 2028 | |
b19f009d SB |
2029 | cprman = devm_kzalloc(dev, sizeof(*cprman) + |
2030 | sizeof(*cprman->onecell.hws) * asize, | |
56eb3a2e | 2031 | GFP_KERNEL); |
41691b88 EA |
2032 | if (!cprman) |
2033 | return -ENOMEM; | |
2034 | ||
2035 | spin_lock_init(&cprman->regs_lock); | |
2036 | cprman->dev = dev; | |
2037 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2038 | cprman->regs = devm_ioremap_resource(dev, res); | |
2039 | if (IS_ERR(cprman->regs)) | |
2040 | return PTR_ERR(cprman->regs); | |
2041 | ||
8a39e9fa EA |
2042 | memcpy(cprman->real_parent_names, cprman_parent_names, |
2043 | sizeof(cprman_parent_names)); | |
2044 | of_clk_parent_fill(dev->of_node, cprman->real_parent_names, | |
2045 | ARRAY_SIZE(cprman_parent_names)); | |
2046 | ||
2047 | /* | |
2048 | * Make sure the external oscillator has been registered. | |
2049 | * | |
2050 | * The other (DSI) clocks are not present on older device | |
2051 | * trees, which we still need to support for backwards | |
2052 | * compatibility. | |
2053 | */ | |
2054 | if (!cprman->real_parent_names[0]) | |
41691b88 EA |
2055 | return -ENODEV; |
2056 | ||
2057 | platform_set_drvdata(pdev, cprman); | |
2058 | ||
b19f009d SB |
2059 | cprman->onecell.num = asize; |
2060 | hws = cprman->onecell.hws; | |
41691b88 | 2061 | |
56eb3a2e MS |
2062 | for (i = 0; i < asize; i++) { |
2063 | desc = &clk_desc_array[i]; | |
2064 | if (desc->clk_register && desc->data) | |
b19f009d | 2065 | hws[i] = desc->clk_register(cprman, desc->data); |
56eb3a2e | 2066 | } |
cfbab8fb | 2067 | |
b19f009d | 2068 | ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); |
9e400c5c EA |
2069 | if (ret) |
2070 | return ret; | |
2071 | ||
b19f009d SB |
2072 | return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, |
2073 | &cprman->onecell); | |
41691b88 EA |
2074 | } |
2075 | ||
2076 | static const struct of_device_id bcm2835_clk_of_match[] = { | |
2077 | { .compatible = "brcm,bcm2835-cprman", }, | |
2078 | {} | |
2079 | }; | |
2080 | MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); | |
2081 | ||
2082 | static struct platform_driver bcm2835_clk_driver = { | |
2083 | .driver = { | |
2084 | .name = "bcm2835-clk", | |
2085 | .of_match_table = bcm2835_clk_of_match, | |
2086 | }, | |
2087 | .probe = bcm2835_clk_probe, | |
2088 | }; | |
2089 | ||
2090 | builtin_platform_driver(bcm2835_clk_driver); | |
2091 | ||
2092 | MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); | |
2093 | MODULE_DESCRIPTION("BCM2835 clock driver"); | |
2094 | MODULE_LICENSE("GPL v2"); |