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75fabc3f | 1 | /* |
41691b88 | 2 | * Copyright (C) 2010,2015 Broadcom |
75fabc3f SA |
3 | * Copyright (C) 2012 Stephen Warren |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
41691b88 EA |
20 | /** |
21 | * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) | |
22 | * | |
23 | * The clock tree on the 2835 has several levels. There's a root | |
24 | * oscillator running at 19.2Mhz. After the oscillator there are 5 | |
25 | * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", | |
26 | * and "HDMI displays". Those 5 PLLs each can divide their output to | |
27 | * produce up to 4 channels. Finally, there is the level of clocks to | |
28 | * be consumed by other hardware components (like "H264" or "HDMI | |
29 | * state machine"), which divide off of some subset of the PLL | |
30 | * channels. | |
31 | * | |
32 | * All of the clocks in the tree are exposed in the DT, because the DT | |
33 | * may want to make assignments of the final layer of clocks to the | |
34 | * PLL channels, and some components of the hardware will actually | |
35 | * skip layers of the tree (for example, the pixel clock comes | |
36 | * directly from the PLLH PIX channel without using a CM_*CTL clock | |
37 | * generator). | |
38 | */ | |
39 | ||
75fabc3f SA |
40 | #include <linux/clk-provider.h> |
41 | #include <linux/clkdev.h> | |
42 | #include <linux/clk/bcm2835.h> | |
41691b88 | 43 | #include <linux/module.h> |
526d239c | 44 | #include <linux/of.h> |
41691b88 EA |
45 | #include <linux/platform_device.h> |
46 | #include <linux/slab.h> | |
47 | #include <dt-bindings/clock/bcm2835.h> | |
48 | ||
49 | #define CM_PASSWORD 0x5a000000 | |
50 | ||
51 | #define CM_GNRICCTL 0x000 | |
52 | #define CM_GNRICDIV 0x004 | |
53 | # define CM_DIV_FRAC_BITS 12 | |
54 | ||
55 | #define CM_VPUCTL 0x008 | |
56 | #define CM_VPUDIV 0x00c | |
57 | #define CM_SYSCTL 0x010 | |
58 | #define CM_SYSDIV 0x014 | |
59 | #define CM_PERIACTL 0x018 | |
60 | #define CM_PERIADIV 0x01c | |
61 | #define CM_PERIICTL 0x020 | |
62 | #define CM_PERIIDIV 0x024 | |
63 | #define CM_H264CTL 0x028 | |
64 | #define CM_H264DIV 0x02c | |
65 | #define CM_ISPCTL 0x030 | |
66 | #define CM_ISPDIV 0x034 | |
67 | #define CM_V3DCTL 0x038 | |
68 | #define CM_V3DDIV 0x03c | |
69 | #define CM_CAM0CTL 0x040 | |
70 | #define CM_CAM0DIV 0x044 | |
71 | #define CM_CAM1CTL 0x048 | |
72 | #define CM_CAM1DIV 0x04c | |
73 | #define CM_CCP2CTL 0x050 | |
74 | #define CM_CCP2DIV 0x054 | |
75 | #define CM_DSI0ECTL 0x058 | |
76 | #define CM_DSI0EDIV 0x05c | |
77 | #define CM_DSI0PCTL 0x060 | |
78 | #define CM_DSI0PDIV 0x064 | |
79 | #define CM_DPICTL 0x068 | |
80 | #define CM_DPIDIV 0x06c | |
81 | #define CM_GP0CTL 0x070 | |
82 | #define CM_GP0DIV 0x074 | |
83 | #define CM_GP1CTL 0x078 | |
84 | #define CM_GP1DIV 0x07c | |
85 | #define CM_GP2CTL 0x080 | |
86 | #define CM_GP2DIV 0x084 | |
87 | #define CM_HSMCTL 0x088 | |
88 | #define CM_HSMDIV 0x08c | |
89 | #define CM_OTPCTL 0x090 | |
90 | #define CM_OTPDIV 0x094 | |
91 | #define CM_PWMCTL 0x0a0 | |
92 | #define CM_PWMDIV 0x0a4 | |
93 | #define CM_SMICTL 0x0b0 | |
94 | #define CM_SMIDIV 0x0b4 | |
95 | #define CM_TSENSCTL 0x0e0 | |
96 | #define CM_TSENSDIV 0x0e4 | |
97 | #define CM_TIMERCTL 0x0e8 | |
98 | #define CM_TIMERDIV 0x0ec | |
99 | #define CM_UARTCTL 0x0f0 | |
100 | #define CM_UARTDIV 0x0f4 | |
101 | #define CM_VECCTL 0x0f8 | |
102 | #define CM_VECDIV 0x0fc | |
103 | #define CM_PULSECTL 0x190 | |
104 | #define CM_PULSEDIV 0x194 | |
105 | #define CM_SDCCTL 0x1a8 | |
106 | #define CM_SDCDIV 0x1ac | |
107 | #define CM_ARMCTL 0x1b0 | |
108 | #define CM_EMMCCTL 0x1c0 | |
109 | #define CM_EMMCDIV 0x1c4 | |
110 | ||
111 | /* General bits for the CM_*CTL regs */ | |
112 | # define CM_ENABLE BIT(4) | |
113 | # define CM_KILL BIT(5) | |
114 | # define CM_GATE_BIT 6 | |
115 | # define CM_GATE BIT(CM_GATE_BIT) | |
116 | # define CM_BUSY BIT(7) | |
117 | # define CM_BUSYD BIT(8) | |
118 | # define CM_SRC_SHIFT 0 | |
119 | # define CM_SRC_BITS 4 | |
120 | # define CM_SRC_MASK 0xf | |
121 | # define CM_SRC_GND 0 | |
122 | # define CM_SRC_OSC 1 | |
123 | # define CM_SRC_TESTDEBUG0 2 | |
124 | # define CM_SRC_TESTDEBUG1 3 | |
125 | # define CM_SRC_PLLA_CORE 4 | |
126 | # define CM_SRC_PLLA_PER 4 | |
127 | # define CM_SRC_PLLC_CORE0 5 | |
128 | # define CM_SRC_PLLC_PER 5 | |
129 | # define CM_SRC_PLLC_CORE1 8 | |
130 | # define CM_SRC_PLLD_CORE 6 | |
131 | # define CM_SRC_PLLD_PER 6 | |
132 | # define CM_SRC_PLLH_AUX 7 | |
133 | # define CM_SRC_PLLC_CORE1 8 | |
134 | # define CM_SRC_PLLC_CORE2 9 | |
135 | ||
136 | #define CM_OSCCOUNT 0x100 | |
137 | ||
138 | #define CM_PLLA 0x104 | |
139 | # define CM_PLL_ANARST BIT(8) | |
140 | # define CM_PLLA_HOLDPER BIT(7) | |
141 | # define CM_PLLA_LOADPER BIT(6) | |
142 | # define CM_PLLA_HOLDCORE BIT(5) | |
143 | # define CM_PLLA_LOADCORE BIT(4) | |
144 | # define CM_PLLA_HOLDCCP2 BIT(3) | |
145 | # define CM_PLLA_LOADCCP2 BIT(2) | |
146 | # define CM_PLLA_HOLDDSI0 BIT(1) | |
147 | # define CM_PLLA_LOADDSI0 BIT(0) | |
148 | ||
149 | #define CM_PLLC 0x108 | |
150 | # define CM_PLLC_HOLDPER BIT(7) | |
151 | # define CM_PLLC_LOADPER BIT(6) | |
152 | # define CM_PLLC_HOLDCORE2 BIT(5) | |
153 | # define CM_PLLC_LOADCORE2 BIT(4) | |
154 | # define CM_PLLC_HOLDCORE1 BIT(3) | |
155 | # define CM_PLLC_LOADCORE1 BIT(2) | |
156 | # define CM_PLLC_HOLDCORE0 BIT(1) | |
157 | # define CM_PLLC_LOADCORE0 BIT(0) | |
158 | ||
159 | #define CM_PLLD 0x10c | |
160 | # define CM_PLLD_HOLDPER BIT(7) | |
161 | # define CM_PLLD_LOADPER BIT(6) | |
162 | # define CM_PLLD_HOLDCORE BIT(5) | |
163 | # define CM_PLLD_LOADCORE BIT(4) | |
164 | # define CM_PLLD_HOLDDSI1 BIT(3) | |
165 | # define CM_PLLD_LOADDSI1 BIT(2) | |
166 | # define CM_PLLD_HOLDDSI0 BIT(1) | |
167 | # define CM_PLLD_LOADDSI0 BIT(0) | |
168 | ||
169 | #define CM_PLLH 0x110 | |
170 | # define CM_PLLH_LOADRCAL BIT(2) | |
171 | # define CM_PLLH_LOADAUX BIT(1) | |
172 | # define CM_PLLH_LOADPIX BIT(0) | |
173 | ||
174 | #define CM_LOCK 0x114 | |
175 | # define CM_LOCK_FLOCKH BIT(12) | |
176 | # define CM_LOCK_FLOCKD BIT(11) | |
177 | # define CM_LOCK_FLOCKC BIT(10) | |
178 | # define CM_LOCK_FLOCKB BIT(9) | |
179 | # define CM_LOCK_FLOCKA BIT(8) | |
180 | ||
181 | #define CM_EVENT 0x118 | |
182 | #define CM_DSI1ECTL 0x158 | |
183 | #define CM_DSI1EDIV 0x15c | |
184 | #define CM_DSI1PCTL 0x160 | |
185 | #define CM_DSI1PDIV 0x164 | |
186 | #define CM_DFTCTL 0x168 | |
187 | #define CM_DFTDIV 0x16c | |
188 | ||
189 | #define CM_PLLB 0x170 | |
190 | # define CM_PLLB_HOLDARM BIT(1) | |
191 | # define CM_PLLB_LOADARM BIT(0) | |
192 | ||
193 | #define A2W_PLLA_CTRL 0x1100 | |
194 | #define A2W_PLLC_CTRL 0x1120 | |
195 | #define A2W_PLLD_CTRL 0x1140 | |
196 | #define A2W_PLLH_CTRL 0x1160 | |
197 | #define A2W_PLLB_CTRL 0x11e0 | |
198 | # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) | |
199 | # define A2W_PLL_CTRL_PWRDN BIT(16) | |
200 | # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 | |
201 | # define A2W_PLL_CTRL_PDIV_SHIFT 12 | |
202 | # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff | |
203 | # define A2W_PLL_CTRL_NDIV_SHIFT 0 | |
204 | ||
205 | #define A2W_PLLA_ANA0 0x1010 | |
206 | #define A2W_PLLC_ANA0 0x1030 | |
207 | #define A2W_PLLD_ANA0 0x1050 | |
208 | #define A2W_PLLH_ANA0 0x1070 | |
209 | #define A2W_PLLB_ANA0 0x10f0 | |
210 | ||
211 | #define A2W_PLL_KA_SHIFT 7 | |
212 | #define A2W_PLL_KA_MASK GENMASK(9, 7) | |
213 | #define A2W_PLL_KI_SHIFT 19 | |
214 | #define A2W_PLL_KI_MASK GENMASK(21, 19) | |
215 | #define A2W_PLL_KP_SHIFT 15 | |
216 | #define A2W_PLL_KP_MASK GENMASK(18, 15) | |
217 | ||
218 | #define A2W_PLLH_KA_SHIFT 19 | |
219 | #define A2W_PLLH_KA_MASK GENMASK(21, 19) | |
220 | #define A2W_PLLH_KI_LOW_SHIFT 22 | |
221 | #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) | |
222 | #define A2W_PLLH_KI_HIGH_SHIFT 0 | |
223 | #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) | |
224 | #define A2W_PLLH_KP_SHIFT 1 | |
225 | #define A2W_PLLH_KP_MASK GENMASK(4, 1) | |
226 | ||
227 | #define A2W_XOSC_CTRL 0x1190 | |
228 | # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) | |
229 | # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) | |
230 | # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) | |
231 | # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) | |
232 | # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) | |
233 | # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) | |
234 | # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) | |
235 | # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) | |
236 | ||
237 | #define A2W_PLLA_FRAC 0x1200 | |
238 | #define A2W_PLLC_FRAC 0x1220 | |
239 | #define A2W_PLLD_FRAC 0x1240 | |
240 | #define A2W_PLLH_FRAC 0x1260 | |
241 | #define A2W_PLLB_FRAC 0x12e0 | |
242 | # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) | |
243 | # define A2W_PLL_FRAC_BITS 20 | |
244 | ||
245 | #define A2W_PLL_CHANNEL_DISABLE BIT(8) | |
246 | #define A2W_PLL_DIV_BITS 8 | |
247 | #define A2W_PLL_DIV_SHIFT 0 | |
248 | ||
249 | #define A2W_PLLA_DSI0 0x1300 | |
250 | #define A2W_PLLA_CORE 0x1400 | |
251 | #define A2W_PLLA_PER 0x1500 | |
252 | #define A2W_PLLA_CCP2 0x1600 | |
253 | ||
254 | #define A2W_PLLC_CORE2 0x1320 | |
255 | #define A2W_PLLC_CORE1 0x1420 | |
256 | #define A2W_PLLC_PER 0x1520 | |
257 | #define A2W_PLLC_CORE0 0x1620 | |
258 | ||
259 | #define A2W_PLLD_DSI0 0x1340 | |
260 | #define A2W_PLLD_CORE 0x1440 | |
261 | #define A2W_PLLD_PER 0x1540 | |
262 | #define A2W_PLLD_DSI1 0x1640 | |
263 | ||
264 | #define A2W_PLLH_AUX 0x1360 | |
265 | #define A2W_PLLH_RCAL 0x1460 | |
266 | #define A2W_PLLH_PIX 0x1560 | |
267 | #define A2W_PLLH_STS 0x1660 | |
268 | ||
269 | #define A2W_PLLH_CTRLR 0x1960 | |
270 | #define A2W_PLLH_FRACR 0x1a60 | |
271 | #define A2W_PLLH_AUXR 0x1b60 | |
272 | #define A2W_PLLH_RCALR 0x1c60 | |
273 | #define A2W_PLLH_PIXR 0x1d60 | |
274 | #define A2W_PLLH_STSR 0x1e60 | |
275 | ||
276 | #define A2W_PLLB_ARM 0x13e0 | |
277 | #define A2W_PLLB_SP0 0x14e0 | |
278 | #define A2W_PLLB_SP1 0x15e0 | |
279 | #define A2W_PLLB_SP2 0x16e0 | |
280 | ||
281 | #define LOCK_TIMEOUT_NS 100000000 | |
282 | #define BCM2835_MAX_FB_RATE 1750000000u | |
283 | ||
284 | struct bcm2835_cprman { | |
285 | struct device *dev; | |
286 | void __iomem *regs; | |
287 | spinlock_t regs_lock; | |
288 | const char *osc_name; | |
289 | ||
290 | struct clk_onecell_data onecell; | |
291 | struct clk *clks[BCM2835_CLOCK_COUNT]; | |
292 | }; | |
293 | ||
294 | static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) | |
295 | { | |
296 | writel(CM_PASSWORD | val, cprman->regs + reg); | |
297 | } | |
298 | ||
299 | static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) | |
300 | { | |
301 | return readl(cprman->regs + reg); | |
302 | } | |
526d239c | 303 | |
75fabc3f SA |
304 | /* |
305 | * These are fixed clocks. They're probably not all root clocks and it may | |
306 | * be possible to turn them on and off but until this is mapped out better | |
307 | * it's the only way they can be used. | |
308 | */ | |
309 | void __init bcm2835_init_clocks(void) | |
310 | { | |
311 | struct clk *clk; | |
312 | int ret; | |
313 | ||
75fabc3f SA |
314 | clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, |
315 | 126000000); | |
0de9f23a | 316 | if (IS_ERR(clk)) |
75fabc3f SA |
317 | pr_err("apb_pclk not registered\n"); |
318 | ||
319 | clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT, | |
320 | 3000000); | |
0de9f23a | 321 | if (IS_ERR(clk)) |
75fabc3f SA |
322 | pr_err("uart0_pclk not registered\n"); |
323 | ret = clk_register_clkdev(clk, NULL, "20201000.uart"); | |
324 | if (ret) | |
325 | pr_err("uart0_pclk alias not registered\n"); | |
326 | ||
327 | clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT, | |
328 | 125000000); | |
0de9f23a | 329 | if (IS_ERR(clk)) |
75fabc3f SA |
330 | pr_err("uart1_pclk not registered\n"); |
331 | ret = clk_register_clkdev(clk, NULL, "20215000.uart"); | |
332 | if (ret) | |
686ea585 | 333 | pr_err("uart1_pclk alias not registered\n"); |
75fabc3f | 334 | } |
41691b88 EA |
335 | |
336 | struct bcm2835_pll_data { | |
337 | const char *name; | |
338 | u32 cm_ctrl_reg; | |
339 | u32 a2w_ctrl_reg; | |
340 | u32 frac_reg; | |
341 | u32 ana_reg_base; | |
342 | u32 reference_enable_mask; | |
343 | /* Bit in CM_LOCK to indicate when the PLL has locked. */ | |
344 | u32 lock_mask; | |
345 | ||
346 | const struct bcm2835_pll_ana_bits *ana; | |
347 | ||
348 | unsigned long min_rate; | |
349 | unsigned long max_rate; | |
350 | /* | |
351 | * Highest rate for the VCO before we have to use the | |
352 | * pre-divide-by-2. | |
353 | */ | |
354 | unsigned long max_fb_rate; | |
355 | }; | |
356 | ||
357 | struct bcm2835_pll_ana_bits { | |
358 | u32 mask0; | |
359 | u32 set0; | |
360 | u32 mask1; | |
361 | u32 set1; | |
362 | u32 mask3; | |
363 | u32 set3; | |
364 | u32 fb_prediv_mask; | |
365 | }; | |
366 | ||
367 | static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { | |
368 | .mask0 = 0, | |
369 | .set0 = 0, | |
370 | .mask1 = ~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK), | |
371 | .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), | |
372 | .mask3 = ~A2W_PLL_KA_MASK, | |
373 | .set3 = (2 << A2W_PLL_KA_SHIFT), | |
374 | .fb_prediv_mask = BIT(14), | |
375 | }; | |
376 | ||
377 | static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { | |
378 | .mask0 = ~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK), | |
379 | .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), | |
380 | .mask1 = ~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK), | |
381 | .set1 = (6 << A2W_PLLH_KP_SHIFT), | |
382 | .mask3 = 0, | |
383 | .set3 = 0, | |
384 | .fb_prediv_mask = BIT(11), | |
385 | }; | |
386 | ||
387 | /* | |
388 | * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera | |
389 | * Port 2) transmitter clock. | |
390 | * | |
391 | * It is in the PX LDO power domain, which is on when the AUDIO domain | |
392 | * is on. | |
393 | */ | |
394 | static const struct bcm2835_pll_data bcm2835_plla_data = { | |
395 | .name = "plla", | |
396 | .cm_ctrl_reg = CM_PLLA, | |
397 | .a2w_ctrl_reg = A2W_PLLA_CTRL, | |
398 | .frac_reg = A2W_PLLA_FRAC, | |
399 | .ana_reg_base = A2W_PLLA_ANA0, | |
400 | .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, | |
401 | .lock_mask = CM_LOCK_FLOCKA, | |
402 | ||
403 | .ana = &bcm2835_ana_default, | |
404 | ||
405 | .min_rate = 600000000u, | |
406 | .max_rate = 2400000000u, | |
407 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
408 | }; | |
409 | ||
410 | /* PLLB is used for the ARM's clock. */ | |
411 | static const struct bcm2835_pll_data bcm2835_pllb_data = { | |
412 | .name = "pllb", | |
413 | .cm_ctrl_reg = CM_PLLB, | |
414 | .a2w_ctrl_reg = A2W_PLLB_CTRL, | |
415 | .frac_reg = A2W_PLLB_FRAC, | |
416 | .ana_reg_base = A2W_PLLB_ANA0, | |
417 | .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, | |
418 | .lock_mask = CM_LOCK_FLOCKB, | |
419 | ||
420 | .ana = &bcm2835_ana_default, | |
421 | ||
422 | .min_rate = 600000000u, | |
423 | .max_rate = 3000000000u, | |
424 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
425 | }; | |
426 | ||
427 | /* | |
428 | * PLLC is the core PLL, used to drive the core VPU clock. | |
429 | * | |
430 | * It is in the PX LDO power domain, which is on when the AUDIO domain | |
431 | * is on. | |
432 | */ | |
433 | static const struct bcm2835_pll_data bcm2835_pllc_data = { | |
434 | .name = "pllc", | |
435 | .cm_ctrl_reg = CM_PLLC, | |
436 | .a2w_ctrl_reg = A2W_PLLC_CTRL, | |
437 | .frac_reg = A2W_PLLC_FRAC, | |
438 | .ana_reg_base = A2W_PLLC_ANA0, | |
439 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
440 | .lock_mask = CM_LOCK_FLOCKC, | |
441 | ||
442 | .ana = &bcm2835_ana_default, | |
443 | ||
444 | .min_rate = 600000000u, | |
445 | .max_rate = 3000000000u, | |
446 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
447 | }; | |
448 | ||
449 | /* | |
450 | * PLLD is the display PLL, used to drive DSI display panels. | |
451 | * | |
452 | * It is in the PX LDO power domain, which is on when the AUDIO domain | |
453 | * is on. | |
454 | */ | |
455 | static const struct bcm2835_pll_data bcm2835_plld_data = { | |
456 | .name = "plld", | |
457 | .cm_ctrl_reg = CM_PLLD, | |
458 | .a2w_ctrl_reg = A2W_PLLD_CTRL, | |
459 | .frac_reg = A2W_PLLD_FRAC, | |
460 | .ana_reg_base = A2W_PLLD_ANA0, | |
461 | .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, | |
462 | .lock_mask = CM_LOCK_FLOCKD, | |
463 | ||
464 | .ana = &bcm2835_ana_default, | |
465 | ||
466 | .min_rate = 600000000u, | |
467 | .max_rate = 2400000000u, | |
468 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
469 | }; | |
470 | ||
471 | /* | |
472 | * PLLH is used to supply the pixel clock or the AUX clock for the TV | |
473 | * encoder. | |
474 | * | |
475 | * It is in the HDMI power domain. | |
476 | */ | |
477 | static const struct bcm2835_pll_data bcm2835_pllh_data = { | |
478 | "pllh", | |
479 | .cm_ctrl_reg = CM_PLLH, | |
480 | .a2w_ctrl_reg = A2W_PLLH_CTRL, | |
481 | .frac_reg = A2W_PLLH_FRAC, | |
482 | .ana_reg_base = A2W_PLLH_ANA0, | |
483 | .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, | |
484 | .lock_mask = CM_LOCK_FLOCKH, | |
485 | ||
486 | .ana = &bcm2835_ana_pllh, | |
487 | ||
488 | .min_rate = 600000000u, | |
489 | .max_rate = 3000000000u, | |
490 | .max_fb_rate = BCM2835_MAX_FB_RATE, | |
491 | }; | |
492 | ||
493 | struct bcm2835_pll_divider_data { | |
494 | const char *name; | |
495 | const struct bcm2835_pll_data *source_pll; | |
496 | u32 cm_reg; | |
497 | u32 a2w_reg; | |
498 | ||
499 | u32 load_mask; | |
500 | u32 hold_mask; | |
501 | u32 fixed_divider; | |
502 | }; | |
503 | ||
504 | static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = { | |
505 | .name = "plla_core", | |
506 | .source_pll = &bcm2835_plla_data, | |
507 | .cm_reg = CM_PLLA, | |
508 | .a2w_reg = A2W_PLLA_CORE, | |
509 | .load_mask = CM_PLLA_LOADCORE, | |
510 | .hold_mask = CM_PLLA_HOLDCORE, | |
511 | .fixed_divider = 1, | |
512 | }; | |
513 | ||
514 | static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = { | |
515 | .name = "plla_per", | |
516 | .source_pll = &bcm2835_plla_data, | |
517 | .cm_reg = CM_PLLA, | |
518 | .a2w_reg = A2W_PLLA_PER, | |
519 | .load_mask = CM_PLLA_LOADPER, | |
520 | .hold_mask = CM_PLLA_HOLDPER, | |
521 | .fixed_divider = 1, | |
522 | }; | |
523 | ||
524 | static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = { | |
525 | .name = "pllb_arm", | |
526 | .source_pll = &bcm2835_pllb_data, | |
527 | .cm_reg = CM_PLLB, | |
528 | .a2w_reg = A2W_PLLB_ARM, | |
529 | .load_mask = CM_PLLB_LOADARM, | |
530 | .hold_mask = CM_PLLB_HOLDARM, | |
531 | .fixed_divider = 1, | |
532 | }; | |
533 | ||
534 | static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = { | |
535 | .name = "pllc_core0", | |
536 | .source_pll = &bcm2835_pllc_data, | |
537 | .cm_reg = CM_PLLC, | |
538 | .a2w_reg = A2W_PLLC_CORE0, | |
539 | .load_mask = CM_PLLC_LOADCORE0, | |
540 | .hold_mask = CM_PLLC_HOLDCORE0, | |
541 | .fixed_divider = 1, | |
542 | }; | |
543 | ||
544 | static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = { | |
545 | .name = "pllc_core1", .source_pll = &bcm2835_pllc_data, | |
546 | .cm_reg = CM_PLLC, A2W_PLLC_CORE1, | |
547 | .load_mask = CM_PLLC_LOADCORE1, | |
548 | .hold_mask = CM_PLLC_HOLDCORE1, | |
549 | .fixed_divider = 1, | |
550 | }; | |
551 | ||
552 | static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = { | |
553 | .name = "pllc_core2", | |
554 | .source_pll = &bcm2835_pllc_data, | |
555 | .cm_reg = CM_PLLC, | |
556 | .a2w_reg = A2W_PLLC_CORE2, | |
557 | .load_mask = CM_PLLC_LOADCORE2, | |
558 | .hold_mask = CM_PLLC_HOLDCORE2, | |
559 | .fixed_divider = 1, | |
560 | }; | |
561 | ||
562 | static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = { | |
563 | .name = "pllc_per", | |
564 | .source_pll = &bcm2835_pllc_data, | |
565 | .cm_reg = CM_PLLC, | |
566 | .a2w_reg = A2W_PLLC_PER, | |
567 | .load_mask = CM_PLLC_LOADPER, | |
568 | .hold_mask = CM_PLLC_HOLDPER, | |
569 | .fixed_divider = 1, | |
570 | }; | |
571 | ||
572 | static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = { | |
573 | .name = "plld_core", | |
574 | .source_pll = &bcm2835_plld_data, | |
575 | .cm_reg = CM_PLLD, | |
576 | .a2w_reg = A2W_PLLD_CORE, | |
577 | .load_mask = CM_PLLD_LOADCORE, | |
578 | .hold_mask = CM_PLLD_HOLDCORE, | |
579 | .fixed_divider = 1, | |
580 | }; | |
581 | ||
582 | static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = { | |
583 | .name = "plld_per", | |
584 | .source_pll = &bcm2835_plld_data, | |
585 | .cm_reg = CM_PLLD, | |
586 | .a2w_reg = A2W_PLLD_PER, | |
587 | .load_mask = CM_PLLD_LOADPER, | |
588 | .hold_mask = CM_PLLD_HOLDPER, | |
589 | .fixed_divider = 1, | |
590 | }; | |
591 | ||
592 | static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = { | |
593 | .name = "pllh_rcal", | |
594 | .source_pll = &bcm2835_pllh_data, | |
595 | .cm_reg = CM_PLLH, | |
596 | .a2w_reg = A2W_PLLH_RCAL, | |
597 | .load_mask = CM_PLLH_LOADRCAL, | |
598 | .hold_mask = 0, | |
599 | .fixed_divider = 10, | |
600 | }; | |
601 | ||
602 | static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = { | |
603 | .name = "pllh_aux", | |
604 | .source_pll = &bcm2835_pllh_data, | |
605 | .cm_reg = CM_PLLH, | |
606 | .a2w_reg = A2W_PLLH_AUX, | |
607 | .load_mask = CM_PLLH_LOADAUX, | |
608 | .hold_mask = 0, | |
609 | .fixed_divider = 10, | |
610 | }; | |
611 | ||
612 | static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = { | |
613 | .name = "pllh_pix", | |
614 | .source_pll = &bcm2835_pllh_data, | |
615 | .cm_reg = CM_PLLH, | |
616 | .a2w_reg = A2W_PLLH_PIX, | |
617 | .load_mask = CM_PLLH_LOADPIX, | |
618 | .hold_mask = 0, | |
619 | .fixed_divider = 10, | |
620 | }; | |
621 | ||
622 | struct bcm2835_clock_data { | |
623 | const char *name; | |
624 | ||
625 | const char *const *parents; | |
626 | int num_mux_parents; | |
627 | ||
628 | u32 ctl_reg; | |
629 | u32 div_reg; | |
630 | ||
631 | /* Number of integer bits in the divider */ | |
632 | u32 int_bits; | |
633 | /* Number of fractional bits in the divider */ | |
634 | u32 frac_bits; | |
635 | ||
636 | bool is_vpu_clock; | |
637 | }; | |
638 | ||
639 | static const char *const bcm2835_clock_per_parents[] = { | |
640 | "gnd", | |
641 | "xosc", | |
642 | "testdebug0", | |
643 | "testdebug1", | |
644 | "plla_per", | |
645 | "pllc_per", | |
646 | "plld_per", | |
647 | "pllh_aux", | |
648 | }; | |
649 | ||
650 | static const char *const bcm2835_clock_vpu_parents[] = { | |
651 | "gnd", | |
652 | "xosc", | |
653 | "testdebug0", | |
654 | "testdebug1", | |
655 | "plla_core", | |
656 | "pllc_core0", | |
657 | "plld_core", | |
658 | "pllh_aux", | |
659 | "pllc_core1", | |
660 | "pllc_core2", | |
661 | }; | |
662 | ||
663 | static const char *const bcm2835_clock_osc_parents[] = { | |
664 | "gnd", | |
665 | "xosc", | |
666 | "testdebug0", | |
667 | "testdebug1" | |
668 | }; | |
669 | ||
670 | /* | |
671 | * Used for a 1Mhz clock for the system clocksource, and also used by | |
672 | * the watchdog timer and the camera pulse generator. | |
673 | */ | |
674 | static const struct bcm2835_clock_data bcm2835_clock_timer_data = { | |
675 | .name = "timer", | |
676 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), | |
677 | .parents = bcm2835_clock_osc_parents, | |
678 | .ctl_reg = CM_TIMERCTL, | |
679 | .div_reg = CM_TIMERDIV, | |
680 | .int_bits = 6, | |
681 | .frac_bits = 12, | |
682 | }; | |
683 | ||
684 | /* One Time Programmable Memory clock. Maximum 10Mhz. */ | |
685 | static const struct bcm2835_clock_data bcm2835_clock_otp_data = { | |
686 | .name = "otp", | |
687 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), | |
688 | .parents = bcm2835_clock_osc_parents, | |
689 | .ctl_reg = CM_OTPCTL, | |
690 | .div_reg = CM_OTPDIV, | |
691 | .int_bits = 4, | |
692 | .frac_bits = 0, | |
693 | }; | |
694 | ||
695 | /* | |
696 | * VPU clock. This doesn't have an enable bit, since it drives the | |
697 | * bus for everything else, and is special so it doesn't need to be | |
698 | * gated for rate changes. It is also known as "clk_audio" in various | |
699 | * hardware documentation. | |
700 | */ | |
701 | static const struct bcm2835_clock_data bcm2835_clock_vpu_data = { | |
702 | .name = "vpu", | |
703 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
704 | .parents = bcm2835_clock_vpu_parents, | |
705 | .ctl_reg = CM_VPUCTL, | |
706 | .div_reg = CM_VPUDIV, | |
707 | .int_bits = 12, | |
708 | .frac_bits = 8, | |
709 | .is_vpu_clock = true, | |
710 | }; | |
711 | ||
712 | static const struct bcm2835_clock_data bcm2835_clock_v3d_data = { | |
713 | .name = "v3d", | |
714 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
715 | .parents = bcm2835_clock_vpu_parents, | |
716 | .ctl_reg = CM_V3DCTL, | |
717 | .div_reg = CM_V3DDIV, | |
718 | .int_bits = 4, | |
719 | .frac_bits = 8, | |
720 | }; | |
721 | ||
722 | static const struct bcm2835_clock_data bcm2835_clock_isp_data = { | |
723 | .name = "isp", | |
724 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
725 | .parents = bcm2835_clock_vpu_parents, | |
726 | .ctl_reg = CM_ISPCTL, | |
727 | .div_reg = CM_ISPDIV, | |
728 | .int_bits = 4, | |
729 | .frac_bits = 8, | |
730 | }; | |
731 | ||
732 | static const struct bcm2835_clock_data bcm2835_clock_h264_data = { | |
733 | .name = "h264", | |
734 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
735 | .parents = bcm2835_clock_vpu_parents, | |
736 | .ctl_reg = CM_H264CTL, | |
737 | .div_reg = CM_H264DIV, | |
738 | .int_bits = 4, | |
739 | .frac_bits = 8, | |
740 | }; | |
741 | ||
742 | /* TV encoder clock. Only operating frequency is 108Mhz. */ | |
743 | static const struct bcm2835_clock_data bcm2835_clock_vec_data = { | |
744 | .name = "vec", | |
745 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
746 | .parents = bcm2835_clock_per_parents, | |
747 | .ctl_reg = CM_VECCTL, | |
748 | .div_reg = CM_VECDIV, | |
749 | .int_bits = 4, | |
750 | .frac_bits = 0, | |
751 | }; | |
752 | ||
753 | static const struct bcm2835_clock_data bcm2835_clock_uart_data = { | |
754 | .name = "uart", | |
755 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
756 | .parents = bcm2835_clock_per_parents, | |
757 | .ctl_reg = CM_UARTCTL, | |
758 | .div_reg = CM_UARTDIV, | |
759 | .int_bits = 10, | |
760 | .frac_bits = 12, | |
761 | }; | |
762 | ||
763 | /* HDMI state machine */ | |
764 | static const struct bcm2835_clock_data bcm2835_clock_hsm_data = { | |
765 | .name = "hsm", | |
766 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
767 | .parents = bcm2835_clock_per_parents, | |
768 | .ctl_reg = CM_HSMCTL, | |
769 | .div_reg = CM_HSMDIV, | |
770 | .int_bits = 4, | |
771 | .frac_bits = 8, | |
772 | }; | |
773 | ||
774 | /* | |
775 | * Secondary SDRAM clock. Used for low-voltage modes when the PLL in | |
776 | * the SDRAM controller can't be used. | |
777 | */ | |
778 | static const struct bcm2835_clock_data bcm2835_clock_sdram_data = { | |
779 | .name = "sdram", | |
780 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), | |
781 | .parents = bcm2835_clock_vpu_parents, | |
782 | .ctl_reg = CM_SDCCTL, | |
783 | .div_reg = CM_SDCDIV, | |
784 | .int_bits = 6, | |
785 | .frac_bits = 0, | |
786 | }; | |
787 | ||
788 | /* Clock for the temperature sensor. Generally run at 2Mhz, max 5Mhz. */ | |
789 | static const struct bcm2835_clock_data bcm2835_clock_tsens_data = { | |
790 | .name = "tsens", | |
791 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), | |
792 | .parents = bcm2835_clock_osc_parents, | |
793 | .ctl_reg = CM_TSENSCTL, | |
794 | .div_reg = CM_TSENSDIV, | |
795 | .int_bits = 5, | |
796 | .frac_bits = 0, | |
797 | }; | |
798 | ||
799 | /* Arasan EMMC clock */ | |
800 | static const struct bcm2835_clock_data bcm2835_clock_emmc_data = { | |
801 | .name = "emmc", | |
802 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
803 | .parents = bcm2835_clock_per_parents, | |
804 | .ctl_reg = CM_EMMCCTL, | |
805 | .div_reg = CM_EMMCDIV, | |
806 | .int_bits = 4, | |
807 | .frac_bits = 8, | |
808 | }; | |
809 | ||
cfbab8fb RP |
810 | static const struct bcm2835_clock_data bcm2835_clock_pwm_data = { |
811 | .name = "pwm", | |
812 | .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), | |
813 | .parents = bcm2835_clock_per_parents, | |
814 | .ctl_reg = CM_PWMCTL, | |
815 | .div_reg = CM_PWMDIV, | |
816 | .int_bits = 12, | |
817 | .frac_bits = 12, | |
818 | }; | |
819 | ||
41691b88 EA |
820 | struct bcm2835_pll { |
821 | struct clk_hw hw; | |
822 | struct bcm2835_cprman *cprman; | |
823 | const struct bcm2835_pll_data *data; | |
824 | }; | |
825 | ||
826 | static int bcm2835_pll_is_on(struct clk_hw *hw) | |
827 | { | |
828 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
829 | struct bcm2835_cprman *cprman = pll->cprman; | |
830 | const struct bcm2835_pll_data *data = pll->data; | |
831 | ||
832 | return cprman_read(cprman, data->a2w_ctrl_reg) & | |
833 | A2W_PLL_CTRL_PRST_DISABLE; | |
834 | } | |
835 | ||
836 | static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, | |
837 | unsigned long parent_rate, | |
838 | u32 *ndiv, u32 *fdiv) | |
839 | { | |
840 | u64 div; | |
841 | ||
842 | div = (u64)rate << A2W_PLL_FRAC_BITS; | |
843 | do_div(div, parent_rate); | |
844 | ||
845 | *ndiv = div >> A2W_PLL_FRAC_BITS; | |
846 | *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); | |
847 | } | |
848 | ||
849 | static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, | |
850 | u32 ndiv, u32 fdiv, u32 pdiv) | |
851 | { | |
852 | u64 rate; | |
853 | ||
854 | if (pdiv == 0) | |
855 | return 0; | |
856 | ||
857 | rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); | |
858 | do_div(rate, pdiv); | |
859 | return rate >> A2W_PLL_FRAC_BITS; | |
860 | } | |
861 | ||
862 | static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
863 | unsigned long *parent_rate) | |
864 | { | |
865 | u32 ndiv, fdiv; | |
866 | ||
867 | bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); | |
868 | ||
869 | return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); | |
870 | } | |
871 | ||
872 | static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, | |
873 | unsigned long parent_rate) | |
874 | { | |
875 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
876 | struct bcm2835_cprman *cprman = pll->cprman; | |
877 | const struct bcm2835_pll_data *data = pll->data; | |
878 | u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); | |
879 | u32 ndiv, pdiv, fdiv; | |
880 | bool using_prediv; | |
881 | ||
882 | if (parent_rate == 0) | |
883 | return 0; | |
884 | ||
885 | fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; | |
886 | ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; | |
887 | pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; | |
888 | using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & | |
889 | data->ana->fb_prediv_mask; | |
890 | ||
891 | if (using_prediv) | |
892 | ndiv *= 2; | |
893 | ||
894 | return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); | |
895 | } | |
896 | ||
897 | static void bcm2835_pll_off(struct clk_hw *hw) | |
898 | { | |
899 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
900 | struct bcm2835_cprman *cprman = pll->cprman; | |
901 | const struct bcm2835_pll_data *data = pll->data; | |
902 | ||
903 | cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); | |
904 | cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN); | |
905 | } | |
906 | ||
907 | static int bcm2835_pll_on(struct clk_hw *hw) | |
908 | { | |
909 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
910 | struct bcm2835_cprman *cprman = pll->cprman; | |
911 | const struct bcm2835_pll_data *data = pll->data; | |
912 | ktime_t timeout; | |
913 | ||
914 | /* Take the PLL out of reset. */ | |
915 | cprman_write(cprman, data->cm_ctrl_reg, | |
916 | cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); | |
917 | ||
918 | /* Wait for the PLL to lock. */ | |
919 | timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
920 | while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { | |
921 | if (ktime_after(ktime_get(), timeout)) { | |
922 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
923 | clk_hw_get_name(hw)); | |
924 | return -ETIMEDOUT; | |
925 | } | |
926 | ||
927 | cpu_relax(); | |
928 | } | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
933 | static void | |
934 | bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) | |
935 | { | |
936 | int i; | |
937 | ||
938 | /* | |
939 | * ANA register setup is done as a series of writes to | |
940 | * ANA3-ANA0, in that order. This lets us write all 4 | |
941 | * registers as a single cycle of the serdes interface (taking | |
942 | * 100 xosc clocks), whereas if we were to update ana0, 1, and | |
943 | * 3 individually through their partial-write registers, each | |
944 | * would be their own serdes cycle. | |
945 | */ | |
946 | for (i = 3; i >= 0; i--) | |
947 | cprman_write(cprman, ana_reg_base + i * 4, ana[i]); | |
948 | } | |
949 | ||
950 | static int bcm2835_pll_set_rate(struct clk_hw *hw, | |
951 | unsigned long rate, unsigned long parent_rate) | |
952 | { | |
953 | struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); | |
954 | struct bcm2835_cprman *cprman = pll->cprman; | |
955 | const struct bcm2835_pll_data *data = pll->data; | |
956 | bool was_using_prediv, use_fb_prediv, do_ana_setup_first; | |
957 | u32 ndiv, fdiv, a2w_ctl; | |
958 | u32 ana[4]; | |
959 | int i; | |
960 | ||
961 | if (rate < data->min_rate || rate > data->max_rate) { | |
962 | dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n", | |
963 | clk_hw_get_name(hw), rate, | |
964 | data->min_rate, data->max_rate); | |
965 | return -EINVAL; | |
966 | } | |
967 | ||
968 | if (rate > data->max_fb_rate) { | |
969 | use_fb_prediv = true; | |
970 | rate /= 2; | |
971 | } else { | |
972 | use_fb_prediv = false; | |
973 | } | |
974 | ||
975 | bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); | |
976 | ||
977 | for (i = 3; i >= 0; i--) | |
978 | ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); | |
979 | ||
980 | was_using_prediv = ana[1] & data->ana->fb_prediv_mask; | |
981 | ||
982 | ana[0] &= ~data->ana->mask0; | |
983 | ana[0] |= data->ana->set0; | |
984 | ana[1] &= ~data->ana->mask1; | |
985 | ana[1] |= data->ana->set1; | |
986 | ana[3] &= ~data->ana->mask3; | |
987 | ana[3] |= data->ana->set3; | |
988 | ||
989 | if (was_using_prediv && !use_fb_prediv) { | |
990 | ana[1] &= ~data->ana->fb_prediv_mask; | |
991 | do_ana_setup_first = true; | |
992 | } else if (!was_using_prediv && use_fb_prediv) { | |
993 | ana[1] |= data->ana->fb_prediv_mask; | |
994 | do_ana_setup_first = false; | |
995 | } else { | |
996 | do_ana_setup_first = true; | |
997 | } | |
998 | ||
999 | /* Unmask the reference clock from the oscillator. */ | |
1000 | cprman_write(cprman, A2W_XOSC_CTRL, | |
1001 | cprman_read(cprman, A2W_XOSC_CTRL) | | |
1002 | data->reference_enable_mask); | |
1003 | ||
1004 | if (do_ana_setup_first) | |
1005 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
1006 | ||
1007 | /* Set the PLL multiplier from the oscillator. */ | |
1008 | cprman_write(cprman, data->frac_reg, fdiv); | |
1009 | ||
1010 | a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); | |
1011 | a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; | |
1012 | a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; | |
1013 | a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; | |
1014 | a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; | |
1015 | cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); | |
1016 | ||
1017 | if (!do_ana_setup_first) | |
1018 | bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static const struct clk_ops bcm2835_pll_clk_ops = { | |
1024 | .is_prepared = bcm2835_pll_is_on, | |
1025 | .prepare = bcm2835_pll_on, | |
1026 | .unprepare = bcm2835_pll_off, | |
1027 | .recalc_rate = bcm2835_pll_get_rate, | |
1028 | .set_rate = bcm2835_pll_set_rate, | |
1029 | .round_rate = bcm2835_pll_round_rate, | |
1030 | }; | |
1031 | ||
1032 | struct bcm2835_pll_divider { | |
1033 | struct clk_divider div; | |
1034 | struct bcm2835_cprman *cprman; | |
1035 | const struct bcm2835_pll_divider_data *data; | |
1036 | }; | |
1037 | ||
1038 | static struct bcm2835_pll_divider * | |
1039 | bcm2835_pll_divider_from_hw(struct clk_hw *hw) | |
1040 | { | |
1041 | return container_of(hw, struct bcm2835_pll_divider, div.hw); | |
1042 | } | |
1043 | ||
1044 | static int bcm2835_pll_divider_is_on(struct clk_hw *hw) | |
1045 | { | |
1046 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1047 | struct bcm2835_cprman *cprman = divider->cprman; | |
1048 | const struct bcm2835_pll_divider_data *data = divider->data; | |
1049 | ||
1050 | return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); | |
1051 | } | |
1052 | ||
1053 | static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, | |
1054 | unsigned long rate, | |
1055 | unsigned long *parent_rate) | |
1056 | { | |
1057 | return clk_divider_ops.round_rate(hw, rate, parent_rate); | |
1058 | } | |
1059 | ||
1060 | static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, | |
1061 | unsigned long parent_rate) | |
1062 | { | |
1063 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1064 | struct bcm2835_cprman *cprman = divider->cprman; | |
1065 | const struct bcm2835_pll_divider_data *data = divider->data; | |
1066 | u32 div = cprman_read(cprman, data->a2w_reg); | |
1067 | ||
1068 | div &= (1 << A2W_PLL_DIV_BITS) - 1; | |
1069 | if (div == 0) | |
1070 | div = 256; | |
1071 | ||
1072 | return parent_rate / div; | |
1073 | } | |
1074 | ||
1075 | static void bcm2835_pll_divider_off(struct clk_hw *hw) | |
1076 | { | |
1077 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1078 | struct bcm2835_cprman *cprman = divider->cprman; | |
1079 | const struct bcm2835_pll_divider_data *data = divider->data; | |
1080 | ||
1081 | cprman_write(cprman, data->cm_reg, | |
1082 | (cprman_read(cprman, data->cm_reg) & | |
1083 | ~data->load_mask) | data->hold_mask); | |
1084 | cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE); | |
1085 | } | |
1086 | ||
1087 | static int bcm2835_pll_divider_on(struct clk_hw *hw) | |
1088 | { | |
1089 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1090 | struct bcm2835_cprman *cprman = divider->cprman; | |
1091 | const struct bcm2835_pll_divider_data *data = divider->data; | |
1092 | ||
1093 | cprman_write(cprman, data->a2w_reg, | |
1094 | cprman_read(cprman, data->a2w_reg) & | |
1095 | ~A2W_PLL_CHANNEL_DISABLE); | |
1096 | ||
1097 | cprman_write(cprman, data->cm_reg, | |
1098 | cprman_read(cprman, data->cm_reg) & ~data->hold_mask); | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, | |
1104 | unsigned long rate, | |
1105 | unsigned long parent_rate) | |
1106 | { | |
1107 | struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); | |
1108 | struct bcm2835_cprman *cprman = divider->cprman; | |
1109 | const struct bcm2835_pll_divider_data *data = divider->data; | |
1110 | u32 cm; | |
1111 | int ret; | |
1112 | ||
1113 | ret = clk_divider_ops.set_rate(hw, rate, parent_rate); | |
1114 | if (ret) | |
1115 | return ret; | |
1116 | ||
1117 | cm = cprman_read(cprman, data->cm_reg); | |
1118 | cprman_write(cprman, data->cm_reg, cm | data->load_mask); | |
1119 | cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static const struct clk_ops bcm2835_pll_divider_clk_ops = { | |
1125 | .is_prepared = bcm2835_pll_divider_is_on, | |
1126 | .prepare = bcm2835_pll_divider_on, | |
1127 | .unprepare = bcm2835_pll_divider_off, | |
1128 | .recalc_rate = bcm2835_pll_divider_get_rate, | |
1129 | .set_rate = bcm2835_pll_divider_set_rate, | |
1130 | .round_rate = bcm2835_pll_divider_round_rate, | |
1131 | }; | |
1132 | ||
1133 | /* | |
1134 | * The CM dividers do fixed-point division, so we can't use the | |
1135 | * generic integer divider code like the PLL dividers do (and we can't | |
1136 | * fake it by having some fixed shifts preceding it in the clock tree, | |
1137 | * because we'd run out of bits in a 32-bit unsigned long). | |
1138 | */ | |
1139 | struct bcm2835_clock { | |
1140 | struct clk_hw hw; | |
1141 | struct bcm2835_cprman *cprman; | |
1142 | const struct bcm2835_clock_data *data; | |
1143 | }; | |
1144 | ||
1145 | static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) | |
1146 | { | |
1147 | return container_of(hw, struct bcm2835_clock, hw); | |
1148 | } | |
1149 | ||
1150 | static int bcm2835_clock_is_on(struct clk_hw *hw) | |
1151 | { | |
1152 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1153 | struct bcm2835_cprman *cprman = clock->cprman; | |
1154 | const struct bcm2835_clock_data *data = clock->data; | |
1155 | ||
1156 | return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; | |
1157 | } | |
1158 | ||
1159 | static u32 bcm2835_clock_choose_div(struct clk_hw *hw, | |
1160 | unsigned long rate, | |
9c95b32c RP |
1161 | unsigned long parent_rate, |
1162 | bool round_up) | |
41691b88 EA |
1163 | { |
1164 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1165 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c RP |
1166 | u32 unused_frac_mask = |
1167 | GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; | |
41691b88 | 1168 | u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; |
9c95b32c | 1169 | u64 rem; |
41691b88 EA |
1170 | u32 div; |
1171 | ||
9c95b32c | 1172 | rem = do_div(temp, rate); |
41691b88 EA |
1173 | div = temp; |
1174 | ||
9c95b32c RP |
1175 | /* Round up and mask off the unused bits */ |
1176 | if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) | |
1177 | div += unused_frac_mask + 1; | |
1178 | div &= ~unused_frac_mask; | |
41691b88 EA |
1179 | |
1180 | /* Clamp to the limits. */ | |
1181 | div = max(div, unused_frac_mask + 1); | |
1182 | div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, | |
1183 | CM_DIV_FRAC_BITS - data->frac_bits)); | |
1184 | ||
1185 | return div; | |
1186 | } | |
1187 | ||
1188 | static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, | |
1189 | unsigned long parent_rate, | |
1190 | u32 div) | |
1191 | { | |
1192 | const struct bcm2835_clock_data *data = clock->data; | |
1193 | u64 temp; | |
1194 | ||
1195 | /* | |
1196 | * The divisor is a 12.12 fixed point field, but only some of | |
1197 | * the bits are populated in any given clock. | |
1198 | */ | |
1199 | div >>= CM_DIV_FRAC_BITS - data->frac_bits; | |
1200 | div &= (1 << (data->int_bits + data->frac_bits)) - 1; | |
1201 | ||
1202 | if (div == 0) | |
1203 | return 0; | |
1204 | ||
1205 | temp = (u64)parent_rate << data->frac_bits; | |
1206 | ||
1207 | do_div(temp, div); | |
1208 | ||
1209 | return temp; | |
1210 | } | |
1211 | ||
41691b88 EA |
1212 | static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, |
1213 | unsigned long parent_rate) | |
1214 | { | |
1215 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1216 | struct bcm2835_cprman *cprman = clock->cprman; | |
1217 | const struct bcm2835_clock_data *data = clock->data; | |
1218 | u32 div = cprman_read(cprman, data->div_reg); | |
1219 | ||
1220 | return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); | |
1221 | } | |
1222 | ||
1223 | static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) | |
1224 | { | |
1225 | struct bcm2835_cprman *cprman = clock->cprman; | |
1226 | const struct bcm2835_clock_data *data = clock->data; | |
1227 | ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); | |
1228 | ||
1229 | while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { | |
1230 | if (ktime_after(ktime_get(), timeout)) { | |
1231 | dev_err(cprman->dev, "%s: couldn't lock PLL\n", | |
1232 | clk_hw_get_name(&clock->hw)); | |
1233 | return; | |
1234 | } | |
1235 | cpu_relax(); | |
1236 | } | |
1237 | } | |
1238 | ||
1239 | static void bcm2835_clock_off(struct clk_hw *hw) | |
1240 | { | |
1241 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1242 | struct bcm2835_cprman *cprman = clock->cprman; | |
1243 | const struct bcm2835_clock_data *data = clock->data; | |
1244 | ||
1245 | spin_lock(&cprman->regs_lock); | |
1246 | cprman_write(cprman, data->ctl_reg, | |
1247 | cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); | |
1248 | spin_unlock(&cprman->regs_lock); | |
1249 | ||
1250 | /* BUSY will remain high until the divider completes its cycle. */ | |
1251 | bcm2835_clock_wait_busy(clock); | |
1252 | } | |
1253 | ||
1254 | static int bcm2835_clock_on(struct clk_hw *hw) | |
1255 | { | |
1256 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1257 | struct bcm2835_cprman *cprman = clock->cprman; | |
1258 | const struct bcm2835_clock_data *data = clock->data; | |
1259 | ||
1260 | spin_lock(&cprman->regs_lock); | |
1261 | cprman_write(cprman, data->ctl_reg, | |
1262 | cprman_read(cprman, data->ctl_reg) | | |
1263 | CM_ENABLE | | |
1264 | CM_GATE); | |
1265 | spin_unlock(&cprman->regs_lock); | |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | ||
1270 | static int bcm2835_clock_set_rate(struct clk_hw *hw, | |
1271 | unsigned long rate, unsigned long parent_rate) | |
1272 | { | |
1273 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1274 | struct bcm2835_cprman *cprman = clock->cprman; | |
1275 | const struct bcm2835_clock_data *data = clock->data; | |
9c95b32c | 1276 | u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); |
41691b88 EA |
1277 | |
1278 | cprman_write(cprman, data->div_reg, div); | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
6d18b8ad RP |
1283 | static int bcm2835_clock_determine_rate(struct clk_hw *hw, |
1284 | struct clk_rate_request *req) | |
1285 | { | |
1286 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1287 | struct clk_hw *parent, *best_parent = NULL; | |
1288 | unsigned long rate, best_rate = 0; | |
1289 | unsigned long prate, best_prate = 0; | |
1290 | size_t i; | |
1291 | u32 div; | |
1292 | ||
1293 | /* | |
1294 | * Select parent clock that results in the closest but lower rate | |
1295 | */ | |
1296 | for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { | |
1297 | parent = clk_hw_get_parent_by_index(hw, i); | |
1298 | if (!parent) | |
1299 | continue; | |
1300 | prate = clk_hw_get_rate(parent); | |
1301 | div = bcm2835_clock_choose_div(hw, req->rate, prate, true); | |
1302 | rate = bcm2835_clock_rate_from_divisor(clock, prate, div); | |
1303 | if (rate > best_rate && rate <= req->rate) { | |
1304 | best_parent = parent; | |
1305 | best_prate = prate; | |
1306 | best_rate = rate; | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | if (!best_parent) | |
1311 | return -EINVAL; | |
1312 | ||
1313 | req->best_parent_hw = best_parent; | |
1314 | req->best_parent_rate = best_prate; | |
1315 | ||
1316 | req->rate = best_rate; | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) | |
1322 | { | |
1323 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1324 | struct bcm2835_cprman *cprman = clock->cprman; | |
1325 | const struct bcm2835_clock_data *data = clock->data; | |
1326 | u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; | |
1327 | ||
1328 | cprman_write(cprman, data->ctl_reg, src); | |
1329 | return 0; | |
1330 | } | |
1331 | ||
1332 | static u8 bcm2835_clock_get_parent(struct clk_hw *hw) | |
1333 | { | |
1334 | struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); | |
1335 | struct bcm2835_cprman *cprman = clock->cprman; | |
1336 | const struct bcm2835_clock_data *data = clock->data; | |
1337 | u32 src = cprman_read(cprman, data->ctl_reg); | |
1338 | ||
1339 | return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; | |
1340 | } | |
1341 | ||
1342 | ||
41691b88 EA |
1343 | static const struct clk_ops bcm2835_clock_clk_ops = { |
1344 | .is_prepared = bcm2835_clock_is_on, | |
1345 | .prepare = bcm2835_clock_on, | |
1346 | .unprepare = bcm2835_clock_off, | |
1347 | .recalc_rate = bcm2835_clock_get_rate, | |
1348 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1349 | .determine_rate = bcm2835_clock_determine_rate, |
1350 | .set_parent = bcm2835_clock_set_parent, | |
1351 | .get_parent = bcm2835_clock_get_parent, | |
41691b88 EA |
1352 | }; |
1353 | ||
1354 | static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) | |
1355 | { | |
1356 | return true; | |
1357 | } | |
1358 | ||
1359 | /* | |
1360 | * The VPU clock can never be disabled (it doesn't have an ENABLE | |
1361 | * bit), so it gets its own set of clock ops. | |
1362 | */ | |
1363 | static const struct clk_ops bcm2835_vpu_clock_clk_ops = { | |
1364 | .is_prepared = bcm2835_vpu_clock_is_on, | |
1365 | .recalc_rate = bcm2835_clock_get_rate, | |
1366 | .set_rate = bcm2835_clock_set_rate, | |
6d18b8ad RP |
1367 | .determine_rate = bcm2835_clock_determine_rate, |
1368 | .set_parent = bcm2835_clock_set_parent, | |
1369 | .get_parent = bcm2835_clock_get_parent, | |
41691b88 EA |
1370 | }; |
1371 | ||
1372 | static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman, | |
1373 | const struct bcm2835_pll_data *data) | |
1374 | { | |
1375 | struct bcm2835_pll *pll; | |
1376 | struct clk_init_data init; | |
1377 | ||
1378 | memset(&init, 0, sizeof(init)); | |
1379 | ||
1380 | /* All of the PLLs derive from the external oscillator. */ | |
1381 | init.parent_names = &cprman->osc_name; | |
1382 | init.num_parents = 1; | |
1383 | init.name = data->name; | |
1384 | init.ops = &bcm2835_pll_clk_ops; | |
1385 | init.flags = CLK_IGNORE_UNUSED; | |
1386 | ||
1387 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
1388 | if (!pll) | |
1389 | return NULL; | |
1390 | ||
1391 | pll->cprman = cprman; | |
1392 | pll->data = data; | |
1393 | pll->hw.init = &init; | |
1394 | ||
1395 | return devm_clk_register(cprman->dev, &pll->hw); | |
1396 | } | |
1397 | ||
1398 | static struct clk * | |
1399 | bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, | |
1400 | const struct bcm2835_pll_divider_data *data) | |
1401 | { | |
1402 | struct bcm2835_pll_divider *divider; | |
1403 | struct clk_init_data init; | |
1404 | struct clk *clk; | |
1405 | const char *divider_name; | |
1406 | ||
1407 | if (data->fixed_divider != 1) { | |
1408 | divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, | |
1409 | "%s_prediv", data->name); | |
1410 | if (!divider_name) | |
1411 | return NULL; | |
1412 | } else { | |
1413 | divider_name = data->name; | |
1414 | } | |
1415 | ||
1416 | memset(&init, 0, sizeof(init)); | |
1417 | ||
1418 | init.parent_names = &data->source_pll->name; | |
1419 | init.num_parents = 1; | |
1420 | init.name = divider_name; | |
1421 | init.ops = &bcm2835_pll_divider_clk_ops; | |
1422 | init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; | |
1423 | ||
1424 | divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); | |
1425 | if (!divider) | |
1426 | return NULL; | |
1427 | ||
1428 | divider->div.reg = cprman->regs + data->a2w_reg; | |
1429 | divider->div.shift = A2W_PLL_DIV_SHIFT; | |
1430 | divider->div.width = A2W_PLL_DIV_BITS; | |
1431 | divider->div.flags = 0; | |
1432 | divider->div.lock = &cprman->regs_lock; | |
1433 | divider->div.hw.init = &init; | |
1434 | divider->div.table = NULL; | |
1435 | ||
1436 | divider->cprman = cprman; | |
1437 | divider->data = data; | |
1438 | ||
1439 | clk = devm_clk_register(cprman->dev, ÷r->div.hw); | |
1440 | if (IS_ERR(clk)) | |
1441 | return clk; | |
1442 | ||
1443 | /* | |
1444 | * PLLH's channels have a fixed divide by 10 afterwards, which | |
1445 | * is what our consumers are actually using. | |
1446 | */ | |
1447 | if (data->fixed_divider != 1) { | |
1448 | return clk_register_fixed_factor(cprman->dev, data->name, | |
1449 | divider_name, | |
1450 | CLK_SET_RATE_PARENT, | |
1451 | 1, | |
1452 | data->fixed_divider); | |
1453 | } | |
1454 | ||
1455 | return clk; | |
1456 | } | |
1457 | ||
1458 | static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman, | |
1459 | const struct bcm2835_clock_data *data) | |
1460 | { | |
1461 | struct bcm2835_clock *clock; | |
1462 | struct clk_init_data init; | |
6d18b8ad RP |
1463 | const char *parents[1 << CM_SRC_BITS]; |
1464 | size_t i; | |
41691b88 EA |
1465 | |
1466 | /* | |
6d18b8ad RP |
1467 | * Replace our "xosc" references with the oscillator's |
1468 | * actual name. | |
41691b88 | 1469 | */ |
6d18b8ad RP |
1470 | for (i = 0; i < data->num_mux_parents; i++) { |
1471 | if (strcmp(data->parents[i], "xosc") == 0) | |
1472 | parents[i] = cprman->osc_name; | |
1473 | else | |
1474 | parents[i] = data->parents[i]; | |
41691b88 EA |
1475 | } |
1476 | ||
1477 | memset(&init, 0, sizeof(init)); | |
6d18b8ad RP |
1478 | init.parent_names = parents; |
1479 | init.num_parents = data->num_mux_parents; | |
41691b88 EA |
1480 | init.name = data->name; |
1481 | init.flags = CLK_IGNORE_UNUSED; | |
1482 | ||
1483 | if (data->is_vpu_clock) { | |
1484 | init.ops = &bcm2835_vpu_clock_clk_ops; | |
1485 | } else { | |
1486 | init.ops = &bcm2835_clock_clk_ops; | |
1487 | init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; | |
1488 | } | |
1489 | ||
1490 | clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); | |
1491 | if (!clock) | |
1492 | return NULL; | |
1493 | ||
1494 | clock->cprman = cprman; | |
1495 | clock->data = data; | |
1496 | clock->hw.init = &init; | |
1497 | ||
1498 | return devm_clk_register(cprman->dev, &clock->hw); | |
1499 | } | |
1500 | ||
1501 | static int bcm2835_clk_probe(struct platform_device *pdev) | |
1502 | { | |
1503 | struct device *dev = &pdev->dev; | |
1504 | struct clk **clks; | |
1505 | struct bcm2835_cprman *cprman; | |
1506 | struct resource *res; | |
1507 | ||
1508 | cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL); | |
1509 | if (!cprman) | |
1510 | return -ENOMEM; | |
1511 | ||
1512 | spin_lock_init(&cprman->regs_lock); | |
1513 | cprman->dev = dev; | |
1514 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1515 | cprman->regs = devm_ioremap_resource(dev, res); | |
1516 | if (IS_ERR(cprman->regs)) | |
1517 | return PTR_ERR(cprman->regs); | |
1518 | ||
1519 | cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0); | |
1520 | if (!cprman->osc_name) | |
1521 | return -ENODEV; | |
1522 | ||
1523 | platform_set_drvdata(pdev, cprman); | |
1524 | ||
1525 | cprman->onecell.clk_num = BCM2835_CLOCK_COUNT; | |
1526 | cprman->onecell.clks = cprman->clks; | |
1527 | clks = cprman->clks; | |
1528 | ||
1529 | clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data); | |
1530 | clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data); | |
1531 | clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data); | |
1532 | clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data); | |
1533 | clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data); | |
1534 | ||
1535 | clks[BCM2835_PLLA_CORE] = | |
1536 | bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data); | |
1537 | clks[BCM2835_PLLA_PER] = | |
1538 | bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data); | |
1539 | clks[BCM2835_PLLC_CORE0] = | |
1540 | bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data); | |
1541 | clks[BCM2835_PLLC_CORE1] = | |
1542 | bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data); | |
1543 | clks[BCM2835_PLLC_CORE2] = | |
1544 | bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data); | |
1545 | clks[BCM2835_PLLC_PER] = | |
1546 | bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data); | |
1547 | clks[BCM2835_PLLD_CORE] = | |
1548 | bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data); | |
1549 | clks[BCM2835_PLLD_PER] = | |
1550 | bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data); | |
1551 | clks[BCM2835_PLLH_RCAL] = | |
1552 | bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data); | |
1553 | clks[BCM2835_PLLH_AUX] = | |
1554 | bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data); | |
1555 | clks[BCM2835_PLLH_PIX] = | |
1556 | bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data); | |
1557 | ||
1558 | clks[BCM2835_CLOCK_TIMER] = | |
1559 | bcm2835_register_clock(cprman, &bcm2835_clock_timer_data); | |
1560 | clks[BCM2835_CLOCK_OTP] = | |
1561 | bcm2835_register_clock(cprman, &bcm2835_clock_otp_data); | |
1562 | clks[BCM2835_CLOCK_TSENS] = | |
1563 | bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data); | |
1564 | clks[BCM2835_CLOCK_VPU] = | |
1565 | bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data); | |
1566 | clks[BCM2835_CLOCK_V3D] = | |
1567 | bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data); | |
1568 | clks[BCM2835_CLOCK_ISP] = | |
1569 | bcm2835_register_clock(cprman, &bcm2835_clock_isp_data); | |
1570 | clks[BCM2835_CLOCK_H264] = | |
1571 | bcm2835_register_clock(cprman, &bcm2835_clock_h264_data); | |
1572 | clks[BCM2835_CLOCK_V3D] = | |
1573 | bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data); | |
1574 | clks[BCM2835_CLOCK_SDRAM] = | |
1575 | bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data); | |
1576 | clks[BCM2835_CLOCK_UART] = | |
1577 | bcm2835_register_clock(cprman, &bcm2835_clock_uart_data); | |
1578 | clks[BCM2835_CLOCK_VEC] = | |
1579 | bcm2835_register_clock(cprman, &bcm2835_clock_vec_data); | |
1580 | clks[BCM2835_CLOCK_HSM] = | |
1581 | bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data); | |
1582 | clks[BCM2835_CLOCK_EMMC] = | |
1583 | bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data); | |
1584 | ||
1585 | /* | |
1586 | * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if | |
1587 | * you have the debug bit set in the power manager, which we | |
1588 | * don't bother exposing) are individual gates off of the | |
1589 | * non-stop vpu clock. | |
1590 | */ | |
1591 | clks[BCM2835_CLOCK_PERI_IMAGE] = | |
1592 | clk_register_gate(dev, "peri_image", "vpu", | |
1593 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, | |
1594 | cprman->regs + CM_PERIICTL, CM_GATE_BIT, | |
1595 | 0, &cprman->regs_lock); | |
1596 | ||
cfbab8fb RP |
1597 | clks[BCM2835_CLOCK_PWM] = |
1598 | bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data); | |
1599 | ||
41691b88 EA |
1600 | return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, |
1601 | &cprman->onecell); | |
1602 | } | |
1603 | ||
1604 | static const struct of_device_id bcm2835_clk_of_match[] = { | |
1605 | { .compatible = "brcm,bcm2835-cprman", }, | |
1606 | {} | |
1607 | }; | |
1608 | MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); | |
1609 | ||
1610 | static struct platform_driver bcm2835_clk_driver = { | |
1611 | .driver = { | |
1612 | .name = "bcm2835-clk", | |
1613 | .of_match_table = bcm2835_clk_of_match, | |
1614 | }, | |
1615 | .probe = bcm2835_clk_probe, | |
1616 | }; | |
1617 | ||
1618 | builtin_platform_driver(bcm2835_clk_driver); | |
1619 | ||
1620 | MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); | |
1621 | MODULE_DESCRIPTION("BCM2835 clock driver"); | |
1622 | MODULE_LICENSE("GPL v2"); |