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0e646c52 LPC |
1 | /* |
2 | * AXI clkgen driver | |
3 | * | |
4 | * Copyright 2012-2013 Analog Devices Inc. | |
5 | * Author: Lars-Peter Clausen <lars@metafoo.de> | |
6 | * | |
7 | * Licensed under the GPL-2. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
12 | #include <linux/clk-provider.h> | |
0e646c52 LPC |
13 | #include <linux/slab.h> |
14 | #include <linux/io.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/err.h> | |
18 | ||
1887c3a6 | 19 | #define AXI_CLKGEN_V2_REG_RESET 0x40 |
62d1e782 | 20 | #define AXI_CLKGEN_V2_REG_CLKSEL 0x44 |
1887c3a6 LPC |
21 | #define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70 |
22 | #define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74 | |
23 | ||
24 | #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1) | |
25 | #define AXI_CLKGEN_V2_RESET_ENABLE BIT(0) | |
26 | ||
27 | #define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29) | |
28 | #define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28) | |
29 | ||
30 | #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16) | |
31 | ||
32 | #define MMCM_REG_CLKOUT0_1 0x08 | |
33 | #define MMCM_REG_CLKOUT0_2 0x09 | |
34 | #define MMCM_REG_CLK_FB1 0x14 | |
35 | #define MMCM_REG_CLK_FB2 0x15 | |
36 | #define MMCM_REG_CLK_DIV 0x16 | |
37 | #define MMCM_REG_LOCK1 0x18 | |
38 | #define MMCM_REG_LOCK2 0x19 | |
39 | #define MMCM_REG_LOCK3 0x1a | |
40 | #define MMCM_REG_FILTER1 0x4e | |
41 | #define MMCM_REG_FILTER2 0x4f | |
42 | ||
51ee2f1d LPC |
43 | #define MMCM_CLKOUT_NOCOUNT BIT(6) |
44 | ||
45 | #define MMCM_CLK_DIV_NOCOUNT BIT(12) | |
46 | ||
0e646c52 LPC |
47 | struct axi_clkgen { |
48 | void __iomem *base; | |
49 | struct clk_hw clk_hw; | |
50 | }; | |
51 | ||
52 | static uint32_t axi_clkgen_lookup_filter(unsigned int m) | |
53 | { | |
54 | switch (m) { | |
55 | case 0: | |
56 | return 0x01001990; | |
57 | case 1: | |
58 | return 0x01001190; | |
59 | case 2: | |
60 | return 0x01009890; | |
61 | case 3: | |
62 | return 0x01001890; | |
63 | case 4: | |
64 | return 0x01008890; | |
65 | case 5 ... 8: | |
66 | return 0x01009090; | |
67 | case 9 ... 11: | |
68 | return 0x01000890; | |
69 | case 12: | |
70 | return 0x08009090; | |
71 | case 13 ... 22: | |
72 | return 0x01001090; | |
73 | case 23 ... 36: | |
74 | return 0x01008090; | |
75 | case 37 ... 46: | |
76 | return 0x08001090; | |
77 | default: | |
78 | return 0x08008090; | |
79 | } | |
80 | } | |
81 | ||
82 | static const uint32_t axi_clkgen_lock_table[] = { | |
83 | 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8, | |
84 | 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8, | |
85 | 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339, | |
86 | 0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271, | |
87 | 0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4, | |
88 | 0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190, | |
89 | 0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e, | |
90 | 0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c, | |
91 | 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113, | |
92 | }; | |
93 | ||
94 | static uint32_t axi_clkgen_lookup_lock(unsigned int m) | |
95 | { | |
96 | if (m < ARRAY_SIZE(axi_clkgen_lock_table)) | |
97 | return axi_clkgen_lock_table[m]; | |
98 | return 0x1f1f00fa; | |
99 | } | |
100 | ||
101 | static const unsigned int fpfd_min = 10000; | |
102 | static const unsigned int fpfd_max = 300000; | |
103 | static const unsigned int fvco_min = 600000; | |
104 | static const unsigned int fvco_max = 1200000; | |
105 | ||
106 | static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout, | |
107 | unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout) | |
108 | { | |
109 | unsigned long d, d_min, d_max, _d_min, _d_max; | |
110 | unsigned long m, m_min, m_max; | |
111 | unsigned long f, dout, best_f, fvco; | |
112 | ||
113 | fin /= 1000; | |
114 | fout /= 1000; | |
115 | ||
116 | best_f = ULONG_MAX; | |
117 | *best_d = 0; | |
118 | *best_m = 0; | |
119 | *best_dout = 0; | |
120 | ||
121 | d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1); | |
122 | d_max = min_t(unsigned long, fin / fpfd_min, 80); | |
123 | ||
124 | m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1); | |
125 | m_max = min_t(unsigned long, fvco_max * d_max / fin, 64); | |
126 | ||
127 | for (m = m_min; m <= m_max; m++) { | |
128 | _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max)); | |
129 | _d_max = min(d_max, fin * m / fvco_min); | |
130 | ||
131 | for (d = _d_min; d <= _d_max; d++) { | |
132 | fvco = fin * m / d; | |
133 | ||
134 | dout = DIV_ROUND_CLOSEST(fvco, fout); | |
135 | dout = clamp_t(unsigned long, dout, 1, 128); | |
136 | f = fvco / dout; | |
137 | if (abs(f - fout) < abs(best_f - fout)) { | |
138 | best_f = f; | |
139 | *best_d = d; | |
140 | *best_m = m; | |
141 | *best_dout = dout; | |
142 | if (best_f == fout) | |
143 | return; | |
144 | } | |
145 | } | |
146 | } | |
147 | } | |
148 | ||
149 | static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low, | |
150 | unsigned int *high, unsigned int *edge, unsigned int *nocount) | |
151 | { | |
152 | if (divider == 1) | |
153 | *nocount = 1; | |
154 | else | |
155 | *nocount = 0; | |
156 | ||
157 | *high = divider / 2; | |
158 | *edge = divider % 2; | |
159 | *low = divider - *high; | |
160 | } | |
161 | ||
162 | static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, | |
163 | unsigned int reg, unsigned int val) | |
164 | { | |
165 | writel(val, axi_clkgen->base + reg); | |
166 | } | |
167 | ||
168 | static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, | |
169 | unsigned int reg, unsigned int *val) | |
170 | { | |
171 | *val = readl(axi_clkgen->base + reg); | |
172 | } | |
173 | ||
1887c3a6 LPC |
174 | static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) |
175 | { | |
176 | unsigned int timeout = 10000; | |
177 | unsigned int val; | |
178 | ||
179 | do { | |
180 | axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val); | |
181 | } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout); | |
182 | ||
183 | if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) | |
184 | return -EIO; | |
185 | ||
186 | return val & 0xffff; | |
187 | } | |
188 | ||
d95b599c | 189 | static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, |
1887c3a6 LPC |
190 | unsigned int reg, unsigned int *val) |
191 | { | |
192 | unsigned int reg_val; | |
193 | int ret; | |
194 | ||
195 | ret = axi_clkgen_wait_non_busy(axi_clkgen); | |
196 | if (ret < 0) | |
197 | return ret; | |
198 | ||
199 | reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ; | |
200 | reg_val |= (reg << 16); | |
201 | ||
202 | axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); | |
203 | ||
204 | ret = axi_clkgen_wait_non_busy(axi_clkgen); | |
205 | if (ret < 0) | |
206 | return ret; | |
207 | ||
208 | *val = ret; | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
d95b599c | 213 | static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, |
1887c3a6 LPC |
214 | unsigned int reg, unsigned int val, unsigned int mask) |
215 | { | |
216 | unsigned int reg_val = 0; | |
217 | int ret; | |
218 | ||
219 | ret = axi_clkgen_wait_non_busy(axi_clkgen); | |
220 | if (ret < 0) | |
221 | return ret; | |
222 | ||
223 | if (mask != 0xffff) { | |
d95b599c | 224 | axi_clkgen_mmcm_read(axi_clkgen, reg, ®_val); |
1887c3a6 LPC |
225 | reg_val &= ~mask; |
226 | } | |
227 | ||
228 | reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask); | |
229 | ||
230 | axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
d95b599c | 235 | static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, |
1887c3a6 LPC |
236 | bool enable) |
237 | { | |
238 | unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE; | |
239 | ||
240 | if (enable) | |
241 | val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE; | |
242 | ||
243 | axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val); | |
244 | } | |
245 | ||
0e646c52 LPC |
246 | static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) |
247 | { | |
248 | return container_of(clk_hw, struct axi_clkgen, clk_hw); | |
249 | } | |
250 | ||
251 | static int axi_clkgen_set_rate(struct clk_hw *clk_hw, | |
252 | unsigned long rate, unsigned long parent_rate) | |
253 | { | |
254 | struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); | |
255 | unsigned int d, m, dout; | |
256 | unsigned int nocount; | |
257 | unsigned int high; | |
258 | unsigned int edge; | |
259 | unsigned int low; | |
260 | uint32_t filter; | |
261 | uint32_t lock; | |
262 | ||
263 | if (parent_rate == 0 || rate == 0) | |
264 | return -EINVAL; | |
265 | ||
266 | axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout); | |
267 | ||
268 | if (d == 0 || dout == 0 || m == 0) | |
269 | return -EINVAL; | |
270 | ||
271 | filter = axi_clkgen_lookup_filter(m - 1); | |
272 | lock = axi_clkgen_lookup_lock(m - 1); | |
273 | ||
0e646c52 | 274 | axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount); |
1887c3a6 LPC |
275 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_1, |
276 | (high << 6) | low, 0xefff); | |
277 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_2, | |
278 | (edge << 7) | (nocount << 6), 0x03ff); | |
0e646c52 LPC |
279 | |
280 | axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount); | |
1887c3a6 LPC |
281 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV, |
282 | (edge << 13) | (nocount << 12) | (high << 6) | low, 0x3fff); | |
0e646c52 LPC |
283 | |
284 | axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount); | |
1887c3a6 LPC |
285 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB1, |
286 | (high << 6) | low, 0xefff); | |
287 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB2, | |
288 | (edge << 7) | (nocount << 6), 0x03ff); | |
289 | ||
290 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff); | |
291 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2, | |
292 | (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); | |
293 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3, | |
294 | (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); | |
295 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900); | |
296 | axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900); | |
0e646c52 LPC |
297 | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate, | |
302 | unsigned long *parent_rate) | |
303 | { | |
304 | unsigned int d, m, dout; | |
305 | ||
306 | axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout); | |
307 | ||
308 | if (d == 0 || dout == 0 || m == 0) | |
309 | return -EINVAL; | |
310 | ||
311 | return *parent_rate / d * m / dout; | |
312 | } | |
313 | ||
314 | static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, | |
315 | unsigned long parent_rate) | |
316 | { | |
317 | struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); | |
318 | unsigned int d, m, dout; | |
319 | unsigned int reg; | |
320 | unsigned long long tmp; | |
321 | ||
51ee2f1d LPC |
322 | axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, ®); |
323 | if (reg & MMCM_CLKOUT_NOCOUNT) { | |
324 | dout = 1; | |
325 | } else { | |
326 | axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, ®); | |
327 | dout = (reg & 0x3f) + ((reg >> 6) & 0x3f); | |
328 | } | |
329 | ||
1887c3a6 | 330 | axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, ®); |
51ee2f1d LPC |
331 | if (reg & MMCM_CLK_DIV_NOCOUNT) |
332 | d = 1; | |
333 | else | |
334 | d = (reg & 0x3f) + ((reg >> 6) & 0x3f); | |
335 | ||
336 | axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, ®); | |
337 | if (reg & MMCM_CLKOUT_NOCOUNT) { | |
338 | m = 1; | |
339 | } else { | |
340 | axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, ®); | |
341 | m = (reg & 0x3f) + ((reg >> 6) & 0x3f); | |
342 | } | |
0e646c52 LPC |
343 | |
344 | if (d == 0 || dout == 0) | |
345 | return 0; | |
346 | ||
347 | tmp = (unsigned long long)(parent_rate / d) * m; | |
348 | do_div(tmp, dout); | |
349 | ||
3d6f1c72 | 350 | return min_t(unsigned long long, tmp, ULONG_MAX); |
0e646c52 LPC |
351 | } |
352 | ||
1887c3a6 LPC |
353 | static int axi_clkgen_enable(struct clk_hw *clk_hw) |
354 | { | |
355 | struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); | |
356 | ||
357 | axi_clkgen_mmcm_enable(axi_clkgen, true); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static void axi_clkgen_disable(struct clk_hw *clk_hw) | |
363 | { | |
364 | struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); | |
365 | ||
366 | axi_clkgen_mmcm_enable(axi_clkgen, false); | |
367 | } | |
368 | ||
62d1e782 LPC |
369 | static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index) |
370 | { | |
371 | struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); | |
372 | ||
373 | axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
378 | static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw) | |
379 | { | |
380 | struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); | |
381 | unsigned int parent; | |
382 | ||
383 | axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent); | |
384 | ||
385 | return parent; | |
386 | } | |
387 | ||
0e646c52 LPC |
388 | static const struct clk_ops axi_clkgen_ops = { |
389 | .recalc_rate = axi_clkgen_recalc_rate, | |
390 | .round_rate = axi_clkgen_round_rate, | |
391 | .set_rate = axi_clkgen_set_rate, | |
1887c3a6 LPC |
392 | .enable = axi_clkgen_enable, |
393 | .disable = axi_clkgen_disable, | |
62d1e782 LPC |
394 | .set_parent = axi_clkgen_set_parent, |
395 | .get_parent = axi_clkgen_get_parent, | |
0e646c52 LPC |
396 | }; |
397 | ||
1887c3a6 LPC |
398 | static const struct of_device_id axi_clkgen_ids[] = { |
399 | { | |
1887c3a6 | 400 | .compatible = "adi,axi-clkgen-2.00.a", |
1887c3a6 LPC |
401 | }, |
402 | { }, | |
403 | }; | |
404 | MODULE_DEVICE_TABLE(of, axi_clkgen_ids); | |
405 | ||
0e646c52 LPC |
406 | static int axi_clkgen_probe(struct platform_device *pdev) |
407 | { | |
1887c3a6 | 408 | const struct of_device_id *id; |
0e646c52 LPC |
409 | struct axi_clkgen *axi_clkgen; |
410 | struct clk_init_data init; | |
62d1e782 | 411 | const char *parent_names[2]; |
0e646c52 LPC |
412 | const char *clk_name; |
413 | struct resource *mem; | |
62d1e782 | 414 | unsigned int i; |
e0d30bb9 | 415 | int ret; |
0e646c52 | 416 | |
1887c3a6 LPC |
417 | if (!pdev->dev.of_node) |
418 | return -ENODEV; | |
419 | ||
420 | id = of_match_node(axi_clkgen_ids, pdev->dev.of_node); | |
421 | if (!id) | |
422 | return -ENODEV; | |
423 | ||
0e646c52 LPC |
424 | axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL); |
425 | if (!axi_clkgen) | |
426 | return -ENOMEM; | |
427 | ||
428 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
429 | axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem); | |
430 | if (IS_ERR(axi_clkgen->base)) | |
431 | return PTR_ERR(axi_clkgen->base); | |
432 | ||
62d1e782 LPC |
433 | init.num_parents = of_clk_get_parent_count(pdev->dev.of_node); |
434 | if (init.num_parents < 1 || init.num_parents > 2) | |
0e646c52 LPC |
435 | return -EINVAL; |
436 | ||
62d1e782 LPC |
437 | for (i = 0; i < init.num_parents; i++) { |
438 | parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i); | |
439 | if (!parent_names[i]) | |
440 | return -EINVAL; | |
441 | } | |
442 | ||
0e646c52 LPC |
443 | clk_name = pdev->dev.of_node->name; |
444 | of_property_read_string(pdev->dev.of_node, "clock-output-names", | |
445 | &clk_name); | |
446 | ||
447 | init.name = clk_name; | |
448 | init.ops = &axi_clkgen_ops; | |
62d1e782 LPC |
449 | init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; |
450 | init.parent_names = parent_names; | |
0e646c52 | 451 | |
1887c3a6 LPC |
452 | axi_clkgen_mmcm_enable(axi_clkgen, false); |
453 | ||
0e646c52 | 454 | axi_clkgen->clk_hw.init = &init; |
e0d30bb9 SB |
455 | ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw); |
456 | if (ret) | |
457 | return ret; | |
0e646c52 | 458 | |
e0d30bb9 SB |
459 | return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get, |
460 | &axi_clkgen->clk_hw); | |
0e646c52 LPC |
461 | } |
462 | ||
463 | static int axi_clkgen_remove(struct platform_device *pdev) | |
464 | { | |
465 | of_clk_del_provider(pdev->dev.of_node); | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
0e646c52 LPC |
470 | static struct platform_driver axi_clkgen_driver = { |
471 | .driver = { | |
472 | .name = "adi-axi-clkgen", | |
0e646c52 LPC |
473 | .of_match_table = axi_clkgen_ids, |
474 | }, | |
475 | .probe = axi_clkgen_probe, | |
476 | .remove = axi_clkgen_remove, | |
477 | }; | |
478 | module_platform_driver(axi_clkgen_driver); | |
479 | ||
480 | MODULE_LICENSE("GPL v2"); | |
481 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
482 | MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator"); |