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2e62246b MV |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (C) 2018 ROHM Semiconductors | |
3 | ||
4 | #include <linux/kernel.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/init.h> | |
7 | #include <linux/err.h> | |
8 | #include <linux/platform_device.h> | |
9 | #include <linux/slab.h> | |
ae866dec | 10 | #include <linux/mfd/rohm-generic.h> |
2e62246b MV |
11 | #include <linux/clk-provider.h> |
12 | #include <linux/clkdev.h> | |
13 | #include <linux/regmap.h> | |
14 | ||
ae866dec MV |
15 | /* clk control registers */ |
16 | /* BD70528 */ | |
17 | #define BD70528_REG_OUT32K 0x2c | |
18 | /* BD71828 */ | |
19 | #define BD71828_REG_OUT32K 0x4B | |
20 | /* BD71837 and BD71847 */ | |
21 | #define BD718XX_REG_OUT32K 0x2E | |
22 | ||
23 | /* | |
24 | * BD71837, BD71847, BD70528 and BD71828 all use bit [0] to clk output control | |
25 | */ | |
26 | #define CLK_OUT_EN_MASK BIT(0) | |
27 | ||
28 | ||
2e62246b MV |
29 | struct bd718xx_clk { |
30 | struct clk_hw hw; | |
31 | u8 reg; | |
32 | u8 mask; | |
33 | struct platform_device *pdev; | |
2a6a7aac | 34 | struct rohm_regmap_dev *mfd; |
2e62246b MV |
35 | }; |
36 | ||
ae866dec | 37 | static int bd71837_clk_set(struct bd718xx_clk *c, unsigned int status) |
2e62246b | 38 | { |
2e62246b MV |
39 | return regmap_update_bits(c->mfd->regmap, c->reg, c->mask, status); |
40 | } | |
41 | ||
42 | static void bd71837_clk_disable(struct clk_hw *hw) | |
43 | { | |
44 | int rv; | |
45 | struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw); | |
46 | ||
ae866dec | 47 | rv = bd71837_clk_set(c, 0); |
2e62246b MV |
48 | if (rv) |
49 | dev_dbg(&c->pdev->dev, "Failed to disable 32K clk (%d)\n", rv); | |
50 | } | |
51 | ||
52 | static int bd71837_clk_enable(struct clk_hw *hw) | |
53 | { | |
ae866dec MV |
54 | struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw); |
55 | ||
56 | return bd71837_clk_set(c, 0xffffffff); | |
2e62246b MV |
57 | } |
58 | ||
59 | static int bd71837_clk_is_enabled(struct clk_hw *hw) | |
60 | { | |
61 | int enabled; | |
62 | int rval; | |
63 | struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw); | |
64 | ||
65 | rval = regmap_read(c->mfd->regmap, c->reg, &enabled); | |
66 | ||
67 | if (rval) | |
68 | return rval; | |
69 | ||
70 | return enabled & c->mask; | |
71 | } | |
72 | ||
73 | static const struct clk_ops bd71837_clk_ops = { | |
74 | .prepare = &bd71837_clk_enable, | |
75 | .unprepare = &bd71837_clk_disable, | |
76 | .is_prepared = &bd71837_clk_is_enabled, | |
77 | }; | |
78 | ||
79 | static int bd71837_clk_probe(struct platform_device *pdev) | |
80 | { | |
81 | struct bd718xx_clk *c; | |
82 | int rval = -ENOMEM; | |
83 | const char *parent_clk; | |
84 | struct device *parent = pdev->dev.parent; | |
2a6a7aac | 85 | struct rohm_regmap_dev *mfd = dev_get_drvdata(parent); |
2e62246b MV |
86 | struct clk_init_data init = { |
87 | .name = "bd718xx-32k-out", | |
88 | .ops = &bd71837_clk_ops, | |
89 | }; | |
1b1c26b2 | 90 | enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data; |
2e62246b MV |
91 | |
92 | c = devm_kzalloc(&pdev->dev, sizeof(*c), GFP_KERNEL); | |
93 | if (!c) | |
94 | return -ENOMEM; | |
95 | ||
96 | init.num_parents = 1; | |
97 | parent_clk = of_clk_get_parent_name(parent->of_node, 0); | |
98 | ||
99 | init.parent_names = &parent_clk; | |
100 | if (!parent_clk) { | |
101 | dev_err(&pdev->dev, "No parent clk found\n"); | |
102 | return -EINVAL; | |
103 | } | |
1b1c26b2 | 104 | switch (chip) { |
0dae7f58 MV |
105 | case ROHM_CHIP_TYPE_BD71837: |
106 | case ROHM_CHIP_TYPE_BD71847: | |
107 | c->reg = BD718XX_REG_OUT32K; | |
ae866dec MV |
108 | c->mask = CLK_OUT_EN_MASK; |
109 | break; | |
110 | case ROHM_CHIP_TYPE_BD71828: | |
111 | c->reg = BD71828_REG_OUT32K; | |
112 | c->mask = CLK_OUT_EN_MASK; | |
0dae7f58 MV |
113 | break; |
114 | case ROHM_CHIP_TYPE_BD70528: | |
ae866dec MV |
115 | c->reg = BD70528_REG_OUT32K; |
116 | c->mask = CLK_OUT_EN_MASK; | |
0dae7f58 MV |
117 | break; |
118 | default: | |
119 | dev_err(&pdev->dev, "Unknown clk chip\n"); | |
120 | return -EINVAL; | |
121 | } | |
2e62246b MV |
122 | c->mfd = mfd; |
123 | c->pdev = pdev; | |
124 | c->hw.init = &init; | |
125 | ||
126 | of_property_read_string_index(parent->of_node, | |
127 | "clock-output-names", 0, &init.name); | |
128 | ||
129 | rval = devm_clk_hw_register(&pdev->dev, &c->hw); | |
130 | if (rval) { | |
131 | dev_err(&pdev->dev, "failed to register 32K clk"); | |
132 | return rval; | |
133 | } | |
134 | rval = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get, | |
135 | &c->hw); | |
136 | if (rval) | |
137 | dev_err(&pdev->dev, "adding clk provider failed\n"); | |
138 | ||
139 | return rval; | |
140 | } | |
141 | ||
1b1c26b2 MV |
142 | static const struct platform_device_id bd718x7_clk_id[] = { |
143 | { "bd71837-clk", ROHM_CHIP_TYPE_BD71837 }, | |
144 | { "bd71847-clk", ROHM_CHIP_TYPE_BD71847 }, | |
145 | { "bd70528-clk", ROHM_CHIP_TYPE_BD70528 }, | |
ae866dec | 146 | { "bd71828-clk", ROHM_CHIP_TYPE_BD71828 }, |
1b1c26b2 MV |
147 | { }, |
148 | }; | |
149 | MODULE_DEVICE_TABLE(platform, bd718x7_clk_id); | |
150 | ||
2e62246b MV |
151 | static struct platform_driver bd71837_clk = { |
152 | .driver = { | |
153 | .name = "bd718xx-clk", | |
154 | }, | |
155 | .probe = bd71837_clk_probe, | |
1b1c26b2 | 156 | .id_table = bd718x7_clk_id, |
2e62246b MV |
157 | }; |
158 | ||
159 | module_platform_driver(bd71837_clk); | |
160 | ||
161 | MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); | |
0dae7f58 | 162 | MODULE_DESCRIPTION("BD71837/BD71847/BD70528 chip clk driver"); |
2e62246b | 163 | MODULE_LICENSE("GPL"); |
8ad1193e | 164 | MODULE_ALIAS("platform:bd718xx-clk"); |