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1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Bitmain BM1880 SoC clock driver | |
4 | * | |
5 | * Copyright (c) 2019 Linaro Ltd. | |
6 | * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | |
7 | */ | |
8 | ||
9 | #include <linux/clk-provider.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of_address.h> | |
13 | #include <linux/of_device.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/slab.h> | |
16 | ||
17 | #include <dt-bindings/clock/bm1880-clock.h> | |
18 | ||
19 | #define BM1880_CLK_MPLL_CTL 0x00 | |
20 | #define BM1880_CLK_SPLL_CTL 0x04 | |
21 | #define BM1880_CLK_FPLL_CTL 0x08 | |
22 | #define BM1880_CLK_DDRPLL_CTL 0x0c | |
23 | ||
24 | #define BM1880_CLK_ENABLE0 0x00 | |
25 | #define BM1880_CLK_ENABLE1 0x04 | |
26 | #define BM1880_CLK_SELECT 0x20 | |
27 | #define BM1880_CLK_DIV0 0x40 | |
28 | #define BM1880_CLK_DIV1 0x44 | |
29 | #define BM1880_CLK_DIV2 0x48 | |
30 | #define BM1880_CLK_DIV3 0x4c | |
31 | #define BM1880_CLK_DIV4 0x50 | |
32 | #define BM1880_CLK_DIV5 0x54 | |
33 | #define BM1880_CLK_DIV6 0x58 | |
34 | #define BM1880_CLK_DIV7 0x5c | |
35 | #define BM1880_CLK_DIV8 0x60 | |
36 | #define BM1880_CLK_DIV9 0x64 | |
37 | #define BM1880_CLK_DIV10 0x68 | |
38 | #define BM1880_CLK_DIV11 0x6c | |
39 | #define BM1880_CLK_DIV12 0x70 | |
40 | #define BM1880_CLK_DIV13 0x74 | |
41 | #define BM1880_CLK_DIV14 0x78 | |
42 | #define BM1880_CLK_DIV15 0x7c | |
43 | #define BM1880_CLK_DIV16 0x80 | |
44 | #define BM1880_CLK_DIV17 0x84 | |
45 | #define BM1880_CLK_DIV18 0x88 | |
46 | #define BM1880_CLK_DIV19 0x8c | |
47 | #define BM1880_CLK_DIV20 0x90 | |
48 | #define BM1880_CLK_DIV21 0x94 | |
49 | #define BM1880_CLK_DIV22 0x98 | |
50 | #define BM1880_CLK_DIV23 0x9c | |
51 | #define BM1880_CLK_DIV24 0xa0 | |
52 | #define BM1880_CLK_DIV25 0xa4 | |
53 | #define BM1880_CLK_DIV26 0xa8 | |
54 | #define BM1880_CLK_DIV27 0xac | |
55 | #define BM1880_CLK_DIV28 0xb0 | |
56 | ||
57 | #define to_bm1880_pll_clk(_hw) container_of(_hw, struct bm1880_pll_hw_clock, hw) | |
58 | #define to_bm1880_div_clk(_hw) container_of(_hw, struct bm1880_div_hw_clock, hw) | |
59 | ||
60 | static DEFINE_SPINLOCK(bm1880_clk_lock); | |
61 | ||
62 | struct bm1880_clock_data { | |
63 | void __iomem *pll_base; | |
64 | void __iomem *sys_base; | |
65 | struct clk_hw_onecell_data hw_data; | |
66 | }; | |
67 | ||
68 | struct bm1880_gate_clock { | |
69 | unsigned int id; | |
70 | const char *name; | |
71 | const char *parent; | |
72 | u32 gate_reg; | |
73 | s8 gate_shift; | |
74 | unsigned long flags; | |
75 | }; | |
76 | ||
77 | struct bm1880_mux_clock { | |
78 | unsigned int id; | |
79 | const char *name; | |
80 | const char * const *parents; | |
81 | s8 num_parents; | |
82 | u32 reg; | |
83 | s8 shift; | |
84 | unsigned long flags; | |
85 | }; | |
86 | ||
87 | struct bm1880_div_clock { | |
88 | unsigned int id; | |
89 | const char *name; | |
90 | u32 reg; | |
91 | u8 shift; | |
92 | u8 width; | |
93 | u32 initval; | |
94 | const struct clk_div_table *table; | |
95 | unsigned long flags; | |
96 | }; | |
97 | ||
98 | struct bm1880_div_hw_clock { | |
99 | struct bm1880_div_clock div; | |
100 | void __iomem *base; | |
101 | spinlock_t *lock; | |
102 | struct clk_hw hw; | |
103 | struct clk_init_data init; | |
104 | }; | |
105 | ||
106 | struct bm1880_composite_clock { | |
107 | unsigned int id; | |
108 | const char *name; | |
109 | const char *parent; | |
110 | const char * const *parents; | |
111 | unsigned int num_parents; | |
112 | unsigned long flags; | |
113 | ||
114 | u32 gate_reg; | |
115 | u32 mux_reg; | |
116 | u32 div_reg; | |
117 | ||
118 | s8 gate_shift; | |
119 | s8 mux_shift; | |
120 | s8 div_shift; | |
121 | s8 div_width; | |
122 | s16 div_initval; | |
123 | const struct clk_div_table *table; | |
124 | }; | |
125 | ||
126 | struct bm1880_pll_clock { | |
127 | unsigned int id; | |
128 | const char *name; | |
129 | u32 reg; | |
130 | unsigned long flags; | |
131 | }; | |
132 | ||
133 | struct bm1880_pll_hw_clock { | |
134 | struct bm1880_pll_clock pll; | |
135 | void __iomem *base; | |
136 | struct clk_hw hw; | |
137 | struct clk_init_data init; | |
138 | }; | |
139 | ||
140 | static const struct clk_ops bm1880_pll_ops; | |
141 | static const struct clk_ops bm1880_clk_div_ops; | |
142 | ||
143 | #define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ | |
144 | _div_shift, _div_width, _div_initval, _table, \ | |
145 | _flags) { \ | |
146 | .id = _id, \ | |
147 | .parent = _parent, \ | |
148 | .name = _name, \ | |
149 | .gate_reg = _gate_reg, \ | |
150 | .gate_shift = _gate_shift, \ | |
151 | .div_reg = _div_reg, \ | |
152 | .div_shift = _div_shift, \ | |
153 | .div_width = _div_width, \ | |
154 | .div_initval = _div_initval, \ | |
155 | .table = _table, \ | |
156 | .mux_shift = -1, \ | |
157 | .flags = _flags, \ | |
158 | } | |
159 | ||
160 | #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \ | |
161 | _mux_reg, _mux_shift, _flags) { \ | |
162 | .id = _id, \ | |
163 | .parents = _parents, \ | |
164 | .num_parents = ARRAY_SIZE(_parents), \ | |
165 | .name = _name, \ | |
166 | .gate_reg = _gate_reg, \ | |
167 | .gate_shift = _gate_shift, \ | |
168 | .div_shift = -1, \ | |
169 | .mux_reg = _mux_reg, \ | |
170 | .mux_shift = _mux_shift, \ | |
171 | .flags = _flags, \ | |
172 | } | |
173 | ||
174 | #define CLK_PLL(_id, _name, _parent, _reg, _flags) { \ | |
175 | .pll.id = _id, \ | |
176 | .pll.name = _name, \ | |
177 | .pll.reg = _reg, \ | |
178 | .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, \ | |
179 | &bm1880_pll_ops, \ | |
180 | _flags), \ | |
181 | } | |
182 | ||
183 | #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \ | |
184 | _table, _flags) { \ | |
185 | .div.id = _id, \ | |
186 | .div.name = _name, \ | |
187 | .div.reg = _reg, \ | |
188 | .div.shift = _shift, \ | |
189 | .div.width = _width, \ | |
190 | .div.initval = _initval, \ | |
191 | .div.table = _table, \ | |
192 | .hw.init = CLK_HW_INIT_HW(_name, _parent, \ | |
193 | &bm1880_clk_div_ops, \ | |
194 | _flags), \ | |
195 | } | |
196 | ||
197 | static struct clk_parent_data bm1880_pll_parent[] = { | |
198 | { .fw_name = "osc", .name = "osc" }, | |
199 | }; | |
200 | ||
201 | /* | |
202 | * All PLL clocks are marked as CRITICAL, hence they are very crucial | |
203 | * for the functioning of the SoC | |
204 | */ | |
205 | static struct bm1880_pll_hw_clock bm1880_pll_clks[] = { | |
206 | CLK_PLL(BM1880_CLK_MPLL, "clk_mpll", bm1880_pll_parent, | |
207 | BM1880_CLK_MPLL_CTL, 0), | |
208 | CLK_PLL(BM1880_CLK_SPLL, "clk_spll", bm1880_pll_parent, | |
209 | BM1880_CLK_SPLL_CTL, 0), | |
210 | CLK_PLL(BM1880_CLK_FPLL, "clk_fpll", bm1880_pll_parent, | |
211 | BM1880_CLK_FPLL_CTL, 0), | |
212 | CLK_PLL(BM1880_CLK_DDRPLL, "clk_ddrpll", bm1880_pll_parent, | |
213 | BM1880_CLK_DDRPLL_CTL, 0), | |
214 | }; | |
215 | ||
216 | /* | |
217 | * Clocks marked as CRITICAL are needed for the proper functioning | |
218 | * of the SoC. | |
219 | */ | |
220 | static const struct bm1880_gate_clock bm1880_gate_clks[] = { | |
221 | { BM1880_CLK_AHB_ROM, "clk_ahb_rom", "clk_mux_axi6", | |
222 | BM1880_CLK_ENABLE0, 2, 0 }, | |
223 | { BM1880_CLK_AXI_SRAM, "clk_axi_sram", "clk_axi1", | |
224 | BM1880_CLK_ENABLE0, 3, 0 }, | |
225 | /* | |
226 | * Since this clock is sourcing the DDR memory, let's mark it as | |
227 | * critical to avoid gating. | |
228 | */ | |
229 | { BM1880_CLK_DDR_AXI, "clk_ddr_axi", "clk_mux_axi6", | |
230 | BM1880_CLK_ENABLE0, 4, CLK_IS_CRITICAL }, | |
231 | { BM1880_CLK_APB_EFUSE, "clk_apb_efuse", "clk_mux_axi6", | |
232 | BM1880_CLK_ENABLE0, 6, 0 }, | |
233 | { BM1880_CLK_AXI5_EMMC, "clk_axi5_emmc", "clk_axi5", | |
234 | BM1880_CLK_ENABLE0, 7, 0 }, | |
235 | { BM1880_CLK_AXI5_SD, "clk_axi5_sd", "clk_axi5", | |
236 | BM1880_CLK_ENABLE0, 10, 0 }, | |
237 | { BM1880_CLK_AXI4_ETH0, "clk_axi4_eth0", "clk_axi4", | |
238 | BM1880_CLK_ENABLE0, 14, 0 }, | |
239 | { BM1880_CLK_AXI4_ETH1, "clk_axi4_eth1", "clk_axi4", | |
240 | BM1880_CLK_ENABLE0, 16, 0 }, | |
241 | { BM1880_CLK_AXI1_GDMA, "clk_axi1_gdma", "clk_axi1", | |
242 | BM1880_CLK_ENABLE0, 17, 0 }, | |
243 | /* Don't gate GPIO clocks as it is not owned by the GPIO driver */ | |
244 | { BM1880_CLK_APB_GPIO, "clk_apb_gpio", "clk_mux_axi6", | |
245 | BM1880_CLK_ENABLE0, 18, CLK_IGNORE_UNUSED }, | |
246 | { BM1880_CLK_APB_GPIO_INTR, "clk_apb_gpio_intr", "clk_mux_axi6", | |
247 | BM1880_CLK_ENABLE0, 19, CLK_IGNORE_UNUSED }, | |
248 | { BM1880_CLK_AXI1_MINER, "clk_axi1_miner", "clk_axi1", | |
249 | BM1880_CLK_ENABLE0, 21, 0 }, | |
250 | { BM1880_CLK_AHB_SF, "clk_ahb_sf", "clk_mux_axi6", | |
251 | BM1880_CLK_ENABLE0, 22, 0 }, | |
252 | /* | |
253 | * Not sure which module this clock is sourcing but gating this clock | |
254 | * prevents the system from booting. So, let's mark it as critical. | |
255 | */ | |
256 | { BM1880_CLK_SDMA_AXI, "clk_sdma_axi", "clk_axi5", | |
257 | BM1880_CLK_ENABLE0, 23, CLK_IS_CRITICAL }, | |
258 | { BM1880_CLK_APB_I2C, "clk_apb_i2c", "clk_mux_axi6", | |
259 | BM1880_CLK_ENABLE0, 25, 0 }, | |
260 | { BM1880_CLK_APB_WDT, "clk_apb_wdt", "clk_mux_axi6", | |
261 | BM1880_CLK_ENABLE0, 26, 0 }, | |
262 | { BM1880_CLK_APB_JPEG, "clk_apb_jpeg", "clk_axi6", | |
263 | BM1880_CLK_ENABLE0, 27, 0 }, | |
264 | { BM1880_CLK_AXI5_NF, "clk_axi5_nf", "clk_axi5", | |
265 | BM1880_CLK_ENABLE0, 29, 0 }, | |
266 | { BM1880_CLK_APB_NF, "clk_apb_nf", "clk_axi6", | |
267 | BM1880_CLK_ENABLE0, 30, 0 }, | |
268 | { BM1880_CLK_APB_PWM, "clk_apb_pwm", "clk_mux_axi6", | |
269 | BM1880_CLK_ENABLE1, 0, 0 }, | |
270 | { BM1880_CLK_RV, "clk_rv", "clk_mux_rv", | |
271 | BM1880_CLK_ENABLE1, 1, 0 }, | |
272 | { BM1880_CLK_APB_SPI, "clk_apb_spi", "clk_mux_axi6", | |
273 | BM1880_CLK_ENABLE1, 2, 0 }, | |
274 | { BM1880_CLK_UART_500M, "clk_uart_500m", "clk_div_uart_500m", | |
275 | BM1880_CLK_ENABLE1, 4, 0 }, | |
276 | { BM1880_CLK_APB_UART, "clk_apb_uart", "clk_axi6", | |
277 | BM1880_CLK_ENABLE1, 5, 0 }, | |
278 | { BM1880_CLK_APB_I2S, "clk_apb_i2s", "clk_axi6", | |
279 | BM1880_CLK_ENABLE1, 6, 0 }, | |
280 | { BM1880_CLK_AXI4_USB, "clk_axi4_usb", "clk_axi4", | |
281 | BM1880_CLK_ENABLE1, 7, 0 }, | |
282 | { BM1880_CLK_APB_USB, "clk_apb_usb", "clk_axi6", | |
283 | BM1880_CLK_ENABLE1, 8, 0 }, | |
284 | { BM1880_CLK_12M_USB, "clk_12m_usb", "clk_div_12m_usb", | |
285 | BM1880_CLK_ENABLE1, 11, 0 }, | |
286 | { BM1880_CLK_APB_VIDEO, "clk_apb_video", "clk_axi6", | |
287 | BM1880_CLK_ENABLE1, 12, 0 }, | |
288 | { BM1880_CLK_APB_VPP, "clk_apb_vpp", "clk_axi6", | |
289 | BM1880_CLK_ENABLE1, 15, 0 }, | |
290 | { BM1880_CLK_AXI6, "clk_axi6", "clk_mux_axi6", | |
291 | BM1880_CLK_ENABLE1, 21, 0 }, | |
292 | }; | |
293 | ||
294 | static const char * const clk_a53_parents[] = { "clk_spll", "clk_mpll" }; | |
295 | static const char * const clk_rv_parents[] = { "clk_div_1_rv", "clk_div_0_rv" }; | |
296 | static const char * const clk_axi1_parents[] = { "clk_div_1_axi1", "clk_div_0_axi1" }; | |
297 | static const char * const clk_axi6_parents[] = { "clk_div_1_axi6", "clk_div_0_axi6" }; | |
298 | ||
299 | static const struct bm1880_mux_clock bm1880_mux_clks[] = { | |
300 | { BM1880_CLK_MUX_RV, "clk_mux_rv", clk_rv_parents, 2, | |
301 | BM1880_CLK_SELECT, 1, 0 }, | |
302 | { BM1880_CLK_MUX_AXI6, "clk_mux_axi6", clk_axi6_parents, 2, | |
303 | BM1880_CLK_SELECT, 3, 0 }, | |
304 | }; | |
305 | ||
306 | static const struct clk_div_table bm1880_div_table_0[] = { | |
307 | { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, | |
308 | { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, | |
309 | { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, | |
310 | { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, | |
311 | { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, | |
312 | { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, | |
313 | { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, | |
314 | { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, | |
315 | { 0, 0 } | |
316 | }; | |
317 | ||
318 | static const struct clk_div_table bm1880_div_table_1[] = { | |
319 | { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, | |
320 | { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, | |
321 | { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, | |
322 | { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, | |
323 | { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, | |
324 | { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, | |
325 | { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, | |
326 | { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, | |
327 | { 127, 128 }, { 0, 0 } | |
328 | }; | |
329 | ||
330 | static const struct clk_div_table bm1880_div_table_2[] = { | |
331 | { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, | |
332 | { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, | |
333 | { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, | |
334 | { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, | |
335 | { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, | |
336 | { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, | |
337 | { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, | |
338 | { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, | |
339 | { 127, 128 }, { 255, 256 }, { 0, 0 } | |
340 | }; | |
341 | ||
342 | static const struct clk_div_table bm1880_div_table_3[] = { | |
343 | { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, | |
344 | { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, | |
345 | { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, | |
346 | { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, | |
347 | { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, | |
348 | { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, | |
349 | { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, | |
350 | { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, | |
351 | { 127, 128 }, { 255, 256 }, { 511, 512 }, { 0, 0 } | |
352 | }; | |
353 | ||
354 | static const struct clk_div_table bm1880_div_table_4[] = { | |
355 | { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, | |
356 | { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, | |
357 | { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, | |
358 | { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, | |
359 | { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, | |
360 | { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, | |
361 | { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, | |
362 | { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, | |
363 | { 127, 128 }, { 255, 256 }, { 511, 512 }, { 65535, 65536 }, | |
364 | { 0, 0 } | |
365 | }; | |
366 | ||
367 | /* | |
368 | * Clocks marked as CRITICAL are needed for the proper functioning | |
369 | * of the SoC. | |
370 | */ | |
371 | static struct bm1880_div_hw_clock bm1880_div_clks[] = { | |
372 | CLK_DIV(BM1880_CLK_DIV_0_RV, "clk_div_0_rv", &bm1880_pll_clks[1].hw, | |
373 | BM1880_CLK_DIV12, 16, 5, 1, bm1880_div_table_0, 0), | |
374 | CLK_DIV(BM1880_CLK_DIV_1_RV, "clk_div_1_rv", &bm1880_pll_clks[2].hw, | |
375 | BM1880_CLK_DIV13, 16, 5, 1, bm1880_div_table_0, 0), | |
376 | CLK_DIV(BM1880_CLK_DIV_UART_500M, "clk_div_uart_500m", &bm1880_pll_clks[2].hw, | |
377 | BM1880_CLK_DIV15, 16, 7, 3, bm1880_div_table_1, 0), | |
378 | CLK_DIV(BM1880_CLK_DIV_0_AXI1, "clk_div_0_axi1", &bm1880_pll_clks[0].hw, | |
379 | BM1880_CLK_DIV21, 16, 5, 2, bm1880_div_table_0, | |
380 | 0), | |
381 | CLK_DIV(BM1880_CLK_DIV_1_AXI1, "clk_div_1_axi1", &bm1880_pll_clks[2].hw, | |
382 | BM1880_CLK_DIV22, 16, 5, 3, bm1880_div_table_0, | |
383 | 0), | |
384 | CLK_DIV(BM1880_CLK_DIV_0_AXI6, "clk_div_0_axi6", &bm1880_pll_clks[2].hw, | |
385 | BM1880_CLK_DIV27, 16, 5, 15, bm1880_div_table_0, | |
386 | 0), | |
387 | CLK_DIV(BM1880_CLK_DIV_1_AXI6, "clk_div_1_axi6", &bm1880_pll_clks[0].hw, | |
388 | BM1880_CLK_DIV28, 16, 5, 11, bm1880_div_table_0, | |
389 | 0), | |
390 | CLK_DIV(BM1880_CLK_DIV_12M_USB, "clk_div_12m_usb", &bm1880_pll_clks[2].hw, | |
391 | BM1880_CLK_DIV18, 16, 7, 125, bm1880_div_table_1, 0), | |
392 | }; | |
393 | ||
394 | /* | |
395 | * Clocks marked as CRITICAL are all needed for the proper functioning | |
396 | * of the SoC. | |
397 | */ | |
398 | static struct bm1880_composite_clock bm1880_composite_clks[] = { | |
399 | /* | |
400 | * Since clk_a53 and clk_50m_a53 clocks are sourcing the CPU core, | |
401 | * let's mark them as critical to avoid gating. | |
402 | */ | |
403 | GATE_MUX(BM1880_CLK_A53, "clk_a53", clk_a53_parents, | |
404 | BM1880_CLK_ENABLE0, 0, BM1880_CLK_SELECT, 0, | |
405 | CLK_IS_CRITICAL), | |
406 | GATE_DIV(BM1880_CLK_50M_A53, "clk_50m_a53", "clk_fpll", | |
407 | BM1880_CLK_ENABLE0, 1, BM1880_CLK_DIV0, 16, 5, 30, | |
408 | bm1880_div_table_0, CLK_IS_CRITICAL), | |
409 | GATE_DIV(BM1880_CLK_EFUSE, "clk_efuse", "clk_fpll", | |
410 | BM1880_CLK_ENABLE0, 5, BM1880_CLK_DIV1, 16, 7, 60, | |
411 | bm1880_div_table_1, 0), | |
412 | GATE_DIV(BM1880_CLK_EMMC, "clk_emmc", "clk_fpll", | |
413 | BM1880_CLK_ENABLE0, 8, BM1880_CLK_DIV2, 16, 5, 15, | |
414 | bm1880_div_table_0, 0), | |
415 | GATE_DIV(BM1880_CLK_100K_EMMC, "clk_100k_emmc", "clk_div_12m_usb", | |
416 | BM1880_CLK_ENABLE0, 9, BM1880_CLK_DIV3, 16, 8, 120, | |
417 | bm1880_div_table_2, 0), | |
418 | GATE_DIV(BM1880_CLK_SD, "clk_sd", "clk_fpll", | |
419 | BM1880_CLK_ENABLE0, 11, BM1880_CLK_DIV4, 16, 5, 15, | |
420 | bm1880_div_table_0, 0), | |
421 | GATE_DIV(BM1880_CLK_100K_SD, "clk_100k_sd", "clk_div_12m_usb", | |
422 | BM1880_CLK_ENABLE0, 12, BM1880_CLK_DIV5, 16, 8, 120, | |
423 | bm1880_div_table_2, 0), | |
424 | GATE_DIV(BM1880_CLK_500M_ETH0, "clk_500m_eth0", "clk_fpll", | |
425 | BM1880_CLK_ENABLE0, 13, BM1880_CLK_DIV6, 16, 5, 3, | |
426 | bm1880_div_table_0, 0), | |
427 | GATE_DIV(BM1880_CLK_500M_ETH1, "clk_500m_eth1", "clk_fpll", | |
428 | BM1880_CLK_ENABLE0, 15, BM1880_CLK_DIV7, 16, 5, 3, | |
429 | bm1880_div_table_0, 0), | |
430 | /* Don't gate GPIO clocks as it is not owned by the GPIO driver */ | |
431 | GATE_DIV(BM1880_CLK_GPIO_DB, "clk_gpio_db", "clk_div_12m_usb", | |
432 | BM1880_CLK_ENABLE0, 20, BM1880_CLK_DIV8, 16, 16, 120, | |
433 | bm1880_div_table_4, CLK_IGNORE_UNUSED), | |
434 | GATE_DIV(BM1880_CLK_SDMA_AUD, "clk_sdma_aud", "clk_fpll", | |
435 | BM1880_CLK_ENABLE0, 24, BM1880_CLK_DIV9, 16, 7, 61, | |
436 | bm1880_div_table_1, 0), | |
437 | GATE_DIV(BM1880_CLK_JPEG_AXI, "clk_jpeg_axi", "clk_fpll", | |
438 | BM1880_CLK_ENABLE0, 28, BM1880_CLK_DIV10, 16, 5, 4, | |
439 | bm1880_div_table_0, 0), | |
440 | GATE_DIV(BM1880_CLK_NF, "clk_nf", "clk_fpll", | |
441 | BM1880_CLK_ENABLE0, 31, BM1880_CLK_DIV11, 16, 5, 30, | |
442 | bm1880_div_table_0, 0), | |
443 | GATE_DIV(BM1880_CLK_TPU_AXI, "clk_tpu_axi", "clk_spll", | |
444 | BM1880_CLK_ENABLE1, 3, BM1880_CLK_DIV14, 16, 5, 1, | |
445 | bm1880_div_table_0, 0), | |
446 | GATE_DIV(BM1880_CLK_125M_USB, "clk_125m_usb", "clk_fpll", | |
447 | BM1880_CLK_ENABLE1, 9, BM1880_CLK_DIV16, 16, 5, 12, | |
448 | bm1880_div_table_0, 0), | |
449 | GATE_DIV(BM1880_CLK_33K_USB, "clk_33k_usb", "clk_div_12m_usb", | |
450 | BM1880_CLK_ENABLE1, 10, BM1880_CLK_DIV17, 16, 9, 363, | |
451 | bm1880_div_table_3, 0), | |
452 | GATE_DIV(BM1880_CLK_VIDEO_AXI, "clk_video_axi", "clk_fpll", | |
453 | BM1880_CLK_ENABLE1, 13, BM1880_CLK_DIV19, 16, 5, 4, | |
454 | bm1880_div_table_0, 0), | |
455 | GATE_DIV(BM1880_CLK_VPP_AXI, "clk_vpp_axi", "clk_fpll", | |
456 | BM1880_CLK_ENABLE1, 14, BM1880_CLK_DIV20, 16, 5, 4, | |
457 | bm1880_div_table_0, 0), | |
458 | GATE_MUX(BM1880_CLK_AXI1, "clk_axi1", clk_axi1_parents, | |
459 | BM1880_CLK_ENABLE1, 15, BM1880_CLK_SELECT, 2, 0), | |
460 | GATE_DIV(BM1880_CLK_AXI2, "clk_axi2", "clk_fpll", | |
461 | BM1880_CLK_ENABLE1, 17, BM1880_CLK_DIV23, 16, 5, 3, | |
462 | bm1880_div_table_0, 0), | |
463 | GATE_DIV(BM1880_CLK_AXI3, "clk_axi3", "clk_mux_rv", | |
464 | BM1880_CLK_ENABLE1, 18, BM1880_CLK_DIV24, 16, 5, 2, | |
465 | bm1880_div_table_0, 0), | |
466 | GATE_DIV(BM1880_CLK_AXI4, "clk_axi4", "clk_fpll", | |
467 | BM1880_CLK_ENABLE1, 19, BM1880_CLK_DIV25, 16, 5, 6, | |
468 | bm1880_div_table_0, 0), | |
469 | GATE_DIV(BM1880_CLK_AXI5, "clk_axi5", "clk_fpll", | |
470 | BM1880_CLK_ENABLE1, 20, BM1880_CLK_DIV26, 16, 5, 15, | |
471 | bm1880_div_table_0, 0), | |
472 | }; | |
473 | ||
474 | static unsigned long bm1880_pll_rate_calc(u32 regval, unsigned long parent_rate) | |
475 | { | |
476 | u64 numerator; | |
59ef4da4 | 477 | u32 fbdiv, refdiv; |
1ab4601d MS |
478 | u32 postdiv1, postdiv2, denominator; |
479 | ||
480 | fbdiv = (regval >> 16) & 0xfff; | |
1ab4601d MS |
481 | refdiv = regval & 0x1f; |
482 | postdiv1 = (regval >> 8) & 0x7; | |
483 | postdiv2 = (regval >> 12) & 0x7; | |
484 | ||
485 | numerator = parent_rate * fbdiv; | |
486 | denominator = refdiv * postdiv1 * postdiv2; | |
487 | do_div(numerator, denominator); | |
488 | ||
489 | return (unsigned long)numerator; | |
490 | } | |
491 | ||
492 | static unsigned long bm1880_pll_recalc_rate(struct clk_hw *hw, | |
493 | unsigned long parent_rate) | |
494 | { | |
495 | struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw); | |
496 | unsigned long rate; | |
497 | u32 regval; | |
498 | ||
499 | regval = readl(pll_hw->base + pll_hw->pll.reg); | |
500 | rate = bm1880_pll_rate_calc(regval, parent_rate); | |
501 | ||
502 | return rate; | |
503 | } | |
504 | ||
505 | static const struct clk_ops bm1880_pll_ops = { | |
506 | .recalc_rate = bm1880_pll_recalc_rate, | |
507 | }; | |
508 | ||
509 | static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_clk, | |
510 | void __iomem *sys_base) | |
511 | { | |
512 | struct clk_hw *hw; | |
513 | int err; | |
514 | ||
515 | pll_clk->base = sys_base; | |
516 | hw = &pll_clk->hw; | |
517 | ||
518 | err = clk_hw_register(NULL, hw); | |
519 | if (err) | |
520 | return ERR_PTR(err); | |
521 | ||
522 | return hw; | |
523 | } | |
524 | ||
525 | static void bm1880_clk_unregister_pll(struct clk_hw *hw) | |
526 | { | |
527 | struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw); | |
528 | ||
529 | clk_hw_unregister(hw); | |
530 | kfree(pll_hw); | |
531 | } | |
532 | ||
533 | static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks, | |
534 | int num_clks, | |
535 | struct bm1880_clock_data *data) | |
536 | { | |
537 | struct clk_hw *hw; | |
538 | void __iomem *pll_base = data->pll_base; | |
539 | int i; | |
540 | ||
541 | for (i = 0; i < num_clks; i++) { | |
542 | struct bm1880_pll_hw_clock *bm1880_clk = &clks[i]; | |
543 | ||
544 | hw = bm1880_clk_register_pll(bm1880_clk, pll_base); | |
545 | if (IS_ERR(hw)) { | |
546 | pr_err("%s: failed to register clock %s\n", | |
547 | __func__, bm1880_clk->pll.name); | |
548 | goto err_clk; | |
549 | } | |
550 | ||
551 | data->hw_data.hws[clks[i].pll.id] = hw; | |
552 | } | |
553 | ||
554 | return 0; | |
555 | ||
556 | err_clk: | |
557 | while (i--) | |
558 | bm1880_clk_unregister_pll(data->hw_data.hws[clks[i].pll.id]); | |
559 | ||
560 | return PTR_ERR(hw); | |
561 | } | |
562 | ||
563 | static int bm1880_clk_register_mux(const struct bm1880_mux_clock *clks, | |
564 | int num_clks, | |
565 | struct bm1880_clock_data *data) | |
566 | { | |
567 | struct clk_hw *hw; | |
568 | void __iomem *sys_base = data->sys_base; | |
569 | int i; | |
570 | ||
571 | for (i = 0; i < num_clks; i++) { | |
572 | hw = clk_hw_register_mux(NULL, clks[i].name, | |
573 | clks[i].parents, | |
574 | clks[i].num_parents, | |
575 | clks[i].flags, | |
576 | sys_base + clks[i].reg, | |
577 | clks[i].shift, 1, 0, | |
578 | &bm1880_clk_lock); | |
579 | if (IS_ERR(hw)) { | |
580 | pr_err("%s: failed to register clock %s\n", | |
581 | __func__, clks[i].name); | |
582 | goto err_clk; | |
583 | } | |
584 | ||
585 | data->hw_data.hws[clks[i].id] = hw; | |
586 | } | |
587 | ||
588 | return 0; | |
589 | ||
590 | err_clk: | |
591 | while (i--) | |
592 | clk_hw_unregister_mux(data->hw_data.hws[clks[i].id]); | |
593 | ||
594 | return PTR_ERR(hw); | |
595 | } | |
596 | ||
597 | static unsigned long bm1880_clk_div_recalc_rate(struct clk_hw *hw, | |
598 | unsigned long parent_rate) | |
599 | { | |
600 | struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); | |
601 | struct bm1880_div_clock *div = &div_hw->div; | |
602 | void __iomem *reg_addr = div_hw->base + div->reg; | |
603 | unsigned int val; | |
604 | unsigned long rate; | |
605 | ||
606 | if (!(readl(reg_addr) & BIT(3))) { | |
607 | val = div->initval; | |
608 | } else { | |
609 | val = readl(reg_addr) >> div->shift; | |
610 | val &= clk_div_mask(div->width); | |
611 | } | |
612 | ||
613 | rate = divider_recalc_rate(hw, parent_rate, val, div->table, | |
614 | div->flags, div->width); | |
615 | ||
616 | return rate; | |
617 | } | |
618 | ||
619 | static long bm1880_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, | |
620 | unsigned long *prate) | |
621 | { | |
622 | struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); | |
623 | struct bm1880_div_clock *div = &div_hw->div; | |
624 | void __iomem *reg_addr = div_hw->base + div->reg; | |
625 | ||
626 | if (div->flags & CLK_DIVIDER_READ_ONLY) { | |
627 | u32 val; | |
628 | ||
629 | val = readl(reg_addr) >> div->shift; | |
630 | val &= clk_div_mask(div->width); | |
631 | ||
632 | return divider_ro_round_rate(hw, rate, prate, div->table, | |
633 | div->width, div->flags, | |
634 | val); | |
635 | } | |
636 | ||
637 | return divider_round_rate(hw, rate, prate, div->table, | |
638 | div->width, div->flags); | |
639 | } | |
640 | ||
641 | static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, | |
642 | unsigned long parent_rate) | |
643 | { | |
644 | struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); | |
645 | struct bm1880_div_clock *div = &div_hw->div; | |
646 | void __iomem *reg_addr = div_hw->base + div->reg; | |
647 | unsigned long flags = 0; | |
648 | int value; | |
649 | u32 val; | |
650 | ||
651 | value = divider_get_val(rate, parent_rate, div->table, | |
652 | div->width, div_hw->div.flags); | |
653 | if (value < 0) | |
654 | return value; | |
655 | ||
656 | if (div_hw->lock) | |
657 | spin_lock_irqsave(div_hw->lock, flags); | |
658 | else | |
659 | __acquire(div_hw->lock); | |
660 | ||
661 | val = readl(reg_addr); | |
662 | val &= ~(clk_div_mask(div->width) << div_hw->div.shift); | |
663 | val |= (u32)value << div->shift; | |
664 | writel(val, reg_addr); | |
665 | ||
666 | if (div_hw->lock) | |
667 | spin_unlock_irqrestore(div_hw->lock, flags); | |
668 | else | |
669 | __release(div_hw->lock); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | static const struct clk_ops bm1880_clk_div_ops = { | |
675 | .recalc_rate = bm1880_clk_div_recalc_rate, | |
676 | .round_rate = bm1880_clk_div_round_rate, | |
677 | .set_rate = bm1880_clk_div_set_rate, | |
678 | }; | |
679 | ||
680 | static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_clk, | |
681 | void __iomem *sys_base) | |
682 | { | |
683 | struct clk_hw *hw; | |
684 | int err; | |
685 | ||
686 | div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; | |
687 | div_clk->base = sys_base; | |
688 | div_clk->lock = &bm1880_clk_lock; | |
689 | ||
690 | hw = &div_clk->hw; | |
691 | err = clk_hw_register(NULL, hw); | |
692 | if (err) | |
693 | return ERR_PTR(err); | |
694 | ||
695 | return hw; | |
696 | } | |
697 | ||
698 | static void bm1880_clk_unregister_div(struct clk_hw *hw) | |
699 | { | |
700 | struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); | |
701 | ||
702 | clk_hw_unregister(hw); | |
703 | kfree(div_hw); | |
704 | } | |
705 | ||
706 | static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks, | |
707 | int num_clks, | |
708 | struct bm1880_clock_data *data) | |
709 | { | |
710 | struct clk_hw *hw; | |
711 | void __iomem *sys_base = data->sys_base; | |
712 | unsigned int i, id; | |
713 | ||
714 | for (i = 0; i < num_clks; i++) { | |
715 | struct bm1880_div_hw_clock *bm1880_clk = &clks[i]; | |
716 | ||
717 | hw = bm1880_clk_register_div(bm1880_clk, sys_base); | |
718 | if (IS_ERR(hw)) { | |
719 | pr_err("%s: failed to register clock %s\n", | |
720 | __func__, bm1880_clk->div.name); | |
721 | goto err_clk; | |
722 | } | |
723 | ||
724 | id = clks[i].div.id; | |
725 | data->hw_data.hws[id] = hw; | |
726 | } | |
727 | ||
728 | return 0; | |
729 | ||
730 | err_clk: | |
731 | while (i--) | |
732 | bm1880_clk_unregister_div(data->hw_data.hws[clks[i].div.id]); | |
733 | ||
734 | return PTR_ERR(hw); | |
735 | } | |
736 | ||
737 | static int bm1880_clk_register_gate(const struct bm1880_gate_clock *clks, | |
738 | int num_clks, | |
739 | struct bm1880_clock_data *data) | |
740 | { | |
741 | struct clk_hw *hw; | |
742 | void __iomem *sys_base = data->sys_base; | |
743 | int i; | |
744 | ||
745 | for (i = 0; i < num_clks; i++) { | |
746 | hw = clk_hw_register_gate(NULL, clks[i].name, | |
747 | clks[i].parent, | |
748 | clks[i].flags, | |
749 | sys_base + clks[i].gate_reg, | |
750 | clks[i].gate_shift, 0, | |
751 | &bm1880_clk_lock); | |
752 | if (IS_ERR(hw)) { | |
753 | pr_err("%s: failed to register clock %s\n", | |
754 | __func__, clks[i].name); | |
755 | goto err_clk; | |
756 | } | |
757 | ||
758 | data->hw_data.hws[clks[i].id] = hw; | |
759 | } | |
760 | ||
761 | return 0; | |
762 | ||
763 | err_clk: | |
764 | while (i--) | |
765 | clk_hw_unregister_gate(data->hw_data.hws[clks[i].id]); | |
766 | ||
767 | return PTR_ERR(hw); | |
768 | } | |
769 | ||
770 | static struct clk_hw *bm1880_clk_register_composite(struct bm1880_composite_clock *clks, | |
771 | void __iomem *sys_base) | |
772 | { | |
773 | struct clk_hw *hw; | |
774 | struct clk_mux *mux = NULL; | |
775 | struct clk_gate *gate = NULL; | |
776 | struct bm1880_div_hw_clock *div_hws = NULL; | |
777 | struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL; | |
778 | const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL; | |
779 | const char * const *parent_names; | |
780 | const char *parent; | |
781 | int num_parents; | |
782 | int ret; | |
783 | ||
784 | if (clks->mux_shift >= 0) { | |
785 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
786 | if (!mux) | |
787 | return ERR_PTR(-ENOMEM); | |
788 | ||
789 | mux->reg = sys_base + clks->mux_reg; | |
790 | mux->mask = 1; | |
791 | mux->shift = clks->mux_shift; | |
792 | mux_hw = &mux->hw; | |
793 | mux_ops = &clk_mux_ops; | |
794 | mux->lock = &bm1880_clk_lock; | |
795 | ||
796 | parent_names = clks->parents; | |
797 | num_parents = clks->num_parents; | |
798 | } else { | |
799 | parent = clks->parent; | |
800 | parent_names = &parent; | |
801 | num_parents = 1; | |
802 | } | |
803 | ||
804 | if (clks->gate_shift >= 0) { | |
805 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
806 | if (!gate) { | |
807 | ret = -ENOMEM; | |
808 | goto err_out; | |
809 | } | |
810 | ||
811 | gate->reg = sys_base + clks->gate_reg; | |
812 | gate->bit_idx = clks->gate_shift; | |
813 | gate->lock = &bm1880_clk_lock; | |
814 | ||
815 | gate_hw = &gate->hw; | |
816 | gate_ops = &clk_gate_ops; | |
817 | } | |
818 | ||
819 | if (clks->div_shift >= 0) { | |
820 | div_hws = kzalloc(sizeof(*div_hws), GFP_KERNEL); | |
821 | if (!div_hws) { | |
822 | ret = -ENOMEM; | |
823 | goto err_out; | |
824 | } | |
825 | ||
826 | div_hws->base = sys_base; | |
827 | div_hws->div.reg = clks->div_reg; | |
828 | div_hws->div.shift = clks->div_shift; | |
829 | div_hws->div.width = clks->div_width; | |
830 | div_hws->div.table = clks->table; | |
831 | div_hws->div.initval = clks->div_initval; | |
832 | div_hws->lock = &bm1880_clk_lock; | |
833 | div_hws->div.flags = CLK_DIVIDER_ONE_BASED | | |
834 | CLK_DIVIDER_ALLOW_ZERO; | |
835 | ||
836 | div_hw = &div_hws->hw; | |
837 | div_ops = &bm1880_clk_div_ops; | |
838 | } | |
839 | ||
840 | hw = clk_hw_register_composite(NULL, clks->name, parent_names, | |
841 | num_parents, mux_hw, mux_ops, div_hw, | |
842 | div_ops, gate_hw, gate_ops, | |
843 | clks->flags); | |
844 | ||
845 | if (IS_ERR(hw)) { | |
846 | ret = PTR_ERR(hw); | |
847 | goto err_out; | |
848 | } | |
849 | ||
850 | return hw; | |
851 | ||
852 | err_out: | |
853 | kfree(div_hws); | |
854 | kfree(gate); | |
855 | kfree(mux); | |
856 | ||
857 | return ERR_PTR(ret); | |
858 | } | |
859 | ||
860 | static int bm1880_clk_register_composites(struct bm1880_composite_clock *clks, | |
861 | int num_clks, | |
862 | struct bm1880_clock_data *data) | |
863 | { | |
864 | struct clk_hw *hw; | |
865 | void __iomem *sys_base = data->sys_base; | |
866 | int i; | |
867 | ||
868 | for (i = 0; i < num_clks; i++) { | |
869 | struct bm1880_composite_clock *bm1880_clk = &clks[i]; | |
870 | ||
871 | hw = bm1880_clk_register_composite(bm1880_clk, sys_base); | |
872 | if (IS_ERR(hw)) { | |
873 | pr_err("%s: failed to register clock %s\n", | |
874 | __func__, bm1880_clk->name); | |
875 | goto err_clk; | |
876 | } | |
877 | ||
878 | data->hw_data.hws[clks[i].id] = hw; | |
879 | } | |
880 | ||
881 | return 0; | |
882 | ||
883 | err_clk: | |
884 | while (i--) | |
885 | clk_hw_unregister_composite(data->hw_data.hws[clks[i].id]); | |
886 | ||
887 | return PTR_ERR(hw); | |
888 | } | |
889 | ||
890 | static int bm1880_clk_probe(struct platform_device *pdev) | |
891 | { | |
892 | struct bm1880_clock_data *clk_data; | |
893 | void __iomem *pll_base, *sys_base; | |
894 | struct device *dev = &pdev->dev; | |
895 | struct resource *res; | |
896 | int num_clks, i; | |
897 | ||
898 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
899 | pll_base = devm_ioremap_resource(&pdev->dev, res); | |
900 | if (IS_ERR(pll_base)) | |
901 | return PTR_ERR(pll_base); | |
902 | ||
903 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
904 | sys_base = devm_ioremap_resource(&pdev->dev, res); | |
905 | if (IS_ERR(sys_base)) | |
906 | return PTR_ERR(sys_base); | |
907 | ||
908 | num_clks = ARRAY_SIZE(bm1880_pll_clks) + | |
909 | ARRAY_SIZE(bm1880_div_clks) + | |
910 | ARRAY_SIZE(bm1880_mux_clks) + | |
911 | ARRAY_SIZE(bm1880_composite_clks) + | |
912 | ARRAY_SIZE(bm1880_gate_clks); | |
913 | ||
914 | clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, | |
915 | num_clks), GFP_KERNEL); | |
916 | if (!clk_data) | |
917 | return -ENOMEM; | |
918 | ||
919 | clk_data->pll_base = pll_base; | |
920 | clk_data->sys_base = sys_base; | |
921 | ||
922 | for (i = 0; i < num_clks; i++) | |
923 | clk_data->hw_data.hws[i] = ERR_PTR(-ENOENT); | |
924 | ||
925 | clk_data->hw_data.num = num_clks; | |
926 | ||
927 | bm1880_clk_register_plls(bm1880_pll_clks, | |
928 | ARRAY_SIZE(bm1880_pll_clks), | |
929 | clk_data); | |
930 | ||
931 | bm1880_clk_register_divs(bm1880_div_clks, | |
932 | ARRAY_SIZE(bm1880_div_clks), | |
933 | clk_data); | |
934 | ||
935 | bm1880_clk_register_mux(bm1880_mux_clks, | |
936 | ARRAY_SIZE(bm1880_mux_clks), | |
937 | clk_data); | |
938 | ||
939 | bm1880_clk_register_composites(bm1880_composite_clks, | |
940 | ARRAY_SIZE(bm1880_composite_clks), | |
941 | clk_data); | |
942 | ||
943 | bm1880_clk_register_gate(bm1880_gate_clks, | |
944 | ARRAY_SIZE(bm1880_gate_clks), | |
945 | clk_data); | |
946 | ||
947 | return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, | |
948 | &clk_data->hw_data); | |
949 | } | |
950 | ||
951 | static const struct of_device_id bm1880_of_match[] = { | |
952 | { .compatible = "bitmain,bm1880-clk", }, | |
953 | {} | |
954 | }; | |
955 | MODULE_DEVICE_TABLE(of, bm1880_of_match); | |
956 | ||
957 | static struct platform_driver bm1880_clk_driver = { | |
958 | .driver = { | |
959 | .name = "bm1880-clk", | |
960 | .of_match_table = bm1880_of_match, | |
961 | }, | |
962 | .probe = bm1880_clk_probe, | |
963 | }; | |
964 | module_platform_driver(bm1880_clk_driver); | |
965 | ||
966 | MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); | |
967 | MODULE_DESCRIPTION("Clock driver for Bitmain BM1880 SoC"); | |
968 | MODULE_LICENSE("GPL v2"); |