[mirror_ubuntu-jammy-kernel.git] / drivers / clk / clk-composite.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/slab.h>

static u8 clk_composite_get_parent(struct clk_hw *hw)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *mux_ops = composite->mux_ops;
	struct clk_hw *mux_hw = composite->mux_hw;

	__clk_hw_set_clk(mux_hw, hw);

	return mux_ops->get_parent(mux_hw);
}

static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *mux_ops = composite->mux_ops;
	struct clk_hw *mux_hw = composite->mux_hw;

	__clk_hw_set_clk(mux_hw, hw);

	return mux_ops->set_parent(mux_hw, index);
}

static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
					    unsigned long parent_rate)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	struct clk_hw *rate_hw = composite->rate_hw;

	__clk_hw_set_clk(rate_hw, hw);

	return rate_ops->recalc_rate(rate_hw, parent_rate);
}

static int clk_composite_determine_rate(struct clk_hw *hw,
					struct clk_rate_request *req)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	const struct clk_ops *mux_ops = composite->mux_ops;
	struct clk_hw *rate_hw = composite->rate_hw;
	struct clk_hw *mux_hw = composite->mux_hw;
	struct clk_hw *parent;
	unsigned long parent_rate;
	long tmp_rate, best_rate = 0;
	unsigned long rate_diff;
	unsigned long best_rate_diff = ULONG_MAX;
	long rate;
	int i;

	if (rate_hw && rate_ops && rate_ops->determine_rate) {
		__clk_hw_set_clk(rate_hw, hw);
		return rate_ops->determine_rate(rate_hw, req);
	} else if (rate_hw && rate_ops && rate_ops->round_rate &&
		   mux_hw && mux_ops && mux_ops->set_parent) {
		req->best_parent_hw = NULL;

		if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
			parent = clk_hw_get_parent(mux_hw);
			req->best_parent_hw = parent;
			req->best_parent_rate = clk_hw_get_rate(parent);

			rate = rate_ops->round_rate(rate_hw, req->rate,
						    &req->best_parent_rate);
			if (rate < 0)
				return rate;

			req->rate = rate;
			return 0;
		}

		for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
			parent = clk_hw_get_parent_by_index(mux_hw, i);
			if (!parent)
				continue;

			parent_rate = clk_hw_get_rate(parent);

			tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
							&parent_rate);
			if (tmp_rate < 0)
				continue;

			rate_diff = abs(req->rate - tmp_rate);

			if (!rate_diff || !req->best_parent_hw
				       || best_rate_diff > rate_diff) {
				req->best_parent_hw = parent;
				req->best_parent_rate = parent_rate;
				best_rate_diff = rate_diff;
				best_rate = tmp_rate;
			}

			if (!rate_diff)
				return 0;
		}

		req->rate = best_rate;
		return 0;
	} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
		__clk_hw_set_clk(mux_hw, hw);
		return mux_ops->determine_rate(mux_hw, req);
	} else {
		pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
		return -EINVAL;
	}
}

static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
				  unsigned long *prate)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	struct clk_hw *rate_hw = composite->rate_hw;

	__clk_hw_set_clk(rate_hw, hw);

	return rate_ops->round_rate(rate_hw, rate, prate);
}

static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
			       unsigned long parent_rate)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	struct clk_hw *rate_hw = composite->rate_hw;

	__clk_hw_set_clk(rate_hw, hw);

	return rate_ops->set_rate(rate_hw, rate, parent_rate);
}

static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
					     unsigned long rate,
					     unsigned long parent_rate,
					     u8 index)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *rate_ops = composite->rate_ops;
	const struct clk_ops *mux_ops = composite->mux_ops;
	struct clk_hw *rate_hw = composite->rate_hw;
	struct clk_hw *mux_hw = composite->mux_hw;
	unsigned long temp_rate;

	__clk_hw_set_clk(rate_hw, hw);
	__clk_hw_set_clk(mux_hw, hw);

	temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
	if (temp_rate > rate) {
		rate_ops->set_rate(rate_hw, rate, parent_rate);
		mux_ops->set_parent(mux_hw, index);
	} else {
		mux_ops->set_parent(mux_hw, index);
		rate_ops->set_rate(rate_hw, rate, parent_rate);
	}

	return 0;
}

static int clk_composite_is_enabled(struct clk_hw *hw)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *gate_ops = composite->gate_ops;
	struct clk_hw *gate_hw = composite->gate_hw;

	__clk_hw_set_clk(gate_hw, hw);

	return gate_ops->is_enabled(gate_hw);
}

static int clk_composite_enable(struct clk_hw *hw)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *gate_ops = composite->gate_ops;
	struct clk_hw *gate_hw = composite->gate_hw;

	__clk_hw_set_clk(gate_hw, hw);

	return gate_ops->enable(gate_hw);
}

static void clk_composite_disable(struct clk_hw *hw)
{
	struct clk_composite *composite = to_clk_composite(hw);
	const struct clk_ops *gate_ops = composite->gate_ops;
	struct clk_hw *gate_hw = composite->gate_hw;

	__clk_hw_set_clk(gate_hw, hw);

	gate_ops->disable(gate_hw);
}

static struct clk_hw *__clk_hw_register_composite(struct device *dev,
			const char *name, const char * const *parent_names,
			const struct clk_parent_data *pdata, int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	struct clk_hw *hw;
	struct clk_init_data init = {};
	struct clk_composite *composite;
	struct clk_ops *clk_composite_ops;
	int ret;

	composite = kzalloc(sizeof(*composite), GFP_KERNEL);
	if (!composite)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.flags = flags;
	if (parent_names)
		init.parent_names = parent_names;
	else
		init.parent_data = pdata;
	init.num_parents = num_parents;
	hw = &composite->hw;

	clk_composite_ops = &composite->ops;

	if (mux_hw && mux_ops) {
		if (!mux_ops->get_parent) {
			hw = ERR_PTR(-EINVAL);
			goto err;
		}

		composite->mux_hw = mux_hw;
		composite->mux_ops = mux_ops;
		clk_composite_ops->get_parent = clk_composite_get_parent;
		if (mux_ops->set_parent)
			clk_composite_ops->set_parent = clk_composite_set_parent;
		if (mux_ops->determine_rate)
			clk_composite_ops->determine_rate = clk_composite_determine_rate;
	}

	if (rate_hw && rate_ops) {
		if (!rate_ops->recalc_rate) {
			hw = ERR_PTR(-EINVAL);
			goto err;
		}
		clk_composite_ops->recalc_rate = clk_composite_recalc_rate;

		if (rate_ops->determine_rate)
			clk_composite_ops->determine_rate =
				clk_composite_determine_rate;
		else if (rate_ops->round_rate)
			clk_composite_ops->round_rate =
				clk_composite_round_rate;

		/* .set_rate requires either .round_rate or .determine_rate */
		if (rate_ops->set_rate) {
			if (rate_ops->determine_rate || rate_ops->round_rate)
				clk_composite_ops->set_rate =
						clk_composite_set_rate;
			else
				WARN(1, "%s: missing round_rate op is required\n",
						__func__);
		}

		composite->rate_hw = rate_hw;
		composite->rate_ops = rate_ops;
	}

	if (mux_hw && mux_ops && rate_hw && rate_ops) {
		if (mux_ops->set_parent && rate_ops->set_rate)
			clk_composite_ops->set_rate_and_parent =
			clk_composite_set_rate_and_parent;
	}

	if (gate_hw && gate_ops) {
		if (!gate_ops->is_enabled || !gate_ops->enable ||
		    !gate_ops->disable) {
			hw = ERR_PTR(-EINVAL);
			goto err;
		}

		composite->gate_hw = gate_hw;
		composite->gate_ops = gate_ops;
		clk_composite_ops->is_enabled = clk_composite_is_enabled;
		clk_composite_ops->enable = clk_composite_enable;
		clk_composite_ops->disable = clk_composite_disable;
	}

	init.ops = clk_composite_ops;
	composite->hw.init = &init;

	ret = clk_hw_register(dev, hw);
	if (ret) {
		hw = ERR_PTR(ret);
		goto err;
	}

	if (composite->mux_hw)
		composite->mux_hw->clk = hw->clk;

	if (composite->rate_hw)
		composite->rate_hw->clk = hw->clk;

	if (composite->gate_hw)
		composite->gate_hw->clk = hw->clk;

	return hw;

err:
	kfree(composite);
	return hw;
}

struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
			const char * const *parent_names, int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	return __clk_hw_register_composite(dev, name, parent_names, NULL,
					   num_parents, mux_hw, mux_ops,
					   rate_hw, rate_ops, gate_hw,
					   gate_ops, flags);
}
EXPORT_SYMBOL_GPL(clk_hw_register_composite);

struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
			const char *name,
			const struct clk_parent_data *parent_data,
			int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	return __clk_hw_register_composite(dev, name, NULL, parent_data,
					   num_parents, mux_hw, mux_ops,
					   rate_hw, rate_ops, gate_hw,
					   gate_ops, flags);
}

struct clk *clk_register_composite(struct device *dev, const char *name,
			const char * const *parent_names, int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	struct clk_hw *hw;

	hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
			mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
			flags);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}

struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
			const struct clk_parent_data *parent_data,
			int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	struct clk_hw *hw;

	hw = clk_hw_register_composite_pdata(dev, name, parent_data,
			num_parents, mux_hw, mux_ops, rate_hw, rate_ops,
			gate_hw, gate_ops, flags);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}

void clk_unregister_composite(struct clk *clk)
{
	struct clk_composite *composite;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	composite = to_clk_composite(hw);

	clk_unregister(clk);
	kfree(composite);
}

void clk_hw_unregister_composite(struct clk_hw *hw)
{
	struct clk_composite *composite;

	composite = to_clk_composite(hw);

	clk_hw_unregister(hw);
	kfree(composite);
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_composite);

static void devm_clk_hw_release_composite(struct device *dev, void *res)
{
	clk_hw_unregister_composite(*(struct clk_hw **)res);
}

static struct clk_hw *__devm_clk_hw_register_composite(struct device *dev,
			const char *name, const char * const *parent_names,
			const struct clk_parent_data *pdata, int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	struct clk_hw **ptr, *hw;

	ptr = devres_alloc(devm_clk_hw_release_composite, sizeof(*ptr),
			   GFP_KERNEL);
	if (!ptr)
		return ERR_PTR(-ENOMEM);

	hw = __clk_hw_register_composite(dev, name, parent_names, pdata,
					 num_parents, mux_hw, mux_ops, rate_hw,
					 rate_ops, gate_hw, gate_ops, flags);

	if (!IS_ERR(hw)) {
		*ptr = hw;
		devres_add(dev, ptr);
	} else {
		devres_free(ptr);
	}

	return hw;
}

struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
			const char *name,
			const struct clk_parent_data *parent_data,
			int num_parents,
			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
			unsigned long flags)
{
	return __devm_clk_hw_register_composite(dev, name, NULL, parent_data,
						num_parents, mux_hw, mux_ops,
						rate_hw, rate_ops, gate_hw,
						gate_ops, flags);
}
Commit	Line	Data
e1bd55e5	1	// SPDX-License-Identifier: GPL-2.0
ece70094 PG	2	/*
ece70094 PG	3	* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
ece70094 PG	4	*/
ece70094 PG	5
ece70094	6	#include <linux/clk-provider.h>
0eba7707	7	#include <linux/device.h>
ece70094 PG	8	#include <linux/err.h>
	9	#include <linux/slab.h>
	10
ece70094 PG	11	static u8 clk_composite_get_parent(struct clk_hw *hw)
	12	{
	13	struct clk_composite *composite = to_clk_composite(hw);
	14	const struct clk_ops *mux_ops = composite->mux_ops;
	15	struct clk_hw *mux_hw = composite->mux_hw;
	16
4e907ef6	17	__clk_hw_set_clk(mux_hw, hw);
ece70094 PG	18
	19	return mux_ops->get_parent(mux_hw);
	20	}
	21
	22	static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
	23	{
	24	struct clk_composite *composite = to_clk_composite(hw);
	25	const struct clk_ops *mux_ops = composite->mux_ops;
	26	struct clk_hw *mux_hw = composite->mux_hw;
	27
4e907ef6	28	__clk_hw_set_clk(mux_hw, hw);
ece70094 PG	29
	30	return mux_ops->set_parent(mux_hw, index);
	31	}
	32
	33	static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
	34	unsigned long parent_rate)
	35	{
	36	struct clk_composite *composite = to_clk_composite(hw);
d3a1c7be MT	37	const struct clk_ops *rate_ops = composite->rate_ops;
d3a1c7be MT	38	struct clk_hw *rate_hw = composite->rate_hw;
ece70094	39
4e907ef6	40	__clk_hw_set_clk(rate_hw, hw);
ece70094	41
d3a1c7be	42	return rate_ops->recalc_rate(rate_hw, parent_rate);
ece70094 PG	43	}
ece70094 PG	44
0817b62c BB	45	static int clk_composite_determine_rate(struct clk_hw *hw,
0817b62c BB	46	struct clk_rate_request *req)
107f3198 EL	47	{
	48	struct clk_composite *composite = to_clk_composite(hw);
	49	const struct clk_ops *rate_ops = composite->rate_ops;
	50	const struct clk_ops *mux_ops = composite->mux_ops;
	51	struct clk_hw *rate_hw = composite->rate_hw;
	52	struct clk_hw *mux_hw = composite->mux_hw;
2f508a95	53	struct clk_hw *parent;
3eb635f1 BB	54	unsigned long parent_rate;
	55	long tmp_rate, best_rate = 0;
	56	unsigned long rate_diff;
	57	unsigned long best_rate_diff = ULONG_MAX;
0817b62c	58	long rate;
3eb635f1	59	int i;
107f3198 EL	60
107f3198 EL	61	if (rate_hw && rate_ops && rate_ops->determine_rate) {
4e907ef6	62	__clk_hw_set_clk(rate_hw, hw);
0817b62c	63	return rate_ops->determine_rate(rate_hw, req);
3eb635f1 BB	64	} else if (rate_hw && rate_ops && rate_ops->round_rate &&
3eb635f1 BB	65	mux_hw && mux_ops && mux_ops->set_parent) {
0817b62c	66	req->best_parent_hw = NULL;
3eb635f1	67
98d8a60e	68	if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
2f508a95 SB	69	parent = clk_hw_get_parent(mux_hw);
	70	req->best_parent_hw = parent;
	71	req->best_parent_rate = clk_hw_get_rate(parent);
3eb635f1	72
0817b62c BB	73	rate = rate_ops->round_rate(rate_hw, req->rate,
	74	&req->best_parent_rate);
	75	if (rate < 0)
	76	return rate;
	77
	78	req->rate = rate;
	79	return 0;
3eb635f1 BB	80	}
3eb635f1 BB	81
497295af	82	for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
2f508a95	83	parent = clk_hw_get_parent_by_index(mux_hw, i);
3eb635f1 BB	84	if (!parent)
	85	continue;
	86
2f508a95	87	parent_rate = clk_hw_get_rate(parent);
3eb635f1	88
0817b62c	89	tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
3eb635f1 BB	90	&parent_rate);
	91	if (tmp_rate < 0)
	92	continue;
	93
0817b62c	94	rate_diff = abs(req->rate - tmp_rate);
3eb635f1	95
0817b62c	96	if (!rate_diff \|\| !req->best_parent_hw
3eb635f1	97	\|\| best_rate_diff > rate_diff) {
2f508a95	98	req->best_parent_hw = parent;
0817b62c	99	req->best_parent_rate = parent_rate;
3eb635f1 BB	100	best_rate_diff = rate_diff;
	101	best_rate = tmp_rate;
	102	}
	103
	104	if (!rate_diff)
0817b62c	105	return 0;
3eb635f1 BB	106	}
3eb635f1 BB	107
0817b62c BB	108	req->rate = best_rate;
0817b62c BB	109	return 0;
107f3198	110	} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
4e907ef6	111	__clk_hw_set_clk(mux_hw, hw);
0817b62c	112	return mux_ops->determine_rate(mux_hw, req);
107f3198 EL	113	} else {
107f3198 EL	114	pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
57d866e6	115	return -EINVAL;
107f3198 EL	116	}
	117	}
	118
ece70094 PG	119	static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
	120	unsigned long *prate)
	121	{
	122	struct clk_composite *composite = to_clk_composite(hw);
d3a1c7be MT	123	const struct clk_ops *rate_ops = composite->rate_ops;
d3a1c7be MT	124	struct clk_hw *rate_hw = composite->rate_hw;
ece70094	125
4e907ef6	126	__clk_hw_set_clk(rate_hw, hw);
ece70094	127
d3a1c7be	128	return rate_ops->round_rate(rate_hw, rate, prate);
ece70094 PG	129	}
	130
	131	static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
	132	unsigned long parent_rate)
	133	{
	134	struct clk_composite *composite = to_clk_composite(hw);
d3a1c7be MT	135	const struct clk_ops *rate_ops = composite->rate_ops;
d3a1c7be MT	136	struct clk_hw *rate_hw = composite->rate_hw;
ece70094	137
4e907ef6	138	__clk_hw_set_clk(rate_hw, hw);
ece70094	139
d3a1c7be	140	return rate_ops->set_rate(rate_hw, rate, parent_rate);
ece70094 PG	141	}
ece70094 PG	142
9e52cec0 FX	143	static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
	144	unsigned long rate,
	145	unsigned long parent_rate,
	146	u8 index)
	147	{
	148	struct clk_composite *composite = to_clk_composite(hw);
	149	const struct clk_ops *rate_ops = composite->rate_ops;
	150	const struct clk_ops *mux_ops = composite->mux_ops;
	151	struct clk_hw *rate_hw = composite->rate_hw;
	152	struct clk_hw *mux_hw = composite->mux_hw;
	153	unsigned long temp_rate;
	154
	155	__clk_hw_set_clk(rate_hw, hw);
	156	__clk_hw_set_clk(mux_hw, hw);
	157
	158	temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
	159	if (temp_rate > rate) {
	160	rate_ops->set_rate(rate_hw, rate, parent_rate);
	161	mux_ops->set_parent(mux_hw, index);
	162	} else {
	163	mux_ops->set_parent(mux_hw, index);
	164	rate_ops->set_rate(rate_hw, rate, parent_rate);
	165	}
	166
	167	return 0;
	168	}
	169
ece70094 PG	170	static int clk_composite_is_enabled(struct clk_hw *hw)
	171	{
	172	struct clk_composite *composite = to_clk_composite(hw);
	173	const struct clk_ops *gate_ops = composite->gate_ops;
	174	struct clk_hw *gate_hw = composite->gate_hw;
	175
4e907ef6	176	__clk_hw_set_clk(gate_hw, hw);
ece70094 PG	177
	178	return gate_ops->is_enabled(gate_hw);
	179	}
	180
	181	static int clk_composite_enable(struct clk_hw *hw)
	182	{
	183	struct clk_composite *composite = to_clk_composite(hw);
	184	const struct clk_ops *gate_ops = composite->gate_ops;
	185	struct clk_hw *gate_hw = composite->gate_hw;
	186
4e907ef6	187	__clk_hw_set_clk(gate_hw, hw);
ece70094 PG	188
	189	return gate_ops->enable(gate_hw);
	190	}
	191
	192	static void clk_composite_disable(struct clk_hw *hw)
	193	{
	194	struct clk_composite *composite = to_clk_composite(hw);
	195	const struct clk_ops *gate_ops = composite->gate_ops;
	196	struct clk_hw *gate_hw = composite->gate_hw;
	197
4e907ef6	198	__clk_hw_set_clk(gate_hw, hw);
ece70094 PG	199
	200	gate_ops->disable(gate_hw);
	201	}
	202
73ef6572 MW	203	static struct clk_hw __clk_hw_register_composite(struct device dev,
	204	const char name, const char const *parent_names,
	205	const struct clk_parent_data *pdata, int num_parents,
ece70094	206	struct clk_hw mux_hw, const struct clk_ops mux_ops,
d3a1c7be	207	struct clk_hw rate_hw, const struct clk_ops rate_ops,
ece70094 PG	208	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	209	unsigned long flags)
	210	{
49cb392d	211	struct clk_hw *hw;
cc819cf8	212	struct clk_init_data init = {};
ece70094 PG	213	struct clk_composite *composite;
ece70094 PG	214	struct clk_ops *clk_composite_ops;
49cb392d	215	int ret;
ece70094 PG	216
ece70094 PG	217	composite = kzalloc(sizeof(*composite), GFP_KERNEL);
d122db7e	218	if (!composite)
ece70094	219	return ERR_PTR(-ENOMEM);
ece70094 PG	220
ece70094 PG	221	init.name = name;
90b6c5c7	222	init.flags = flags;
73ef6572 MW	223	if (parent_names)
	224	init.parent_names = parent_names;
	225	else
	226	init.parent_data = pdata;
ece70094	227	init.num_parents = num_parents;
49cb392d	228	hw = &composite->hw;
ece70094 PG	229
	230	clk_composite_ops = &composite->ops;
	231
	232	if (mux_hw && mux_ops) {
0c02cf2f	233	if (!mux_ops->get_parent) {
49cb392d	234	hw = ERR_PTR(-EINVAL);
ece70094 PG	235	goto err;
	236	}
	237
	238	composite->mux_hw = mux_hw;
	239	composite->mux_ops = mux_ops;
	240	clk_composite_ops->get_parent = clk_composite_get_parent;
0c02cf2f HS	241	if (mux_ops->set_parent)
0c02cf2f HS	242	clk_composite_ops->set_parent = clk_composite_set_parent;
107f3198 EL	243	if (mux_ops->determine_rate)
107f3198 EL	244	clk_composite_ops->determine_rate = clk_composite_determine_rate;
ece70094 PG	245	}
ece70094 PG	246
d3a1c7be	247	if (rate_hw && rate_ops) {
f363e215	248	if (!rate_ops->recalc_rate) {
49cb392d	249	hw = ERR_PTR(-EINVAL);
ece70094 PG	250	goto err;
ece70094 PG	251	}
5a994e15	252	clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
ece70094	253
5a994e15 MT	254	if (rate_ops->determine_rate)
	255	clk_composite_ops->determine_rate =
	256	clk_composite_determine_rate;
	257	else if (rate_ops->round_rate)
	258	clk_composite_ops->round_rate =
	259	clk_composite_round_rate;
	260
	261	/* .set_rate requires either .round_rate or .determine_rate */
	262	if (rate_ops->set_rate) {
	263	if (rate_ops->determine_rate \|\| rate_ops->round_rate)
	264	clk_composite_ops->set_rate =
	265	clk_composite_set_rate;
	266	else
	267	WARN(1, "%s: missing round_rate op is required\n",
	268	__func__);
f363e215 MT	269	}
f363e215 MT	270
d3a1c7be MT	271	composite->rate_hw = rate_hw;
d3a1c7be MT	272	composite->rate_ops = rate_ops;
ece70094 PG	273	}
ece70094 PG	274
9e52cec0 FX	275	if (mux_hw && mux_ops && rate_hw && rate_ops) {
	276	if (mux_ops->set_parent && rate_ops->set_rate)
	277	clk_composite_ops->set_rate_and_parent =
	278	clk_composite_set_rate_and_parent;
	279	}
	280
ece70094 PG	281	if (gate_hw && gate_ops) {
	282	if (!gate_ops->is_enabled \|\| !gate_ops->enable \|\|
	283	!gate_ops->disable) {
49cb392d	284	hw = ERR_PTR(-EINVAL);
ece70094 PG	285	goto err;
	286	}
	287
	288	composite->gate_hw = gate_hw;
	289	composite->gate_ops = gate_ops;
	290	clk_composite_ops->is_enabled = clk_composite_is_enabled;
	291	clk_composite_ops->enable = clk_composite_enable;
	292	clk_composite_ops->disable = clk_composite_disable;
	293	}
	294
	295	init.ops = clk_composite_ops;
	296	composite->hw.init = &init;
	297
49cb392d SB	298	ret = clk_hw_register(dev, hw);
	299	if (ret) {
	300	hw = ERR_PTR(ret);
ece70094	301	goto err;
49cb392d	302	}
ece70094 PG	303
ece70094 PG	304	if (composite->mux_hw)
49cb392d	305	composite->mux_hw->clk = hw->clk;
ece70094	306
d3a1c7be	307	if (composite->rate_hw)
49cb392d	308	composite->rate_hw->clk = hw->clk;
ece70094 PG	309
ece70094 PG	310	if (composite->gate_hw)
49cb392d	311	composite->gate_hw->clk = hw->clk;
ece70094	312
49cb392d	313	return hw;
ece70094 PG	314
	315	err:
	316	kfree(composite);
49cb392d SB	317	return hw;
	318	}
	319
73ef6572 MW	320	struct clk_hw clk_hw_register_composite(struct device dev, const char *name,
	321	const char * const *parent_names, int num_parents,
	322	struct clk_hw mux_hw, const struct clk_ops mux_ops,
	323	struct clk_hw rate_hw, const struct clk_ops rate_ops,
	324	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	325	unsigned long flags)
	326	{
	327	return __clk_hw_register_composite(dev, name, parent_names, NULL,
	328	num_parents, mux_hw, mux_ops,
	329	rate_hw, rate_ops, gate_hw,
	330	gate_ops, flags);
	331	}
d7d7518f	332	EXPORT_SYMBOL_GPL(clk_hw_register_composite);
73ef6572 MW	333
	334	struct clk_hw clk_hw_register_composite_pdata(struct device dev,
	335	const char *name,
	336	const struct clk_parent_data *parent_data,
	337	int num_parents,
	338	struct clk_hw mux_hw, const struct clk_ops mux_ops,
	339	struct clk_hw rate_hw, const struct clk_ops rate_ops,
	340	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	341	unsigned long flags)
	342	{
	343	return __clk_hw_register_composite(dev, name, NULL, parent_data,
	344	num_parents, mux_hw, mux_ops,
	345	rate_hw, rate_ops, gate_hw,
	346	gate_ops, flags);
	347	}
	348
49cb392d SB	349	struct clk clk_register_composite(struct device dev, const char *name,
	350	const char * const *parent_names, int num_parents,
	351	struct clk_hw mux_hw, const struct clk_ops mux_ops,
	352	struct clk_hw rate_hw, const struct clk_ops rate_ops,
	353	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	354	unsigned long flags)
	355	{
	356	struct clk_hw *hw;
	357
	358	hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
	359	mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
	360	flags);
	361	if (IS_ERR(hw))
	362	return ERR_CAST(hw);
	363	return hw->clk;
ece70094	364	}
92a39d90	365
73ef6572 MW	366	struct clk clk_register_composite_pdata(struct device dev, const char *name,
	367	const struct clk_parent_data *parent_data,
	368	int num_parents,
	369	struct clk_hw mux_hw, const struct clk_ops mux_ops,
	370	struct clk_hw rate_hw, const struct clk_ops rate_ops,
	371	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	372	unsigned long flags)
	373	{
	374	struct clk_hw *hw;
	375
	376	hw = clk_hw_register_composite_pdata(dev, name, parent_data,
	377	num_parents, mux_hw, mux_ops, rate_hw, rate_ops,
	378	gate_hw, gate_ops, flags);
	379	if (IS_ERR(hw))
	380	return ERR_CAST(hw);
	381	return hw->clk;
	382	}
	383
92a39d90 MR	384	void clk_unregister_composite(struct clk *clk)
	385	{
	386	struct clk_composite *composite;
	387	struct clk_hw *hw;
	388
	389	hw = __clk_get_hw(clk);
	390	if (!hw)
	391	return;
	392
	393	composite = to_clk_composite(hw);
	394
	395	clk_unregister(clk);
	396	kfree(composite);
	397	}
d8549bcd MS	398
	399	void clk_hw_unregister_composite(struct clk_hw *hw)
	400	{
	401	struct clk_composite *composite;
	402
	403	composite = to_clk_composite(hw);
	404
	405	clk_hw_unregister(hw);
	406	kfree(composite);
	407	}
	408	EXPORT_SYMBOL_GPL(clk_hw_unregister_composite);
0eba7707 MW	409
	410	static void devm_clk_hw_release_composite(struct device dev, void res)
	411	{
	412	clk_hw_unregister_composite((struct clk_hw *)res);
	413	}
	414
	415	static struct clk_hw __devm_clk_hw_register_composite(struct device dev,
	416	const char name, const char const *parent_names,
	417	const struct clk_parent_data *pdata, int num_parents,
	418	struct clk_hw mux_hw, const struct clk_ops mux_ops,
	419	struct clk_hw rate_hw, const struct clk_ops rate_ops,
	420	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	421	unsigned long flags)
	422	{
	423	struct clk_hw *ptr, hw;
	424
	425	ptr = devres_alloc(devm_clk_hw_release_composite, sizeof(*ptr),
	426	GFP_KERNEL);
	427	if (!ptr)
	428	return ERR_PTR(-ENOMEM);
	429
	430	hw = __clk_hw_register_composite(dev, name, parent_names, pdata,
	431	num_parents, mux_hw, mux_ops, rate_hw,
	432	rate_ops, gate_hw, gate_ops, flags);
	433
	434	if (!IS_ERR(hw)) {
	435	*ptr = hw;
	436	devres_add(dev, ptr);
	437	} else {
	438	devres_free(ptr);
	439	}
	440
	441	return hw;
	442	}
	443
	444	struct clk_hw devm_clk_hw_register_composite_pdata(struct device dev,
	445	const char *name,
	446	const struct clk_parent_data *parent_data,
	447	int num_parents,
	448	struct clk_hw mux_hw, const struct clk_ops mux_ops,
	449	struct clk_hw rate_hw, const struct clk_ops rate_ops,
	450	struct clk_hw gate_hw, const struct clk_ops gate_ops,
	451	unsigned long flags)
	452	{
	453	return __devm_clk_hw_register_composite(dev, name, NULL, parent_data,
	454	num_parents, mux_hw, mux_ops,
	455	rate_hw, rate_ops, gate_hw,
	456	gate_ops, flags);
	457	}