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9d9f78ed MT |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> | |
4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Adjustable divider clock implementation | |
11 | */ | |
12 | ||
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/string.h> | |
1a3cd184 | 19 | #include <linux/log2.h> |
9d9f78ed MT |
20 | |
21 | /* | |
22 | * DOC: basic adjustable divider clock that cannot gate | |
23 | * | |
24 | * Traits of this clock: | |
25 | * prepare - clk_prepare only ensures that parents are prepared | |
26 | * enable - clk_enable only ensures that parents are enabled | |
9556f9da | 27 | * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) |
9d9f78ed MT |
28 | * parent - fixed parent. No clk_set_parent support |
29 | */ | |
30 | ||
bca9690b | 31 | #define div_mask(width) ((1 << (width)) - 1) |
6d9252bd | 32 | |
fab88ca7 SB |
33 | static unsigned int _get_table_maxdiv(const struct clk_div_table *table, |
34 | u8 width) | |
357c3f0a | 35 | { |
fab88ca7 | 36 | unsigned int maxdiv = 0, mask = div_mask(width); |
357c3f0a RN |
37 | const struct clk_div_table *clkt; |
38 | ||
39 | for (clkt = table; clkt->div; clkt++) | |
fab88ca7 | 40 | if (clkt->div > maxdiv && clkt->val <= mask) |
357c3f0a RN |
41 | maxdiv = clkt->div; |
42 | return maxdiv; | |
43 | } | |
44 | ||
774b5143 MC |
45 | static unsigned int _get_table_mindiv(const struct clk_div_table *table) |
46 | { | |
47 | unsigned int mindiv = UINT_MAX; | |
48 | const struct clk_div_table *clkt; | |
49 | ||
50 | for (clkt = table; clkt->div; clkt++) | |
51 | if (clkt->div < mindiv) | |
52 | mindiv = clkt->div; | |
53 | return mindiv; | |
54 | } | |
55 | ||
bca9690b SB |
56 | static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width, |
57 | unsigned long flags) | |
6d9252bd | 58 | { |
bca9690b SB |
59 | if (flags & CLK_DIVIDER_ONE_BASED) |
60 | return div_mask(width); | |
61 | if (flags & CLK_DIVIDER_POWER_OF_TWO) | |
62 | return 1 << div_mask(width); | |
63 | if (table) | |
fab88ca7 | 64 | return _get_table_maxdiv(table, width); |
bca9690b | 65 | return div_mask(width) + 1; |
6d9252bd RN |
66 | } |
67 | ||
357c3f0a RN |
68 | static unsigned int _get_table_div(const struct clk_div_table *table, |
69 | unsigned int val) | |
70 | { | |
71 | const struct clk_div_table *clkt; | |
72 | ||
73 | for (clkt = table; clkt->div; clkt++) | |
74 | if (clkt->val == val) | |
75 | return clkt->div; | |
76 | return 0; | |
77 | } | |
78 | ||
bca9690b | 79 | static unsigned int _get_div(const struct clk_div_table *table, |
afe76c8f | 80 | unsigned int val, unsigned long flags, u8 width) |
6d9252bd | 81 | { |
bca9690b | 82 | if (flags & CLK_DIVIDER_ONE_BASED) |
6d9252bd | 83 | return val; |
bca9690b | 84 | if (flags & CLK_DIVIDER_POWER_OF_TWO) |
6d9252bd | 85 | return 1 << val; |
afe76c8f JQ |
86 | if (flags & CLK_DIVIDER_MAX_AT_ZERO) |
87 | return val ? val : div_mask(width) + 1; | |
bca9690b SB |
88 | if (table) |
89 | return _get_table_div(table, val); | |
6d9252bd RN |
90 | return val + 1; |
91 | } | |
92 | ||
357c3f0a RN |
93 | static unsigned int _get_table_val(const struct clk_div_table *table, |
94 | unsigned int div) | |
95 | { | |
96 | const struct clk_div_table *clkt; | |
97 | ||
98 | for (clkt = table; clkt->div; clkt++) | |
99 | if (clkt->div == div) | |
100 | return clkt->val; | |
101 | return 0; | |
102 | } | |
103 | ||
bca9690b | 104 | static unsigned int _get_val(const struct clk_div_table *table, |
afe76c8f | 105 | unsigned int div, unsigned long flags, u8 width) |
6d9252bd | 106 | { |
bca9690b | 107 | if (flags & CLK_DIVIDER_ONE_BASED) |
6d9252bd | 108 | return div; |
bca9690b | 109 | if (flags & CLK_DIVIDER_POWER_OF_TWO) |
6d9252bd | 110 | return __ffs(div); |
afe76c8f JQ |
111 | if (flags & CLK_DIVIDER_MAX_AT_ZERO) |
112 | return (div == div_mask(width) + 1) ? 0 : div; | |
bca9690b SB |
113 | if (table) |
114 | return _get_table_val(table, div); | |
6d9252bd RN |
115 | return div - 1; |
116 | } | |
9d9f78ed | 117 | |
bca9690b SB |
118 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, |
119 | unsigned int val, | |
120 | const struct clk_div_table *table, | |
3f68ef05 | 121 | unsigned long flags, unsigned long width) |
9d9f78ed | 122 | { |
bca9690b | 123 | unsigned int div; |
9d9f78ed | 124 | |
3f68ef05 | 125 | div = _get_div(table, val, flags, width); |
6d9252bd | 126 | if (!div) { |
bca9690b | 127 | WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO), |
056b2053 | 128 | "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", |
2f508a95 | 129 | clk_hw_get_name(hw)); |
6d9252bd RN |
130 | return parent_rate; |
131 | } | |
9d9f78ed | 132 | |
9556f9da | 133 | return DIV_ROUND_UP_ULL((u64)parent_rate, div); |
9d9f78ed | 134 | } |
bca9690b SB |
135 | EXPORT_SYMBOL_GPL(divider_recalc_rate); |
136 | ||
137 | static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, | |
138 | unsigned long parent_rate) | |
139 | { | |
140 | struct clk_divider *divider = to_clk_divider(hw); | |
141 | unsigned int val; | |
142 | ||
143 | val = clk_readl(divider->reg) >> divider->shift; | |
144 | val &= div_mask(divider->width); | |
145 | ||
146 | return divider_recalc_rate(hw, parent_rate, val, divider->table, | |
3f68ef05 | 147 | divider->flags, divider->width); |
bca9690b | 148 | } |
9d9f78ed | 149 | |
357c3f0a RN |
150 | static bool _is_valid_table_div(const struct clk_div_table *table, |
151 | unsigned int div) | |
152 | { | |
153 | const struct clk_div_table *clkt; | |
154 | ||
155 | for (clkt = table; clkt->div; clkt++) | |
156 | if (clkt->div == div) | |
157 | return true; | |
158 | return false; | |
159 | } | |
160 | ||
bca9690b SB |
161 | static bool _is_valid_div(const struct clk_div_table *table, unsigned int div, |
162 | unsigned long flags) | |
357c3f0a | 163 | { |
bca9690b | 164 | if (flags & CLK_DIVIDER_POWER_OF_TWO) |
1a3cd184 | 165 | return is_power_of_2(div); |
bca9690b SB |
166 | if (table) |
167 | return _is_valid_table_div(table, div); | |
357c3f0a RN |
168 | return true; |
169 | } | |
170 | ||
dd23c2cd MC |
171 | static int _round_up_table(const struct clk_div_table *table, int div) |
172 | { | |
173 | const struct clk_div_table *clkt; | |
fe52e750 | 174 | int up = INT_MAX; |
dd23c2cd MC |
175 | |
176 | for (clkt = table; clkt->div; clkt++) { | |
177 | if (clkt->div == div) | |
178 | return clkt->div; | |
179 | else if (clkt->div < div) | |
180 | continue; | |
181 | ||
182 | if ((clkt->div - div) < (up - div)) | |
183 | up = clkt->div; | |
184 | } | |
185 | ||
186 | return up; | |
187 | } | |
188 | ||
774b5143 MC |
189 | static int _round_down_table(const struct clk_div_table *table, int div) |
190 | { | |
191 | const struct clk_div_table *clkt; | |
192 | int down = _get_table_mindiv(table); | |
193 | ||
194 | for (clkt = table; clkt->div; clkt++) { | |
195 | if (clkt->div == div) | |
196 | return clkt->div; | |
197 | else if (clkt->div > div) | |
198 | continue; | |
199 | ||
200 | if ((div - clkt->div) < (div - down)) | |
201 | down = clkt->div; | |
202 | } | |
203 | ||
204 | return down; | |
205 | } | |
206 | ||
bca9690b SB |
207 | static int _div_round_up(const struct clk_div_table *table, |
208 | unsigned long parent_rate, unsigned long rate, | |
209 | unsigned long flags) | |
dd23c2cd | 210 | { |
9556f9da | 211 | int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); |
dd23c2cd | 212 | |
bca9690b | 213 | if (flags & CLK_DIVIDER_POWER_OF_TWO) |
dd23c2cd | 214 | div = __roundup_pow_of_two(div); |
bca9690b SB |
215 | if (table) |
216 | div = _round_up_table(table, div); | |
dd23c2cd MC |
217 | |
218 | return div; | |
219 | } | |
220 | ||
bca9690b SB |
221 | static int _div_round_closest(const struct clk_div_table *table, |
222 | unsigned long parent_rate, unsigned long rate, | |
223 | unsigned long flags) | |
774b5143 | 224 | { |
93155142 | 225 | int up, down; |
26bac95a | 226 | unsigned long up_rate, down_rate; |
774b5143 | 227 | |
9556f9da | 228 | up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); |
93155142 | 229 | down = parent_rate / rate; |
774b5143 | 230 | |
bca9690b | 231 | if (flags & CLK_DIVIDER_POWER_OF_TWO) { |
93155142 UKK |
232 | up = __roundup_pow_of_two(up); |
233 | down = __rounddown_pow_of_two(down); | |
bca9690b | 234 | } else if (table) { |
93155142 UKK |
235 | up = _round_up_table(table, up); |
236 | down = _round_down_table(table, down); | |
774b5143 MC |
237 | } |
238 | ||
9556f9da BN |
239 | up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); |
240 | down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); | |
26bac95a UKK |
241 | |
242 | return (rate - up_rate) <= (down_rate - rate) ? up : down; | |
774b5143 MC |
243 | } |
244 | ||
bca9690b SB |
245 | static int _div_round(const struct clk_div_table *table, |
246 | unsigned long parent_rate, unsigned long rate, | |
247 | unsigned long flags) | |
774b5143 | 248 | { |
bca9690b SB |
249 | if (flags & CLK_DIVIDER_ROUND_CLOSEST) |
250 | return _div_round_closest(table, parent_rate, rate, flags); | |
774b5143 | 251 | |
bca9690b | 252 | return _div_round_up(table, parent_rate, rate, flags); |
774b5143 MC |
253 | } |
254 | ||
bca9690b SB |
255 | static bool _is_best_div(unsigned long rate, unsigned long now, |
256 | unsigned long best, unsigned long flags) | |
774b5143 | 257 | { |
bca9690b | 258 | if (flags & CLK_DIVIDER_ROUND_CLOSEST) |
774b5143 MC |
259 | return abs(rate - now) < abs(rate - best); |
260 | ||
261 | return now <= rate && now > best; | |
262 | } | |
263 | ||
bca9690b SB |
264 | static int _next_div(const struct clk_div_table *table, int div, |
265 | unsigned long flags) | |
0e2de78e MC |
266 | { |
267 | div++; | |
268 | ||
bca9690b | 269 | if (flags & CLK_DIVIDER_POWER_OF_TWO) |
0e2de78e | 270 | return __roundup_pow_of_two(div); |
bca9690b SB |
271 | if (table) |
272 | return _round_up_table(table, div); | |
0e2de78e MC |
273 | |
274 | return div; | |
275 | } | |
276 | ||
22833a91 MR |
277 | static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent, |
278 | unsigned long rate, | |
bca9690b SB |
279 | unsigned long *best_parent_rate, |
280 | const struct clk_div_table *table, u8 width, | |
281 | unsigned long flags) | |
9d9f78ed | 282 | { |
9d9f78ed MT |
283 | int i, bestdiv = 0; |
284 | unsigned long parent_rate, best = 0, now, maxdiv; | |
081c9025 | 285 | unsigned long parent_rate_saved = *best_parent_rate; |
9d9f78ed MT |
286 | |
287 | if (!rate) | |
288 | rate = 1; | |
289 | ||
bca9690b | 290 | maxdiv = _get_maxdiv(table, width, flags); |
9d9f78ed | 291 | |
98d8a60e | 292 | if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { |
81536e07 | 293 | parent_rate = *best_parent_rate; |
bca9690b | 294 | bestdiv = _div_round(table, parent_rate, rate, flags); |
9d9f78ed MT |
295 | bestdiv = bestdiv == 0 ? 1 : bestdiv; |
296 | bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; | |
297 | return bestdiv; | |
298 | } | |
299 | ||
300 | /* | |
301 | * The maximum divider we can use without overflowing | |
302 | * unsigned long in rate * i below | |
303 | */ | |
304 | maxdiv = min(ULONG_MAX / rate, maxdiv); | |
305 | ||
653d1452 MY |
306 | for (i = _next_div(table, 0, flags); i <= maxdiv; |
307 | i = _next_div(table, i, flags)) { | |
081c9025 SG |
308 | if (rate * i == parent_rate_saved) { |
309 | /* | |
310 | * It's the most ideal case if the requested rate can be | |
311 | * divided from parent clock without needing to change | |
312 | * parent rate, so return the divider immediately. | |
313 | */ | |
314 | *best_parent_rate = parent_rate_saved; | |
315 | return i; | |
316 | } | |
22833a91 | 317 | parent_rate = clk_hw_round_rate(parent, rate * i); |
9556f9da | 318 | now = DIV_ROUND_UP_ULL((u64)parent_rate, i); |
bca9690b | 319 | if (_is_best_div(rate, now, best, flags)) { |
9d9f78ed MT |
320 | bestdiv = i; |
321 | best = now; | |
322 | *best_parent_rate = parent_rate; | |
323 | } | |
324 | } | |
325 | ||
326 | if (!bestdiv) { | |
bca9690b | 327 | bestdiv = _get_maxdiv(table, width, flags); |
22833a91 | 328 | *best_parent_rate = clk_hw_round_rate(parent, 1); |
9d9f78ed MT |
329 | } |
330 | ||
331 | return bestdiv; | |
332 | } | |
333 | ||
22833a91 MR |
334 | long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
335 | unsigned long rate, unsigned long *prate, | |
336 | const struct clk_div_table *table, | |
337 | u8 width, unsigned long flags) | |
9d9f78ed MT |
338 | { |
339 | int div; | |
bca9690b | 340 | |
22833a91 | 341 | div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags); |
9d9f78ed | 342 | |
9556f9da | 343 | return DIV_ROUND_UP_ULL((u64)*prate, div); |
9d9f78ed | 344 | } |
22833a91 | 345 | EXPORT_SYMBOL_GPL(divider_round_rate_parent); |
9d9f78ed | 346 | |
bca9690b SB |
347 | static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, |
348 | unsigned long *prate) | |
9d9f78ed MT |
349 | { |
350 | struct clk_divider *divider = to_clk_divider(hw); | |
bca9690b SB |
351 | int bestdiv; |
352 | ||
353 | /* if read only, just return current value */ | |
354 | if (divider->flags & CLK_DIVIDER_READ_ONLY) { | |
2cf9a578 | 355 | bestdiv = clk_readl(divider->reg) >> divider->shift; |
bca9690b | 356 | bestdiv &= div_mask(divider->width); |
afe76c8f JQ |
357 | bestdiv = _get_div(divider->table, bestdiv, divider->flags, |
358 | divider->width); | |
9556f9da | 359 | return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); |
bca9690b SB |
360 | } |
361 | ||
362 | return divider_round_rate(hw, rate, prate, divider->table, | |
363 | divider->width, divider->flags); | |
364 | } | |
365 | ||
366 | int divider_get_val(unsigned long rate, unsigned long parent_rate, | |
367 | const struct clk_div_table *table, u8 width, | |
368 | unsigned long flags) | |
369 | { | |
6d9252bd | 370 | unsigned int div, value; |
9d9f78ed | 371 | |
9556f9da | 372 | div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); |
dd23c2cd | 373 | |
bca9690b | 374 | if (!_is_valid_div(table, div, flags)) |
dd23c2cd MC |
375 | return -EINVAL; |
376 | ||
afe76c8f | 377 | value = _get_val(table, div, flags, width); |
bca9690b SB |
378 | |
379 | return min_t(unsigned int, value, div_mask(width)); | |
380 | } | |
381 | EXPORT_SYMBOL_GPL(divider_get_val); | |
382 | ||
383 | static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |
384 | unsigned long parent_rate) | |
385 | { | |
386 | struct clk_divider *divider = to_clk_divider(hw); | |
2316a7a3 | 387 | int value; |
bca9690b SB |
388 | unsigned long flags = 0; |
389 | u32 val; | |
9d9f78ed | 390 | |
bca9690b SB |
391 | value = divider_get_val(rate, parent_rate, divider->table, |
392 | divider->width, divider->flags); | |
2316a7a3 AF |
393 | if (value < 0) |
394 | return value; | |
9d9f78ed MT |
395 | |
396 | if (divider->lock) | |
397 | spin_lock_irqsave(divider->lock, flags); | |
661e2180 SB |
398 | else |
399 | __acquire(divider->lock); | |
9d9f78ed | 400 | |
d57dfe75 | 401 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { |
bca9690b | 402 | val = div_mask(divider->width) << (divider->shift + 16); |
d57dfe75 | 403 | } else { |
aa514ce3 | 404 | val = clk_readl(divider->reg); |
bca9690b | 405 | val &= ~(div_mask(divider->width) << divider->shift); |
d57dfe75 | 406 | } |
2316a7a3 | 407 | val |= (u32)value << divider->shift; |
aa514ce3 | 408 | clk_writel(val, divider->reg); |
9d9f78ed MT |
409 | |
410 | if (divider->lock) | |
411 | spin_unlock_irqrestore(divider->lock, flags); | |
661e2180 SB |
412 | else |
413 | __release(divider->lock); | |
9d9f78ed MT |
414 | |
415 | return 0; | |
416 | } | |
9d9f78ed | 417 | |
822c250e | 418 | const struct clk_ops clk_divider_ops = { |
9d9f78ed MT |
419 | .recalc_rate = clk_divider_recalc_rate, |
420 | .round_rate = clk_divider_round_rate, | |
421 | .set_rate = clk_divider_set_rate, | |
422 | }; | |
423 | EXPORT_SYMBOL_GPL(clk_divider_ops); | |
424 | ||
50359819 HS |
425 | const struct clk_ops clk_divider_ro_ops = { |
426 | .recalc_rate = clk_divider_recalc_rate, | |
427 | .round_rate = clk_divider_round_rate, | |
428 | }; | |
429 | EXPORT_SYMBOL_GPL(clk_divider_ro_ops); | |
430 | ||
eb7d264f | 431 | static struct clk_hw *_register_divider(struct device *dev, const char *name, |
9d9f78ed MT |
432 | const char *parent_name, unsigned long flags, |
433 | void __iomem *reg, u8 shift, u8 width, | |
357c3f0a RN |
434 | u8 clk_divider_flags, const struct clk_div_table *table, |
435 | spinlock_t *lock) | |
9d9f78ed MT |
436 | { |
437 | struct clk_divider *div; | |
eb7d264f | 438 | struct clk_hw *hw; |
0197b3ea | 439 | struct clk_init_data init; |
eb7d264f | 440 | int ret; |
9d9f78ed | 441 | |
d57dfe75 HZ |
442 | if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { |
443 | if (width + shift > 16) { | |
444 | pr_warn("divider value exceeds LOWORD field\n"); | |
445 | return ERR_PTR(-EINVAL); | |
446 | } | |
447 | } | |
448 | ||
27d54591 | 449 | /* allocate the divider */ |
d122db7e SB |
450 | div = kzalloc(sizeof(*div), GFP_KERNEL); |
451 | if (!div) | |
27d54591 | 452 | return ERR_PTR(-ENOMEM); |
9d9f78ed | 453 | |
0197b3ea | 454 | init.name = name; |
50359819 HS |
455 | if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) |
456 | init.ops = &clk_divider_ro_ops; | |
457 | else | |
458 | init.ops = &clk_divider_ops; | |
f7d8caad | 459 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
460 | init.parent_names = (parent_name ? &parent_name: NULL); |
461 | init.num_parents = (parent_name ? 1 : 0); | |
462 | ||
9d9f78ed MT |
463 | /* struct clk_divider assignments */ |
464 | div->reg = reg; | |
465 | div->shift = shift; | |
466 | div->width = width; | |
467 | div->flags = clk_divider_flags; | |
468 | div->lock = lock; | |
0197b3ea | 469 | div->hw.init = &init; |
357c3f0a | 470 | div->table = table; |
9d9f78ed | 471 | |
27d54591 | 472 | /* register the clock */ |
eb7d264f SB |
473 | hw = &div->hw; |
474 | ret = clk_hw_register(dev, hw); | |
475 | if (ret) { | |
27d54591 | 476 | kfree(div); |
eb7d264f SB |
477 | hw = ERR_PTR(ret); |
478 | } | |
9d9f78ed | 479 | |
eb7d264f | 480 | return hw; |
9d9f78ed | 481 | } |
357c3f0a RN |
482 | |
483 | /** | |
484 | * clk_register_divider - register a divider clock with the clock framework | |
485 | * @dev: device registering this clock | |
486 | * @name: name of this clock | |
487 | * @parent_name: name of clock's parent | |
488 | * @flags: framework-specific flags | |
489 | * @reg: register address to adjust divider | |
490 | * @shift: number of bits to shift the bitfield | |
491 | * @width: width of the bitfield | |
492 | * @clk_divider_flags: divider-specific flags for this clock | |
493 | * @lock: shared register lock for this clock | |
494 | */ | |
495 | struct clk *clk_register_divider(struct device *dev, const char *name, | |
496 | const char *parent_name, unsigned long flags, | |
497 | void __iomem *reg, u8 shift, u8 width, | |
498 | u8 clk_divider_flags, spinlock_t *lock) | |
499 | { | |
eb7d264f SB |
500 | struct clk_hw *hw; |
501 | ||
502 | hw = _register_divider(dev, name, parent_name, flags, reg, shift, | |
357c3f0a | 503 | width, clk_divider_flags, NULL, lock); |
eb7d264f SB |
504 | if (IS_ERR(hw)) |
505 | return ERR_CAST(hw); | |
506 | return hw->clk; | |
357c3f0a | 507 | } |
4c5eeea9 | 508 | EXPORT_SYMBOL_GPL(clk_register_divider); |
357c3f0a | 509 | |
eb7d264f SB |
510 | /** |
511 | * clk_hw_register_divider - register a divider clock with the clock framework | |
512 | * @dev: device registering this clock | |
513 | * @name: name of this clock | |
514 | * @parent_name: name of clock's parent | |
515 | * @flags: framework-specific flags | |
516 | * @reg: register address to adjust divider | |
517 | * @shift: number of bits to shift the bitfield | |
518 | * @width: width of the bitfield | |
519 | * @clk_divider_flags: divider-specific flags for this clock | |
520 | * @lock: shared register lock for this clock | |
521 | */ | |
522 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, | |
523 | const char *parent_name, unsigned long flags, | |
524 | void __iomem *reg, u8 shift, u8 width, | |
525 | u8 clk_divider_flags, spinlock_t *lock) | |
526 | { | |
527 | return _register_divider(dev, name, parent_name, flags, reg, shift, | |
528 | width, clk_divider_flags, NULL, lock); | |
529 | } | |
530 | EXPORT_SYMBOL_GPL(clk_hw_register_divider); | |
531 | ||
357c3f0a RN |
532 | /** |
533 | * clk_register_divider_table - register a table based divider clock with | |
534 | * the clock framework | |
535 | * @dev: device registering this clock | |
536 | * @name: name of this clock | |
537 | * @parent_name: name of clock's parent | |
538 | * @flags: framework-specific flags | |
539 | * @reg: register address to adjust divider | |
540 | * @shift: number of bits to shift the bitfield | |
541 | * @width: width of the bitfield | |
542 | * @clk_divider_flags: divider-specific flags for this clock | |
543 | * @table: array of divider/value pairs ending with a div set to 0 | |
544 | * @lock: shared register lock for this clock | |
545 | */ | |
546 | struct clk *clk_register_divider_table(struct device *dev, const char *name, | |
547 | const char *parent_name, unsigned long flags, | |
548 | void __iomem *reg, u8 shift, u8 width, | |
549 | u8 clk_divider_flags, const struct clk_div_table *table, | |
550 | spinlock_t *lock) | |
551 | { | |
eb7d264f SB |
552 | struct clk_hw *hw; |
553 | ||
554 | hw = _register_divider(dev, name, parent_name, flags, reg, shift, | |
357c3f0a | 555 | width, clk_divider_flags, table, lock); |
eb7d264f SB |
556 | if (IS_ERR(hw)) |
557 | return ERR_CAST(hw); | |
558 | return hw->clk; | |
357c3f0a | 559 | } |
4c5eeea9 | 560 | EXPORT_SYMBOL_GPL(clk_register_divider_table); |
4e3c021f | 561 | |
eb7d264f SB |
562 | /** |
563 | * clk_hw_register_divider_table - register a table based divider clock with | |
564 | * the clock framework | |
565 | * @dev: device registering this clock | |
566 | * @name: name of this clock | |
567 | * @parent_name: name of clock's parent | |
568 | * @flags: framework-specific flags | |
569 | * @reg: register address to adjust divider | |
570 | * @shift: number of bits to shift the bitfield | |
571 | * @width: width of the bitfield | |
572 | * @clk_divider_flags: divider-specific flags for this clock | |
573 | * @table: array of divider/value pairs ending with a div set to 0 | |
574 | * @lock: shared register lock for this clock | |
575 | */ | |
576 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, | |
577 | const char *name, const char *parent_name, unsigned long flags, | |
578 | void __iomem *reg, u8 shift, u8 width, | |
579 | u8 clk_divider_flags, const struct clk_div_table *table, | |
580 | spinlock_t *lock) | |
581 | { | |
582 | return _register_divider(dev, name, parent_name, flags, reg, shift, | |
583 | width, clk_divider_flags, table, lock); | |
584 | } | |
585 | EXPORT_SYMBOL_GPL(clk_hw_register_divider_table); | |
586 | ||
4e3c021f KK |
587 | void clk_unregister_divider(struct clk *clk) |
588 | { | |
589 | struct clk_divider *div; | |
590 | struct clk_hw *hw; | |
591 | ||
592 | hw = __clk_get_hw(clk); | |
593 | if (!hw) | |
594 | return; | |
595 | ||
596 | div = to_clk_divider(hw); | |
597 | ||
598 | clk_unregister(clk); | |
599 | kfree(div); | |
600 | } | |
601 | EXPORT_SYMBOL_GPL(clk_unregister_divider); | |
eb7d264f SB |
602 | |
603 | /** | |
604 | * clk_hw_unregister_divider - unregister a clk divider | |
605 | * @hw: hardware-specific clock data to unregister | |
606 | */ | |
607 | void clk_hw_unregister_divider(struct clk_hw *hw) | |
608 | { | |
609 | struct clk_divider *div; | |
610 | ||
611 | div = to_clk_divider(hw); | |
612 | ||
613 | clk_hw_unregister(hw); | |
614 | kfree(div); | |
615 | } | |
616 | EXPORT_SYMBOL_GPL(clk_hw_unregister_divider); |