[mirror_ubuntu-focal-kernel.git] / drivers / clk / clk-divider.c

/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Adjustable divider clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/log2.h>

/*
 * DOC: basic adjustable divider clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
 * parent - fixed parent.  No clk_set_parent support
 */

#define div_mask(width)	((1 << (width)) - 1)

static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
				      u8 width)
{
	unsigned int maxdiv = 0, mask = div_mask(width);
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div > maxdiv && clkt->val <= mask)
			maxdiv = clkt->div;
	return maxdiv;
}

static unsigned int _get_table_mindiv(const struct clk_div_table *table)
{
	unsigned int mindiv = UINT_MAX;
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div < mindiv)
			mindiv = clkt->div;
	return mindiv;
}

static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
				unsigned long flags)
{
	if (flags & CLK_DIVIDER_ONE_BASED)
		return div_mask(width);
	if (flags & CLK_DIVIDER_POWER_OF_TWO)
		return 1 << div_mask(width);
	if (table)
		return _get_table_maxdiv(table, width);
	return div_mask(width) + 1;
}

static unsigned int _get_table_div(const struct clk_div_table *table,
							unsigned int val)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->val == val)
			return clkt->div;
	return 0;
}

static unsigned int _get_div(const struct clk_div_table *table,
			     unsigned int val, unsigned long flags, u8 width)
{
	if (flags & CLK_DIVIDER_ONE_BASED)
		return val;
	if (flags & CLK_DIVIDER_POWER_OF_TWO)
		return 1 << val;
	if (flags & CLK_DIVIDER_MAX_AT_ZERO)
		return val ? val : div_mask(width) + 1;
	if (table)
		return _get_table_div(table, val);
	return val + 1;
}

static unsigned int _get_table_val(const struct clk_div_table *table,
							unsigned int div)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div == div)
			return clkt->val;
	return 0;
}

static unsigned int _get_val(const struct clk_div_table *table,
			     unsigned int div, unsigned long flags, u8 width)
{
	if (flags & CLK_DIVIDER_ONE_BASED)
		return div;
	if (flags & CLK_DIVIDER_POWER_OF_TWO)
		return __ffs(div);
	if (flags & CLK_DIVIDER_MAX_AT_ZERO)
		return (div == div_mask(width) + 1) ? 0 : div;
	if (table)
		return  _get_table_val(table, div);
	return div - 1;
}

unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
				  unsigned int val,
				  const struct clk_div_table *table,
				  unsigned long flags)
{
	struct clk_divider *divider = to_clk_divider(hw);
	unsigned int div;

	div = _get_div(table, val, flags, divider->width);
	if (!div) {
		WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
			"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
			clk_hw_get_name(hw));
		return parent_rate;
	}

	return DIV_ROUND_UP_ULL((u64)parent_rate, div);
}
EXPORT_SYMBOL_GPL(divider_recalc_rate);

static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	unsigned int val;

	val = clk_readl(divider->reg) >> divider->shift;
	val &= div_mask(divider->width);

	return divider_recalc_rate(hw, parent_rate, val, divider->table,
				   divider->flags);
}

static bool _is_valid_table_div(const struct clk_div_table *table,
							 unsigned int div)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div == div)
			return true;
	return false;
}

static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
			  unsigned long flags)
{
	if (flags & CLK_DIVIDER_POWER_OF_TWO)
		return is_power_of_2(div);
	if (table)
		return _is_valid_table_div(table, div);
	return true;
}

static int _round_up_table(const struct clk_div_table *table, int div)
{
	const struct clk_div_table *clkt;
	int up = INT_MAX;

	for (clkt = table; clkt->div; clkt++) {
		if (clkt->div == div)
			return clkt->div;
		else if (clkt->div < div)
			continue;

		if ((clkt->div - div) < (up - div))
			up = clkt->div;
	}

	return up;
}

static int _round_down_table(const struct clk_div_table *table, int div)
{
	const struct clk_div_table *clkt;
	int down = _get_table_mindiv(table);

	for (clkt = table; clkt->div; clkt++) {
		if (clkt->div == div)
			return clkt->div;
		else if (clkt->div > div)
			continue;

		if ((div - clkt->div) < (div - down))
			down = clkt->div;
	}

	return down;
}

static int _div_round_up(const struct clk_div_table *table,
			 unsigned long parent_rate, unsigned long rate,
			 unsigned long flags)
{
	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);

	if (flags & CLK_DIVIDER_POWER_OF_TWO)
		div = __roundup_pow_of_two(div);
	if (table)
		div = _round_up_table(table, div);

	return div;
}

static int _div_round_closest(const struct clk_div_table *table,
			      unsigned long parent_rate, unsigned long rate,
			      unsigned long flags)
{
	int up, down;
	unsigned long up_rate, down_rate;

	up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
	down = parent_rate / rate;

	if (flags & CLK_DIVIDER_POWER_OF_TWO) {
		up = __roundup_pow_of_two(up);
		down = __rounddown_pow_of_two(down);
	} else if (table) {
		up = _round_up_table(table, up);
		down = _round_down_table(table, down);
	}

	up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
	down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);

	return (rate - up_rate) <= (down_rate - rate) ? up : down;
}

static int _div_round(const struct clk_div_table *table,
		      unsigned long parent_rate, unsigned long rate,
		      unsigned long flags)
{
	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
		return _div_round_closest(table, parent_rate, rate, flags);

	return _div_round_up(table, parent_rate, rate, flags);
}

static bool _is_best_div(unsigned long rate, unsigned long now,
			 unsigned long best, unsigned long flags)
{
	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
		return abs(rate - now) < abs(rate - best);

	return now <= rate && now > best;
}

static int _next_div(const struct clk_div_table *table, int div,
		     unsigned long flags)
{
	div++;

	if (flags & CLK_DIVIDER_POWER_OF_TWO)
		return __roundup_pow_of_two(div);
	if (table)
		return _round_up_table(table, div);

	return div;
}

static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
			       unsigned long rate,
			       unsigned long *best_parent_rate,
			       const struct clk_div_table *table, u8 width,
			       unsigned long flags)
{
	int i, bestdiv = 0;
	unsigned long parent_rate, best = 0, now, maxdiv;
	unsigned long parent_rate_saved = *best_parent_rate;

	if (!rate)
		rate = 1;

	maxdiv = _get_maxdiv(table, width, flags);

	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
		parent_rate = *best_parent_rate;
		bestdiv = _div_round(table, parent_rate, rate, flags);
		bestdiv = bestdiv == 0 ? 1 : bestdiv;
		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
		return bestdiv;
	}

	/*
	 * The maximum divider we can use without overflowing
	 * unsigned long in rate * i below
	 */
	maxdiv = min(ULONG_MAX / rate, maxdiv);

	for (i = _next_div(table, 0, flags); i <= maxdiv;
					     i = _next_div(table, i, flags)) {
		if (rate * i == parent_rate_saved) {
			/*
			 * It's the most ideal case if the requested rate can be
			 * divided from parent clock without needing to change
			 * parent rate, so return the divider immediately.
			 */
			*best_parent_rate = parent_rate_saved;
			return i;
		}
		parent_rate = clk_hw_round_rate(parent, rate * i);
		now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
		if (_is_best_div(rate, now, best, flags)) {
			bestdiv = i;
			best = now;
			*best_parent_rate = parent_rate;
		}
	}

	if (!bestdiv) {
		bestdiv = _get_maxdiv(table, width, flags);
		*best_parent_rate = clk_hw_round_rate(parent, 1);
	}

	return bestdiv;
}

long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
			       unsigned long rate, unsigned long *prate,
			       const struct clk_div_table *table,
			       u8 width, unsigned long flags)
{
	int div;

	div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);

	return DIV_ROUND_UP_ULL((u64)*prate, div);
}
EXPORT_SYMBOL_GPL(divider_round_rate_parent);

static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	int bestdiv;

	/* if read only, just return current value */
	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
		bestdiv = clk_readl(divider->reg) >> divider->shift;
		bestdiv &= div_mask(divider->width);
		bestdiv = _get_div(divider->table, bestdiv, divider->flags,
			divider->width);
		return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
	}

	return divider_round_rate(hw, rate, prate, divider->table,
				  divider->width, divider->flags);
}

int divider_get_val(unsigned long rate, unsigned long parent_rate,
		    const struct clk_div_table *table, u8 width,
		    unsigned long flags)
{
	unsigned int div, value;

	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);

	if (!_is_valid_div(table, div, flags))
		return -EINVAL;

	value = _get_val(table, div, flags, width);

	return min_t(unsigned int, value, div_mask(width));
}
EXPORT_SYMBOL_GPL(divider_get_val);

static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	struct clk_divider *divider = to_clk_divider(hw);
	unsigned int value;
	unsigned long flags = 0;
	u32 val;

	value = divider_get_val(rate, parent_rate, divider->table,
				divider->width, divider->flags);

	if (divider->lock)
		spin_lock_irqsave(divider->lock, flags);
	else
		__acquire(divider->lock);

	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
		val = div_mask(divider->width) << (divider->shift + 16);
	} else {
		val = clk_readl(divider->reg);
		val &= ~(div_mask(divider->width) << divider->shift);
	}
	val |= value << divider->shift;
	clk_writel(val, divider->reg);

	if (divider->lock)
		spin_unlock_irqrestore(divider->lock, flags);
	else
		__release(divider->lock);

	return 0;
}

const struct clk_ops clk_divider_ops = {
	.recalc_rate = clk_divider_recalc_rate,
	.round_rate = clk_divider_round_rate,
	.set_rate = clk_divider_set_rate,
};
EXPORT_SYMBOL_GPL(clk_divider_ops);

const struct clk_ops clk_divider_ro_ops = {
	.recalc_rate = clk_divider_recalc_rate,
	.round_rate = clk_divider_round_rate,
};
EXPORT_SYMBOL_GPL(clk_divider_ro_ops);

static struct clk_hw *_register_divider(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock)
{
	struct clk_divider *div;
	struct clk_hw *hw;
	struct clk_init_data init;
	int ret;

	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
		if (width + shift > 16) {
			pr_warn("divider value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the divider */
	div = kzalloc(sizeof(*div), GFP_KERNEL);
	if (!div)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
		init.ops = &clk_divider_ro_ops;
	else
		init.ops = &clk_divider_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = (parent_name ? &parent_name: NULL);
	init.num_parents = (parent_name ? 1 : 0);

	/* struct clk_divider assignments */
	div->reg = reg;
	div->shift = shift;
	div->width = width;
	div->flags = clk_divider_flags;
	div->lock = lock;
	div->hw.init = &init;
	div->table = table;

	/* register the clock */
	hw = &div->hw;
	ret = clk_hw_register(dev, hw);
	if (ret) {
		kfree(div);
		hw = ERR_PTR(ret);
	}

	return hw;
}

/**
 * clk_register_divider - register a divider clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
struct clk *clk_register_divider(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, spinlock_t *lock)
{
	struct clk_hw *hw;

	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,
			width, clk_divider_flags, NULL, lock);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}
EXPORT_SYMBOL_GPL(clk_register_divider);

/**
 * clk_hw_register_divider - register a divider clock with the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @lock: shared register lock for this clock
 */
struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, spinlock_t *lock)
{
	return _register_divider(dev, name, parent_name, flags, reg, shift,
			width, clk_divider_flags, NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_hw_register_divider);

/**
 * clk_register_divider_table - register a table based divider clock with
 * the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
struct clk *clk_register_divider_table(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock)
{
	struct clk_hw *hw;

	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,
			width, clk_divider_flags, table, lock);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}
EXPORT_SYMBOL_GPL(clk_register_divider_table);

/**
 * clk_hw_register_divider_table - register a table based divider clock with
 * the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
struct clk_hw *clk_hw_register_divider_table(struct device *dev,
		const char *name, const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock)
{
	return _register_divider(dev, name, parent_name, flags, reg, shift,
			width, clk_divider_flags, table, lock);
}
EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);

void clk_unregister_divider(struct clk *clk)
{
	struct clk_divider *div;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	div = to_clk_divider(hw);

	clk_unregister(clk);
	kfree(div);
}
EXPORT_SYMBOL_GPL(clk_unregister_divider);

/**
 * clk_hw_unregister_divider - unregister a clk divider
 * @hw: hardware-specific clock data to unregister
 */
void clk_hw_unregister_divider(struct clk_hw *hw)
{
	struct clk_divider *div;

	div = to_clk_divider(hw);

	clk_hw_unregister(hw);
	kfree(div);
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_divider);
Commit	Line	Data
9d9f78ed MT	1	/*
	2	* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	3	* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
	4	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Adjustable divider clock implementation
	11	*/
	12
	13	#include <linux/clk-provider.h>
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18	#include <linux/string.h>
1a3cd184	19	#include <linux/log2.h>
9d9f78ed MT	20
	21	/*
	22	* DOC: basic adjustable divider clock that cannot gate
	23	*
	24	* Traits of this clock:
	25	* prepare - clk_prepare only ensures that parents are prepared
	26	* enable - clk_enable only ensures that parents are enabled
9556f9da	27	* rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
9d9f78ed MT	28	* parent - fixed parent. No clk_set_parent support
	29	*/
	30
bca9690b	31	#define div_mask(width) ((1 << (width)) - 1)
6d9252bd	32
fab88ca7 SB	33	static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
fab88ca7 SB	34	u8 width)
357c3f0a	35	{
fab88ca7	36	unsigned int maxdiv = 0, mask = div_mask(width);
357c3f0a RN	37	const struct clk_div_table *clkt;
	38
	39	for (clkt = table; clkt->div; clkt++)
fab88ca7	40	if (clkt->div > maxdiv && clkt->val <= mask)
357c3f0a RN	41	maxdiv = clkt->div;
	42	return maxdiv;
	43	}
	44
774b5143 MC	45	static unsigned int _get_table_mindiv(const struct clk_div_table *table)
	46	{
	47	unsigned int mindiv = UINT_MAX;
	48	const struct clk_div_table *clkt;
	49
	50	for (clkt = table; clkt->div; clkt++)
	51	if (clkt->div < mindiv)
	52	mindiv = clkt->div;
	53	return mindiv;
	54	}
	55
bca9690b SB	56	static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
bca9690b SB	57	unsigned long flags)
6d9252bd	58	{
bca9690b SB	59	if (flags & CLK_DIVIDER_ONE_BASED)
	60	return div_mask(width);
	61	if (flags & CLK_DIVIDER_POWER_OF_TWO)
	62	return 1 << div_mask(width);
	63	if (table)
fab88ca7	64	return _get_table_maxdiv(table, width);
bca9690b	65	return div_mask(width) + 1;
6d9252bd RN	66	}
6d9252bd RN	67
357c3f0a RN	68	static unsigned int _get_table_div(const struct clk_div_table *table,
	69	unsigned int val)
	70	{
	71	const struct clk_div_table *clkt;
	72
	73	for (clkt = table; clkt->div; clkt++)
	74	if (clkt->val == val)
	75	return clkt->div;
	76	return 0;
	77	}
	78
bca9690b	79	static unsigned int _get_div(const struct clk_div_table *table,
afe76c8f	80	unsigned int val, unsigned long flags, u8 width)
6d9252bd	81	{
bca9690b	82	if (flags & CLK_DIVIDER_ONE_BASED)
6d9252bd	83	return val;
bca9690b	84	if (flags & CLK_DIVIDER_POWER_OF_TWO)
6d9252bd	85	return 1 << val;
afe76c8f JQ	86	if (flags & CLK_DIVIDER_MAX_AT_ZERO)
afe76c8f JQ	87	return val ? val : div_mask(width) + 1;
bca9690b SB	88	if (table)
bca9690b SB	89	return _get_table_div(table, val);
6d9252bd RN	90	return val + 1;
	91	}
	92
357c3f0a RN	93	static unsigned int _get_table_val(const struct clk_div_table *table,
	94	unsigned int div)
	95	{
	96	const struct clk_div_table *clkt;
	97
	98	for (clkt = table; clkt->div; clkt++)
	99	if (clkt->div == div)
	100	return clkt->val;
	101	return 0;
	102	}
	103
bca9690b	104	static unsigned int _get_val(const struct clk_div_table *table,
afe76c8f	105	unsigned int div, unsigned long flags, u8 width)
6d9252bd	106	{
bca9690b	107	if (flags & CLK_DIVIDER_ONE_BASED)
6d9252bd	108	return div;
bca9690b	109	if (flags & CLK_DIVIDER_POWER_OF_TWO)
6d9252bd	110	return __ffs(div);
afe76c8f JQ	111	if (flags & CLK_DIVIDER_MAX_AT_ZERO)
afe76c8f JQ	112	return (div == div_mask(width) + 1) ? 0 : div;
bca9690b SB	113	if (table)
bca9690b SB	114	return _get_table_val(table, div);
6d9252bd RN	115	return div - 1;
6d9252bd RN	116	}
9d9f78ed	117
bca9690b SB	118	unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
	119	unsigned int val,
	120	const struct clk_div_table *table,
	121	unsigned long flags)
9d9f78ed	122	{
afe76c8f	123	struct clk_divider *divider = to_clk_divider(hw);
bca9690b	124	unsigned int div;
9d9f78ed	125
afe76c8f	126	div = _get_div(table, val, flags, divider->width);
6d9252bd	127	if (!div) {
bca9690b	128	WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
056b2053	129	"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
2f508a95	130	clk_hw_get_name(hw));
6d9252bd RN	131	return parent_rate;
6d9252bd RN	132	}
9d9f78ed	133
9556f9da	134	return DIV_ROUND_UP_ULL((u64)parent_rate, div);
9d9f78ed	135	}
bca9690b SB	136	EXPORT_SYMBOL_GPL(divider_recalc_rate);
	137
	138	static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
	139	unsigned long parent_rate)
	140	{
	141	struct clk_divider *divider = to_clk_divider(hw);
	142	unsigned int val;
	143
	144	val = clk_readl(divider->reg) >> divider->shift;
	145	val &= div_mask(divider->width);
	146
	147	return divider_recalc_rate(hw, parent_rate, val, divider->table,
	148	divider->flags);
	149	}
9d9f78ed	150
357c3f0a RN	151	static bool _is_valid_table_div(const struct clk_div_table *table,
	152	unsigned int div)
	153	{
	154	const struct clk_div_table *clkt;
	155
	156	for (clkt = table; clkt->div; clkt++)
	157	if (clkt->div == div)
	158	return true;
	159	return false;
	160	}
	161
bca9690b SB	162	static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
bca9690b SB	163	unsigned long flags)
357c3f0a	164	{
bca9690b	165	if (flags & CLK_DIVIDER_POWER_OF_TWO)
1a3cd184	166	return is_power_of_2(div);
bca9690b SB	167	if (table)
bca9690b SB	168	return _is_valid_table_div(table, div);
357c3f0a RN	169	return true;
	170	}
	171
dd23c2cd MC	172	static int _round_up_table(const struct clk_div_table *table, int div)
	173	{
	174	const struct clk_div_table *clkt;
fe52e750	175	int up = INT_MAX;
dd23c2cd MC	176
	177	for (clkt = table; clkt->div; clkt++) {
	178	if (clkt->div == div)
	179	return clkt->div;
	180	else if (clkt->div < div)
	181	continue;
	182
	183	if ((clkt->div - div) < (up - div))
	184	up = clkt->div;
	185	}
	186
	187	return up;
	188	}
	189
774b5143 MC	190	static int _round_down_table(const struct clk_div_table *table, int div)
	191	{
	192	const struct clk_div_table *clkt;
	193	int down = _get_table_mindiv(table);
	194
	195	for (clkt = table; clkt->div; clkt++) {
	196	if (clkt->div == div)
	197	return clkt->div;
	198	else if (clkt->div > div)
	199	continue;
	200
	201	if ((div - clkt->div) < (div - down))
	202	down = clkt->div;
	203	}
	204
	205	return down;
	206	}
	207
bca9690b SB	208	static int _div_round_up(const struct clk_div_table *table,
	209	unsigned long parent_rate, unsigned long rate,
	210	unsigned long flags)
dd23c2cd	211	{
9556f9da	212	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
dd23c2cd	213
bca9690b	214	if (flags & CLK_DIVIDER_POWER_OF_TWO)
dd23c2cd	215	div = __roundup_pow_of_two(div);
bca9690b SB	216	if (table)
bca9690b SB	217	div = _round_up_table(table, div);
dd23c2cd MC	218
	219	return div;
	220	}
	221
bca9690b SB	222	static int _div_round_closest(const struct clk_div_table *table,
	223	unsigned long parent_rate, unsigned long rate,
	224	unsigned long flags)
774b5143	225	{
93155142	226	int up, down;
26bac95a	227	unsigned long up_rate, down_rate;
774b5143	228
9556f9da	229	up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
93155142	230	down = parent_rate / rate;
774b5143	231
bca9690b	232	if (flags & CLK_DIVIDER_POWER_OF_TWO) {
93155142 UKK	233	up = __roundup_pow_of_two(up);
93155142 UKK	234	down = __rounddown_pow_of_two(down);
bca9690b	235	} else if (table) {
93155142 UKK	236	up = _round_up_table(table, up);
93155142 UKK	237	down = _round_down_table(table, down);
774b5143 MC	238	}
774b5143 MC	239
9556f9da BN	240	up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
9556f9da BN	241	down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
26bac95a UKK	242
26bac95a UKK	243	return (rate - up_rate) <= (down_rate - rate) ? up : down;
774b5143 MC	244	}
774b5143 MC	245
bca9690b SB	246	static int _div_round(const struct clk_div_table *table,
	247	unsigned long parent_rate, unsigned long rate,
	248	unsigned long flags)
774b5143	249	{
bca9690b SB	250	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
bca9690b SB	251	return _div_round_closest(table, parent_rate, rate, flags);
774b5143	252
bca9690b	253	return _div_round_up(table, parent_rate, rate, flags);
774b5143 MC	254	}
774b5143 MC	255
bca9690b SB	256	static bool _is_best_div(unsigned long rate, unsigned long now,
bca9690b SB	257	unsigned long best, unsigned long flags)
774b5143	258	{
bca9690b	259	if (flags & CLK_DIVIDER_ROUND_CLOSEST)
774b5143 MC	260	return abs(rate - now) < abs(rate - best);
	261
	262	return now <= rate && now > best;
	263	}
	264
bca9690b SB	265	static int _next_div(const struct clk_div_table *table, int div,
bca9690b SB	266	unsigned long flags)
0e2de78e MC	267	{
	268	div++;
	269
bca9690b	270	if (flags & CLK_DIVIDER_POWER_OF_TWO)
0e2de78e	271	return __roundup_pow_of_two(div);
bca9690b SB	272	if (table)
bca9690b SB	273	return _round_up_table(table, div);
0e2de78e MC	274
	275	return div;
	276	}
	277
22833a91 MR	278	static int clk_divider_bestdiv(struct clk_hw hw, struct clk_hw parent,
22833a91 MR	279	unsigned long rate,
bca9690b SB	280	unsigned long *best_parent_rate,
	281	const struct clk_div_table *table, u8 width,
	282	unsigned long flags)
9d9f78ed	283	{
9d9f78ed MT	284	int i, bestdiv = 0;
9d9f78ed MT	285	unsigned long parent_rate, best = 0, now, maxdiv;
081c9025	286	unsigned long parent_rate_saved = *best_parent_rate;
9d9f78ed MT	287
	288	if (!rate)
	289	rate = 1;
	290
bca9690b	291	maxdiv = _get_maxdiv(table, width, flags);
9d9f78ed	292
98d8a60e	293	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
81536e07	294	parent_rate = *best_parent_rate;
bca9690b	295	bestdiv = _div_round(table, parent_rate, rate, flags);
9d9f78ed MT	296	bestdiv = bestdiv == 0 ? 1 : bestdiv;
	297	bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
	298	return bestdiv;
	299	}
	300
	301	/*
	302	* The maximum divider we can use without overflowing
	303	* unsigned long in rate * i below
	304	*/
	305	maxdiv = min(ULONG_MAX / rate, maxdiv);
	306
653d1452 MY	307	for (i = _next_div(table, 0, flags); i <= maxdiv;
653d1452 MY	308	i = _next_div(table, i, flags)) {
081c9025 SG	309	if (rate * i == parent_rate_saved) {
	310	/*
	311	* It's the most ideal case if the requested rate can be
	312	* divided from parent clock without needing to change
	313	* parent rate, so return the divider immediately.
	314	*/
	315	*best_parent_rate = parent_rate_saved;
	316	return i;
	317	}
22833a91	318	parent_rate = clk_hw_round_rate(parent, rate * i);
9556f9da	319	now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
bca9690b	320	if (_is_best_div(rate, now, best, flags)) {
9d9f78ed MT	321	bestdiv = i;
	322	best = now;
	323	*best_parent_rate = parent_rate;
	324	}
	325	}
	326
	327	if (!bestdiv) {
bca9690b	328	bestdiv = _get_maxdiv(table, width, flags);
22833a91	329	*best_parent_rate = clk_hw_round_rate(parent, 1);
9d9f78ed MT	330	}
	331
	332	return bestdiv;
	333	}
	334
22833a91 MR	335	long divider_round_rate_parent(struct clk_hw hw, struct clk_hw parent,
	336	unsigned long rate, unsigned long *prate,
	337	const struct clk_div_table *table,
	338	u8 width, unsigned long flags)
9d9f78ed MT	339	{
9d9f78ed MT	340	int div;
bca9690b	341
22833a91	342	div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);
9d9f78ed	343
9556f9da	344	return DIV_ROUND_UP_ULL((u64)*prate, div);
9d9f78ed	345	}
22833a91	346	EXPORT_SYMBOL_GPL(divider_round_rate_parent);
9d9f78ed	347
bca9690b SB	348	static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
bca9690b SB	349	unsigned long *prate)
9d9f78ed MT	350	{
9d9f78ed MT	351	struct clk_divider *divider = to_clk_divider(hw);
bca9690b SB	352	int bestdiv;
	353
	354	/* if read only, just return current value */
	355	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
2cf9a578	356	bestdiv = clk_readl(divider->reg) >> divider->shift;
bca9690b	357	bestdiv &= div_mask(divider->width);
afe76c8f JQ	358	bestdiv = _get_div(divider->table, bestdiv, divider->flags,
afe76c8f JQ	359	divider->width);
9556f9da	360	return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
bca9690b SB	361	}
	362
	363	return divider_round_rate(hw, rate, prate, divider->table,
	364	divider->width, divider->flags);
	365	}
	366
	367	int divider_get_val(unsigned long rate, unsigned long parent_rate,
	368	const struct clk_div_table *table, u8 width,
	369	unsigned long flags)
	370	{
6d9252bd	371	unsigned int div, value;
9d9f78ed	372
9556f9da	373	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
dd23c2cd	374
bca9690b	375	if (!_is_valid_div(table, div, flags))
dd23c2cd MC	376	return -EINVAL;
dd23c2cd MC	377
afe76c8f	378	value = _get_val(table, div, flags, width);
bca9690b SB	379
	380	return min_t(unsigned int, value, div_mask(width));
	381	}
	382	EXPORT_SYMBOL_GPL(divider_get_val);
	383
	384	static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
	385	unsigned long parent_rate)
	386	{
	387	struct clk_divider *divider = to_clk_divider(hw);
	388	unsigned int value;
	389	unsigned long flags = 0;
	390	u32 val;
9d9f78ed	391
bca9690b SB	392	value = divider_get_val(rate, parent_rate, divider->table,
bca9690b SB	393	divider->width, divider->flags);
9d9f78ed MT	394
	395	if (divider->lock)
	396	spin_lock_irqsave(divider->lock, flags);
661e2180 SB	397	else
661e2180 SB	398	__acquire(divider->lock);
9d9f78ed	399
d57dfe75	400	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
bca9690b	401	val = div_mask(divider->width) << (divider->shift + 16);
d57dfe75	402	} else {
aa514ce3	403	val = clk_readl(divider->reg);
bca9690b	404	val &= ~(div_mask(divider->width) << divider->shift);
d57dfe75	405	}
6d9252bd	406	val \|= value << divider->shift;
aa514ce3	407	clk_writel(val, divider->reg);
9d9f78ed MT	408
	409	if (divider->lock)
	410	spin_unlock_irqrestore(divider->lock, flags);
661e2180 SB	411	else
661e2180 SB	412	__release(divider->lock);
9d9f78ed MT	413
	414	return 0;
	415	}
9d9f78ed	416
822c250e	417	const struct clk_ops clk_divider_ops = {
9d9f78ed MT	418	.recalc_rate = clk_divider_recalc_rate,
	419	.round_rate = clk_divider_round_rate,
	420	.set_rate = clk_divider_set_rate,
	421	};
	422	EXPORT_SYMBOL_GPL(clk_divider_ops);
	423
50359819 HS	424	const struct clk_ops clk_divider_ro_ops = {
	425	.recalc_rate = clk_divider_recalc_rate,
	426	.round_rate = clk_divider_round_rate,
	427	};
	428	EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
	429
eb7d264f	430	static struct clk_hw _register_divider(struct device dev, const char *name,
9d9f78ed MT	431	const char *parent_name, unsigned long flags,
9d9f78ed MT	432	void __iomem *reg, u8 shift, u8 width,
357c3f0a RN	433	u8 clk_divider_flags, const struct clk_div_table *table,
357c3f0a RN	434	spinlock_t *lock)
9d9f78ed MT	435	{
9d9f78ed MT	436	struct clk_divider *div;
eb7d264f	437	struct clk_hw *hw;
0197b3ea	438	struct clk_init_data init;
eb7d264f	439	int ret;
9d9f78ed	440
d57dfe75 HZ	441	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
	442	if (width + shift > 16) {
	443	pr_warn("divider value exceeds LOWORD field\n");
	444	return ERR_PTR(-EINVAL);
	445	}
	446	}
	447
27d54591	448	/* allocate the divider */
d122db7e SB	449	div = kzalloc(sizeof(*div), GFP_KERNEL);
d122db7e SB	450	if (!div)
27d54591	451	return ERR_PTR(-ENOMEM);
9d9f78ed	452
0197b3ea	453	init.name = name;
50359819 HS	454	if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
	455	init.ops = &clk_divider_ro_ops;
	456	else
	457	init.ops = &clk_divider_ops;
f7d8caad	458	init.flags = flags \| CLK_IS_BASIC;
0197b3ea SK	459	init.parent_names = (parent_name ? &parent_name: NULL);
	460	init.num_parents = (parent_name ? 1 : 0);
	461
9d9f78ed MT	462	/* struct clk_divider assignments */
	463	div->reg = reg;
	464	div->shift = shift;
	465	div->width = width;
	466	div->flags = clk_divider_flags;
	467	div->lock = lock;
0197b3ea	468	div->hw.init = &init;
357c3f0a	469	div->table = table;
9d9f78ed	470
27d54591	471	/* register the clock */
eb7d264f SB	472	hw = &div->hw;
	473	ret = clk_hw_register(dev, hw);
	474	if (ret) {
27d54591	475	kfree(div);
eb7d264f SB	476	hw = ERR_PTR(ret);
eb7d264f SB	477	}
9d9f78ed	478
eb7d264f	479	return hw;
9d9f78ed	480	}
357c3f0a RN	481
	482	/**
	483	* clk_register_divider - register a divider clock with the clock framework
	484	* @dev: device registering this clock
	485	* @name: name of this clock
	486	* @parent_name: name of clock's parent
	487	* @flags: framework-specific flags
	488	* @reg: register address to adjust divider
	489	* @shift: number of bits to shift the bitfield
	490	* @width: width of the bitfield
	491	* @clk_divider_flags: divider-specific flags for this clock
	492	* @lock: shared register lock for this clock
	493	*/
	494	struct clk clk_register_divider(struct device dev, const char *name,
	495	const char *parent_name, unsigned long flags,
	496	void __iomem *reg, u8 shift, u8 width,
	497	u8 clk_divider_flags, spinlock_t *lock)
	498	{
eb7d264f SB	499	struct clk_hw *hw;
	500
	501	hw = _register_divider(dev, name, parent_name, flags, reg, shift,
357c3f0a	502	width, clk_divider_flags, NULL, lock);
eb7d264f SB	503	if (IS_ERR(hw))
	504	return ERR_CAST(hw);
	505	return hw->clk;
357c3f0a	506	}
4c5eeea9	507	EXPORT_SYMBOL_GPL(clk_register_divider);
357c3f0a	508
eb7d264f SB	509	/**
	510	* clk_hw_register_divider - register a divider clock with the clock framework
	511	* @dev: device registering this clock
	512	* @name: name of this clock
	513	* @parent_name: name of clock's parent
	514	* @flags: framework-specific flags
	515	* @reg: register address to adjust divider
	516	* @shift: number of bits to shift the bitfield
	517	* @width: width of the bitfield
	518	* @clk_divider_flags: divider-specific flags for this clock
	519	* @lock: shared register lock for this clock
	520	*/
	521	struct clk_hw clk_hw_register_divider(struct device dev, const char *name,
	522	const char *parent_name, unsigned long flags,
	523	void __iomem *reg, u8 shift, u8 width,
	524	u8 clk_divider_flags, spinlock_t *lock)
	525	{
	526	return _register_divider(dev, name, parent_name, flags, reg, shift,
	527	width, clk_divider_flags, NULL, lock);
	528	}
	529	EXPORT_SYMBOL_GPL(clk_hw_register_divider);
	530
357c3f0a RN	531	/**
	532	* clk_register_divider_table - register a table based divider clock with
	533	* the clock framework
	534	* @dev: device registering this clock
	535	* @name: name of this clock
	536	* @parent_name: name of clock's parent
	537	* @flags: framework-specific flags
	538	* @reg: register address to adjust divider
	539	* @shift: number of bits to shift the bitfield
	540	* @width: width of the bitfield
	541	* @clk_divider_flags: divider-specific flags for this clock
	542	* @table: array of divider/value pairs ending with a div set to 0
	543	* @lock: shared register lock for this clock
	544	*/
	545	struct clk clk_register_divider_table(struct device dev, const char *name,
	546	const char *parent_name, unsigned long flags,
	547	void __iomem *reg, u8 shift, u8 width,
	548	u8 clk_divider_flags, const struct clk_div_table *table,
	549	spinlock_t *lock)
	550	{
eb7d264f SB	551	struct clk_hw *hw;
	552
	553	hw = _register_divider(dev, name, parent_name, flags, reg, shift,
357c3f0a	554	width, clk_divider_flags, table, lock);
eb7d264f SB	555	if (IS_ERR(hw))
	556	return ERR_CAST(hw);
	557	return hw->clk;
357c3f0a	558	}
4c5eeea9	559	EXPORT_SYMBOL_GPL(clk_register_divider_table);
4e3c021f	560
eb7d264f SB	561	/**
	562	* clk_hw_register_divider_table - register a table based divider clock with
	563	* the clock framework
	564	* @dev: device registering this clock
	565	* @name: name of this clock
	566	* @parent_name: name of clock's parent
	567	* @flags: framework-specific flags
	568	* @reg: register address to adjust divider
	569	* @shift: number of bits to shift the bitfield
	570	* @width: width of the bitfield
	571	* @clk_divider_flags: divider-specific flags for this clock
	572	* @table: array of divider/value pairs ending with a div set to 0
	573	* @lock: shared register lock for this clock
	574	*/
	575	struct clk_hw clk_hw_register_divider_table(struct device dev,
	576	const char name, const char parent_name, unsigned long flags,
	577	void __iomem *reg, u8 shift, u8 width,
	578	u8 clk_divider_flags, const struct clk_div_table *table,
	579	spinlock_t *lock)
	580	{
	581	return _register_divider(dev, name, parent_name, flags, reg, shift,
	582	width, clk_divider_flags, table, lock);
	583	}
	584	EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);
	585
4e3c021f KK	586	void clk_unregister_divider(struct clk *clk)
	587	{
	588	struct clk_divider *div;
	589	struct clk_hw *hw;
	590
	591	hw = __clk_get_hw(clk);
	592	if (!hw)
	593	return;
	594
	595	div = to_clk_divider(hw);
	596
	597	clk_unregister(clk);
	598	kfree(div);
	599	}
	600	EXPORT_SYMBOL_GPL(clk_unregister_divider);
eb7d264f SB	601
	602	/**
	603	* clk_hw_unregister_divider - unregister a clk divider
	604	* @hw: hardware-specific clock data to unregister
	605	*/
	606	void clk_hw_unregister_divider(struct clk_hw *hw)
	607	{
	608	struct clk_divider *div;
	609
	610	div = to_clk_divider(hw);
	611
	612	clk_hw_unregister(hw);
	613	kfree(div);
	614	}
	615	EXPORT_SYMBOL_GPL(clk_hw_unregister_divider);