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clk: remove unnecessary EXPORT_SYMBOL_GPL
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1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adjustable divider clock implementation
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <linux/string.h>
19
20/*
21 * DOC: basic adjustable divider clock that cannot gate
22 *
23 * Traits of this clock:
24 * prepare - clk_prepare only ensures that parents are prepared
25 * enable - clk_enable only ensures that parents are enabled
26 * rate - rate is adjustable. clk->rate = parent->rate / divisor
27 * parent - fixed parent. No clk_set_parent support
28 */
29
30#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
31
32#define div_mask(d) ((1 << (d->width)) - 1)
33
34static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate)
36{
37 struct clk_divider *divider = to_clk_divider(hw);
38 unsigned int div;
39
40 div = readl(divider->reg) >> divider->shift;
41 div &= div_mask(divider);
42
43 if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
44 div++;
45
46 return parent_rate / div;
47}
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48
49/*
50 * The reverse of DIV_ROUND_UP: The maximum number which
51 * divided by m is r
52 */
53#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
54
55static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
56 unsigned long *best_parent_rate)
57{
58 struct clk_divider *divider = to_clk_divider(hw);
59 int i, bestdiv = 0;
60 unsigned long parent_rate, best = 0, now, maxdiv;
61
62 if (!rate)
63 rate = 1;
64
65 maxdiv = (1 << divider->width);
66
67 if (divider->flags & CLK_DIVIDER_ONE_BASED)
68 maxdiv--;
69
70 if (!best_parent_rate) {
71 parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
72 bestdiv = DIV_ROUND_UP(parent_rate, rate);
73 bestdiv = bestdiv == 0 ? 1 : bestdiv;
74 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
75 return bestdiv;
76 }
77
78 /*
79 * The maximum divider we can use without overflowing
80 * unsigned long in rate * i below
81 */
82 maxdiv = min(ULONG_MAX / rate, maxdiv);
83
84 for (i = 1; i <= maxdiv; i++) {
85 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
86 MULT_ROUND_UP(rate, i));
87 now = parent_rate / i;
88 if (now <= rate && now > best) {
89 bestdiv = i;
90 best = now;
91 *best_parent_rate = parent_rate;
92 }
93 }
94
95 if (!bestdiv) {
96 bestdiv = (1 << divider->width);
97 if (divider->flags & CLK_DIVIDER_ONE_BASED)
98 bestdiv--;
99 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
100 }
101
102 return bestdiv;
103}
104
105static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long *prate)
107{
108 int div;
109 div = clk_divider_bestdiv(hw, rate, prate);
110
111 if (prate)
112 return *prate / div;
113 else {
114 unsigned long r;
115 r = __clk_get_rate(__clk_get_parent(hw->clk));
116 return r / div;
117 }
118}
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119
120static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
121{
122 struct clk_divider *divider = to_clk_divider(hw);
123 unsigned int div;
124 unsigned long flags = 0;
125 u32 val;
126
127 div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;
128
129 if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
130 div--;
131
132 if (div > div_mask(divider))
133 div = div_mask(divider);
134
135 if (divider->lock)
136 spin_lock_irqsave(divider->lock, flags);
137
138 val = readl(divider->reg);
139 val &= ~(div_mask(divider) << divider->shift);
140 val |= div << divider->shift;
141 writel(val, divider->reg);
142
143 if (divider->lock)
144 spin_unlock_irqrestore(divider->lock, flags);
145
146 return 0;
147}
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148
149struct clk_ops clk_divider_ops = {
150 .recalc_rate = clk_divider_recalc_rate,
151 .round_rate = clk_divider_round_rate,
152 .set_rate = clk_divider_set_rate,
153};
154EXPORT_SYMBOL_GPL(clk_divider_ops);
155
156struct clk *clk_register_divider(struct device *dev, const char *name,
157 const char *parent_name, unsigned long flags,
158 void __iomem *reg, u8 shift, u8 width,
159 u8 clk_divider_flags, spinlock_t *lock)
160{
161 struct clk_divider *div;
162 struct clk *clk;
163
164 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
165
166 if (!div) {
167 pr_err("%s: could not allocate divider clk\n", __func__);
168 return NULL;
169 }
170
171 /* struct clk_divider assignments */
172 div->reg = reg;
173 div->shift = shift;
174 div->width = width;
175 div->flags = clk_divider_flags;
176 div->lock = lock;
177
178 if (parent_name) {
179 div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
180 if (!div->parent[0])
181 goto out;
182 }
183
184 clk = clk_register(dev, name,
185 &clk_divider_ops, &div->hw,
186 div->parent,
187 (parent_name ? 1 : 0),
188 flags);
189 if (clk)
190 return clk;
191
192out:
193 kfree(div->parent[0]);
194 kfree(div);
195
196 return NULL;
197}