[mirror_ubuntu-jammy-kernel.git] / drivers / clk / clk-fractional-divider.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2014 Intel Corporation
 *
 * Adjustable fractional divider clock implementation.
 * Output rate = (m / n) * parent_rate.
 * Uses rational best approximation algorithm.
 */

#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/rational.h>

static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
{
	if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
		return ioread32be(fd->reg);

	return readl(fd->reg);
}

static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
{
	if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
		iowrite32be(val, fd->reg);
	else
		writel(val, fd->reg);
}

static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
					unsigned long parent_rate)
{
	struct clk_fractional_divider *fd = to_clk_fd(hw);
	unsigned long flags = 0;
	unsigned long m, n;
	u32 val;
	u64 ret;

	if (fd->lock)
		spin_lock_irqsave(fd->lock, flags);
	else
		__acquire(fd->lock);

	val = clk_fd_readl(fd);

	if (fd->lock)
		spin_unlock_irqrestore(fd->lock, flags);
	else
		__release(fd->lock);

	m = (val & fd->mmask) >> fd->mshift;
	n = (val & fd->nmask) >> fd->nshift;

	if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
		m++;
		n++;
	}

	if (!n || !m)
		return parent_rate;

	ret = (u64)parent_rate * m;
	do_div(ret, n);

	return ret;
}

static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
					 unsigned long *parent_rate,
					 unsigned long *m, unsigned long *n)
{
	struct clk_fractional_divider *fd = to_clk_fd(hw);
	unsigned long scale;

	/*
	 * Get rate closer to *parent_rate to guarantee there is no overflow
	 * for m and n. In the result it will be the nearest rate left shifted
	 * by (scale - fd->nwidth) bits.
	 */
	scale = fls_long(*parent_rate / rate - 1);
	if (scale > fd->nwidth)
		rate <<= scale - fd->nwidth;

	rational_best_approximation(rate, *parent_rate,
			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
			m, n);
}

static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long *parent_rate)
{
	struct clk_fractional_divider *fd = to_clk_fd(hw);
	unsigned long m, n;
	u64 ret;

	if (!rate || (!clk_hw_can_set_rate_parent(hw) && rate >= *parent_rate))
		return *parent_rate;

	if (fd->approximation)
		fd->approximation(hw, rate, parent_rate, &m, &n);
	else
		clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);

	ret = (u64)*parent_rate * m;
	do_div(ret, n);

	return ret;
}

static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
			   unsigned long parent_rate)
{
	struct clk_fractional_divider *fd = to_clk_fd(hw);
	unsigned long flags = 0;
	unsigned long m, n;
	u32 val;

	rational_best_approximation(rate, parent_rate,
			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
			&m, &n);

	if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
		m--;
		n--;
	}

	if (fd->lock)
		spin_lock_irqsave(fd->lock, flags);
	else
		__acquire(fd->lock);

	val = clk_fd_readl(fd);
	val &= ~(fd->mmask | fd->nmask);
	val |= (m << fd->mshift) | (n << fd->nshift);
	clk_fd_writel(fd, val);

	if (fd->lock)
		spin_unlock_irqrestore(fd->lock, flags);
	else
		__release(fd->lock);

	return 0;
}

const struct clk_ops clk_fractional_divider_ops = {
	.recalc_rate = clk_fd_recalc_rate,
	.round_rate = clk_fd_round_rate,
	.set_rate = clk_fd_set_rate,
};
EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);

struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
		const char *name, const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
		u8 clk_divider_flags, spinlock_t *lock)
{
	struct clk_fractional_divider *fd;
	struct clk_init_data init;
	struct clk_hw *hw;
	int ret;

	fd = kzalloc(sizeof(*fd), GFP_KERNEL);
	if (!fd)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &clk_fractional_divider_ops;
	init.flags = flags;
	init.parent_names = parent_name ? &parent_name : NULL;
	init.num_parents = parent_name ? 1 : 0;

	fd->reg = reg;
	fd->mshift = mshift;
	fd->mwidth = mwidth;
	fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
	fd->nshift = nshift;
	fd->nwidth = nwidth;
	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
	fd->flags = clk_divider_flags;
	fd->lock = lock;
	fd->hw.init = &init;

	hw = &fd->hw;
	ret = clk_hw_register(dev, hw);
	if (ret) {
		kfree(fd);
		hw = ERR_PTR(ret);
	}

	return hw;
}
EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider);

struct clk *clk_register_fractional_divider(struct device *dev,
		const char *name, const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
		u8 clk_divider_flags, spinlock_t *lock)
{
	struct clk_hw *hw;

	hw = clk_hw_register_fractional_divider(dev, name, parent_name, flags,
			reg, mshift, mwidth, nshift, nwidth, clk_divider_flags,
			lock);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}
EXPORT_SYMBOL_GPL(clk_register_fractional_divider);

void clk_hw_unregister_fractional_divider(struct clk_hw *hw)
{
	struct clk_fractional_divider *fd;

	fd = to_clk_fd(hw);

	clk_hw_unregister(hw);
	kfree(fd);
}
Commit	Line	Data
e1bd55e5	1	// SPDX-License-Identifier: GPL-2.0
e2d0e90f HK	2	/*
	3	* Copyright (C) 2014 Intel Corporation
	4	*
e2d0e90f HK	5	* Adjustable fractional divider clock implementation.
e2d0e90f HK	6	* Output rate = (m / n) * parent_rate.
0777591e	7	* Uses rational best approximation algorithm.
e2d0e90f HK	8	*/
	9
	10	#include <linux/clk-provider.h>
62e59c4e	11	#include <linux/io.h>
e2d0e90f HK	12	#include <linux/module.h>
	13	#include <linux/device.h>
	14	#include <linux/slab.h>
0777591e	15	#include <linux/rational.h>
e2d0e90f	16
58a2b4c9 JG	17	static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
	18	{
	19	if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
	20	return ioread32be(fd->reg);
	21
5834fd75	22	return readl(fd->reg);
58a2b4c9 JG	23	}
	24
	25	static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
	26	{
	27	if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
	28	iowrite32be(val, fd->reg);
	29	else
5834fd75	30	writel(val, fd->reg);
58a2b4c9 JG	31	}
58a2b4c9 JG	32
e2d0e90f HK	33	static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
	34	unsigned long parent_rate)
	35	{
	36	struct clk_fractional_divider *fd = to_clk_fd(hw);
	37	unsigned long flags = 0;
0777591e AS	38	unsigned long m, n;
0777591e AS	39	u32 val;
e2d0e90f HK	40	u64 ret;
	41
	42	if (fd->lock)
	43	spin_lock_irqsave(fd->lock, flags);
661e2180 SB	44	else
661e2180 SB	45	__acquire(fd->lock);
e2d0e90f	46
58a2b4c9	47	val = clk_fd_readl(fd);
e2d0e90f HK	48
	49	if (fd->lock)
	50	spin_unlock_irqrestore(fd->lock, flags);
661e2180 SB	51	else
661e2180 SB	52	__release(fd->lock);
e2d0e90f HK	53
	54	m = (val & fd->mmask) >> fd->mshift;
	55	n = (val & fd->nmask) >> fd->nshift;
	56
e983da27 D	57	if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
	58	m++;
	59	n++;
	60	}
	61
6b547836 HK	62	if (!n \|\| !m)
	63	return parent_rate;
	64
feaefa0e	65	ret = (u64)parent_rate * m;
e2d0e90f HK	66	do_div(ret, n);
	67
	68	return ret;
	69	}
	70
ec52e462 EZ	71	static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
	72	unsigned long *parent_rate,
	73	unsigned long m, unsigned long n)
e2d0e90f HK	74	{
e2d0e90f HK	75	struct clk_fractional_divider *fd = to_clk_fd(hw);
0777591e	76	unsigned long scale;
e2d0e90f	77
0777591e AS	78	/*
	79	* Get rate closer to *parent_rate to guarantee there is no overflow
	80	* for m and n. In the result it will be the nearest rate left shifted
	81	* by (scale - fd->nwidth) bits.
	82	*/
	83	scale = fls_long(*parent_rate / rate - 1);
	84	if (scale > fd->nwidth)
	85	rate <<= scale - fd->nwidth;
e2d0e90f	86
0777591e AS	87	rational_best_approximation(rate, *parent_rate,
0777591e AS	88	GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
ec52e462 EZ	89	m, n);
	90	}
	91
	92	static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
	93	unsigned long *parent_rate)
	94	{
	95	struct clk_fractional_divider *fd = to_clk_fd(hw);
	96	unsigned long m, n;
	97	u64 ret;
	98
d13501a2	99	if (!rate \|\| (!clk_hw_can_set_rate_parent(hw) && rate >= *parent_rate))
ec52e462 EZ	100	return *parent_rate;
	101
	102	if (fd->approximation)
	103	fd->approximation(hw, rate, parent_rate, &m, &n);
	104	else
	105	clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
e2d0e90f	106
0777591e AS	107	ret = (u64)parent_rate m;
	108	do_div(ret, n);
	109
	110	return ret;
e2d0e90f HK	111	}
	112
	113	static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
	114	unsigned long parent_rate)
	115	{
	116	struct clk_fractional_divider *fd = to_clk_fd(hw);
	117	unsigned long flags = 0;
0777591e	118	unsigned long m, n;
e2d0e90f HK	119	u32 val;
e2d0e90f HK	120
0777591e AS	121	rational_best_approximation(rate, parent_rate,
	122	GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
	123	&m, &n);
e2d0e90f	124
e983da27 D	125	if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
	126	m--;
	127	n--;
	128	}
	129
e2d0e90f HK	130	if (fd->lock)
e2d0e90f HK	131	spin_lock_irqsave(fd->lock, flags);
661e2180 SB	132	else
661e2180 SB	133	__acquire(fd->lock);
e2d0e90f	134
58a2b4c9	135	val = clk_fd_readl(fd);
e2d0e90f HK	136	val &= ~(fd->mmask \| fd->nmask);
e2d0e90f HK	137	val \|= (m << fd->mshift) \| (n << fd->nshift);
58a2b4c9	138	clk_fd_writel(fd, val);
e2d0e90f HK	139
	140	if (fd->lock)
	141	spin_unlock_irqrestore(fd->lock, flags);
661e2180 SB	142	else
661e2180 SB	143	__release(fd->lock);
e2d0e90f HK	144
	145	return 0;
	146	}
	147
	148	const struct clk_ops clk_fractional_divider_ops = {
	149	.recalc_rate = clk_fd_recalc_rate,
	150	.round_rate = clk_fd_round_rate,
	151	.set_rate = clk_fd_set_rate,
	152	};
	153	EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
	154
39b44cff	155	struct clk_hw clk_hw_register_fractional_divider(struct device dev,
e2d0e90f HK	156	const char name, const char parent_name, unsigned long flags,
	157	void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
	158	u8 clk_divider_flags, spinlock_t *lock)
	159	{
	160	struct clk_fractional_divider *fd;
	161	struct clk_init_data init;
39b44cff SB	162	struct clk_hw *hw;
39b44cff SB	163	int ret;
e2d0e90f HK	164
e2d0e90f HK	165	fd = kzalloc(sizeof(*fd), GFP_KERNEL);
d122db7e	166	if (!fd)
e2d0e90f	167	return ERR_PTR(-ENOMEM);
e2d0e90f HK	168
	169	init.name = name;
	170	init.ops = &clk_fractional_divider_ops;
90b6c5c7	171	init.flags = flags;
e2d0e90f HK	172	init.parent_names = parent_name ? &parent_name : NULL;
	173	init.num_parents = parent_name ? 1 : 0;
	174
	175	fd->reg = reg;
	176	fd->mshift = mshift;
934e2536 AS	177	fd->mwidth = mwidth;
934e2536 AS	178	fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
e2d0e90f	179	fd->nshift = nshift;
934e2536 AS	180	fd->nwidth = nwidth;
934e2536 AS	181	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
e2d0e90f HK	182	fd->flags = clk_divider_flags;
	183	fd->lock = lock;
	184	fd->hw.init = &init;
	185
39b44cff SB	186	hw = &fd->hw;
	187	ret = clk_hw_register(dev, hw);
	188	if (ret) {
e2d0e90f	189	kfree(fd);
39b44cff SB	190	hw = ERR_PTR(ret);
	191	}
	192
	193	return hw;
	194	}
	195	EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider);
e2d0e90f	196
39b44cff SB	197	struct clk clk_register_fractional_divider(struct device dev,
	198	const char name, const char parent_name, unsigned long flags,
	199	void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
	200	u8 clk_divider_flags, spinlock_t *lock)
	201	{
	202	struct clk_hw *hw;
	203
	204	hw = clk_hw_register_fractional_divider(dev, name, parent_name, flags,
	205	reg, mshift, mwidth, nshift, nwidth, clk_divider_flags,
	206	lock);
	207	if (IS_ERR(hw))
	208	return ERR_CAST(hw);
	209	return hw->clk;
e2d0e90f HK	210	}
e2d0e90f HK	211	EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
39b44cff SB	212
	213	void clk_hw_unregister_fractional_divider(struct clk_hw *hw)
	214	{
	215	struct clk_fractional_divider *fd;
	216
	217	fd = to_clk_fd(hw);
	218
	219	clk_hw_unregister(hw);
	220	kfree(fd);
	221	}