[mirror_ubuntu-jammy-kernel.git] / drivers / clk / clk-gate.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * Gated clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>

/**
 * DOC: basic gatable clock which can gate and ungate it's ouput
 *
 * Traits of this clock:
 * prepare - clk_(un)prepare only ensures parent is (un)prepared
 * enable - clk_enable and clk_disable are functional & control gating
 * rate - inherits rate from parent.  No clk_set_rate support
 * parent - fixed parent.  No clk_set_parent support
 */

static inline u32 clk_gate_readl(struct clk_gate *gate)
{
	if (gate->flags & CLK_GATE_BIG_ENDIAN)
		return ioread32be(gate->reg);

	return readl(gate->reg);
}

static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
{
	if (gate->flags & CLK_GATE_BIG_ENDIAN)
		iowrite32be(val, gate->reg);
	else
		writel(val, gate->reg);
}

/*
 * It works on following logic:
 *
 * For enabling clock, enable = 1
 *	set2dis = 1	-> clear bit	-> set = 0
 *	set2dis = 0	-> set bit	-> set = 1
 *
 * For disabling clock, enable = 0
 *	set2dis = 1	-> set bit	-> set = 1
 *	set2dis = 0	-> clear bit	-> set = 0
 *
 * So, result is always: enable xor set2dis.
 */
static void clk_gate_endisable(struct clk_hw *hw, int enable)
{
	struct clk_gate *gate = to_clk_gate(hw);
	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
	unsigned long flags;
	u32 reg;

	set ^= enable;

	if (gate->lock)
		spin_lock_irqsave(gate->lock, flags);
	else
		__acquire(gate->lock);

	if (gate->flags & CLK_GATE_HIWORD_MASK) {
		reg = BIT(gate->bit_idx + 16);
		if (set)
			reg |= BIT(gate->bit_idx);
	} else {
		reg = clk_gate_readl(gate);

		if (set)
			reg |= BIT(gate->bit_idx);
		else
			reg &= ~BIT(gate->bit_idx);
	}

	clk_gate_writel(gate, reg);

	if (gate->lock)
		spin_unlock_irqrestore(gate->lock, flags);
	else
		__release(gate->lock);
}

static int clk_gate_enable(struct clk_hw *hw)
{
	clk_gate_endisable(hw, 1);

	return 0;
}

static void clk_gate_disable(struct clk_hw *hw)
{
	clk_gate_endisable(hw, 0);
}

int clk_gate_is_enabled(struct clk_hw *hw)
{
	u32 reg;
	struct clk_gate *gate = to_clk_gate(hw);

	reg = clk_gate_readl(gate);

	/* if a set bit disables this clk, flip it before masking */
	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
		reg ^= BIT(gate->bit_idx);

	reg &= BIT(gate->bit_idx);

	return reg ? 1 : 0;
}
EXPORT_SYMBOL_GPL(clk_gate_is_enabled);

const struct clk_ops clk_gate_ops = {
	.enable = clk_gate_enable,
	.disable = clk_gate_disable,
	.is_enabled = clk_gate_is_enabled,
};
EXPORT_SYMBOL_GPL(clk_gate_ops);

struct clk_hw *__clk_hw_register_gate(struct device *dev,
		struct device_node *np, const char *name,
		const char *parent_name, const struct clk_hw *parent_hw,
		const struct clk_parent_data *parent_data,
		unsigned long flags,
		void __iomem *reg, u8 bit_idx,
		u8 clk_gate_flags, spinlock_t *lock)
{
	struct clk_gate *gate;
	struct clk_hw *hw;
	struct clk_init_data init = {};
	int ret = -EINVAL;

	if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
		if (bit_idx > 15) {
			pr_err("gate bit exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the gate */
	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	if (!gate)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &clk_gate_ops;
	init.flags = flags;
	init.parent_names = parent_name ? &parent_name : NULL;
	init.parent_hws = parent_hw ? &parent_hw : NULL;
	init.parent_data = parent_data;
	if (parent_name || parent_hw || parent_data)
		init.num_parents = 1;
	else
		init.num_parents = 0;

	/* struct clk_gate assignments */
	gate->reg = reg;
	gate->bit_idx = bit_idx;
	gate->flags = clk_gate_flags;
	gate->lock = lock;
	gate->hw.init = &init;

	hw = &gate->hw;
	if (dev || !np)
		ret = clk_hw_register(dev, hw);
	else if (np)
		ret = of_clk_hw_register(np, hw);
	if (ret) {
		kfree(gate);
		hw = ERR_PTR(ret);
	}

	return hw;

}
EXPORT_SYMBOL_GPL(__clk_hw_register_gate);

struct clk *clk_register_gate(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 bit_idx,
		u8 clk_gate_flags, spinlock_t *lock)
{
	struct clk_hw *hw;

	hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
				  bit_idx, clk_gate_flags, lock);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}
EXPORT_SYMBOL_GPL(clk_register_gate);

void clk_unregister_gate(struct clk *clk)
{
	struct clk_gate *gate;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	gate = to_clk_gate(hw);

	clk_unregister(clk);
	kfree(gate);
}
EXPORT_SYMBOL_GPL(clk_unregister_gate);

void clk_hw_unregister_gate(struct clk_hw *hw)
{
	struct clk_gate *gate;

	gate = to_clk_gate(hw);

	clk_hw_unregister(hw);
	kfree(gate);
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);
Commit	Line	Data
e1bd55e5	1	// SPDX-License-Identifier: GPL-2.0
9d9f78ed MT	2	/*
	3	* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
	4	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
	5	*
9d9f78ed MT	6	* Gated clock implementation
	7	*/
	8
	9	#include <linux/clk-provider.h>
	10	#include <linux/module.h>
	11	#include <linux/slab.h>
	12	#include <linux/io.h>
	13	#include <linux/err.h>
	14	#include <linux/string.h>
	15
	16	/**
	17	* DOC: basic gatable clock which can gate and ungate it's ouput
	18	*
	19	* Traits of this clock:
	20	* prepare - clk_(un)prepare only ensures parent is (un)prepared
	21	* enable - clk_enable and clk_disable are functional & control gating
	22	* rate - inherits rate from parent. No clk_set_rate support
	23	* parent - fixed parent. No clk_set_parent support
	24	*/
	25
d1c8a501 JG	26	static inline u32 clk_gate_readl(struct clk_gate *gate)
	27	{
	28	if (gate->flags & CLK_GATE_BIG_ENDIAN)
	29	return ioread32be(gate->reg);
	30
5834fd75	31	return readl(gate->reg);
d1c8a501 JG	32	}
	33
	34	static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
	35	{
	36	if (gate->flags & CLK_GATE_BIG_ENDIAN)
	37	iowrite32be(val, gate->reg);
	38	else
5834fd75	39	writel(val, gate->reg);
d1c8a501 JG	40	}
d1c8a501 JG	41
fbc42aab VK	42	/*
	43	* It works on following logic:
	44	*
	45	* For enabling clock, enable = 1
	46	* set2dis = 1 -> clear bit -> set = 0
	47	* set2dis = 0 -> set bit -> set = 1
	48	*
	49	* For disabling clock, enable = 0
	50	* set2dis = 1 -> set bit -> set = 1
	51	* set2dis = 0 -> clear bit -> set = 0
	52	*
	53	* So, result is always: enable xor set2dis.
	54	*/
	55	static void clk_gate_endisable(struct clk_hw *hw, int enable)
9d9f78ed	56	{
fbc42aab VK	57	struct clk_gate *gate = to_clk_gate(hw);
fbc42aab VK	58	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
3f649ab7	59	unsigned long flags;
fbc42aab VK	60	u32 reg;
	61
	62	set ^= enable;
9d9f78ed MT	63
	64	if (gate->lock)
	65	spin_lock_irqsave(gate->lock, flags);
661e2180 SB	66	else
661e2180 SB	67	__acquire(gate->lock);
9d9f78ed	68
04577994 HZ	69	if (gate->flags & CLK_GATE_HIWORD_MASK) {
	70	reg = BIT(gate->bit_idx + 16);
	71	if (set)
	72	reg \|= BIT(gate->bit_idx);
	73	} else {
d1c8a501	74	reg = clk_gate_readl(gate);
04577994 HZ	75
	76	if (set)
	77	reg \|= BIT(gate->bit_idx);
	78	else
	79	reg &= ~BIT(gate->bit_idx);
	80	}
9d9f78ed	81
d1c8a501	82	clk_gate_writel(gate, reg);
9d9f78ed MT	83
	84	if (gate->lock)
	85	spin_unlock_irqrestore(gate->lock, flags);
661e2180 SB	86	else
661e2180 SB	87	__release(gate->lock);
9d9f78ed MT	88	}
	89
	90	static int clk_gate_enable(struct clk_hw *hw)
	91	{
fbc42aab	92	clk_gate_endisable(hw, 1);
9d9f78ed MT	93
	94	return 0;
	95	}
9d9f78ed MT	96
	97	static void clk_gate_disable(struct clk_hw *hw)
	98	{
fbc42aab	99	clk_gate_endisable(hw, 0);
9d9f78ed	100	}
9d9f78ed	101
0a9c869d	102	int clk_gate_is_enabled(struct clk_hw *hw)
9d9f78ed MT	103	{
	104	u32 reg;
	105	struct clk_gate *gate = to_clk_gate(hw);
	106
d1c8a501	107	reg = clk_gate_readl(gate);
9d9f78ed MT	108
	109	/* if a set bit disables this clk, flip it before masking */
	110	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
	111	reg ^= BIT(gate->bit_idx);
	112
	113	reg &= BIT(gate->bit_idx);
	114
	115	return reg ? 1 : 0;
	116	}
0a9c869d	117	EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
9d9f78ed	118
822c250e	119	const struct clk_ops clk_gate_ops = {
9d9f78ed MT	120	.enable = clk_gate_enable,
	121	.disable = clk_gate_disable,
	122	.is_enabled = clk_gate_is_enabled,
	123	};
	124	EXPORT_SYMBOL_GPL(clk_gate_ops);
	125
194efb6e SB	126	struct clk_hw __clk_hw_register_gate(struct device dev,
	127	struct device_node np, const char name,
	128	const char parent_name, const struct clk_hw parent_hw,
	129	const struct clk_parent_data *parent_data,
	130	unsigned long flags,
9d9f78ed MT	131	void __iomem *reg, u8 bit_idx,
	132	u8 clk_gate_flags, spinlock_t *lock)
	133	{
	134	struct clk_gate *gate;
e270d8cb	135	struct clk_hw *hw;
cc819cf8	136	struct clk_init_data init = {};
194efb6e	137	int ret = -EINVAL;
9d9f78ed	138
04577994	139	if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
2e9dcdae	140	if (bit_idx > 15) {
04577994 HZ	141	pr_err("gate bit exceeds LOWORD field\n");
	142	return ERR_PTR(-EINVAL);
	143	}
	144	}
	145
27d54591	146	/* allocate the gate */
d122db7e SB	147	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
d122db7e SB	148	if (!gate)
27d54591	149	return ERR_PTR(-ENOMEM);
9d9f78ed	150
0197b3ea SK	151	init.name = name;
0197b3ea SK	152	init.ops = &clk_gate_ops;
90b6c5c7	153	init.flags = flags;
295face9	154	init.parent_names = parent_name ? &parent_name : NULL;
194efb6e SB	155	init.parent_hws = parent_hw ? &parent_hw : NULL;
	156	init.parent_data = parent_data;
	157	if (parent_name \|\| parent_hw \|\| parent_data)
	158	init.num_parents = 1;
	159	else
	160	init.num_parents = 0;
0197b3ea	161
9d9f78ed MT	162	/* struct clk_gate assignments */
	163	gate->reg = reg;
	164	gate->bit_idx = bit_idx;
	165	gate->flags = clk_gate_flags;
	166	gate->lock = lock;
0197b3ea	167	gate->hw.init = &init;
9d9f78ed	168
e270d8cb	169	hw = &gate->hw;
194efb6e SB	170	if (dev \|\| !np)
	171	ret = clk_hw_register(dev, hw);
	172	else if (np)
	173	ret = of_clk_hw_register(np, hw);
e270d8cb	174	if (ret) {
27d54591	175	kfree(gate);
e270d8cb SB	176	hw = ERR_PTR(ret);
e270d8cb SB	177	}
27d54591	178
e270d8cb	179	return hw;
194efb6e	180
e270d8cb	181	}
194efb6e	182	EXPORT_SYMBOL_GPL(__clk_hw_register_gate);
e270d8cb SB	183
	184	struct clk clk_register_gate(struct device dev, const char *name,
	185	const char *parent_name, unsigned long flags,
	186	void __iomem *reg, u8 bit_idx,
	187	u8 clk_gate_flags, spinlock_t *lock)
	188	{
	189	struct clk_hw *hw;
	190
	191	hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
	192	bit_idx, clk_gate_flags, lock);
	193	if (IS_ERR(hw))
	194	return ERR_CAST(hw);
	195	return hw->clk;
9d9f78ed	196	}
5cfe10bb	197	EXPORT_SYMBOL_GPL(clk_register_gate);
4e3c021f KK	198
	199	void clk_unregister_gate(struct clk *clk)
	200	{
	201	struct clk_gate *gate;
	202	struct clk_hw *hw;
	203
	204	hw = __clk_get_hw(clk);
	205	if (!hw)
	206	return;
	207
	208	gate = to_clk_gate(hw);
	209
	210	clk_unregister(clk);
	211	kfree(gate);
	212	}
	213	EXPORT_SYMBOL_GPL(clk_unregister_gate);
e270d8cb SB	214
	215	void clk_hw_unregister_gate(struct clk_hw *hw)
	216	{
	217	struct clk_gate *gate;
	218
	219	gate = to_clk_gate(hw);
	220
	221	clk_hw_unregister(hw);
	222	kfree(gate);
	223	}
	224	EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);