[mirror_ubuntu-artful-kernel.git] / drivers / clk / clk-mux.c

/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Simple multiplexer clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>

/*
 * DOC: basic adjustable multiplexer clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is only affected by parent switching.  No clk_set_rate support
 * parent - parent is adjustable through clk_set_parent
 */

static u8 clk_mux_get_parent(struct clk_hw *hw)
{
	struct clk_mux *mux = to_clk_mux(hw);
	int num_parents = clk_hw_get_num_parents(hw);
	u32 val;

	/*
	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
	 * to 0x7 (index starts at one)
	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	 * val = 0x4 really means "bit 2, index starts at bit 0"
	 */
	val = clk_readl(mux->reg) >> mux->shift;
	val &= mux->mask;

	if (mux->table) {
		int i;

		for (i = 0; i < num_parents; i++)
			if (mux->table[i] == val)
				return i;
		return -EINVAL;
	}

	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
		val = ffs(val) - 1;

	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
		val--;

	if (val >= num_parents)
		return -EINVAL;

	return val;
}

static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_mux *mux = to_clk_mux(hw);
	u32 val;
	unsigned long flags = 0;

	if (mux->table) {
		index = mux->table[index];
	} else {
		if (mux->flags & CLK_MUX_INDEX_BIT)
			index = 1 << index;

		if (mux->flags & CLK_MUX_INDEX_ONE)
			index++;
	}

	if (mux->lock)
		spin_lock_irqsave(mux->lock, flags);
	else
		__acquire(mux->lock);

	if (mux->flags & CLK_MUX_HIWORD_MASK) {
		val = mux->mask << (mux->shift + 16);
	} else {
		val = clk_readl(mux->reg);
		val &= ~(mux->mask << mux->shift);
	}
	val |= index << mux->shift;
	clk_writel(val, mux->reg);

	if (mux->lock)
		spin_unlock_irqrestore(mux->lock, flags);
	else
		__release(mux->lock);

	return 0;
}

const struct clk_ops clk_mux_ops = {
	.get_parent = clk_mux_get_parent,
	.set_parent = clk_mux_set_parent,
	.determine_rate = __clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_mux_ops);

const struct clk_ops clk_mux_ro_ops = {
	.get_parent = clk_mux_get_parent,
};
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);

struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{
	struct clk_mux *mux;
	struct clk_hw *hw;
	struct clk_init_data init;
	u8 width = 0;
	int ret;

	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
		width = fls(mask) - ffs(mask) + 1;
		if (width + shift > 16) {
			pr_err("mux value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the mux */
	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
	if (!mux) {
		pr_err("%s: could not allocate mux clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	if (clk_mux_flags & CLK_MUX_READ_ONLY)
		init.ops = &clk_mux_ro_ops;
	else
		init.ops = &clk_mux_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	/* struct clk_mux assignments */
	mux->reg = reg;
	mux->shift = shift;
	mux->mask = mask;
	mux->flags = clk_mux_flags;
	mux->lock = lock;
	mux->table = table;
	mux->hw.init = &init;

	hw = &mux->hw;
	ret = clk_hw_register(dev, hw);
	if (ret) {
		kfree(mux);
		hw = ERR_PTR(ret);
	}

	return hw;
}
EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);

struct clk *clk_register_mux_table(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{
	struct clk_hw *hw;

	hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
				       flags, reg, shift, mask, clk_mux_flags,
				       table, lock);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}
EXPORT_SYMBOL_GPL(clk_register_mux_table);

struct clk *clk_register_mux(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock)
{
	u32 mask = BIT(width) - 1;

	return clk_register_mux_table(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_mux);

struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock)
{
	u32 mask = BIT(width) - 1;

	return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_hw_register_mux);

void clk_unregister_mux(struct clk *clk)
{
	struct clk_mux *mux;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	mux = to_clk_mux(hw);

	clk_unregister(clk);
	kfree(mux);
}
EXPORT_SYMBOL_GPL(clk_unregister_mux);

void clk_hw_unregister_mux(struct clk_hw *hw)
{
	struct clk_mux *mux;

	mux = to_clk_mux(hw);

	clk_hw_unregister(hw);
	kfree(mux);
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);
Commit	Line	Data
9d9f78ed MT	1	/*
	2	* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	3	* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
	4	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Simple multiplexer clock implementation
	11	*/
	12
9d9f78ed MT	13	#include <linux/clk-provider.h>
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18
	19	/*
	20	* DOC: basic adjustable multiplexer clock that cannot gate
	21	*
	22	* Traits of this clock:
	23	* prepare - clk_prepare only ensures that parents are prepared
	24	* enable - clk_enable only ensures that parents are enabled
	25	* rate - rate is only affected by parent switching. No clk_set_rate support
	26	* parent - parent is adjustable through clk_set_parent
	27	*/
	28
9d9f78ed MT	29	static u8 clk_mux_get_parent(struct clk_hw *hw)
	30	{
	31	struct clk_mux *mux = to_clk_mux(hw);
497295af	32	int num_parents = clk_hw_get_num_parents(hw);
9d9f78ed MT	33	u32 val;
	34
	35	/*
	36	* FIXME need a mux-specific flag to determine if val is bitwise or numeric
	37	* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
	38	* to 0x7 (index starts at one)
	39	* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	40	* val = 0x4 really means "bit 2, index starts at bit 0"
	41	*/
aa514ce3	42	val = clk_readl(mux->reg) >> mux->shift;
ce4f3313 PDS	43	val &= mux->mask;
	44
	45	if (mux->table) {
	46	int i;
	47
	48	for (i = 0; i < num_parents; i++)
	49	if (mux->table[i] == val)
	50	return i;
	51	return -EINVAL;
	52	}
9d9f78ed MT	53
	54	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
	55	val = ffs(val) - 1;
	56
	57	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
	58	val--;
	59
ce4f3313	60	if (val >= num_parents)
9d9f78ed MT	61	return -EINVAL;
	62
	63	return val;
	64	}
9d9f78ed MT	65
	66	static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
	67	{
	68	struct clk_mux *mux = to_clk_mux(hw);
	69	u32 val;
	70	unsigned long flags = 0;
	71
3837bd27	72	if (mux->table) {
ce4f3313	73	index = mux->table[index];
3837bd27	74	} else {
ce4f3313	75	if (mux->flags & CLK_MUX_INDEX_BIT)
6793b3cd	76	index = 1 << index;
ce4f3313 PDS	77
	78	if (mux->flags & CLK_MUX_INDEX_ONE)
	79	index++;
	80	}
9d9f78ed MT	81
	82	if (mux->lock)
	83	spin_lock_irqsave(mux->lock, flags);
661e2180 SB	84	else
661e2180 SB	85	__acquire(mux->lock);
9d9f78ed	86
ba492e90 HZ	87	if (mux->flags & CLK_MUX_HIWORD_MASK) {
	88	val = mux->mask << (mux->shift + 16);
	89	} else {
aa514ce3	90	val = clk_readl(mux->reg);
ba492e90 HZ	91	val &= ~(mux->mask << mux->shift);
ba492e90 HZ	92	}
9d9f78ed	93	val \|= index << mux->shift;
aa514ce3	94	clk_writel(val, mux->reg);
9d9f78ed MT	95
	96	if (mux->lock)
	97	spin_unlock_irqrestore(mux->lock, flags);
661e2180 SB	98	else
661e2180 SB	99	__release(mux->lock);
9d9f78ed MT	100
	101	return 0;
	102	}
9d9f78ed	103
822c250e	104	const struct clk_ops clk_mux_ops = {
9d9f78ed MT	105	.get_parent = clk_mux_get_parent,
9d9f78ed MT	106	.set_parent = clk_mux_set_parent,
e366fdd7	107	.determine_rate = __clk_mux_determine_rate,
9d9f78ed MT	108	};
	109	EXPORT_SYMBOL_GPL(clk_mux_ops);
	110
c57acd14 TF	111	const struct clk_ops clk_mux_ro_ops = {
	112	.get_parent = clk_mux_get_parent,
	113	};
	114	EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
	115
264b3171	116	struct clk_hw clk_hw_register_mux_table(struct device dev, const char *name,
2893c379 SH	117	const char * const *parent_names, u8 num_parents,
2893c379 SH	118	unsigned long flags,
ce4f3313 PDS	119	void __iomem *reg, u8 shift, u32 mask,
ce4f3313 PDS	120	u8 clk_mux_flags, u32 table, spinlock_t lock)
9d9f78ed MT	121	{
9d9f78ed MT	122	struct clk_mux *mux;
264b3171	123	struct clk_hw *hw;
0197b3ea	124	struct clk_init_data init;
ba492e90	125	u8 width = 0;
264b3171	126	int ret;
ba492e90 HZ	127
	128	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
	129	width = fls(mask) - ffs(mask) + 1;
	130	if (width + shift > 16) {
	131	pr_err("mux value exceeds LOWORD field\n");
	132	return ERR_PTR(-EINVAL);
	133	}
	134	}
9d9f78ed	135
27d54591	136	/* allocate the mux */
10363b58	137	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
9d9f78ed MT	138	if (!mux) {
	139	pr_err("%s: could not allocate mux clk\n", __func__);
	140	return ERR_PTR(-ENOMEM);
	141	}
	142
0197b3ea	143	init.name = name;
c57acd14 TF	144	if (clk_mux_flags & CLK_MUX_READ_ONLY)
	145	init.ops = &clk_mux_ro_ops;
	146	else
	147	init.ops = &clk_mux_ops;
f7d8caad	148	init.flags = flags \| CLK_IS_BASIC;
0197b3ea SK	149	init.parent_names = parent_names;
	150	init.num_parents = num_parents;
	151
9d9f78ed MT	152	/* struct clk_mux assignments */
	153	mux->reg = reg;
	154	mux->shift = shift;
ce4f3313	155	mux->mask = mask;
9d9f78ed MT	156	mux->flags = clk_mux_flags;
9d9f78ed MT	157	mux->lock = lock;
ce4f3313	158	mux->table = table;
31df9db9	159	mux->hw.init = &init;
9d9f78ed	160
264b3171 SB	161	hw = &mux->hw;
	162	ret = clk_hw_register(dev, hw);
	163	if (ret) {
27d54591	164	kfree(mux);
264b3171 SB	165	hw = ERR_PTR(ret);
264b3171 SB	166	}
27d54591	167
264b3171 SB	168	return hw;
	169	}
	170	EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);
	171
	172	struct clk clk_register_mux_table(struct device dev, const char *name,
	173	const char * const *parent_names, u8 num_parents,
	174	unsigned long flags,
	175	void __iomem *reg, u8 shift, u32 mask,
	176	u8 clk_mux_flags, u32 table, spinlock_t lock)
	177	{
	178	struct clk_hw *hw;
	179
	180	hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
	181	flags, reg, shift, mask, clk_mux_flags,
	182	table, lock);
	183	if (IS_ERR(hw))
	184	return ERR_CAST(hw);
	185	return hw->clk;
9d9f78ed	186	}
5cfe10bb	187	EXPORT_SYMBOL_GPL(clk_register_mux_table);
ce4f3313 PDS	188
ce4f3313 PDS	189	struct clk clk_register_mux(struct device dev, const char *name,
2893c379 SH	190	const char * const *parent_names, u8 num_parents,
2893c379 SH	191	unsigned long flags,
ce4f3313 PDS	192	void __iomem *reg, u8 shift, u8 width,
	193	u8 clk_mux_flags, spinlock_t *lock)
	194	{
	195	u32 mask = BIT(width) - 1;
	196
	197	return clk_register_mux_table(dev, name, parent_names, num_parents,
	198	flags, reg, shift, mask, clk_mux_flags,
	199	NULL, lock);
	200	}
5cfe10bb	201	EXPORT_SYMBOL_GPL(clk_register_mux);
4e3c021f	202
264b3171 SB	203	struct clk_hw clk_hw_register_mux(struct device dev, const char *name,
	204	const char * const *parent_names, u8 num_parents,
	205	unsigned long flags,
	206	void __iomem *reg, u8 shift, u8 width,
	207	u8 clk_mux_flags, spinlock_t *lock)
	208	{
	209	u32 mask = BIT(width) - 1;
	210
	211	return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
	212	flags, reg, shift, mask, clk_mux_flags,
	213	NULL, lock);
	214	}
	215	EXPORT_SYMBOL_GPL(clk_hw_register_mux);
	216
4e3c021f KK	217	void clk_unregister_mux(struct clk *clk)
	218	{
	219	struct clk_mux *mux;
	220	struct clk_hw *hw;
	221
	222	hw = __clk_get_hw(clk);
	223	if (!hw)
	224	return;
	225
	226	mux = to_clk_mux(hw);
	227
	228	clk_unregister(clk);
	229	kfree(mux);
	230	}
	231	EXPORT_SYMBOL_GPL(clk_unregister_mux);
264b3171 SB	232
	233	void clk_hw_unregister_mux(struct clk_hw *hw)
	234	{
	235	struct clk_mux *mux;
	236
	237	mux = to_clk_mux(hw);
	238
	239	clk_hw_unregister(hw);
	240	kfree(mux);
	241	}
	242	EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);