[mirror_ubuntu-bionic-kernel.git] / drivers / clk / clk-mux.c

/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Simple multiplexer clock implementation
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>

/*
 * DOC: basic adjustable multiplexer clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is only affected by parent switching.  No clk_set_rate support
 * parent - parent is adjustable through clk_set_parent
 */

#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)

static u8 clk_mux_get_parent(struct clk_hw *hw)
{
	struct clk_mux *mux = to_clk_mux(hw);
	int num_parents = __clk_get_num_parents(hw->clk);
	u32 val;

	/*
	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
	 * to 0x7 (index starts at one)
	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	 * val = 0x4 really means "bit 2, index starts at bit 0"
	 */
	val = clk_readl(mux->reg) >> mux->shift;
	val &= mux->mask;

	if (mux->table) {
		int i;

		for (i = 0; i < num_parents; i++)
			if (mux->table[i] == val)
				return i;
		return -EINVAL;
	}

	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
		val = ffs(val) - 1;

	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
		val--;

	if (val >= num_parents)
		return -EINVAL;

	return val;
}

static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_mux *mux = to_clk_mux(hw);
	u32 val;
	unsigned long flags = 0;

	if (mux->table)
		index = mux->table[index];

	else {
		if (mux->flags & CLK_MUX_INDEX_BIT)
			index = (1 << ffs(index));

		if (mux->flags & CLK_MUX_INDEX_ONE)
			index++;
	}

	if (mux->lock)
		spin_lock_irqsave(mux->lock, flags);

	if (mux->flags & CLK_MUX_HIWORD_MASK) {
		val = mux->mask << (mux->shift + 16);
	} else {
		val = clk_readl(mux->reg);
		val &= ~(mux->mask << mux->shift);
	}
	val |= index << mux->shift;
	clk_writel(val, mux->reg);

	if (mux->lock)
		spin_unlock_irqrestore(mux->lock, flags);

	return 0;
}

const struct clk_ops clk_mux_ops = {
	.get_parent = clk_mux_get_parent,
	.set_parent = clk_mux_set_parent,
	.determine_rate = __clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_mux_ops);

const struct clk_ops clk_mux_ro_ops = {
	.get_parent = clk_mux_get_parent,
};
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);

struct clk *clk_register_mux_table(struct device *dev, const char *name,
		const char **parent_names, u8 num_parents, unsigned long flags,
		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{
	struct clk_mux *mux;
	struct clk *clk;
	struct clk_init_data init;
	u8 width = 0;

	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
		width = fls(mask) - ffs(mask) + 1;
		if (width + shift > 16) {
			pr_err("mux value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the mux */
	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
	if (!mux) {
		pr_err("%s: could not allocate mux clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	if (clk_mux_flags & CLK_MUX_READ_ONLY)
		init.ops = &clk_mux_ro_ops;
	else
		init.ops = &clk_mux_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	/* struct clk_mux assignments */
	mux->reg = reg;
	mux->shift = shift;
	mux->mask = mask;
	mux->flags = clk_mux_flags;
	mux->lock = lock;
	mux->table = table;
	mux->hw.init = &init;

	clk = clk_register(dev, &mux->hw);

	if (IS_ERR(clk))
		kfree(mux);

	return clk;
}
EXPORT_SYMBOL_GPL(clk_register_mux_table);

struct clk *clk_register_mux(struct device *dev, const char *name,
		const char **parent_names, u8 num_parents, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock)
{
	u32 mask = BIT(width) - 1;

	return clk_register_mux_table(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_mux);
Commit	Line	Data
9d9f78ed MT	1	/*
	2	* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
	3	* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
	4	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Simple multiplexer clock implementation
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/clk-provider.h>
	15	#include <linux/module.h>
	16	#include <linux/slab.h>
	17	#include <linux/io.h>
	18	#include <linux/err.h>
	19
	20	/*
	21	* DOC: basic adjustable multiplexer clock that cannot gate
	22	*
	23	* Traits of this clock:
	24	* prepare - clk_prepare only ensures that parents are prepared
	25	* enable - clk_enable only ensures that parents are enabled
	26	* rate - rate is only affected by parent switching. No clk_set_rate support
	27	* parent - parent is adjustable through clk_set_parent
	28	*/
	29
	30	#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
	31
	32	static u8 clk_mux_get_parent(struct clk_hw *hw)
	33	{
	34	struct clk_mux *mux = to_clk_mux(hw);
ce4f3313	35	int num_parents = __clk_get_num_parents(hw->clk);
9d9f78ed MT	36	u32 val;
	37
	38	/*
	39	* FIXME need a mux-specific flag to determine if val is bitwise or numeric
	40	* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
	41	* to 0x7 (index starts at one)
	42	* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	43	* val = 0x4 really means "bit 2, index starts at bit 0"
	44	*/
aa514ce3	45	val = clk_readl(mux->reg) >> mux->shift;
ce4f3313 PDS	46	val &= mux->mask;
	47
	48	if (mux->table) {
	49	int i;
	50
	51	for (i = 0; i < num_parents; i++)
	52	if (mux->table[i] == val)
	53	return i;
	54	return -EINVAL;
	55	}
9d9f78ed MT	56
	57	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
	58	val = ffs(val) - 1;
	59
	60	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
	61	val--;
	62
ce4f3313	63	if (val >= num_parents)
9d9f78ed MT	64	return -EINVAL;
	65
	66	return val;
	67	}
9d9f78ed MT	68
	69	static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
	70	{
	71	struct clk_mux *mux = to_clk_mux(hw);
	72	u32 val;
	73	unsigned long flags = 0;
	74
ce4f3313 PDS	75	if (mux->table)
ce4f3313 PDS	76	index = mux->table[index];
9d9f78ed	77
ce4f3313 PDS	78	else {
	79	if (mux->flags & CLK_MUX_INDEX_BIT)
	80	index = (1 << ffs(index));
	81
	82	if (mux->flags & CLK_MUX_INDEX_ONE)
	83	index++;
	84	}
9d9f78ed MT	85
	86	if (mux->lock)
	87	spin_lock_irqsave(mux->lock, flags);
	88
ba492e90 HZ	89	if (mux->flags & CLK_MUX_HIWORD_MASK) {
	90	val = mux->mask << (mux->shift + 16);
	91	} else {
aa514ce3	92	val = clk_readl(mux->reg);
ba492e90 HZ	93	val &= ~(mux->mask << mux->shift);
ba492e90 HZ	94	}
9d9f78ed	95	val \|= index << mux->shift;
aa514ce3	96	clk_writel(val, mux->reg);
9d9f78ed MT	97
	98	if (mux->lock)
	99	spin_unlock_irqrestore(mux->lock, flags);
	100
	101	return 0;
	102	}
9d9f78ed	103
822c250e	104	const struct clk_ops clk_mux_ops = {
9d9f78ed MT	105	.get_parent = clk_mux_get_parent,
9d9f78ed MT	106	.set_parent = clk_mux_set_parent,
e366fdd7	107	.determine_rate = __clk_mux_determine_rate,
9d9f78ed MT	108	};
	109	EXPORT_SYMBOL_GPL(clk_mux_ops);
	110
c57acd14 TF	111	const struct clk_ops clk_mux_ro_ops = {
	112	.get_parent = clk_mux_get_parent,
	113	};
	114	EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
	115
ce4f3313	116	struct clk clk_register_mux_table(struct device dev, const char *name,
d305fb78	117	const char **parent_names, u8 num_parents, unsigned long flags,
ce4f3313 PDS	118	void __iomem *reg, u8 shift, u32 mask,
ce4f3313 PDS	119	u8 clk_mux_flags, u32 table, spinlock_t lock)
9d9f78ed MT	120	{
9d9f78ed MT	121	struct clk_mux *mux;
27d54591	122	struct clk *clk;
0197b3ea	123	struct clk_init_data init;
ba492e90 HZ	124	u8 width = 0;
	125
	126	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
	127	width = fls(mask) - ffs(mask) + 1;
	128	if (width + shift > 16) {
	129	pr_err("mux value exceeds LOWORD field\n");
	130	return ERR_PTR(-EINVAL);
	131	}
	132	}
9d9f78ed	133
27d54591	134	/* allocate the mux */
10363b58	135	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
9d9f78ed MT	136	if (!mux) {
	137	pr_err("%s: could not allocate mux clk\n", __func__);
	138	return ERR_PTR(-ENOMEM);
	139	}
	140
0197b3ea	141	init.name = name;
c57acd14 TF	142	if (clk_mux_flags & CLK_MUX_READ_ONLY)
	143	init.ops = &clk_mux_ro_ops;
	144	else
	145	init.ops = &clk_mux_ops;
f7d8caad	146	init.flags = flags \| CLK_IS_BASIC;
0197b3ea SK	147	init.parent_names = parent_names;
	148	init.num_parents = num_parents;
	149
9d9f78ed MT	150	/* struct clk_mux assignments */
	151	mux->reg = reg;
	152	mux->shift = shift;
ce4f3313	153	mux->mask = mask;
9d9f78ed MT	154	mux->flags = clk_mux_flags;
9d9f78ed MT	155	mux->lock = lock;
ce4f3313	156	mux->table = table;
31df9db9	157	mux->hw.init = &init;
9d9f78ed	158
0197b3ea	159	clk = clk_register(dev, &mux->hw);
27d54591 MT	160
	161	if (IS_ERR(clk))
	162	kfree(mux);
	163
	164	return clk;
9d9f78ed	165	}
5cfe10bb	166	EXPORT_SYMBOL_GPL(clk_register_mux_table);
ce4f3313 PDS	167
	168	struct clk clk_register_mux(struct device dev, const char *name,
	169	const char **parent_names, u8 num_parents, unsigned long flags,
	170	void __iomem *reg, u8 shift, u8 width,
	171	u8 clk_mux_flags, spinlock_t *lock)
	172	{
	173	u32 mask = BIT(width) - 1;
	174
	175	return clk_register_mux_table(dev, name, parent_names, num_parents,
	176	flags, reg, shift, mask, clk_mux_flags,
	177	NULL, lock);
	178	}
5cfe10bb	179	EXPORT_SYMBOL_GPL(clk_register_mux);