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555eae97 TY |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
93a17c05 | 8 | * clock driver for Freescale QorIQ SoCs. |
555eae97 TY |
9 | */ |
10 | #include <linux/clk-provider.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
c11eede6 | 14 | #include <linux/of_address.h> |
555eae97 TY |
15 | #include <linux/of_platform.h> |
16 | #include <linux/of.h> | |
17 | #include <linux/slab.h> | |
18 | ||
19 | struct cmux_clk { | |
20 | struct clk_hw hw; | |
21 | void __iomem *reg; | |
57bfd7ee | 22 | unsigned int clk_per_pll; |
555eae97 TY |
23 | u32 flags; |
24 | }; | |
25 | ||
26 | #define PLL_KILL BIT(31) | |
27 | #define CLKSEL_SHIFT 27 | |
28 | #define CLKSEL_ADJUST BIT(0) | |
29 | #define to_cmux_clk(p) container_of(p, struct cmux_clk, hw) | |
30 | ||
555eae97 TY |
31 | static int cmux_set_parent(struct clk_hw *hw, u8 idx) |
32 | { | |
33 | struct cmux_clk *clk = to_cmux_clk(hw); | |
34 | u32 clksel; | |
35 | ||
57bfd7ee | 36 | clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll; |
555eae97 TY |
37 | if (clk->flags & CLKSEL_ADJUST) |
38 | clksel += 8; | |
39 | clksel = (clksel & 0xf) << CLKSEL_SHIFT; | |
40 | iowrite32be(clksel, clk->reg); | |
41 | ||
42 | return 0; | |
43 | } | |
44 | ||
45 | static u8 cmux_get_parent(struct clk_hw *hw) | |
46 | { | |
47 | struct cmux_clk *clk = to_cmux_clk(hw); | |
48 | u32 clksel; | |
49 | ||
50 | clksel = ioread32be(clk->reg); | |
51 | clksel = (clksel >> CLKSEL_SHIFT) & 0xf; | |
52 | if (clk->flags & CLKSEL_ADJUST) | |
53 | clksel -= 8; | |
57bfd7ee | 54 | clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4; |
555eae97 TY |
55 | |
56 | return clksel; | |
57 | } | |
58 | ||
334680dd | 59 | static const struct clk_ops cmux_ops = { |
555eae97 TY |
60 | .get_parent = cmux_get_parent, |
61 | .set_parent = cmux_set_parent, | |
62 | }; | |
63 | ||
64 | static void __init core_mux_init(struct device_node *np) | |
65 | { | |
66 | struct clk *clk; | |
67 | struct clk_init_data init; | |
68 | struct cmux_clk *cmux_clk; | |
69 | struct device_node *node; | |
70 | int rc, count, i; | |
71 | u32 offset; | |
72 | const char *clk_name; | |
73 | const char **parent_names; | |
57bfd7ee | 74 | struct of_phandle_args clkspec; |
555eae97 TY |
75 | |
76 | rc = of_property_read_u32(np, "reg", &offset); | |
77 | if (rc) { | |
78 | pr_err("%s: could not get reg property\n", np->name); | |
79 | return; | |
80 | } | |
81 | ||
82 | /* get the input clock source count */ | |
83 | count = of_property_count_strings(np, "clock-names"); | |
84 | if (count < 0) { | |
85 | pr_err("%s: get clock count error\n", np->name); | |
86 | return; | |
87 | } | |
a9247225 | 88 | parent_names = kcalloc(count, sizeof(char *), GFP_KERNEL); |
8002cab6 | 89 | if (!parent_names) |
555eae97 | 90 | return; |
555eae97 TY |
91 | |
92 | for (i = 0; i < count; i++) | |
93 | parent_names[i] = of_clk_get_parent_name(np, i); | |
94 | ||
13c25f57 | 95 | cmux_clk = kzalloc(sizeof(*cmux_clk), GFP_KERNEL); |
8002cab6 | 96 | if (!cmux_clk) |
555eae97 | 97 | goto err_name; |
8002cab6 | 98 | |
00fa6e5d TY |
99 | cmux_clk->reg = of_iomap(np, 0); |
100 | if (!cmux_clk->reg) { | |
101 | pr_err("%s: could not map register\n", __func__); | |
102 | goto err_clk; | |
103 | } | |
555eae97 | 104 | |
57bfd7ee TY |
105 | rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0, |
106 | &clkspec); | |
107 | if (rc) { | |
108 | pr_err("%s: parse clock node error\n", __func__); | |
109 | goto err_clk; | |
110 | } | |
111 | ||
112 | cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np, | |
113 | "clock-output-names"); | |
114 | of_node_put(clkspec.np); | |
115 | ||
555eae97 TY |
116 | node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"); |
117 | if (node && (offset >= 0x80)) | |
118 | cmux_clk->flags = CLKSEL_ADJUST; | |
119 | ||
120 | rc = of_property_read_string_index(np, "clock-output-names", | |
78f4a63e | 121 | 0, &clk_name); |
555eae97 TY |
122 | if (rc) { |
123 | pr_err("%s: read clock names error\n", np->name); | |
124 | goto err_clk; | |
125 | } | |
126 | ||
127 | init.name = clk_name; | |
128 | init.ops = &cmux_ops; | |
129 | init.parent_names = parent_names; | |
130 | init.num_parents = count; | |
131 | init.flags = 0; | |
132 | cmux_clk->hw.init = &init; | |
133 | ||
134 | clk = clk_register(NULL, &cmux_clk->hw); | |
135 | if (IS_ERR(clk)) { | |
136 | pr_err("%s: could not register clock\n", clk_name); | |
137 | goto err_clk; | |
138 | } | |
139 | ||
140 | rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
141 | if (rc) { | |
142 | pr_err("Could not register clock provider for node:%s\n", | |
78f4a63e | 143 | np->name); |
555eae97 TY |
144 | goto err_clk; |
145 | } | |
146 | goto err_name; | |
147 | ||
148 | err_clk: | |
149 | kfree(cmux_clk); | |
150 | err_name: | |
151 | /* free *_names because they are reallocated when registered */ | |
152 | kfree(parent_names); | |
153 | } | |
154 | ||
155 | static void __init core_pll_init(struct device_node *np) | |
156 | { | |
00fa6e5d | 157 | u32 mult; |
555eae97 TY |
158 | int i, rc, count; |
159 | const char *clk_name, *parent_name; | |
160 | struct clk_onecell_data *onecell_data; | |
161 | struct clk **subclks; | |
00fa6e5d | 162 | void __iomem *base; |
555eae97 | 163 | |
00fa6e5d TY |
164 | base = of_iomap(np, 0); |
165 | if (!base) { | |
93a17c05 | 166 | pr_err("clk-qoriq: iomap error\n"); |
555eae97 TY |
167 | return; |
168 | } | |
169 | ||
170 | /* get the multiple of PLL */ | |
00fa6e5d | 171 | mult = ioread32be(base); |
555eae97 TY |
172 | |
173 | /* check if this PLL is disabled */ | |
174 | if (mult & PLL_KILL) { | |
175 | pr_debug("PLL:%s is disabled\n", np->name); | |
00fa6e5d | 176 | goto err_map; |
555eae97 TY |
177 | } |
178 | mult = (mult >> 1) & 0x3f; | |
179 | ||
180 | parent_name = of_clk_get_parent_name(np, 0); | |
181 | if (!parent_name) { | |
182 | pr_err("PLL: %s must have a parent\n", np->name); | |
00fa6e5d | 183 | goto err_map; |
555eae97 TY |
184 | } |
185 | ||
186 | count = of_property_count_strings(np, "clock-output-names"); | |
187 | if (count < 0 || count > 4) { | |
188 | pr_err("%s: clock is not supported\n", np->name); | |
00fa6e5d | 189 | goto err_map; |
555eae97 TY |
190 | } |
191 | ||
a9247225 | 192 | subclks = kcalloc(count, sizeof(struct clk *), GFP_KERNEL); |
8002cab6 | 193 | if (!subclks) |
00fa6e5d | 194 | goto err_map; |
555eae97 | 195 | |
13c25f57 | 196 | onecell_data = kzalloc(sizeof(*onecell_data), GFP_KERNEL); |
8002cab6 | 197 | if (!onecell_data) |
555eae97 | 198 | goto err_clks; |
555eae97 TY |
199 | |
200 | for (i = 0; i < count; i++) { | |
201 | rc = of_property_read_string_index(np, "clock-output-names", | |
78f4a63e | 202 | i, &clk_name); |
555eae97 TY |
203 | if (rc) { |
204 | pr_err("%s: could not get clock names\n", np->name); | |
205 | goto err_cell; | |
206 | } | |
207 | ||
208 | /* | |
209 | * when count == 4, there are 4 output clocks: | |
210 | * /1, /2, /3, /4 respectively | |
211 | * when count < 4, there are at least 2 output clocks: | |
212 | * /1, /2, (/4, if count == 3) respectively. | |
213 | */ | |
214 | if (count == 4) | |
215 | subclks[i] = clk_register_fixed_factor(NULL, clk_name, | |
216 | parent_name, 0, mult, 1 + i); | |
217 | else | |
218 | ||
219 | subclks[i] = clk_register_fixed_factor(NULL, clk_name, | |
220 | parent_name, 0, mult, 1 << i); | |
221 | ||
222 | if (IS_ERR(subclks[i])) { | |
223 | pr_err("%s: could not register clock\n", clk_name); | |
224 | goto err_cell; | |
225 | } | |
226 | } | |
227 | ||
228 | onecell_data->clks = subclks; | |
229 | onecell_data->clk_num = count; | |
230 | ||
231 | rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); | |
232 | if (rc) { | |
233 | pr_err("Could not register clk provider for node:%s\n", | |
78f4a63e | 234 | np->name); |
555eae97 TY |
235 | goto err_cell; |
236 | } | |
237 | ||
00fa6e5d | 238 | iounmap(base); |
555eae97 TY |
239 | return; |
240 | err_cell: | |
241 | kfree(onecell_data); | |
242 | err_clks: | |
243 | kfree(subclks); | |
00fa6e5d TY |
244 | err_map: |
245 | iounmap(base); | |
246 | } | |
247 | ||
248 | static void __init sysclk_init(struct device_node *node) | |
249 | { | |
250 | struct clk *clk; | |
251 | const char *clk_name = node->name; | |
252 | struct device_node *np = of_get_parent(node); | |
253 | u32 rate; | |
254 | ||
255 | if (!np) { | |
93a17c05 | 256 | pr_err("qoriq-clk: could not get parent node\n"); |
00fa6e5d TY |
257 | return; |
258 | } | |
259 | ||
260 | if (of_property_read_u32(np, "clock-frequency", &rate)) { | |
261 | of_node_put(node); | |
262 | return; | |
263 | } | |
264 | ||
265 | of_property_read_string(np, "clock-output-names", &clk_name); | |
266 | ||
267 | clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate); | |
268 | if (!IS_ERR(clk)) | |
269 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
555eae97 | 270 | } |
66619ac5 KH |
271 | CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); |
272 | CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init); | |
273 | CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init); | |
274 | CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init); | |
275 | CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init); | |
276 | CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init); |