[mirror_ubuntu-artful-kernel.git] / drivers / clk / clk-tango4.c

#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/init.h>
#include <linux/io.h>

#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
static struct clk *clks[CLK_COUNT];
static struct clk_onecell_data clk_data = { clks, CLK_COUNT };

#define SYSCLK_DIV	0x20
#define CPUCLK_DIV	0x24
#define DIV_BYPASS	BIT(23)

/*** CLKGEN_PLL ***/
#define extract_pll_n(val)	((val >>  0) & ((1u << 7) - 1))
#define extract_pll_k(val)	((val >> 13) & ((1u << 3) - 1))
#define extract_pll_m(val)	((val >> 16) & ((1u << 3) - 1))
#define extract_pll_isel(val)	((val >> 24) & ((1u << 3) - 1))

static void __init make_pll(int idx, const char *parent, void __iomem *base)
{
	char name[8];
	u32 val, mul, div;

	sprintf(name, "pll%d", idx);
	val = readl(base + idx * 8);
	mul =  extract_pll_n(val) + 1;
	div = (extract_pll_m(val) + 1) << extract_pll_k(val);
	clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
	if (extract_pll_isel(val) != 1)
		panic("%s: input not set to XTAL_IN\n", name);
}

static void __init make_cd(int idx, void __iomem *base)
{
	char name[8];
	u32 val, mul, div;

	sprintf(name, "cd%d", idx);
	val = readl(base + idx * 8);
	mul =  1 << 27;
	div = (2 << 27) + val;
	clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);
	if (val > 0xf0000000)
		panic("%s: unsupported divider %x\n", name, val);
}

static void __init tango4_clkgen_setup(struct device_node *np)
{
	struct clk **pp = clk_data.clks;
	void __iomem *base = of_iomap(np, 0);
	const char *parent = of_clk_get_parent_name(np, 0);

	if (!base)
		panic("%s: invalid address\n", np->name);

	if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
		panic("%s: unsupported cpuclk setup\n", np->name);

	if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
		panic("%s: unsupported sysclk setup\n", np->name);

	writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */

	make_pll(0, parent, base);
	make_pll(1, parent, base);
	make_pll(2, parent, base);
	make_cd(2, base + 0x80);
	make_cd(6, base + 0x80);

	pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
			base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
	pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);
	pp[2] = clk_register_fixed_factor(NULL,  "usb_clk", "cd2", 0, 1, 2);
	pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);

	if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))
		panic("%s: clk registration failed\n", np->name);

	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
		panic("%s: clk provider registration failed\n", np->name);
}
CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
Commit	Line	Data
ed12dfc9 MG	1	#include <linux/kernel.h>
	2	#include <linux/clk-provider.h>
	3	#include <linux/of_address.h>
	4	#include <linux/init.h>
	5	#include <linux/io.h>
	6
fefe0535 MG	7	#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
	8	static struct clk *clks[CLK_COUNT];
	9	static struct clk_onecell_data clk_data = { clks, CLK_COUNT };
ed12dfc9	10
fefe0535 MG	11	#define SYSCLK_DIV 0x20
	12	#define CPUCLK_DIV 0x24
	13	#define DIV_BYPASS BIT(23)
ed12dfc9	14
fefe0535 MG	15	/* CLKGEN_PLL */
	16	#define extract_pll_n(val) ((val >> 0) & ((1u << 7) - 1))
	17	#define extract_pll_k(val) ((val >> 13) & ((1u << 3) - 1))
	18	#define extract_pll_m(val) ((val >> 16) & ((1u << 3) - 1))
	19	#define extract_pll_isel(val) ((val >> 24) & ((1u << 3) - 1))
ed12dfc9 MG	20
	21	static void __init make_pll(int idx, const char parent, void __iomem base)
	22	{
	23	char name[8];
	24	u32 val, mul, div;
	25
	26	sprintf(name, "pll%d", idx);
fefe0535 MG	27	val = readl(base + idx * 8);
	28	mul = extract_pll_n(val) + 1;
	29	div = (extract_pll_m(val) + 1) << extract_pll_k(val);
ed12dfc9	30	clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
fefe0535 MG	31	if (extract_pll_isel(val) != 1)
fefe0535 MG	32	panic("%s: input not set to XTAL_IN\n", name);
ed12dfc9 MG	33	}
ed12dfc9 MG	34
fefe0535	35	static void __init make_cd(int idx, void __iomem *base)
ed12dfc9	36	{
fefe0535 MG	37	char name[8];
fefe0535 MG	38	u32 val, mul, div;
ed12dfc9	39
fefe0535 MG	40	sprintf(name, "cd%d", idx);
	41	val = readl(base + idx * 8);
	42	mul = 1 << 27;
	43	div = (2 << 27) + val;
	44	clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);
	45	if (val > 0xf0000000)
	46	panic("%s: unsupported divider %x\n", name, val);
ed12dfc9 MG	47	}
	48
	49	static void __init tango4_clkgen_setup(struct device_node *np)
	50	{
fefe0535	51	struct clk **pp = clk_data.clks;
ed12dfc9 MG	52	void __iomem *base = of_iomap(np, 0);
	53	const char *parent = of_clk_get_parent_name(np, 0);
	54
	55	if (!base)
fefe0535 MG	56	panic("%s: invalid address\n", np->name);
	57
	58	if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
	59	panic("%s: unsupported cpuclk setup\n", np->name);
	60
	61	if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
	62	panic("%s: unsupported sysclk setup\n", np->name);
	63
	64	writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */
ed12dfc9 MG	65
	66	make_pll(0, parent, base);
	67	make_pll(1, parent, base);
fefe0535 MG	68	make_pll(2, parent, base);
	69	make_cd(2, base + 0x80);
	70	make_cd(6, base + 0x80);
ed12dfc9	71
fefe0535 MG	72	pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
	73	base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
	74	pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);
	75	pp[2] = clk_register_fixed_factor(NULL, "usb_clk", "cd2", 0, 1, 2);
	76	pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);
ed12dfc9	77
fefe0535 MG	78	if (IS_ERR(pp[0]) \|\| IS_ERR(pp[1]) \|\| IS_ERR(pp[2]) \|\| IS_ERR(pp[3]))
fefe0535 MG	79	panic("%s: clk registration failed\n", np->name);
ed12dfc9	80
fefe0535 MG	81	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
fefe0535 MG	82	panic("%s: clk provider registration failed\n", np->name);
ed12dfc9 MG	83	}
ed12dfc9 MG	84	CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);