[mirror_ubuntu-zesty-kernel.git] / drivers / clk / clk-wm831x.c

/*
 * WM831x clock control
 *
 * Copyright 2011-2 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/mfd/wm831x/core.h>

struct wm831x_clk {
	struct wm831x *wm831x;
	struct clk_hw xtal_hw;
	struct clk_hw fll_hw;
	struct clk_hw clkout_hw;
	struct clk *xtal;
	struct clk *fll;
	struct clk *clkout;
	bool xtal_ena;
};

static int wm831x_xtal_is_enabled(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  xtal_hw);

	return clkdata->xtal_ena;
}

static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
					     unsigned long parent_rate)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  xtal_hw);

	if (clkdata->xtal_ena)
		return 32768;
	else
		return 0;
}

static const struct clk_ops wm831x_xtal_ops = {
	.is_enabled = wm831x_xtal_is_enabled,
	.recalc_rate = wm831x_xtal_recalc_rate,
};

static struct clk_init_data wm831x_xtal_init = {
	.name = "xtal",
	.ops = &wm831x_xtal_ops,
	.flags = CLK_IS_ROOT,
};

static const unsigned long wm831x_fll_auto_rates[] = {
	 2048000,
	11289600,
	12000000,
	12288000,
	19200000,
	22579600,
	24000000,
	24576000,
};

static int wm831x_fll_is_enabled(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  fll_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
	if (ret < 0) {
		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
			ret);
		return true;
	}

	return (ret & WM831X_FLL_ENA) != 0;
}

static int wm831x_fll_prepare(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  fll_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
			      WM831X_FLL_ENA, WM831X_FLL_ENA);
	if (ret != 0)
		dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);

	usleep_range(2000, 2000);

	return ret;
}

static void wm831x_fll_unprepare(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  fll_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
	if (ret != 0)
		dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
}

static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
					    unsigned long parent_rate)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  fll_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
	if (ret < 0) {
		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
			ret);
		return 0;
	}

	if (ret & WM831X_FLL_AUTO)
		return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];

	dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");

	return 0;
}

static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
				  unsigned long *unused)
{
	int best = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
		if (abs(wm831x_fll_auto_rates[i] - rate) <
		    abs(wm831x_fll_auto_rates[best] - rate))
			best = i;

	return wm831x_fll_auto_rates[best];
}

static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
			       unsigned long parent_rate)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  fll_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int i;

	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
		if (wm831x_fll_auto_rates[i] == rate)
			break;
	if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
		return -EINVAL;

	if (wm831x_fll_is_enabled(hw))
		return -EPERM;

	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
			       WM831X_FLL_AUTO_FREQ_MASK, i);
}

static const char *wm831x_fll_parents[] = {
	"xtal",
	"clkin",
};

static u8 wm831x_fll_get_parent(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  fll_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	/* AUTO mode is always clocked from the crystal */
	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
	if (ret < 0) {
		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
			ret);
		return 0;
	}

	if (ret & WM831X_FLL_AUTO)
		return 0;

	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
	if (ret < 0) {
		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
			ret);
		return 0;
	}

	switch (ret & WM831X_FLL_CLK_SRC_MASK) {
	case 0:
		return 0;
	case 1:
		return 1;
	default:
		dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
			ret & WM831X_FLL_CLK_SRC_MASK);
		return 0;
	}
}

static const struct clk_ops wm831x_fll_ops = {
	.is_enabled = wm831x_fll_is_enabled,
	.prepare = wm831x_fll_prepare,
	.unprepare = wm831x_fll_unprepare,
	.round_rate = wm831x_fll_round_rate,
	.recalc_rate = wm831x_fll_recalc_rate,
	.set_rate = wm831x_fll_set_rate,
	.get_parent = wm831x_fll_get_parent,
};

static struct clk_init_data wm831x_fll_init = {
	.name = "fll",
	.ops = &wm831x_fll_ops,
	.parent_names = wm831x_fll_parents,
	.num_parents = ARRAY_SIZE(wm831x_fll_parents),
	.flags = CLK_SET_RATE_GATE,
};

static int wm831x_clkout_is_enabled(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  clkout_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
	if (ret < 0) {
		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
			ret);
		return true;
	}

	return (ret & WM831X_CLKOUT_ENA) != 0;
}

static int wm831x_clkout_prepare(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  clkout_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	ret = wm831x_reg_unlock(wm831x);
	if (ret != 0) {
		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
		return ret;
	}

	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
			      WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
	if (ret != 0)
		dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);

	wm831x_reg_lock(wm831x);

	return ret;
}

static void wm831x_clkout_unprepare(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  clkout_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	ret = wm831x_reg_unlock(wm831x);
	if (ret != 0) {
		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
		return;
	}

	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
			      WM831X_CLKOUT_ENA, 0);
	if (ret != 0)
		dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);

	wm831x_reg_lock(wm831x);
}

static const char *wm831x_clkout_parents[] = {
	"fll",
	"xtal",
};

static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  clkout_hw);
	struct wm831x *wm831x = clkdata->wm831x;
	int ret;

	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
	if (ret < 0) {
		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
			ret);
		return 0;
	}

	if (ret & WM831X_CLKOUT_SRC)
		return 1;
	else
		return 0;
}

static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
{
	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
						  clkout_hw);
	struct wm831x *wm831x = clkdata->wm831x;

	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
			       WM831X_CLKOUT_SRC,
			       parent << WM831X_CLKOUT_SRC_SHIFT);
}

static const struct clk_ops wm831x_clkout_ops = {
	.is_enabled = wm831x_clkout_is_enabled,
	.prepare = wm831x_clkout_prepare,
	.unprepare = wm831x_clkout_unprepare,
	.get_parent = wm831x_clkout_get_parent,
	.set_parent = wm831x_clkout_set_parent,
};

static struct clk_init_data wm831x_clkout_init = {
	.name = "clkout",
	.ops = &wm831x_clkout_ops,
	.parent_names = wm831x_clkout_parents,
	.num_parents = ARRAY_SIZE(wm831x_clkout_parents),
	.flags = CLK_SET_RATE_PARENT,
};

static int wm831x_clk_probe(struct platform_device *pdev)
{
	struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
	struct wm831x_clk *clkdata;
	int ret;

	clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
	if (!clkdata)
		return -ENOMEM;

	/* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
	if (ret < 0) {
		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
			ret);
		return ret;
	}
	clkdata->xtal_ena = ret & WM831X_XTAL_ENA;

	clkdata->xtal_hw.init = &wm831x_xtal_init;
	clkdata->xtal = devm_clk_register(&pdev->dev, &clkdata->xtal_hw);
	if (IS_ERR(clkdata->xtal))
		return PTR_ERR(clkdata->xtal);

	clkdata->fll_hw.init = &wm831x_fll_init;
	clkdata->fll = devm_clk_register(&pdev->dev, &clkdata->fll_hw);
	if (IS_ERR(clkdata->fll))
		return PTR_ERR(clkdata->fll);

	clkdata->clkout_hw.init = &wm831x_clkout_init;
	clkdata->clkout = devm_clk_register(&pdev->dev, &clkdata->clkout_hw);
	if (IS_ERR(clkdata->clkout))
		return PTR_ERR(clkdata->clkout);

	dev_set_drvdata(&pdev->dev, clkdata);

	return 0;
}

static int wm831x_clk_remove(struct platform_device *pdev)
{
	return 0;
}

static struct platform_driver wm831x_clk_driver = {
	.probe = wm831x_clk_probe,
	.remove = wm831x_clk_remove,
	.driver		= {
		.name	= "wm831x-clk",
		.owner	= THIS_MODULE,
	},
};

module_platform_driver(wm831x_clk_driver);

/* Module information */
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_DESCRIPTION("WM831x clock driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm831x-clk");
Commit	Line	Data
f05259a6 MB	1	/*
	2	* WM831x clock control
	3	*
	4	* Copyright 2011-2 Wolfson Microelectronics PLC.
	5	*
	6	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/clk.h>
	16	#include <linux/clk-provider.h>
	17	#include <linux/delay.h>
	18	#include <linux/module.h>
	19	#include <linux/slab.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/mfd/wm831x/core.h>
	22
	23	struct wm831x_clk {
	24	struct wm831x *wm831x;
	25	struct clk_hw xtal_hw;
	26	struct clk_hw fll_hw;
	27	struct clk_hw clkout_hw;
	28	struct clk *xtal;
	29	struct clk *fll;
	30	struct clk *clkout;
	31	bool xtal_ena;
	32	};
	33
	34	static int wm831x_xtal_is_enabled(struct clk_hw *hw)
	35	{
	36	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
	37	xtal_hw);
	38
	39	return clkdata->xtal_ena;
	40	}
	41
	42	static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
	43	unsigned long parent_rate)
	44	{
	45	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
	46	xtal_hw);
	47
	48	if (clkdata->xtal_ena)
	49	return 32768;
	50	else
	51	return 0;
	52	}
	53
	54	static const struct clk_ops wm831x_xtal_ops = {
	55	.is_enabled = wm831x_xtal_is_enabled,
	56	.recalc_rate = wm831x_xtal_recalc_rate,
	57	};
	58
	59	static struct clk_init_data wm831x_xtal_init = {
	60	.name = "xtal",
	61	.ops = &wm831x_xtal_ops,
	62	.flags = CLK_IS_ROOT,
	63	};
	64
65	static const unsigned long wm831x_fll_auto_rates[] = {
66	2048000,
67	11289600,
68	12000000,
69	12288000,
70	19200000,
71	22579600,
72	24000000,
73	24576000,
74	};
75
76	static int wm831x_fll_is_enabled(struct clk_hw *hw)
77	{
78	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
79	fll_hw);
80	struct wm831x *wm831x = clkdata->wm831x;
81	int ret;
82
83	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
84	if (ret < 0) {
85	dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
86	ret);
87	return true;
88	}
89
90	return (ret & WM831X_FLL_ENA) != 0;
91	}
92
93	static int wm831x_fll_prepare(struct clk_hw *hw)
94	{
95	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
96	fll_hw);
97	struct wm831x *wm831x = clkdata->wm831x;
98	int ret;
99
6f8b3145	100	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
f05259a6 MB	101	WM831X_FLL_ENA, WM831X_FLL_ENA);
	102	if (ret != 0)
	103	dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
	104
	105	usleep_range(2000, 2000);
	106
	107	return ret;
	108	}
	109
	110	static void wm831x_fll_unprepare(struct clk_hw *hw)
	111	{
	112	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
	113	fll_hw);
	114	struct wm831x *wm831x = clkdata->wm831x;
	115	int ret;
	116
6f8b3145	117	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
f05259a6	118	if (ret != 0)
6f8b3145	119	dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
f05259a6 MB	120	}
	121
	122	static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
	123	unsigned long parent_rate)
	124	{
	125	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
	126	fll_hw);
	127	struct wm831x *wm831x = clkdata->wm831x;
	128	int ret;
	129
	130	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
	131	if (ret < 0) {
	132	dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
	133	ret);
	134	return 0;
	135	}
	136
	137	if (ret & WM831X_FLL_AUTO)
	138	return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
	139
	140	dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
	141
	142	return 0;
	143	}
	144
	145	static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
	146	unsigned long *unused)
	147	{
	148	int best = 0;
	149	int i;
	150
	151	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
	152	if (abs(wm831x_fll_auto_rates[i] - rate) <
	153	abs(wm831x_fll_auto_rates[best] - rate))
	154	best = i;
	155
	156	return wm831x_fll_auto_rates[best];
	157	}
	158
	159	static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
	160	unsigned long parent_rate)
	161	{
	162	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
	163	fll_hw);
	164	struct wm831x *wm831x = clkdata->wm831x;
	165	int i;
	166
	167	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
	168	if (wm831x_fll_auto_rates[i] == rate)
	169	break;
	170	if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
	171	return -EINVAL;
	172
	173	if (wm831x_fll_is_enabled(hw))
	174	return -EPERM;
	175
	176	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
	177	WM831X_FLL_AUTO_FREQ_MASK, i);
	178	}
	179
	180	static const char *wm831x_fll_parents[] = {
	181	"xtal",
	182	"clkin",
	183	};
184
185	static u8 wm831x_fll_get_parent(struct clk_hw *hw)
186	{
187	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
188	fll_hw);
189	struct wm831x *wm831x = clkdata->wm831x;
190	int ret;
191
192	/* AUTO mode is always clocked from the crystal */
193	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
194	if (ret < 0) {
195	dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
196	ret);
197	return 0;
198	}
199
200	if (ret & WM831X_FLL_AUTO)
201	return 0;
202
203	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
204	if (ret < 0) {
205	dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
206	ret);
207	return 0;
208	}
209
210	switch (ret & WM831X_FLL_CLK_SRC_MASK) {
211	case 0:
212	return 0;
213	case 1:
214	return 1;
215	default:
216	dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
217	ret & WM831X_FLL_CLK_SRC_MASK);
218	return 0;
219	}
220	}
221
222	static const struct clk_ops wm831x_fll_ops = {
223	.is_enabled = wm831x_fll_is_enabled,
224	.prepare = wm831x_fll_prepare,
225	.unprepare = wm831x_fll_unprepare,
226	.round_rate = wm831x_fll_round_rate,
227	.recalc_rate = wm831x_fll_recalc_rate,
228	.set_rate = wm831x_fll_set_rate,
229	.get_parent = wm831x_fll_get_parent,
230	};
231
232	static struct clk_init_data wm831x_fll_init = {
233	.name = "fll",
234	.ops = &wm831x_fll_ops,
235	.parent_names = wm831x_fll_parents,
236	.num_parents = ARRAY_SIZE(wm831x_fll_parents),
237	.flags = CLK_SET_RATE_GATE,
238	};
239
240	static int wm831x_clkout_is_enabled(struct clk_hw *hw)
241	{
242	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
243	clkout_hw);
244	struct wm831x *wm831x = clkdata->wm831x;
245	int ret;
246
247	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
248	if (ret < 0) {
249	dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
250	ret);
251	return true;
252	}
253
254	return (ret & WM831X_CLKOUT_ENA) != 0;
255	}
256
257	static int wm831x_clkout_prepare(struct clk_hw *hw)
258	{
259	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
260	clkout_hw);
261	struct wm831x *wm831x = clkdata->wm831x;
262	int ret;
263
264	ret = wm831x_reg_unlock(wm831x);
265	if (ret != 0) {
266	dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
267	return ret;
268	}
269
270	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
271	WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
272	if (ret != 0)
273	dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
274
275	wm831x_reg_lock(wm831x);
276
277	return ret;
278	}
279
280	static void wm831x_clkout_unprepare(struct clk_hw *hw)
281	{
282	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
283	clkout_hw);
284	struct wm831x *wm831x = clkdata->wm831x;
285	int ret;
286
287	ret = wm831x_reg_unlock(wm831x);
288	if (ret != 0) {
289	dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
290	return;
291	}
292
293	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
294	WM831X_CLKOUT_ENA, 0);
295	if (ret != 0)
296	dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
297
298	wm831x_reg_lock(wm831x);
299	}
300
301	static const char *wm831x_clkout_parents[] = {
f05259a6	302	"fll",
bcc7fd20	303	"xtal",
f05259a6 MB	304	};
	305
	306	static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
	307	{
	308	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
	309	clkout_hw);
	310	struct wm831x *wm831x = clkdata->wm831x;
	311	int ret;
	312
	313	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
	314	if (ret < 0) {
	315	dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
	316	ret);
	317	return 0;
	318	}
	319
	320	if (ret & WM831X_CLKOUT_SRC)
f05259a6	321	return 1;
bcc7fd20 AL	322	else
bcc7fd20 AL	323	return 0;
f05259a6 MB	324	}
	325
	326	static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
	327	{
	328	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
	329	clkout_hw);
	330	struct wm831x *wm831x = clkdata->wm831x;
	331
	332	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
	333	WM831X_CLKOUT_SRC,
	334	parent << WM831X_CLKOUT_SRC_SHIFT);
	335	}
	336
	337	static const struct clk_ops wm831x_clkout_ops = {
	338	.is_enabled = wm831x_clkout_is_enabled,
	339	.prepare = wm831x_clkout_prepare,
	340	.unprepare = wm831x_clkout_unprepare,
	341	.get_parent = wm831x_clkout_get_parent,
	342	.set_parent = wm831x_clkout_set_parent,
	343	};
	344
	345	static struct clk_init_data wm831x_clkout_init = {
	346	.name = "clkout",
	347	.ops = &wm831x_clkout_ops,
	348	.parent_names = wm831x_clkout_parents,
	349	.num_parents = ARRAY_SIZE(wm831x_clkout_parents),
	350	.flags = CLK_SET_RATE_PARENT,
	351	};
	352
018ae93f	353	static int wm831x_clk_probe(struct platform_device *pdev)
f05259a6 MB	354	{
	355	struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
	356	struct wm831x_clk *clkdata;
	357	int ret;
	358
	359	clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
	360	if (!clkdata)
	361	return -ENOMEM;
	362
	363	/* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
	364	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
	365	if (ret < 0) {
	366	dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
	367	ret);
	368	return ret;
	369	}
	370	clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
	371
	372	clkdata->xtal_hw.init = &wm831x_xtal_init;
9be9d482	373	clkdata->xtal = devm_clk_register(&pdev->dev, &clkdata->xtal_hw);
980f58a4 SB	374	if (IS_ERR(clkdata->xtal))
980f58a4 SB	375	return PTR_ERR(clkdata->xtal);
f05259a6 MB	376
f05259a6 MB	377	clkdata->fll_hw.init = &wm831x_fll_init;
9be9d482 SB	378	clkdata->fll = devm_clk_register(&pdev->dev, &clkdata->fll_hw);
	379	if (IS_ERR(clkdata->fll))
	380	return PTR_ERR(clkdata->fll);
f05259a6 MB	381
f05259a6 MB	382	clkdata->clkout_hw.init = &wm831x_clkout_init;
9be9d482 SB	383	clkdata->clkout = devm_clk_register(&pdev->dev, &clkdata->clkout_hw);
	384	if (IS_ERR(clkdata->clkout))
	385	return PTR_ERR(clkdata->clkout);
f05259a6 MB	386
	387	dev_set_drvdata(&pdev->dev, clkdata);
	388
	389	return 0;
f05259a6 MB	390	}
f05259a6 MB	391
1fc7ad5d	392	static int wm831x_clk_remove(struct platform_device *pdev)
f05259a6	393	{
f05259a6 MB	394	return 0;
	395	}
	396
	397	static struct platform_driver wm831x_clk_driver = {
	398	.probe = wm831x_clk_probe,
f9cfa630	399	.remove = wm831x_clk_remove,
f05259a6 MB	400	.driver = {
	401	.name = "wm831x-clk",
	402	.owner = THIS_MODULE,
	403	},
	404	};
	405
	406	module_platform_driver(wm831x_clk_driver);
	407
	408	/* Module information */
	409	MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
	410	MODULE_DESCRIPTION("WM831x clock driver");
	411	MODULE_LICENSE("GPL");
	412	MODULE_ALIAS("platform:wm831x-clk");